LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure applicable to wide temperature range based on deep N well

Abstract

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure suitable for wide temperature range application based on a deep N well. The LDMOS structure comprises a SiC substrate layer; the epitaxial layer is arranged on the upper surface of the SiC substrate layer; the drift region extends into the epitaxial layer from the upper surface of the epitaxial layer; the channel region extends into the drift region from the upper surface of the drift region; and the two top layer doped regions are symmetrically arranged on the two sides of the channel region at intervals, and each top layer doped region extends into the drift region from the upper surface of the drift region. According to the LDMOS structure provided by the invention, electric field modulation can be realized, electric field distribution at high temperature can be obviously optimized, and a hot carrier effect can be inhibited, so that the performance of an LDMOS device in high-temperature application is improved, and the LDMOS device can adapt to a relatively large temperature range and is relatively wide in application.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, specifically relating to an LDMOS structure based on a deep N-well suitable for applications over a wide temperature range. Background Technology

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor that has attracted increasing attention and research in integrated circuit device design. Power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) made from SiC have advantages such as high input impedance, good temperature characteristics, strong voltage withstand capability, excellent frequency characteristics, and fast switching speed, and are widely used in various fields.

[0003] SiC LDMOS (Laterally Diffused Metal Oxide Semiconductor) is an important component of BCD (Bipolar-CMOS-DMOS) integrated circuits because its electrodes can be led to the surface.

[0004] However, excessively high temperatures can cause hot carrier effects in LDMOS devices, which can affect their performance in high-temperature applications. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an LDMOS structure based on a deep N-well suitable for applications over a wide temperature range.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a deep N-well-based LDMOS structure suitable for wide temperature range applications, comprising: SiC substrate layer; An epitaxial layer is disposed on the upper surface of the SiC substrate layer, and the epitaxial layer is p-type doped; A drift region extends from the upper surface of the epitaxial layer into the epitaxial layer, and the two side edges of the drift region are at a first preset distance from the two side edges of the epitaxial layer, wherein the drift region is a deep n-well structure; The channel region extends from the upper surface of the drift region into the drift region, and the two side edges of the drift region are at a second predetermined distance from each other, wherein the channel region is a p-well structure; Two top-layer doped regions are symmetrically spaced on both sides of the channel region. Each top-layer doped region extends from the upper surface of the drift region into the drift region, wherein the top-layer doped region is p-type doped.

[0007] In one embodiment of the present invention, the LDMOS structure further includes: Two drain doped regions are symmetrically spaced on one side of the top doped region away from the channel region, and each drain doped region extends from the upper surface of the drift region into the drift region; The bulk doped region extends from the upper surface of the channel region into the channel region; Two source doped regions are symmetrically disposed on both sides of the bulk doped region, and one sidewall of each source doped region is attached to one sidewall of the bulk doped region. Each source doped region extends from the upper surface of the channel region into the channel region.

[0008] In one embodiment of the present invention, the SiC substrate, the source doped region, and the drain doped region are all n-type doped; The bulk doped region is p-type doped.

[0009] In one embodiment of the present invention, the LDMOS structure further includes a field oxide layer, the field oxide layer comprising: Two first field oxide sublayers, each first field oxide sublayer correspondingly covering the top doped region on one side and the drift region between the drain doped region and the channel region; Two second field oxide sublayers are disposed on the drift region and part of the epitaxial layer, respectively, outside the drain doped region.

[0010] In one embodiment of the present invention, both the first field oxide sublayer and the second field oxide sublayer are positive trapezoidal.

[0011] In one embodiment of the present invention, the LDMOS structure further includes: Two gate oxide layers are provided, each of which is disposed on the upper surface of a portion of the first field oxide layer, the upper surface of the channel region, and the upper surface of a portion of the source doped region.

[0012] In one embodiment of the present invention, the LDMOS structure further includes: Two field plates are disposed on the upper surface of the gate oxide layer.

[0013] In one embodiment of the present invention, the LDMOS structure further includes: The electrode structure is disposed on the upper surfaces of the two ends of the drift region, the upper surfaces of the two drain doped regions, the upper surfaces of the two field plates, the upper surfaces of the two source doped regions, and the upper surface of the bulk doped region.

[0014] In one embodiment of the present invention, the electrode structure includes: A bulk electrode is disposed on the upper surface of the bulk electrode doped region; Two source electrodes are respectively disposed on the upper surface of the two source electrode doped regions, and one sidewall of the source electrode is attached to one sidewall of the gate oxide layer; Two drain electrodes are respectively disposed on the upper surface of the two drain electrode doped regions; Two gate electrodes are respectively disposed on the upper surface of the field plate directly above the channel region; Two isolation electrodes are respectively disposed on the upper surface of the epitaxial layer exposed at both ends.

[0015] In one embodiment of the present invention, the depth of the drift region is ≥2µm.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides an LDMOS structure based on a deep N-well suitable for wide temperature range applications. This LDMOS structure utilizes the drift region of a deep N-well structure and two p-type doped top-layer doped regions extending from the upper surface of the drift region into the drift region, together with the p-type doped epitaxial layer, to form a double RESURF structure, thereby achieving electric field modulation. This significantly optimizes the electric field distribution at high temperatures, suppresses the hot carrier effect, and improves the performance of LDMOS devices in high-temperature applications. Furthermore, this LDMOS device can adapt to a wider temperature range and has a wider range of applications.

[0017] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an LDMOS structure based on a deep N-well suitable for wide temperature range applications provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the transfer characteristic curves of an LDMOS structure based on a deep N-well suitable for wide temperature range applications and a traditional LDMOS structure provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the breakdown characteristic curve of an LDMOS structure based on a deep N-well, suitable for applications with a wide temperature range, provided by an embodiment of the present invention.

[0019] Figure label: 1: SiC substrate; 2: Epitaxial layer; 3: Drift region; 4: Channel region; 5: Bulk doped region; 6: Source doped region; 7: Drain doped region; 8: Top doped region; 9: Field oxide layer; 10: Gate oxide layer; 11: Field plate; 12: Bulk electrode; 13: Source electrode; 14: Gate electrode; 15: Drain electrode; 16: Isolation electrode. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0021] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of an LDMOS structure based on a deep N-well suitable for wide temperature range applications, provided by an embodiment of the present invention. The LDMOS structure includes: SiC substrate layer 1; Epitaxial layer 2 is disposed on the upper surface of SiC substrate layer 1, and epitaxial layer 2 is p-type doped; Drift region 3 extends from the upper surface of epitaxial layer 2 into epitaxial layer 2, and the two side edges of drift region 3 have a first preset distance from the two side edges of epitaxial layer 2. Drift region 3 is a deep n-well structure. The channel region 4 extends from the upper surface of the drift region 3 into the drift region 3, and the two side edges of the drift region 3 have a second preset distance from each other. The channel region is a p-well structure. Two top-layer doped regions 8 are symmetrically spaced on both sides of the channel region 4. Each top-layer doped region 8 extends from the upper surface of the drift region 3 into the drift region 3. The top-layer doped region 8 is p-type doped.

[0022] The LDMOS structure provided in this embodiment has a p-type doped epitaxial layer on a SiC substrate, and a drift region of a deep n-well structure is formed within the p-type doped epitaxial layer. It also has two p-type doped top layer regions extending from the upper surface of the drift region into the drift region. Therefore, the epitaxial layer, the drift region and the top layer doped region form a double RESURF (Reduce Surface Field) structure. A p-type top layer is introduced above the drift region of the deep n-well structure, and a p-type epitaxial layer is introduced below it. When a high voltage is applied to the drain, the ionized donors (positive charges) in the drift region are compensated simultaneously from two directions by the ionized acceptors (negative charges) in the upper and lower P-type regions: the top doped region mainly depletes the part of the drift region near the surface, optimizing the lateral (surface) electric field distribution; the epitaxial layer mainly depletes the part of the drift region near the substrate, optimizing the longitudinal (bulk) electric field distribution. This dual charge compensation effect, sandwiched between the top and bottom, forces the depletion region to expand rapidly and uniformly laterally within the drift region, reshaping the originally triangular electric field distribution with high peaks and uneven distribution into a flat high electric field platform that is close to an ideal rectangle, thereby achieving electric field modulation.

[0023] At high temperatures, the increased intrinsic carrier concentration weakens the depletion capability of traditional devices, leading to depletion region shrinkage. The rectangular electric field distribution formed by the double RESURF structure can significantly suppress depletion region shrinkage at high temperatures, optimize the electric field distribution of the device at high temperatures, avoid the generation of current hotspots by local high electric field peaks in traditional devices, reduce additional leakage current caused by impact ionization and hot carrier injection, suppress the hot carrier effect, and thus improve the performance of LDMOS devices in high-temperature applications. Moreover, this LDMOS device can adapt to a temperature range of 300K~773K, making it more widely applicable.

[0024] In this embodiment, the first preset distance and the second preset distance are not specifically limited, and those skilled in the art can choose an appropriate distance according to actual needs. For example, the first preset distance is 5~8µm, and the second preset distance is 10~18µm.

[0025] Preferably, since the top doped region is thinner, the doping concentration of the top doped region 8 is usually greater than that of the drift region 3 to meet charge balance; in order to ensure that the drift region can be completely depleted and avoid premature longitudinal breakdown, the doping concentration of the drift region 3 should be greater than that of the epitaxial layer 2.

[0026] Preferably, the thickness of the SiC substrate 1 is ≥4.5µm, and the SiC substrate 1 is n-type doped, with the doping element being, for example, nitrogen (N), and the doping concentration being 5e15cm. -3 .

[0027] Preferably, the thickness of epitaxial layer 2 is 5~10µm, and epitaxial layer 2 is p-type doped, with the doping element being, for example, aluminum, and the doping concentration being 1e16~3e16cm. -3 .

[0028] It should be noted that the doping concentration and depth of drift region 3 can be adjusted according to the application voltage and application temperature requirements, and this embodiment does not impose specific limitations.

[0029] Preferably, ion implantation is performed on the epitaxial layer 2 to form a drift region 3 with a deep n-well structure at the center of the epitaxial layer 2, wherein the depth of the drift region 3 is ≥2µm.

[0030] Furthermore, the depth of drift region 3 is 2µm to 3µm. A deeper drift region allows the depletion layer to fully expand in the vertical direction, improving the withstand voltage capability, reducing the injection of hot carriers in the high electric field region of the surface, and improving the device's high temperature resistance.

[0031] Preferably, the drift region 3 is n-type doped, and the doping element is, for example, nitrogen (N). The doping concentration of the drift region 3 can be in the range of 4.5e16~6.5e16 cm⁻¹. -3 .

[0032] Preferably, a channel region 4 is formed at the center of the drift region 3 by ion implantation. The channel region 4 has a depth of 0.6 µm and is p-type doped with an element such as aluminum (Al) at a concentration of 5e17 cm⁻¹. -3 .

[0033] Preferably, by ion implantation into the drift region 3, two top doped regions 8 with the same depth and doping concentration are formed in the drift region 3. The depth of the top doped regions 8 is 0.2~0.6 µm, and both top doped regions 8 are p-type doped, with the doping element being, for example, aluminum (Al), and the doping concentration being 8e16~5e17 cm⁻¹. -3 .

[0034] In an optional embodiment, the LDMOS structure further includes: Two drain doped regions 7 are symmetrically spaced on one side of the top doped region 8 away from the channel region 4, and each drain doped region 7 extends from the upper surface of the drift region 3 into the drift region 3. The bulk doped region 5 extends from the upper surface of the channel region 4 into the channel region 4; Two source doped regions 6 are symmetrically disposed on both sides of the bulk doped region 5, and one side wall of each source doped region 6 is attached to one side wall of the bulk doped region 5. Each source doped region 6 extends from the upper surface of the channel region 4 into the channel region 4.

[0035] Preferably, by ion implantation into the drift region 3, two drain doped regions 7 with the same depth and doping concentration are formed in the drift region 3. The depth of the drain doped regions 7 is 0.1~0.3µm, and both drain doped regions 7 are n-type doped, with the doping element being, for example, nitrogen (N).

[0036] Preferably, the bulk doped region 5 is formed by ion implantation into the channel region 4. The depth of the bulk doped region 5 is 0.1~0.3µm, and the bulk doped region 5 is p-type doped, with the doping element being, for example, aluminum (Al).

[0037] Preferably, by ion implantation into the channel region 4, two source doped regions 6 with the same depth and doping concentration are formed in the channel region 4. The depth of the source doped regions 6 is 0.1~0.3µm, and both source doped regions 6 are n-type doped, with the doping element being, for example, nitrogen (N).

[0038] Preferably, the source doped region 6, the drain doped region 7, and the bulk doped region 5 are all heavily doped regions, and the doping concentration of each region is not less than 1e20.

[0039] In an optional embodiment, the LDMOS structure further includes a field oxide layer 9, which comprises: Two first field oxide sublayers, each first field oxide sublayer corresponding to cover the top doped region 8 on one side and the drift region 3 between the drain doped region 7 and the channel region 4; Two second field oxide sublayers are disposed on the drift region 3 and part of the epitaxial layer 2, which are located outside the drain doped region 7.

[0040] In other words, the first field oxide sublayer is located on the upper surface of the drift region 3 between the channel region 4 and the drain doped region 7, and the second field oxide sublayer is located at a certain distance from the edge of the drain doped region 7 away from the channel region 4 to the upper surface of the epitaxial layer 2 and the two edge regions of the epitaxial layer 2.

[0041] Preferably, both the first and second field oxide sublayers are trapezoidal, meaning the width of the upper surface is smaller than the width of the lower surface. This structure enables the inclined edge of the field plate to achieve gradual capacitive coupling with the drift region, causing the surface electric field to decrease linearly along the drift region and improving the uniformity of the transverse electric field.

[0042] Preferably, the thickness of the first and second field oxide sublayers can be ≥0.5µm, and the material is silicon dioxide.

[0043] In an optional embodiment, the LDMOS structure further includes: Two gate oxide layers 10 are disposed on the upper surface of a portion of the first field oxide layer, the upper surface of the channel region 4, and the upper surface of a portion of the source doped region 6.

[0044] Preferably, the thickness of the gate oxide layer 10 can be ≥0.05µm, and the material is silicon dioxide.

[0045] In an optional embodiment, the LDMOS structure further includes: Two field plates 11 are disposed on the upper surface of the gate oxide layer 10.

[0046] This embodiment utilizes a dual RESURF structure consisting of an epitaxial layer 2, a drift region 3, and a top doped region 8, combined with the extension of two field plates 11, to disperse the high electric field region at the gate electrode corner into the drift region. Under high-temperature conditions, this can suppress the formation of an inversion layer on the surface of the drift region, thereby suppressing the increase in leakage current at high temperatures and suppressing the influence of interface traps. Simultaneously, by combining the dual RESURF structure with the two field plates 11, the longitudinal and lateral electric fields are modulated to ensure uniform distribution, thus avoiding excessively high local electric field strength and maintaining stable breakdown voltage, thereby preventing performance changes at high temperatures caused by local overheating.

[0047] Preferably, the thickness of the field plate 11 can be 0.5~1.5µm, and the material is polycrystalline silicon.

[0048] In an optional embodiment, the LDMOS structure further includes: The electrode structure is disposed on the upper surface of both ends of the drift region 3, the upper surface of the two drain doped regions 7, the upper surface of the two field plates 11, the upper surface of the two source doped regions 6, and the upper surface of the bulk doped region 5.

[0049] In an optional embodiment, the electrode structure includes: The body electrode 12 is disposed on the upper surface of the body electrode doped region 5; Two source electrodes 13 are respectively disposed on the upper surface of two source doped regions 6, and one sidewall of the source electrode 13 is attached to one sidewall of the gate oxide layer 10. Two drain electrodes 15 are respectively disposed on the upper surface of the two drain doped regions 7; Two gate electrodes 14 are respectively disposed on the upper surface of the field plate 11 located directly above the channel region 4; Two isolation electrodes 16 are respectively disposed on the upper surface of the epitaxial layer 2 exposed at both ends.

[0050] Currently, existing LDMOS devices suffer from threshold voltage drift at excessively high temperatures, affecting their electrical performance at high temperatures. The LDMOS device provided in this invention, based on the aforementioned structure, further incorporates an isolation electrode 16 connected to the upper surface of the epitaxial layer 2. This isolation electrode not only isolates the device but also helps control threshold voltage drift at high temperatures. This device design improves upon threshold voltage drift caused by temperature increases, optimizing the device's high-temperature electrical characteristics.

[0051] Preferably, the thickness of the first metal layer of the body electrode 12 is 0.5µm, and the thickness of the second metal layer is 4~5µm, and the material is, for example, aluminum.

[0052] Preferably, the first metal layer of the source electrode 13 has a thickness of 0.5µm, and the second metal layer has a thickness of 4~5µm, and the material is, for example, aluminum.

[0053] Preferably, the first metal layer of the drain electrode 15 has a thickness of 0.5µm, and the second metal layer has a thickness of 4~5µm, and the material is, for example, aluminum.

[0054] Preferably, the first metal layer of the gate electrode 14 has a thickness of 0.5µm, and the second metal layer has a thickness of 4~5µm, and the material is, for example, aluminum.

[0055] Preferably, the first metal layer of the isolation electrode 16 has a thickness of 0.5µm, and the second metal layer has a thickness of 4~5µm, and the material is, for example, aluminum.

[0056] To verify the technical effectiveness of the deep N-well-based LDMOS structure suitable for wide temperature range applications provided by this invention, the transfer and breakdown characteristics of the LDMOS structure were simulated. Please refer to [link / reference]. Figure 2 , Figure 2 The solid line in the figure represents the transfer characteristic curve of the LDMOS structure provided by this invention in the range of 300K-773K. Figure 2 The dashed line in the figure represents the transfer characteristic curve of a traditional SiC LDMOS structure in the range of 300K-773K; please refer to [link / reference]. Figure 3 , Figure 3 The breakdown characteristic curves of the LDMOS structure provided by this invention are shown in the range of 300K-773K. At high temperatures, the LDMOS structure provided by this invention, which is suitable for wide temperature range applications, has a breakdown voltage that is stable above 680V at 500°C with fluctuations not exceeding 1V; the threshold voltage is controlled to not exceed 10V, and the fluctuations are significantly reduced compared to the traditional SiC LDMOS structure.

[0057] This invention provides a deep N-well-based LDMOS structure suitable for wide temperature range applications. It utilizes the drift region of the deep N-well structure and the implanted top-layer doped region to form a double RESURF structure with the epitaxial layer, achieving electric field modulation and significantly optimizing the electric field distribution at high temperatures, suppressing hot carrier effects. The double RESURF structure, combined with the extension of the field plate, disperses the high electric field region at the gate electrode corner into the drift region, suppressing the formation of an inversion layer on the drift region surface at high temperatures, thereby suppressing the increase in leakage current at high temperatures, suppressing the influence of interface traps, and avoiding excessively high local electric field strength, thus maintaining stable breakdown voltage and preventing performance changes at high temperatures due to local overheating. The isolation electrode connected to the epitaxial layer surface not only isolates the device but also helps control threshold voltage drift at high temperatures. The LDMOS structure device provided by this invention improves the threshold drift and breakdown voltage changes caused by temperature increases, optimizing the high-temperature electrical characteristics of the device.

[0058] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0059] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0060] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0061] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0062] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A deep N-well-based LDMOS structure suitable for wide temperature range applications, characterized in that, include: SiC substrate layer; An epitaxial layer is disposed on the upper surface of the SiC substrate layer, and the epitaxial layer is p-type doped; A drift region extends from the upper surface of the epitaxial layer into the epitaxial layer, and the two side edges of the drift region are at a first preset distance from the two side edges of the epitaxial layer, wherein the drift region is a deep n-well structure; The channel region extends from the upper surface of the drift region into the drift region, and the two side edges of the drift region are at a second predetermined distance from each other, wherein the channel region is a p-well structure; Two top-layer doped regions are symmetrically spaced on both sides of the channel region. Each top-layer doped region extends from the upper surface of the drift region into the drift region, wherein the top-layer doped region is p-type doped.

2. The LDMOS structure according to claim 1, characterized in that, The LDMOS structure also includes: Two drain doped regions are symmetrically spaced on one side of the top doped region away from the channel region, and each drain doped region extends from the upper surface of the drift region into the drift region; The bulk doped region extends from the upper surface of the channel region into the channel region; Two source doped regions are symmetrically disposed on both sides of the bulk doped region, and one sidewall of each source doped region is attached to one sidewall of the bulk doped region. Each source doped region extends from the upper surface of the channel region into the channel region.

3. The LDMOS structure according to claim 2, characterized in that, The SiC substrate, the source doped region, and the drain doped region are all n-type doped. The bulk doped region is p-type doped.

4. The LDMOS structure according to claim 2, characterized in that, The LDMOS structure further includes a field oxide layer, the field oxide layer comprising: Two first field oxide sublayers, each first field oxide sublayer correspondingly covering the top doped region on one side and the drift region between the drain doped region and the channel region; Two second field oxide sublayers are disposed on the drift region and part of the epitaxial layer, respectively, outside the drain doped region.

5. The LDMOS structure according to claim 4, characterized in that, Both the first and second field oxide sublayers are positive trapezoidal.

6. The LDMOS structure according to claim 4, characterized in that, The LDMOS structure also includes: Two gate oxide layers are provided, each of which is disposed on the upper surface of a portion of the first field oxide layer, the upper surface of the channel region, and the upper surface of a portion of the source doped region.

7. The LDMOS structure according to claim 6, characterized in that, The LDMOS structure also includes: Two field plates are provided, each of which is disposed on the upper surface of the gate oxide layer.

8. The LDMOS structure according to claim 7, characterized in that, The LDMOS structure also includes: The electrode structure is disposed on the upper surfaces of the two ends of the drift region, the upper surfaces of the two drain doped regions, the upper surfaces of the two field plates, the upper surfaces of the two source doped regions, and the upper surface of the bulk doped region.

9. The LDMOS structure according to claim 8, characterized in that, The electrode structure includes: A bulk electrode is disposed on the upper surface of the bulk electrode doped region; Two source electrodes are respectively disposed on the upper surface of the two source electrode doped regions, and one sidewall of the source electrode is attached to one sidewall of the gate oxide layer; Two drain electrodes are respectively disposed on the upper surface of the two drain electrode doped regions; Two gate electrodes are respectively disposed on the upper surface of the field plate directly above the channel region; Two isolation electrodes are respectively disposed on the upper surface of the epitaxial layer exposed at both ends.

10. The LDMOS structure according to claim 1, characterized in that, The depth of the drift region is ≥2µm.

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