Circuit structure for solving single particle inversion and method for solving single particle inversion

By modifying the static memory cell to construct an embedded majority voter, the delay and area problems introduced by the external majority voting circuit are solved, high-reliability single-event upset protection is achieved, and the chip design is optimized.

CN120977347APending Publication Date: 2025-11-18SHANGHAI HUALI INTEGRATED CIRCUIT CORP
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Patent Information

Application Number
CN202511066105.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-30
Publication Date
2025-11-18

AI Technical Summary

Technical Problem

In the prior art, external majority voting circuits introduce additional signal propagation delays, increase chip area and layout and wiring complexity in integrated circuits, and may also be affected by single-event effects, leading to reliability issues.

Method used

The majority voter circuit structure using static memory is constructed by modifying the static memory cells within the chip to build an embedded majority voter. The majority voting logic is implemented using three sets of two-input NAND gates and one three-input NOR gate, reducing the delay and area overhead of external circuits.

Benefits of technology

Without sacrificing or even improving system performance, it significantly optimizes chip area and design complexity, improves circuit reliability in radiated environments, and effectively shields against the effects of single-event upsets.

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Abstract

The invention provides a circuit structure for solving single-particle inversion and a method for solving single-particle inversion. The circuit structure comprises three groups of two-input NAND gates and a three-input NOR gate, wherein the three groups of two-input NAND gates are formed by transforming a first six-transistor static memory unit, and the three-input NOR gate is formed by transforming at least one second six-transistor static memory unit. And the outputs of the three groups of NAND gates are connected to the input of the NOR gate so as to realize a majority voting function on the three paths of redundant input signals. According to the embedded majority voter, the circuit connection of the standard static memory unit is reconstructed, and the embedded majority voter is realized by multiplexing the existing resources on the premise of not changing the layout of a bottom transistor. Compared with the prior art, the scheme effectively solves the problems of extra signal propagation delay and chip area overhead caused by the adoption of an external voter, improves the integration level and time sequence performance of the circuit, and is highly compatible with a standard process.
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