Direct liquid cooling of semiconductor devices

Abstract

A system and associated method for direct liquid cooling of a semiconductor device. The system includes at least one semiconductor device positioned on a chip substrate and at least one cold plate disposed within the chip substrate and containing a cooling liquid. The cold plate is positioned proximate to the semiconductor device and is configured to at least partially dissipate heat from the semiconductor device using a coolant during operation of the semiconductor device.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of priority to and is a continuation-in-part of U.S. Patent No. 18 / 664,744, filed May 15, 2024, entitled “Direct Liquid Cooling of Semiconductor Devices,” to Schulz, and incorporates by reference the entire disclosure thereof. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to direct liquid cooling of semiconductor devices. BACKGROUND

[0004] Cooling of power semiconductors is an important aspect of electronic device management, especially as power density and heat generation within these devices increase. Effective cooling systems are critical to maintaining the reliability and performance of power semiconductor devices, such as MOSFETs and IGBTs, which are indispensable for a wide range of applications from consumer electronics to electric vehicles. Conventional cooling methods, such as metal heat sinks, are often insufficient for high heat flux situations, which has prompted the development of advanced cooling techniques. These include passive and active cooling systems, the use of thermoelectric modules, and immersion in dielectric fluids. The development of cooling techniques seeks to enhance heat dissipation and reduce thermal resistance, thereby enabling power semiconductors to operate effectively within a safe temperature range and extending the operational life of power semiconductors. However, existing technologies often require various isolation components to separate the power semiconductor devices and cooling components, thereby reducing their effectiveness and efficiency. SUMMARY

[0005] The following summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0006] In some implementations, the current subject matter relates to a system that can include at least one semiconductor device positioned on a chip substrate and at least one cold plate disposed within the chip substrate and containing a cooling liquid. The cold plate can be positioned in close proximity to the semiconductor device and can be configured to at least partially dissipate heat from the semiconductor device during operation of the semiconductor device using the cooling liquid.

[0007] In some implementations, the current subject matter includes one or more of the following optional features. The cold plate can include a closed channel containing the cooling liquid.

[0008] In some embodiments, the enclosed channel can include an inlet and an outlet. The inlet can be configured to allow the cooling liquid to flow into the enclosed channel, and the outlet can be configured to allow the cooling liquid to flow out of the enclosed channel. The cooling liquid can be configured to circulate within the enclosed channel.

[0009] In some embodiments, the system can further include at least one other semiconductor device positioned on the chip substrate. The other semiconductor device can be coupled to the semiconductor device. The semiconductor device and the other semiconductor device can be coupled using at least one of: a bond wire, a clip, and any combination thereof.

[0010] In some embodiments, the cold plate can be positioned proximate to the other semiconductor device and configured to at least partially dissipate heat from at least one of the semiconductor device and the other semiconductor device during operation of at least one of the semiconductor device and the other semiconductor device.

[0011] In some embodiments, the system can include at least one other cold plate disposed within the chip substrate. The other cold plate can include another enclosed channel containing a cooling liquid. The other cold plate can be positioned proximate to the other semiconductor device and can be configured to at least partially dissipate heat from the other semiconductor device during operation of the other semiconductor device using the cooling liquid. The other enclosed channel is not connected to the enclosed channel. Alternatively or additionally, the other enclosed channel can be connected to the enclosed channel. The cooling liquid can be configured to circulate between the enclosed channel and the other enclosed channel.

[0012] In some embodiments, one cold plate can be positioned below at least one of the semiconductor device and the other semiconductor device.

[0013] In some embodiments, the semiconductor device can include a semiconductor switching device. The semiconductor switching device can include an insulated gate bipolar transistor. The other semiconductor device can be a diode.

[0014] In some embodiments, the cold plate can be an electrically conductive cold plate.

[0015] In some implementations, the current subject matter relates to a system. The system can include a first semiconductor device positioned on a chip substrate and a first cold plate disposed within the chip substrate and containing a first coolant, where the first cold plate can be positioned proximate to the first semiconductor device and configured to at least partially dissipate heat from the first semiconductor device during operation of the first semiconductor device using the first coolant. The system can also include a second semiconductor device positioned on the chip substrate and a second cold plate disposed within the chip substrate and containing a second coolant, where the second cold plate can be positioned proximate to the second semiconductor device and configured to at least partially dissipate heat from the second semiconductor device during operation of the second semiconductor device using the second coolant. The first cold plate can be galvanically isolated from the second cold plate using an isolation mechanism.

[0016] In some implementations, the current subject matter can include one or more of the following optional features. The first cold plate can include a first enclosed channel containing the coolant. The second cold plate can include a second enclosed channel containing the coolant. At least one of the first enclosed channel and the second enclosed channel can include an inlet and an outlet. The inlet can be configured to allow the coolant to flow into the at least one of the first enclosed channel and the second enclosed channel, and the outlet can be configured to allow the coolant to flow out of the at least one of the first enclosed channel and the second enclosed channel. The coolant can be configured to circulate within the first enclosed channel and the second enclosed channel.

[0017] In some implementations, the first semiconductor device can include an insulated gate bipolar transistor, and the second semiconductor device can be a diode.

[0018] In some implementations, the coolant can be an electrically conductive coolant.

[0019] In some implementations, the current subject matter relates to a system that can include a first cold plate containing a first coolant. The first cold plate can be positioned proximate to a first semiconductor device and configured to at least partially dissipate heat from the first semiconductor device during operation of the first semiconductor device using the first coolant. The system can also include a second cold plate containing a second coolant. The second cold plate can be positioned proximate to a second semiconductor device and configured to at least partially dissipate heat from the second semiconductor device during operation of the second semiconductor device using the second coolant. The second cold plate can be separate from the first cold plate.

[0020] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed implementations. In the drawings,

[0022] FIG. 1A An existing system for cooling one or more semiconductor devices during operation is shown;

[0023] FIG. 1B is a perspective view of an example cooling system for cooling one or more semiconductor devices (e.g., power semiconductor devices) during operation in accordance with some implementations of the current subject matter; FIG. 1A is a circuit schematic diagram of the system shown;

[0024] FIG. 2A is a perspective view of a cooling system for cooling one or more semiconductor devices (e.g., power semiconductor devices) during operation in accordance with some implementations of the current subject matter;

[0025] FIG. 2B is an example of a cold plate or cooling structure (terms used interchangeably) that can be disposed within a chip substrate in accordance with some implementations of the current subject matter;

[0026] FIG. 3 is an example cooling system for cooling one or more semiconductor devices (e.g., power semiconductor devices) during operation in accordance with some implementations of the current subject matter;

[0027] FIG. 4A is another example cooling system for cooling semiconductor devices (e.g., power semiconductor devices) during operation in accordance with some implementations of the current subject matter;

[0028] FIG. 4B is yet another example cooling system for cooling semiconductor devices (e.g., power semiconductor devices) during operation in accordance with some implementations of the current subject matter; and

[0029] FIG. 5 is a top view and corresponding circuit schematic diagram of an example of a cooling system for cooling a plurality of semiconductor devices during operation in accordance with some implementations of the current subject matter. DETAILED DESCRIPTION

[0030] Various methods according to this disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of systems and methods are shown. The devices, systems, components, etc. can be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the current subject matter to those skilled in the art.

[0031] To address these and potential other deficiencies in currently available solutions, one or more embodiments of the current subject matter relate to methods, systems, articles of manufacture, and / or the like that can provide direct liquid cooling of a semiconductor device during operation of the semiconductor device, among other possible advantages.

[0032] In some embodiments, the current subject matter relates to a cooling system that uses direct liquid cooling to cool one or more semiconductor devices. The system can be used to cool semiconductor devices such as, for example and without limitation, semiconductor switching devices (e.g., insulated gate bipolar transistors (IGBTs)), diodes, and / or any other type of semiconductor device. The system can be configured to address sudden increases in temperature of the semiconductor device during operation (e.g., temperature spikes), gradual increases in temperature during operation, and / or maintain the temperature of the semiconductor device (and other circuit elements) at a predetermined temperature.

[0033] The semiconductor device can be positioned on a chip substrate and / or any other substrate, platform, and / or the like (hereinafter, referred to as a “die substrate”). The die substrate can be configured to integrate, incorporate, contain, and / or act as a cold plate, which can be configured to provide cooling to the semiconductor device disposed on the die substrate. The cold plate can include one or more enclosed channels that can contain a cooling liquid. The enclosed channels can be formed within the die substrate using molding, drilling, 3D printing, 3D metal printing, and / or any other desired technique that can enable advanced internal configurations of the enclosed channels and provide improved heat transfer (i.e., dissipation of heat from the semiconductor device positioned on the die substrate).

[0034] The cold plate can be positioned and / or disposed within the die substrate proximate to the location of the semiconductor device on the die substrate. As described above, the cold plate can be configured to at least partially dissipate heat from the semiconductor device during operation of the semiconductor device using the cooling liquid. The cooling liquid can circulate within the enclosed channels and can enter the enclosed channels via an inlet of the enclosed channels and exit the enclosed channels via an outlet of the enclosed channels. The inlet and the outlet can be connected to a source of the cooling liquid (e.g., a container, etc.) that can be configured to maintain the liquid at a predetermined temperature to allow it to cool the semiconductor device.

[0035] The cold plate can be configured to be positioned proximate to the semiconductor device. In some example embodiments, the cold plate can be positioned within and / or on the die substrate directly below and / or beneath and / or adjacent to the semiconductor device. In this way, the cooling liquid circulating within the enclosed channels of the cold plate can directly cool the semiconductor device during operation.

[0036] In some embodiments, the semiconductor device can be coupled to another semiconductor device positioned on the same chip substrate. For example, the semiconductor device can be an IGBT, and the other semiconductor device can be a diode. As can be appreciated, the current subject matter can be used in connection with any type of semiconductor device, power semiconductor device, thyristor, MOSFET, etc. The coupling of the IGBT and the diode can be implemented using at least one of: a bond wire, a clip, and / or any other mechanism and / or any combination thereof. The two (or more) semiconductor devices can be cooled by the same cold plate, where the cold plate can be positioned in close proximity to both semiconductor devices. Thus, the same cold plate can be configured to at least partially dissipate heat from one or both of the semiconductor device and the other semiconductor device during operation of one or both of the semiconductor device and the other semiconductor device.

[0037] Alternatively or additionally, the other semiconductor device can be cooled by its own cold plate, where such second cold plate can be disposed within the chip substrate and include its own enclosed channel containing cooling liquid. The cooling liquid can be the same and / or different than the cooling liquid circulated in the first cold plate. The enclosed channel of the second cold plate can include its own inlet and / or outlet, and / or be connected to the inlet / outlet of the enclosed channel of the first cold plate. In this arrangement, each cold plate can be configured to cool the semiconductor device positioned in close proximity to (e.g., positioned above) that cold plate. The enclosed channels of the two cold plates can or can not be connected to each other. If the channels are connected, the cooling liquid from the enclosed channel of one cold plate can be configured to flow to the enclosed channel of the other cold plate.

[0038] In some embodiments, the cold plate containing cooling liquid can be an electrically conductive cold plate. Alternatively or additionally, the cold plate can be a non-conductive cold plate. As can be appreciated, any other type of cold plate can be used.

[0039] In some embodiments, the current subject matter relates to a direct liquid cooling system for cooling a plurality of semiconductor devices. For example, the system can include a first semiconductor device (e.g., IGBT, MOSFET, thyristor, diode, etc.) positioned on a chip substrate. A first cold plate can be disposed within the chip substrate proximate to and / or beneath the first semiconductor device. The first cold plate can include enclosed channels that can contain a first cooling liquid. The first cold plate can be configured to at least partially dissipate heat from the first semiconductor device using the first cooling liquid during operation of the first semiconductor device. The system can also include a second semiconductor device that can be positioned on the chip substrate. The first and second semiconductor devices can be positioned proximate to and / or adjacent to one another and can be coupled to one another using bond wires, clamps, etc. The second semiconductor device can be cooled by a second cold plate disposed within the chip substrate and positioned proximate to and / or directly beneath the second semiconductor device. The second cold plate can likewise include enclosed channels that can contain a second cooling liquid. The second cold plate can be configured to at least partially dissipate heat from the second semiconductor device using the second cooling liquid during operation of the second semiconductor device. The first and second cold plates can be galvanically isolated from the second cold plate using an isolation mechanism, where the isolation mechanism can include an isolation tube.

[0040] In some embodiments, the cold plates can share an inlet and an outlet, allowing the cooling liquid to flow into and out of both cold plates. Alternatively or additionally, each cold plate can have its own inlet and / or outlet.

[0041] Furthermore, in some embodiments, the current subject matter system can be configured to perform direct liquid cooling of multiple semiconductor devices and / or multiple pairs of semiconductor devices. Each semiconductor device and / or each pair of semiconductor devices and / or group / set of semiconductor devices can be cooled by a single and / or multiple cold plates (e.g., one plate can cool one semiconductor device, one plate can cool multiple semiconductor devices, etc.). As can be appreciated, any manner of arranging the cold plates relative to the semiconductor devices is possible.

[0042] FIG. 1A and FIG. 1BAn existing system 100 and circuit schematic 102 for cooling one or more semiconductor devices during operation is shown. The system 100 can include a substrate layer or heat sink 104, a backside layer 106, an isolation layer 108, and one or more terminals 110, 112, and 114 positioned on the isolation layer 108. The substrate layer 104 is coupled on top of the backside layer 106. The backside layer 106 is coupled on top of the isolation layer 108 and is formed between the isolation layer 108 and the substrate layer 104. The substrate layer 104 can include one or more heat sinks that can provide cooling for semiconductor devices positioned on the isolation layer 108. The layers 104-108 can be formed individually. Alternatively or additionally, one or more layers can be formed within another layer (e.g., by diffusion and / or any other known process). Each of the layers 104-108 can have their own polarity, which can be determined at the time of layer formation.

[0043] One or more semiconductor devices are positioned on the isolation layer 108 and coupled to one or more terminals 110, 112, and / or 114. For example, a semiconductor device 116 (e.g., an insulated gate bipolar transistor (IGBT 1)) and a semiconductor device 116 (e.g., a diode 1) can be coupled to the terminal 110 (e.g., a DC terminal). A semiconductor device 122 (e.g., an IGBT 2) and a semiconductor device 124 (e.g., a diode 2) can be coupled to the terminal 112 (e.g., an AC terminal).

[0044] An insulated gate bipolar transistor (IGBT) is a semiconductor device commonly used in power electronics. The IGBT combines the gate drive characteristics of a metal-oxide-semiconductor field-effect transistor (MOSFET) with the high current and low saturation voltage capability of a bipolar transistor. IGBTs are designed to handle large power levels and are commonly used in inverters, power amplifiers, and switching power supplies.

[0045] The basic structure of an IGBT includes four layers of alternating P-type and N-type semiconductor material, forming a P-N-P-N structure. This is controlled by an insulated gate similar to that of a MOSFET, which regulates the flow of current between the collector and emitter terminals. The gate terminal is insulated from the rest of the transistor by a thin layer of oxide (i.e., the “insulated gate”). The operation of an IGBT is based on the ability of the gate to control a larger current between the collector and emitter, making it an effective switch for high-power applications.

[0046] A diode is a two-terminal semiconductor device that allows current to flow in one direction while blocking current flow in the opposite direction. A diode includes a p-n junction that is formed by doping an acceptor (p-type) on one side of a semiconductor material and a donor (n-type) on the other side. The junction forms a depletion region that acts as a barrier to current flow when the diode is reverse-biased. When forward-biased, an external voltage causes the width of the depletion region to decrease, allowing current to flow. Typically, diodes are used as rectifying devices that convert alternating current (AC) to direct current (DC).

[0047] The semiconductor devices can likewise be coupled using one or more connections 120 and / or 126. For example, semiconductor device 116 and semiconductor device 118 can be coupled together using connection 120, which in turn is coupled to terminal 112. Similarly, semiconductor device 122 and semiconductor device 124 can be coupled together using connection 126, which in turn is coupled to terminal 114 (e.g., another DC terminal). As can be appreciated, any other semiconductor devices (e.g., MOSFETs, thyristors, etc.) and / or any combination of devices can be used. Moreover, semiconductor devices 116 and 118, and semiconductor devices 122 and 124 can be separated using trenches and / or any other separation technique.

[0048] FIG. 1B A circuit schematic 102 is shown for cooling one or more semiconductor devices of the system 100. FIG. 1A In particular, the circuit schematic 102 shows further details of the various connections between the semiconductor devices, including connections 120 and 126. As shown, the semiconductor device 116 (e.g., IGBT 1) includes a collector (C1), a gate (G1), and an emitter (E1). The semiconductor device 118 (e.g., diode 1) is coupled between the collector C1 and the emitter E1 of the semiconductor device 116. The collector C1 of the semiconductor device 116 is coupled to terminal 110 (e.g., a DC terminal). The emitter E1 of the semiconductor device 116 is coupled to terminal 112 (e.g., an AC terminal). FIG. 1B

[0049] Similarly, the semiconductor device 122 (e.g., IGBT 2) includes a collector (C2), a gate (G2), and an emitter (E2). The semiconductor device 124 (e.g., diode 2) is coupled between the collector C2 and the emitter E2 of the semiconductor device 124. The collector C2 of the semiconductor device 122 is coupled to terminal 112 (e.g., an AC terminal). The emitter E2 of the semiconductor device 122 is coupled to terminal 114 (e.g., a DC terminal).

[0050] ​In a conventional system, the isolation layer 108 provides the required isolation between the semiconductor devices 116, 118, 122, and 124 and the substrate layer 104. Otherwise, direct contact between 104 and the semiconductor devices may potentially cause a short circuit between the semiconductor devices 116, 118 and the semiconductor devices 122, 124. However, the isolation layer 108 typically provides insufficient or inadequate thermal conductivity, thereby hindering the effective cooling of the semiconductor devices positioned thereon. This can cause the semiconductor devices to overheat and break down, which in turn can cause a circuit failure. The current subject matter solves these problems by directly mounting the semiconductor devices to the heat sink substrate layer 104, which uses a coolant to provide the necessary cooling.

[0051] FIG. 2A A perspective view of a cooling system 200 for cooling one or more semiconductor devices (e.g., power semiconductor devices) during operation thereof in accordance with some embodiments of the current subject matter is shown.

[0052] The system 200 may include a chip substrate 202, one or more terminals 204 (a, b, c, d) that may be coupled to the chip substrate 202, a cooling inlet 206, a cooling outlet 208, a semiconductor device 210, and a semiconductor device 212. The semiconductor devices 210 and 212 may be coupled to the chip substrate 202. The semiconductor devices 210, 212 may also be coupled to one or more terminals 204. In particular, the terminals 204 may be coupled to one or more terminals of the devices 210, 212.

[0053] The terminals 204 may be coupled to the chip substrate 202 using direct copper bonding (DCB) technology. DCB is a process that enhances the electrical and thermal performance of power electronic devices. It directly attaches a copper conductor to a ceramic substrate by reacting a thin layer of copper oxide on the copper surface with the ceramic at high temperature to form a strong chemical bond without an intermediate layer. DCB provides a robust low-resistance electrical path for power devices, which is advantageous for efficient operation and heat dissipation. It allows for higher power density and improved reliability.

[0054] The chip substrate 202 may include a cooling structure 216 (as FIG. 2B shown), which is disposed within the chip substrate 202, and the semiconductor device 210 and the semiconductor device 212 may be configured to directly contact the cooling structure. The cooling structure 216 may be configured to contain a coolant, which may be supplied to the cooling structure via the cooling inlet 206 and may exit the cooling structure via the cooling outlet 208. The cooling inlet 206 and the cooling outlet 208 may be formed in one or more sides of the chip substrate 202, e.g., as FIG. 2Aas shown. A cooling inlet 206 and a cooling outlet 208 may permit connection of one or more coolant sources ( FIG. 2A not shown). As can be appreciated, the cooling inlet 206 and the cooling outlet 208 may be located at any position on the chip substrate 202 (e.g., the top, bottom, side, etc. of the chip substrate 202). Additionally, although FIG. 2A the cooling inlet 206 and the cooling outlet 208 are shown located on the same side of the chip substrate 202 and adjacent to each other, it can be understood that the inlet 206 and the outlet 208 may be located separately from each other (e.g., as FIG. 2B shown). [[ID=​​​​​​​​​​​​System 200 as shown. System 300 may include a cold plate 302, an inlet 308, and an outlet 310. For example, the cold plate 302 may be similar to the cooling structure 216 shown in FIG. 2. The inlet 308 may be similar to the cooling inlet 206, and the outlet 310 may be similar to the cooling outlet 208, as FIG. 2A-FIG. 2B shown. System 300 may be used to cool a single semiconductor switch and / or a pair of semiconductor devices (e.g., IGBT and diode) during operation.

[0058] As FIG. 3 shown, a semiconductor device 304 (e.g., IGBT) and a semiconductor device 306 (e.g., diode) may be mounted on the cold plate 302. The semiconductor device 304 and the semiconductor device 306 may be connected using a connector 312. The connector 312 may include, for example, bonding wires, clamps, and / or any other type of connector. The connector 312 may be similar to FIG. 1A-FIG. 1B the connectors 120 and / or 126 shown.

[0059] The inlet 308 may be used to allow a coolant (e.g., FIG. 2B the coolant 220 shown) to enter along direction A, as FIG. 3 shown, allow the coolant to travel through the channels of the cold plate 302 towards the outlet 310, and leave the outlet 310 along direction B, as FIG. 3 shown. The travel of the coolant through the cold plate 302 between the inlet 308 and the outlet 310 may allow the semiconductor devices 304 and 306 to be cooled. The inlet 308 and the outlet 310 may be coupled to a coolant source ( FIG. 3 not shown in the figure). The coolant source may cool the liquid and resupply the channels of the cold plate 302 with the cooled coolant for further cooling and / or maintaining the desired operating temperature of the semiconductor devices 304, 306. Alternatively or additionally, the cold plate 302 may be standalone and not include the inlet 308 and / or the outlet 310. The coolant within the cold plate 302 may be kept cooled using any other desired means. As described above, the coolant may include, for example but not limited to, deionized water, ethylene glycol, propylene glycol, mineral oil, and / or any dielectric fluid, and / or any other liquid and / or any combination thereof.

[0060] FIG. 4A Another example cooling system 400 for cooling semiconductor devices (e.g., power semiconductor devices) during operation is shown according to some embodiments of the current subject matter. System 400 may be similar to FIG. 3The system 400 can include a cold plate 402, a cold plate 404, an inlet 414, an outlet 416, and an isolation mechanism 418 connecting an inlet passage 420 and an outlet passage 422. The inlet passage 420 can extend from the inlet 414 through the cold plate 402 to the isolation mechanism 418. The outlet passage 422 can extend from the isolation mechanism 418 through the cold plate 404 to the outlet 416. One or more electrical contacts 410 and 412 can be electrically coupled to the cold plates 402 and 404. For example, the electrical contact 410 can be electrically coupled to the cold plate 402, and the electrical contact 412 can be electrically coupled to the cold plate 404.

[0061] The cold plate 402 and the cold plate 404 can be similar to the cold plate 302. FIG. 3 The inlet 414 can be similar to the inlet 308, and the outlet 416 can be similar to the outlet 310, as FIG. 3 shown. As described above, the system 400 can be used to cool single and / or multiple semiconductor switches and / or pairs of semiconductor devices (e.g., IGBTs and diodes) during operation. The system 400 can allow such semiconductor switches / devices to be cooled from multiple sides. As FIG. 4A shown, the semiconductor device 406 and the semiconductor device 408 can be“sandwiched” between the cold plate 402 and the cold plate 404, thereby enhancing the cooling effect and / or achieving a desired operating temperature of the devices 406, 408. Alternatively or additionally, the semiconductor devices 406, 408 can be positioned on top, bottom, etc. of the cold plates 402 and / or 404, and / or arranged in any desired manner relative to one or both of the cold plates 406, 408.

[0062] Similar to FIG. 3 , the semiconductor device 406 can be an IGBT, and the semiconductor device 408 can be a diode. Both devices can be coupled to the cold plate 402 and the cold plate 404. The electrical contact 410 and / or the electrical contact 412 can be used to connect to the semiconductor device 406 and / or the semiconductor device 408.

[0063] The inlet passage 420 and the outlet passage 422 can be connected using the isolation mechanism 418. The inlet passage 420, the isolation mechanism 418, and the outlet passage 422 can allow a coolant to flow from the inlet 414 through the cold plate 402, the isolation mechanism 418, through the cold plate 404, and to the outlet 416. In particular, the inlet 414 can allow a coolant (e.g., the coolant 220 as FIG. 2B shown) to enter along direction C to allow the coolant to travel through the cold plate 404 toward the inlet passage 420, at which point the coolant can travel through the isolation mechanism 418 along direction E, as FIG. 4AAs shown. The coolant can then continue to pass through the outlet channel 422 in the direction D towards the outlet 416. The coolant traveling between the inlet 414 and the outlet 416 through the cold plates 402 and 404 can allow for "dual" cooling of the semiconductor device 406 and the semiconductor device 404. Similarly, the inlet 414 and the outlet 416 can be connected to a coolant source ( FIG. 4A not shown in the figure). Alternatively or additionally, the system 400 can operate without a coolant source, where the coolant can circulate independently between an inlet point (e.g., defined by the inlet 414) and an outlet point (e.g., defined by the outlet 416). As described above, the coolant can include, for example but not limited to, deionized water, ethylene glycol, propylene glycol, mineral oil, and / or any dielectric fluid, and / or any other liquid and / or any combination thereof.

[0064] As can be understood, the terms "inlet" and "outlet" as used herein are for illustrative purposes only and are not intended to limit the subject matter therein. Thus, the coolant can enter through the outlet and exit through the inlet, and vice versa, thereby allowing the liquid to circulate in any desired direction. In this regard, the direction of liquid flow shown in the figures is again for illustrative purposes only herein and is not intended to limit the current subject matter.

[0065] FIG. 4B Another example cooling system 432 for cooling a semiconductor device (e.g., a power semiconductor device) during operation in accordance with some embodiments of the current subject matter is shown. The system 432 can be similar to FIG. 3 the system 300 shown as well as FIG. 4A the system 400 shown. The system 432 can similarly include cold plates 402 and 404, each of which can be connected to a corresponding inlet / outlet 424, 426, 428, 430. For example, the cold plate 402 can be connected to the inlet / outlets 424 and 426, and the cold plate 404 can be connected to the inlet / outlets 428, 430. Thus, as FIG. 4B shown, each cold plate 402, 404 can be independently connected to one or more coolant sources (same and / or different ( FIG. 4Bcooling fluid can exit through other respective inlet / outlet. For example, for cold plate 402, cooling fluid can be supplied through inlet / outlet 424, can pass through cold plate 402 (as described herein), and can exit through inlet / outlet 426 (and vice versa). A similar arrangement can exist for cold plate 404. Cooling fluid can pass through cold plates 402, 404 in the same direction (e.g., from inlet / outlet 424, 428 to respective inlet / outlet 426, 430) and / or in the opposite direction (e.g., for cold plate 402 from inlet / outlet 424 to inlet / outlet 426, for cold plate 404 from inlet / outlet 430 to inlet / outlet 428, and / or vice versa), as described herein.

[0066] Similar to FIG. 4A System 400, one or more electrical contacts 410 and 412 can be electrically coupled to cold plates 402 and 404. For example, electrical contact 410 can be electrically coupled to cold plate 402, and electrical contact 412 can be electrically coupled to cold plate 404. Cold plate 402 and cold plate 404 can be similar to cold plate 302 as FIG. 3 shown. Further, in some example, non-limiting embodiments, cold plate 402 and cold plate 404 can be galvanically isolated from one another using an isolation mechanism (e.g., isolation mechanism 418 as FIG. 4A shown). Alternatively or additionally, cold plates 402, 404 are separated without the use of an isolation mechanism. Inlet / outlet 424, 426, 428, 430 can be similar to inlet 308 and / or outlet 310 as FIG. 3 shown. Similar to system 400, system 432 can be used to cool single and / or multiple semiconductor switches and / or pairs of semiconductor devices (e.g., IGBTs and diodes) during operation. System 432 likewise can allow for cooling of such semiconductor switches / devices from multiple sides, but in the case of system 432, the cooling plates can be configured to perform cooling independently of one another. In some example, embodiments, one cooling plate can be used as a failsafe cooling device in the event that the other cooling plate fails. Semiconductor devices 406, 408 can be“sandwiched” between and / or positioned on one or both of cold plates 402, 404 and / or positioned in close proximity / adjacent to / to the one or both cold plates in any desired manner. As can be appreciated, any number of semiconductor devices 406, 408 can be positioned on cold plates 402, 404, and / or any number of cold plates 402, 404 can be used (whether connected as FIG. 4A shown, and / or as FIG. 4BThe illustrated cooling plates 402, 404 can be configured to cool one or more semiconductor devices (e.g., IGBTs and / or diodes) and / or to maintain such semiconductor devices at a desired operating temperature (e.g., independently of each other and / or in any combination thereof). This can allow for cooling of multiple semiconductor devices and / or to ensure that such semiconductor devices operate at a desired operating temperature. Further, the cooling plates can be configured to cool only a portion of the semiconductor devices (e.g., among a plurality of semiconductor devices), while other semiconductor devices are not cooled. As can be appreciated, any arrangement of cooling plates and / or semiconductor devices is possible.

[0067] Similar to FIG. 4A The semiconductor devices 406 can be IGBTs and the semiconductor devices 408 can be diodes, and / or vice versa, and / or any other type of semiconductor devices. As discussed herein, the devices 406, 408 can be coupled to the cooling plates 402, 404. The electrical contacts 410 and / or the electrical contacts 412 can be used to connect to the semiconductor devices 406 and / or 408.

[0068] While the cooling plates 402, 404 can be coupled to one or more same / different sources of coolant (same and / or different types of coolant) using respective outlets 424, 426, 428, 430, the system 432 can not use a source of coolant, where the coolant can be independently circulated between the inlet / outlet points (e.g., defined by the inlets / outlets 424, 426 of the cooling plate 402 and the inlets / outlets 428, 430 of the cooling plate 404). As discussed herein, the coolant can include, for example, but not limited to, deionized water, ethylene glycol, propylene glycol, mineral oil, and / or any dielectric fluid, and / or any other liquid and / or any combination thereof.

[0069] FIG. 5 is a top view and corresponding circuit schematic 502 of an example of a cooling system 500 for cooling a plurality of semiconductor devices during operation in accordance with some embodiments of the current subject matter. In particular, the system 500 can be configured to provide cooling and / or desired temperature maintenance for two pairs of semiconductor devices (e.g., pairs of IGBT / diode combinations).

[0070] As FIG. 5As shown, the system 500 can include a chip substrate 504, cold plates 506, 508, an inlet 510 connected to the cold plate 506, an outlet 512 connected to the cold plate 508, an isolation mechanism 514 connected to the cold plate 506 and the cold plate 508. The cold plates 506 and 508 can be positioned on and / or integrated, embedded, bonded, etc. into the chip substrate 504. The inlet 510 can be configured to provide an inlet or port for supplying a coolant to the cold plate 506. The coolant can be circulated through the cold plate 506, then through the isolation mechanism 514 to the cold plate 508. The coolant can then also be circulated through the cold plate 508 and exit through the outlet 512. Both the inlet 510 and the outlet 512 can be used as an entry and / or exit port for the coolant to the cold plates 506, 508. As discussed herein, the inlet 510 and / or the outlet 512 can be coupled to a coolant source, which can maintain the coolant at a desired temperature. Alternatively or additionally, the cold plates 506, 508 can be independent, whereby the coolant can be circulated within and / or between the cold plates 506, 508 and maintained at a desired temperature to allow for direct cooling of the semiconductor devices positioned on the cold plates 506, 508.

[0071] As discussed above, a pair of semiconductor devices can be positioned on each of the cold plates 506, 508. For example, a diode 526 and an IGBT 530 can be positioned on and / or coupled to the cold plate 506. Likewise, a diode 528 and an IGBT 532 can be positioned on and / or coupled to the cold plate 508. The diode 526 can be electrically coupled to the IGBT 530 using a connection 534a. A direct copper bond pad 522 can also be positioned on and / or coupled (e.g., using a DCB process) to the cold plate 506. The IGBT 530 can be electrically coupled to the direct copper bond pad 522 using a connection 534b. The direct copper bond pad 522 can allow for electrical coupling between the two cold plates 506, 508, and thus the pair of semiconductor devices disposed on the respective cold plates. In particular, the direct copper bond pad 522 can be electrically coupled to the cold plate 508 using a connection 536.

[0072] Similar to the arrangement of the cold plate 506, the diode 528 can be electrically coupled to the IGBT 532 using a connection 538a. A direct copper bond pad 524 can also be positioned on and / or coupled (e.g., using a DCB process) to the cold plate 508. The IGBT 532 can be electrically coupled to the direct copper bond pad 524 using a connection 538b. In this case, the direct copper bond pad 524 can include the terminal 518 (e.g., a DC terminal).

[0073] Each cold plate 506 and 508 may include electrical connection terminals to allow semiconductor devices disposed on the cold plates to be electrically coupled to other circuit elements ( FIG. 5 not shown in). These terminals may be similar to terminals 204 (a, b, c, d), as FIG. 2A-FIG. 2B shown. For example, cold plate 506 may include terminal 516 (e.g., DC+ terminal). Cold plate 508 may include terminal 518 (e.g., DC− terminal) and terminal 520 (e.g., AC terminal).

[0074] In addition, the terminals (e.g., gate, collector, emitter) of IGBT devices 524 and 530 may also be coupled to the respective cold plates 506, 508 and / or direct copper bond pads 522, 524. In particular, the collector terminal (C1) of IGBT 530 may be electrically coupled to cold plate 506. The gate terminal (G1) and emitter terminal (E1) of IGBT 530 may be electrically coupled to direct copper bond pad 522. Similarly, the collector terminal (C2) of IGBT 532 may be electrically coupled to cold plate 508. The gate terminal (G2) and emitter terminal (E2) of IGBT 532 may be electrically coupled to direct copper bond pad 524.

[0075] FIG. 5 The circuit schematic diagram 502 shown further illustrates various electrical connections between the semiconductor devices and the terminals. In particular, diode 526 is coupled between the collector C1 and emitter E1 of IGBT 530. The collector C1 of IGBT 530 is coupled to terminal 516 (e.g., DC+ terminal). The emitter E1 of IGBT �30 is coupled to terminal 520 (e.g., AC terminal). Diode 528 is coupled between the collector C2 and emitter E2 of IGBT 532. The collector C2 of IGBT 532 is coupled to terminal 520 (e.g., AC terminal). The emitter E2 of IGBT 532 is coupled to terminal 518 (e.g., DC terminal).

[0076] The arrangement and / or number and / or coupling of the cold plates and / or semiconductor devices provided herein are for illustrative, non-limiting purposes. As can be understood, any type of semiconductor device may be used and / or any type of semiconductor device may be cooled using the FIG. 3-FIG. 5 cooling structure shown. In addition, any number of cold plates and / or arrangements of cold plates may be used for the purpose of cooling semiconductor devices. FIG. 3-FIG. 5

[0077] ​It should be noted that the chip substrate (e.g., chip substrate 504) can integrate, incorporate, contain, and / or be as part of a cold plate and / or have as part of a cold plate (e.g., cold plates 506, 508), each of which can cool one or more semiconductor devices. The cold plate can include one or more enclosed channels (e.g., as shown) that can contain a cooling liquid. The enclosed channels can be formed within the cold plate and / or chip substrate using molding, drilling, 3D printing, 3D metal printing, and / or any other desired technique that can enable advanced internal configurations of the enclosed channels and provide improved heat transfer (i.e., dissipation of heat from the semiconductor devices positioned on the chip substrate). FIG. 2B

[0078] Furthermore, as can be appreciated, the current subject matter can be used in conjunction with any type of semiconductor device, power semiconductor device, thyristor, MOSFET, etc. The coupling of the IGBT and diode can be achieved using at least one of the following: a bond wire, a clip, and / or any other mechanism and / or any combination thereof. Two (or more) semiconductor devices can be cooled by the same cold plate, where the cold plate can be positioned in close proximity to both semiconductor devices. Thus, the same cold plate can be configured to at least partially dissipate heat from one or both of the semiconductor devices and the other semiconductor device during operation of one or both of the semiconductor devices and the other semiconductor device.

[0079] Alternatively or additionally, the other semiconductor device can be cooled by its own cold plate (e.g., diode 526 and IGBT 530 can be cooled using cold plate 506, while diode 528 and IGBT 532 can be cooled using cold plate 508). The cooling liquid can be the same and / or different from the cooling liquid circulated in each cold plate. The cold plates can share an inlet and outlet for the cooling liquid, and / or each plate can have its own inlet and / or outlet.

[0080] In some implementations, the cold plate can be an electrically conductive cold plate. Alternatively or additionally, the cold plate can be a non-conductive cold plate. As can be appreciated, any other type of cold plate can be used.

[0081] The subject systems can advantageously be configured to perform direct liquid cooling of individual and / or multiple semiconductor devices and / or multiple pairs of semiconductor devices. Each semiconductor device and / or each pair of semiconductor devices and / or group / ensemble of semiconductor devices can be cooled by a single and / or multiple cold plates (e.g., one plate can cool one semiconductor device, one plate can cool multiple semiconductor devices, etc.). As can be appreciated, any manner of arranging the cold plates relative to the semiconductor devices is possible.

[0082] ​The components and features of the above-described apparatus can be implemented using any combination of discrete circuits, application specific integrated circuits (ASICs), logic gates, and / or single-chip architectures. Additionally, where appropriate, the features of the apparatus can be implemented using microcontrollers, programmable logic arrays, and / or microprocessors or any combination of the foregoing. It should be noted that hardware, firmware, and / or software elements may be collectively or individually referred to herein as “logic” or “circuitry”.

[0083] It should be understood that the exemplary apparatus shown in the above block diagrams may represent a functional descriptive example of many potential embodiments. Thus, the partitioning, omission, or inclusion of the block functions depicted in the figures does not mean that the hardware components, circuitry, software, and / or elements for implementing these functions must be partitioned, omitted, or included in the embodiments.

[0084] Some embodiments may be described using the phrases “one embodiment” or “an embodiment” or “one implementation” or “some implementations” and derivatives thereof. These terms mean that the particular features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment. The phrase “in one embodiment” (or a derivative thereof) appearing in various places in the specification is not necessarily all referring to the same embodiment. Additionally, unless otherwise stated, the above features are considered to be used in any combination together. Thus, any features discussed separately may be taken together with each other unless it is noted that the features are incompatible with each other.

[0085] It is emphasized that the abstract of the present disclosure is provided to enable a reader to quickly ascertain the nature of the technical disclosure. The abstract is submitted on the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, it can be seen that, for the purpose of streamlining the present disclosure, various features are combined in a single embodiment. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the inventive subject matter lies in less than all of the features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms “comprising” and “wherein” are used as the plain English equivalents of the respective terms “including” and “wherein”. Additionally, the terms “first,” “second,” “third,” etc. are used merely as labels and are not intended to impose numerical requirements on their objects. Further, the use of “including,” “comprising,” or “having” and variations thereof herein means covering the items listed thereafter and their equivalents as well as additional items. Thus, the terms “including,” “comprising,” or “having” and variations thereof are open-ended expressions and may be used interchangeably herein.

[0086] For convenience and clarity, terms such as "top," "bottom," "front," "back," "upper," "lower," "horizontal," "vertical," "side," "lateral," "transverse," "radial," "inner," "outer," "left," and "right," can be used herein to describe the relative positioning and orientation of the various components and features illustrated in the drawings and provided in the following description. These terms are not intended to be limiting, and include words derived from these terms and words of similar import.

[0087] What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and / or methodologies for purposes of describing the aforementioned aspects, but one of ordinary skill in the art will recognize that many further combinations and permutations of the aforementioned aspects are possible. Accordingly, novel architectures are intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0088] In one aspect, a system can include at least one semiconductor device positioned on a chip substrate; and at least one cold plate disposed within the chip substrate and containing a cooling fluid; the at least one cold plate positioned proximate to the at least one semiconductor device and configured to at least partially dissipate heat from the at least one semiconductor device during operation of the at least one semiconductor device using the cooling fluid.

[0089] The system can further include wherein the at least one cold plate includes an enclosed channel containing the cooling fluid.

[0090] The system can further include wherein the enclosed channel includes an inlet and an outlet, wherein the inlet is configured to allow the cooling fluid to flow into the enclosed channel and the outlet is configured to allow the cooling fluid to flow out of the enclosed channel.

[0091] The system can further include wherein the cooling fluid is configured to circulate within the enclosed channel.

[0092] The system can further include at least one other semiconductor device positioned on the chip substrate, the at least one other semiconductor device coupled to the at least one semiconductor device.

[0093] The system can further include wherein the at least one semiconductor device and the at least one other semiconductor device are coupled using at least one of: a bond wire, a clip, and any combination thereof.

[0094] The system can further include wherein the at least one cold plate is positioned proximate to at least one of the at least one semiconductor device and the at least another semiconductor device and is configured to at least partially dissipate heat from at least one of the at least one semiconductor device and the at least another semiconductor device during operation of at least one of the at least one semiconductor device and the at least another semiconductor device.

[0095] The system can further include at least another cold plate disposed within the chip substrate, the at least another cold plate including another enclosed channel containing a cooling fluid; the at least another cold plate positioned proximate to the at least another semiconductor device and configured to at least partially dissipate heat from the at least another semiconductor device during operation of the at least another semiconductor device using the cooling fluid.

[0096] The system can further include wherein the another enclosed channel is not connected to the enclosed channel.

[0097] The system can further include wherein the another enclosed channel is connected to the enclosed channel, wherein the cooling fluid is configured to circulate between the enclosed channel and the another enclosed channel.

[0098] The system can further include wherein the at least one cold plate is positioned below at least one of the at least one semiconductor device and the at least another semiconductor device.

[0099] The system can further include wherein the at least one semiconductor device includes a semiconductor switching device.

[0100] The system can further include wherein the semiconductor switching device includes an insulated gate bipolar transistor.

[0101] The system can further include wherein the at least another semiconductor device is a diode.

[0102] The system can further include wherein the cold plate is an electrically conductive cold plate.

[0103] In one aspect, a system can include a first semiconductor device positioned on a chip substrate; a first cold plate disposed within the chip substrate and containing a first cooling fluid, wherein the first cold plate is positioned proximate to the first semiconductor device and is configured to at least partially dissipate heat from the first semiconductor device during operation of the first semiconductor device using the first cooling fluid; a second semiconductor device positioned on the chip substrate; and a second cold plate disposed within the chip substrate and containing a second cooling fluid, wherein the second cold plate is positioned proximate to the second semiconductor device and is configured to at least partially dissipate heat from the second semiconductor device during operation of the second semiconductor device using the second cooling fluid, wherein the first cold plate is galvanically isolated from the second cold plate using an isolation mechanism.

[0104] The system can also include: wherein the first cold plate includes a first enclosed channel containing a cooling liquid; the second cold plate includes a second enclosed channel containing a cooling liquid; at least one of the first enclosed channel and the second enclosed channel includes an inlet and an outlet, wherein the inlet is configured to allow the cooling liquid to flow into the at least one of the first enclosed channel and the second enclosed channel, and the outlet is configured to allow the cooling liquid to flow out of the at least one of the first enclosed channel and the second enclosed channel; wherein the cooling liquid is configured to circulate within the first enclosed channel and the second enclosed channel.

[0105] The system can also include: wherein the first semiconductor device includes an insulated gate bipolar transistor, and the second semiconductor device is a diode.

[0106] The system can also include: wherein the cold plate is an electrically conductive cold plate.

[0107] In one aspect, a system can include: a first cold plate containing a first cooling liquid, wherein the first cold plate is positioned proximate to a first semiconductor device and is configured to dissipate heat from the first semiconductor device during operation of the first semiconductor device using the first cooling liquid; and a second cold plate containing a second cooling liquid, wherein the second cold plate is positioned proximate to a second semiconductor device and is configured to dissipate heat from the second semiconductor device during operation of the second semiconductor device using the second cooling liquid, wherein the second cold plate is separate from the first cold plate.

[0108] The foregoing description of exemplary embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not with this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application can be directed to the disclosed subject matter in a different manner and generally can include any set of one or more limitations disclosed herein in a different manner or otherwise.

[0109] All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, anterior, posterior, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used only for identification purposes to assist the reader’s understanding of the present disclosure, and do not create limitations, particularly as to the position, orientation, or use of the disclosure. Connection references (e.g., attached, coupled, connected, and joined) are to be construed broadly and will be given their ordinary and accustomed meaning to

[0110] Furthermore, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to connote importance or priority, but are used to distinguish one feature from another. The drawings are for purposes of illustration only and the dimensions, positions, sequences, and relative sizes reflected in the drawings attached hereto can vary.

[0111] The scope of the disclosure is not intended to be limited to the embodiments described herein. Indeed, other various embodiments and modifications thereof, in addition to those described herein, will become apparent to those of ordinary skill in the art from the description and drawings herein. Accordingly, such other embodiments and modifications are intended to fall within the scope of the disclosure. Further, the disclosure has been described herein in the context of particular implementations for particular environments for particular purposes. It will be apparent to those of ordinary skill in the art that the usefulness is not limited to this context and that the disclosure can be beneficially implemented in any number of environments for any number of purposes. Thus, claims expressing the full scope of such disclosure recited herein are intended to be interpreted freely in accordance with the full scope and spirit of the disclosure as described herein.

Claims

1. A system comprising: at least one semiconductor device positioned on a chip substrate; and at least one cold plate disposed within the chip substrate and containing a cooling fluid; the at least one cold plate positioned proximate to the at least one semiconductor device and configured to dissipate heat from the at least one semiconductor device at least partially using the cooling fluid during operation of the at least one semiconductor device. the at least one cold plate comprising an enclosed channel containing the cooling fluid.

2. The system of claim 1, wherein, the enclosed channel comprising an inlet and an outlet, wherein the inlet is configured to allow the cooling fluid to flow into the enclosed channel and the outlet is configured to allow the cooling fluid to flow out of the enclosed channel.

3. The system of claim 2, wherein, the cooling fluid configured to circulate within the enclosed channel.

4. The system of claim 3, wherein, 5. The system of claim 2, further comprising at least one other semiconductor device positioned on the chip substrate, the at least one other semiconductor device coupled to the at least one semiconductor device. the at least one semiconductor device and the at least one other semiconductor device coupled using at least one of: a bond wire, a clip, and any combination thereof.

6. The system of claim 5, wherein, the at least one cold plate positioned proximate to the at least one other semiconductor device and configured to dissipate heat from at least one of the at least one semiconductor device and the at least one other semiconductor device at least partially using the cooling fluid during operation of the at least one of the at least one semiconductor device and the at least one other semiconductor device.

7. The system of claim 5, wherein, 8. The system of claim 5, further comprising at least one other cold plate disposed within the chip substrate, the at least one other cold plate comprising another enclosed channel containing the cooling fluid; the at least one other cold plate positioned proximate to the at least one other semiconductor device and configured to dissipate heat from the at least one other semiconductor device at least partially using the cooling fluid during operation of the at least one other semiconductor device. the another enclosed channel unconnected to the enclosed channel.

9. The system of claim 8, wherein, the another enclosed channel connected to the enclosed channel, wherein the cooling fluid is configured to circulate between the enclosed channel and the another enclosed channel.

10. The system of claim 8, wherein, the at least one cold plate positioned below at least one of the at least one semiconductor device and the at least one other semiconductor device.

11. The system of claim 5, wherein, the at least one semiconductor device comprising a semiconductor switching device.

12. The system of claim 5, wherein, the semiconductor switching device comprising an insulated gate bipolar transistor.

13. The system of claim 12, wherein, the at least one other semiconductor device is a diode.

14. The system of claim 12, wherein, the cold plate is an electrically conductive cold plate.

15. The system of claim 1, wherein, 16. A system comprising: a first semiconductor device positioned on a chip substrate; a first cold plate disposed within the chip substrate and containing a first cooling fluid, wherein the first cold plate is positioned proximate to the first semiconductor device and configured to dissipate heat from the first semiconductor device at least partially using the first cooling fluid during operation of the first semiconductor device; a second semiconductor device positioned on the chip substrate; and a second cold plate disposed within the chip substrate and containing a second cooling fluid, wherein the second cold plate is positioned proximate to the second semiconductor device and configured to dissipate heat from the second semiconductor device at least partially using the second cooling fluid during operation of the second semiconductor device. a second cold plate disposed within the chip substrate and containing a second coolant, wherein the second cold plate is positioned proximate to the second semiconductor device and is configured to at least partially dissipate heat from the second semiconductor device using the second coolant during operation of the second semiconductor device; wherein the first cold plate is galvanically isolated from the second cold plate using an isolation mechanism.

17. The system of claim 16, wherein the first cold plate includes a first enclosed channel containing the coolant; the second cold plate includes a second enclosed channel containing the coolant; At least one of the first enclosed channel and the second enclosed channel includes an inlet and an outlet, wherein, the inlet is configured to allow the coolant to flow into at least one of the first enclosed channel and the second enclosed channel, and the outlet is configured to allow the coolant to flow out of at least one of the first enclosed channel and the second enclosed channel; wherein the coolant is configured to circulate within the first enclosed channel and the second enclosed channel.

18. The system of claim 16, wherein, the first semiconductor device includes an insulated gate bipolar transistor, and the second semiconductor device is a diode.

19. The system of claim 16, wherein, the cold plate is an electrically conductive cold plate.

20. The system of claim 16, wherein, the coolant includes at least one of deionized water, ethylene glycol, propylene glycol, mineral oil, and any combination thereof.

21. A system comprising: a first cold plate containing a first coolant, wherein the first cold plate is positioned proximate to a first semiconductor device and is configured to at least partially dissipate heat from the first semiconductor device using the first coolant during operation of the first semiconductor device; and a second cold plate containing a second coolant, wherein the second cold plate is positioned proximate to a second semiconductor device and is configured to at least partially dissipate heat from the second semiconductor device using the second coolant during operation of the second semiconductor device, wherein the second cold plate is separate from the first cold plate.

Images