Digital filter circuit, filter, method, electronic equipment and storage medium

Abstract

The invention discloses a digital filtering circuit, a filter, a method, electronic equipment and a storage medium, and the circuit comprises a counting module which is used for inputting a sampling clock signal outputted by a modulator, and outputting a clock pulse signal according to the sampling clock signal and a preset oversampling rate; the accumulation module is used for receiving the clock pulse signal, the bit stream signal output by the modulator and the sampling clock signal, performing accumulation operation and down-sampling operation on the bit stream signal based on the clock pulse signal, the sampling clock signal and the target order information, and outputting an integral result signal; and the calculation module is used for receiving the clock pulse signal, the sampling clock signal and the integration result signal, and performing differential operation on the integration result based on the clock pulse signal, the sampling clock signal and the target order information to obtain a target filtering result.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital filter, in particular to a digital filter circuit, a filter, a method, an electronic device and a storage medium. BACKGROUND

[0002] With the continuous upgrading of manufacturing industry, the requirement of high-precision equipment is increasing, and the application scene of servo system is more and more widely. But at the same time, new requirements are put forward for the performance of servo system. As the most important part of servo control system, how to realize fast and accurate current sampling plays a crucial role in improving the performance of servo system. Among many schemes, sigma-delta digital sampling can move the quantization noise from low frequency to high frequency by using oversampling and noise shaping technology. The high frequency signal output by sigma-delta ADC needs to be filtered by a digital filter to obtain a low frequency high precision signal. With the advantages of easy isolation, high precision, anti-interference, good temperature drift performance and so on, it stands out.

[0003] Generally, sigma-delta ADC includes two modules of sigma-delta modulator and digital down-sampling filter. The modulator module needs to oversample and quantize the input signal, and to shape the noise in the passband to reduce the quantization noise in the band and improve the signal-to-noise distortion ratio. Due to the oversampling technology, the output rate of the modulator is very high, which is not suitable for subsequent processing. At the same time, since the quantization noise is moved to the band, a low-pass filter is needed to process the noise. Traditional analog filter is not suitable for working in such a multi-rate system, so digital down-sampling filter becomes the best choice.

[0004] However, in the traditional motor system, the MCU usually does not integrate digital filter peripherals, and because the signal frequency and the sampling frequency are very high, the software processing needs to occupy a lot of software resources. Therefore, the sigma-delta modulator is usually used with FPGA or CPLD, which has the problem of high cost. SUMMARY

[0005] The present application aims to provide a digital filter circuit, a filter, a method, an electronic device and a storage medium, which can reduce the cost of digital filtering.

[0006] In a first aspect, an embodiment of the present application provides a digital filter circuit, comprising:

[0007] A counting module, configured to input a sampling clock signal output by a modulator, and output a clock pulse signal according to the sampling clock signal and a preset oversampling rate;

[0008] an accumulation module, configured to receive the clock pulse signal, a bit stream signal output by the modulator and the sampling clock signal, and perform accumulation operation and down-sampling operation on the bit stream signal based on the clock pulse signal, the sampling clock signal and target order information, and output an integration result signal;

[0009] a calculation module, configured to receive the clock pulse signal, the sampling clock signal and the integration result signal, and perform difference operation on the integration result based on the clock pulse signal, the sampling clock signal and the target order information, and obtain a target filtering result.

[0010] According to some embodiments of the present application, the counting module comprises:

[0011] an OSR counter unit, an input end of the OSR counter unit being connected to the modulator for inputting the sampling clock signal, and output ends of the OSR counter unit being connected to the accumulation module and the calculation module respectively.

[0012] According to some embodiments of the present application, the accumulation module comprises:

[0013] a first adder unit, a first input end of the first adder unit being connected to the modulator for inputting the bit stream signal;

[0014] a first register unit, a data input end of the first register unit being connected to an output end of the first adder unit, and an output end of the first register unit being connected to a second input end of the first adder unit;

[0015] a second adder unit, a first input end of the second adder unit being connected to an output end of the first register unit;

[0016] a first switch unit, a first input end of the first switch unit being connected to an output end of the second adder unit, and a second input end of the first switch unit being connected to an output end of the first adder unit;

[0017] a second register unit, a data input end of the second register unit being connected to an output end of the first switch unit, and an output end of the second register unit being connected to a second input end of the second adder unit;

[0018] a third adder unit, a first input end of the third adder unit being connected to an output end of the second register unit;

[0019] a second switch unit, a first input end of the second switch unit being connected with an output end of the third adder unit, a second input end of the second switch unit being connected with an output end of the first adder unit, and a third input end of the second switch unit being connected with an output end of the second adder unit;

[0020] a third register unit, a data input end of the third register unit being connected with an output end of the second switch unit, and an output end of the third register unit being connected with a second input end of the third adder unit, clock input ends of the first register unit, the second register unit and the third register unit being connected with the modulator for inputting the sampling clock signal;

[0021] a fourth register unit, a data input end of the fourth register unit being connected with an output end of the second switch unit, a clock input end of the fourth register unit being connected with the counting module for inputting the clock pulse signal, and an output end of the fourth register unit being connected with the calculation module.

[0022] According to some embodiments of the present application, the calculation module comprises:

[0023] a fifth register unit, a data input end of the fifth register unit being connected with an output end of the counting module, and a clock input end of the fifth register unit being connected with the modulator for inputting the sampling clock signal;

[0024] a sixth register unit, a data input end of the sixth register unit being connected with an output end of the accumulation module;

[0025] a first value inversion unit, an input end of the value inversion unit being connected with an output end of the sixth register unit;

[0026] a fourth adder unit, a first input end of the fourth adder unit being connected with an output end of the value inversion unit, and a second input end of the fourth adder unit being connected with an output end of the accumulation module;

[0027] a seventh register unit, a data input end of the seventh register unit being connected with an output end of the fourth adder unit;

[0028] a second value inversion unit, an input end of the second value inversion unit being connected with an output end of the seventh register unit;

[0029] a fifth adder unit, a first input end of the fifth adder unit being connected with an output end of the second value inversion unit, and a second input end of the fifth adder unit being connected with an output end of the fourth adder unit;

[0030] a third switch unit, a first input end of the third switch unit being connected with an output end of the fifth adder unit, a second input end of the third switch unit being connected with an output end of the fourth adder unit;

[0031] an eighth register unit, a data input end of the eighth register unit being connected with an output end of the third switch unit;

[0032] a third value negation unit, an input end of the third value negation unit being connected with an output end of the eighth register unit;

[0033] a sixth adder unit, a first input end of the sixth adder unit being connected with an output end of the third value negation unit, a second input end of the sixth adder unit being connected with an output end of the fifth adder unit;

[0034] a fourth switch unit, a first input end of the fourth switch unit being connected with an output end of the sixth adder unit, a second input end of the fourth switch unit being connected with an output end of the fifth adder unit, a third input end of the fourth switch unit being connected with an output end of the fourth adder unit;

[0035] a ninth register unit, a data input end of the ninth register unit being connected with an output end of the fourth switch unit, an output end of the ninth register unit being used for outputting a target filtering result;

[0036] clock input ends of the sixth register unit, the seventh register unit, the eighth register unit and the ninth register unit are all connected with an output end of the fifth register unit.

[0037] In a second aspect, an embodiment of the present application provides a digital filter, comprising the digital filter circuit as described above.

[0038] In a third aspect, an embodiment of the present application provides a filter circuit control method, applied to the digital filter circuit as described above, and the method comprises:

[0039] obtaining target order information;

[0040] if the target order information is first order, controlling a second input end of the first switch unit to be in communication with an output end of the first switch unit, controlling a second input end of the second switch unit to be in communication with an output end of the second switch unit, controlling a second input end of the third switch unit to be in communication with an output end of the third switch unit, and controlling a third input end of the fourth switch unit to be in communication with an output end of the fourth switch unit;

[0041] If the target order information is second order, a first input end of the first switch unit is controlled to be in communication with an output end of the first switch unit, a third input end of the second switch unit is controlled to be in communication with an output end of the second switch unit, a first input end of the third switch unit is controlled to be in communication with an output end of the third switch unit, and a second input end of the fourth switch unit is controlled to be in communication with an output end of the fourth switch unit.

[0042] According to some embodiments of the present application, the method further comprises:

[0043] If the target order information is fast third order;

[0044] a first input end of the first switch unit is controlled to be in communication with an output end of the first switch unit, a third input end of the second switch unit is controlled to be in communication with an output end of the second switch unit, a first input end of the third switch unit is controlled to be in communication with an output end of the third switch unit, and a first input end of the fourth switch unit is controlled to be in communication with an output end of the fourth switch unit.

[0045] According to some embodiments of the present application, the method further comprises:

[0046] If the target order information is third order;

[0047] a first input end of the first switch unit is controlled to be in communication with an output end of the first switch unit, a first input end of the second switch unit is controlled to be in communication with an output end of the second switch unit, a first input end of the third switch unit is controlled to be in communication with an output end of the third switch unit, and a first input end of the fourth switch unit is controlled to be in communication with an output end of the fourth switch unit.

[0048] In a fourth aspect, embodiments of the present application provide an electronic device, comprising:

[0049] at least one processor;

[0050] at least one memory configured to store at least one program;

[0051] When the at least one program is executed by the at least one processor, the filter circuit control method as described above is implemented.

[0052] In a fifth aspect, embodiments of the present application provide a computer readable storage medium, which stores a program executable by a processor, and the program is executed by the processor to implement the filter circuit control method as described above.

[0053] In the embodiment of the present application, the counting module outputs a clock pulse signal according to a sampling clock signal and a preset oversampling rate, the accumulation module performs accumulation operation and downsampling operation on the bit stream signal based on the clock pulse signal, the sampling clock signal and target order information, and outputs an integration result signal, and the calculation module performs difference operation on the integration result based on the clock pulse signal, the sampling clock signal and the target order information, and obtains a target filtering result. Without using FPGA and CPLD, the bit stream signal output by the modulator can be digitally filtered with different orders according to the requirements of different application scenarios, and the cost is reduced.

[0054] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0055] The present application will be further described below in conjunction with the drawings and embodiments, in which:

[0056] Figure 1 A schematic diagram of the digital filtering circuit embodiment provided by the present application is shown in the figure;

[0057] Figure 2 In the digital filtering circuit embodiment provided by the present application, a schematic diagram of the counting module is shown in the figure;

[0058] Figure 3 In the digital filtering circuit embodiment provided by the present application, a schematic diagram of the accumulation module is shown in the figure;

[0059] Figure 4 In the digital filtering circuit embodiment provided by the present application, a schematic diagram of the calculation module is shown in the figure.

[0060] REFERENCE NUMERALS

[0061] Counting module 100, OSR counter unit 110, accumulation module 200, first adder unit 210, first register unit 220, second adder unit 230, first switch unit 240, second register unit 250, third adder unit 260, second switch unit 270, third register unit 280, fourth register unit 290, calculation module 300, fifth register unit 310, sixth register unit 320, first value inversion unit 330, fourth adder unit 340, seventh register unit 350, second value inversion unit 360, fifth adder unit 370, third switch unit 380, eighth register unit 390, third value inversion unit 400, sixth adder unit 410, fourth switch unit 420, ninth register unit 430. DETAILED DESCRIPTION

[0062] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0063] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0064] In the description of this application, "multiple" refers to two or more. The use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or the order in which the technical features are indicated.

[0065] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0066] The following is based on Figures 1 to 4 This application describes a digital filtering circuit, filter, method, electronic device, and storage medium provided in its embodiments.

[0067] This application provides a digital filtering circuit, such as... Figure 1 As shown, it includes:

[0068] The counting module 100 is used to input the sampling clock signal output by the modulator and output a clock pulse signal according to the sampling clock signal and the preset oversampling rate.

[0069] Accumulation module 200 is used to receive clock pulse signal, bit stream signal output by modulator and sampling clock signal, and perform accumulation operation and downsampling operation on bit stream signal based on clock pulse signal, sampling clock signal and target order information, and output integration result signal;

[0070] The calculation module 300 is used to receive clock pulse signals, sampling clock signals and integration result signals, and perform differential operations on the integration result based on the clock pulse signals, sampling clock signals and target order information to obtain the target filtering result.

[0071] In the embodiment of the present application, the counting module 100 outputs a clock pulse signal according to the sampling clock signal and the preset oversampling rate, the accumulation module 200 performs accumulation operation and downsampling operation on the bit stream signal based on the clock pulse signal, the sampling clock signal and the target order information, and outputs an integration result signal, and the calculation module 300 performs difference operation on the integration result based on the clock pulse signal, the sampling clock signal and the target order information, and obtains a target filtering result. Without using FPGA and CPLD, the bit stream signal output by the modulator can be digitally filtered with different orders according to the requirements of different application scenarios, and the cost is reduced.

[0072] In some embodiments of the present application, as shown in Figure 2 the counting module 100 comprises:

[0073] The OSR counter unit 110 is connected to the modulator for inputting the sampling clock signal, and the output end of the OSR counter unit 110 is connected to the accumulation module 200 and the calculation module 300 respectively.

[0074] In the embodiment, the OSR counter unit 110 comprises a configurable 8-bit counter with a counting range of 0-256. The configurable 8-bit counter outputs a clock pulse signal (such as CP_2 in Figure 1 ) when the sampling clock signal (such as CP_1 in Figure 1 ) reaches the configured oversampling rate.

[0075] In some embodiments of the present application, as shown in Figure 3 the accumulation module 200 comprises:

[0076] The first adder unit 210 is connected to the modulator for inputting the bit stream signal;

[0077] The data input end of the first register unit 220 is connected to the output end of the first adder unit 210, and the output end of the first register unit 220 is connected to the second input end of the first adder unit 210;

[0078] The first input end of the second adder unit 230 is connected to the output end of the first register unit 220;

[0079] The first input end of the first switch unit 240 is connected to the output end of the second adder unit 230, and the second input end of the first switch unit 240 is connected to the output end of the first adder unit 210;

[0080] The data input end of the second register unit 250 is connected to the output end of the first switch unit 240, and the output end of the second register unit 250 is connected to the second input end of the second adder unit 230;

[0081] The first input end of the third adder unit 260 is connected to the output end of the second register unit 250.

[0082] The second switch unit 270 has a first input end connected to the output end of the third adder unit 260, a second input end connected to the output end of the first adder unit 210, and a third input end connected to the output end of the second adder unit 230.

[0083] The data input end of the third register unit 280 is connected to the output end of the second switch unit 270, and the output end of the third register unit 280 is connected to the second input end of the third adder unit 260. The clock input ends of the first register unit 220, the second register unit 250 and the third register unit 280 are connected to the modulator for inputting a sampling clock signal.

[0084] The data input end of the fourth register unit 290 is connected to the output end of the second switch unit 270, the clock input end of the fourth register unit 290 is connected to the counting module 100 for inputting a clock pulse signal, and the output end of the fourth register unit 290 is connected to the calculation module 300.

[0085] In the embodiment, by controlling the first switch unit 240 and the second switch unit 270 to be in different conduction states, different order accumulation operations and down-sampling operations can be realized on the bit stream signal, and the integral result signal is output through the fourth register unit 290.

[0086] In some embodiments of the present application, the first adder unit 210, the second adder unit 230 and the third adder unit 260 in the accumulation module 200 all adopt 26-bit adders. The first register unit 220, the second register unit 250, the third register unit 280 and the fourth register unit 290 all adopt register groups. The first switch unit 240 and the second switch unit 270 all adopt multi-way selectors.

[0087] In some embodiments of the present application, as shown in Figure 4 The calculation module 300 includes:

[0088] A fifth register unit 310, a data input terminal of the fifth register unit 310 is connected to an output terminal of the counting module 100, and a clock input terminal of the fifth register unit 310 is connected to the modulator for inputting a sampling clock signal;

[0089] A sixth register unit 320, a data input terminal of the sixth register unit 320 is connected to an output terminal of the accumulating module 200;

[0090] A first value inversion unit 330, an input terminal of the value inversion unit is connected to an output terminal of the sixth register unit 320;

[0091] A fourth adder unit 340, a first input terminal of the fourth adder unit 340 is connected to an output terminal of the value inversion unit, and a second input terminal of the fourth adder unit 340 is connected to an output terminal of the accumulating module 200;

[0092] A seventh register unit 350, a data input terminal of the seventh register unit 350 is connected to an output terminal of the fourth adder unit 340;

[0093] A second value inversion unit 360, an input terminal of the second value inversion unit 360 is connected to an output terminal of the seventh register unit 350;

[0094] A fifth adder unit 370, a first input terminal of the fifth adder unit 370 is connected to an output terminal of the second value inversion unit 360, and a second input terminal of the fifth adder unit 370 is connected to an output terminal of the fourth adder unit 340;

[0095] A third switch unit 380, a first input terminal of the third switch unit 380 is connected to an output terminal of the fifth adder unit 370, and a second input terminal of the third switch unit 380 is connected to an output terminal of the fourth adder unit 340;

[0096] An eighth register unit 390, a data input terminal of the eighth register unit 390 is connected to an output terminal of the third switch unit 380;

[0097] A third value inversion unit 400, an input terminal of the third value inversion unit 400 is connected to an output terminal of the eighth register unit 390;

[0098] A sixth adder unit 410, a first input terminal of the sixth adder unit 410 is connected to an output terminal of the third value inversion unit 400, and a second input terminal of the sixth adder unit 410 is connected to an output terminal of the fifth adder unit 370;

[0099] The first input end of the fourth switch unit 420 is connected with the output end of the sixth adder unit 410, the second input end of the fourth switch unit 420 is connected with the output end of the fifth adder unit 370, and the third input end of the fourth switch unit 420 is connected with the output end of the fourth adder unit 340;

[0100] The data input end of the ninth register unit 430 is connected with the output end of the fourth switch unit 420, and the output end of the ninth register unit 430 is used for outputting the target filtering result.

[0101] The clock input ends of the sixth register unit 320, the seventh register unit 350, the eighth register unit 390 and the ninth register unit 430 are all connected with the output end of the fifth register unit 310.

[0102] In the embodiment, by controlling the conduction states of the third switch unit 380 and the fourth switch unit 420, the differential operation of different orders can be realized, and the target filtering result is outputted through the ninth register unit 430.

[0103] In some embodiments of the application, the sixth register unit 320, the seventh register unit 350, the eighth register unit 390 and the ninth register unit 430 all adopt 26-bit registers, and the fourth adder unit 340, the fifth adder unit 370 and the sixth adder unit 410 all adopt 26-bit adders. The first value inversion unit 330 and the second value inversion unit 360 both adopt value inversion circuits which invert the input bit by bit and add one.

[0104] In addition, the embodiment of the application provides a filtering circuit control method, which is applied to the digital filtering circuit as described above, and the method comprises the steps of:

[0105] Step S100: obtaining target order information;

[0106] Step S200: if the target order information is one order, controlling the second input end of the first switch unit 240 to be in communication with the output end of the first switch unit 240, controlling the second input end of the second switch unit 270 to be in communication with the output end of the second switch unit 270, controlling the second input end of the third switch unit 380 to be in communication with the output end of the third switch unit 380, and controlling the third input end of the fourth switch unit 420 to be in communication with the output end of the fourth switch unit 420;

[0107] Step S300: If the target order information is second order, the first input end of the first switch unit 240 is communicated with the output end of the first switch unit 240, the third input end of the second switch unit 270 is communicated with the output end of the second switch unit 270, the first input end of the third switch unit 380 is communicated with the output end of the third switch unit 380, and the second input end of the fourth switch unit 420 is communicated with the output end of the fourth switch unit 420 are controlled.

[0108] In the embodiment, when the target order information is first order, the digital filter circuit executes Sinc1 algorithm, and the specific algorithm expression is as follows:

[0109]

[0110] wherein, A0=0, n is a natural number, A n is the output value of the first adder unit 210 at the n-th sampling clock signal time, that is, the first adder unit 210 is delayed by one unit through the first register unit 220, the first adder unit 210 accumulates the input bit stream signal, and the first adder unit 210 and the first register unit 220 jointly realize first order accumulation operation.

[0111] a n =A n-1 ;

[0112] wherein, a0=0, A n-1 is the output value of the first adder unit 210 at the n-1-th sampling clock signal time, a n is the output value of the first register unit 220 at the n-th sampling clock signal time.

[0113] b n =A n-1 ;

[0114] wherein, b0=0, b n is the output value of the second register unit 250 at the n-th sampling clock signal time.

[0115] d n =A n-1 ;

[0116] wherein, d0=0, d n is the output value of the third register unit 280 at the n-th sampling clock signal time.

[0117] R n =A (m*OSR-1) ;

[0118] wherein, m=n / OSR, OSR is oversampling rate, R nThe output value of the fourth register unit 290 at the n th sampling clock signal time is output, that is, a first-order down-sampling operation is performed to obtain an integral result signal.

[0119] e n n-1 ;

[0120] wherein e0=0, e n The output value of the sixth register unit 320 at the n th sampling clock signal time.

[0121] E n n n :

[0122] wherein E n The output value of the fourth adder unit 340 at the n th sampling clock signal time.

[0123] The sixth register unit 320 and the fourth adder unit 340 delay the integral result signal by one unit and perform a first-order difference operation.

[0124] h n (m*OSR) ;

[0125] wherein m=n / OSR, h n The output value of the ninth register unit 430 at the n th sampling clock signal time, that is, a target filtering result. When the Sinc1 algorithm is selected, the order of the digital filtering circuit is one order, and thus the first valid value of h n appears at the OSR+1 th time.

[0126] When the target order information is two orders, the digital filtering circuit executes the Sinc2 algorithm, and the specific algorithm expression is as follows:

[0127]

[0128] wherein A0=0, n is a natural number, and A n The output value of the first adder unit 210 at the n th sampling clock signal time, that is, a first-order accumulation operation is performed on the input bit stream signal by delaying one unit through the first register unit 220.

[0129] a n n-1 ;

[0130] wherein a0=0, A n-1 ​​​​​is the output value of the first adder unit 210 at the n-1th sampling clock signal moment, a n is the output value of the first register unit 220 at the n th sampling clock signal moment.

[0131]

[0132] wherein B0=0, B n is the output value of the second adder unit 230 at the n th sampling clock signal moment, that is, the second adder unit 230 performs a second-order accumulation operation on the bit stream signal by delaying one unit through the second register unit 250.

[0133] b n = B n-1 ;

[0134] wherein b0=0.

[0135] d n = B n-1 ;

[0136] wherein d0=0.

[0137] R n = B (m*OSR-1) ;

[0138] wherein m=n / OSR, R n is the output value of the fourth register unit 290 at the n th sampling clock signal moment, that is, a first-order down-sampling operation is performed.

[0139] e n = R n-1 ;

[0140] wherein e0=0.

[0141] E n = R n -e n ;

[0142] The sixth register unit 320 and the fourth adder unit 340 delay the integral result signal by one unit and perform a first-order difference operation.

[0143] f n = E (m*OSR) ;

[0144] wherein f n is the output value of the seventh register unit 350 at the n th sampling clock signal moment.

[0145] F n = E n -f n ;

[0146] wherein, F n is the output value of the fifth adder unit 370 at the n th sampling clock signal time, that is, the integral result signal output by the accumulation module 200 is subjected to a second-order down-sampling operation and a second-order difference operation.

[0147] h n =F (m*OSR) ;

[0148] wherein, h n is the output value of the ninth register unit 430 at the n th sampling clock signal time, that is, the target filtering result, when the Sinc2 algorithm is selected, the order of the digital filtering circuit is two, therefore, starting from the 0 th time, the first valid value of h n appears at the 2*OSR+1 th time.

[0149] In some embodiments of the present application, the method further comprises:

[0150] Step S400: if the target order information is fast three orders;

[0151] Step S500: control the first input end of the first switch unit 240 to be in communication with the output end of the first switch unit 240, and control the third input end of the second switch unit 270 to be in communication with the output end of the second switch unit 270, and control the first input end of the third switch unit 380 to be in communication with the output end of the third switch unit 380, and control the first input end of the fourth switch unit 420 to be in communication with the output end of the fourth switch unit 420.

[0152] In the present embodiment, when the target order information is fast three orders, the digital filtering circuit executes the SincFast algorithm, and the specific algorithm expression is as follows:

[0153]

[0154] wherein, A0=0, n is a natural number, A n is the output value of the first adder unit 210 at the n th sampling clock signal time, that is, through the first register unit 220, the first adder unit 210 delays one unit, and the first adder unit 210 accumulates the input bit stream signal, and the first adder unit 210 and the first register unit 220 jointly realize a first-order accumulation operation.

[0155] a n =A n-1 ;

[0156] wherein, a0=0.

[0157]

[0158] wherein B0= 0, B n is the output value of the second adder unit 230 at the n-th sampling clock signal time, that is, delayed by one unit through the second register unit 250, and the second adder unit 230 performs a second-order accumulation operation on the bit stream signal.

[0159] b n = B n-1 ;

[0160] wherein b0= 0.

[0161] d n = B n-1 ;

[0162] wherein d0= 0.

[0163] R n = B (m*OSR-1) ;

[0164] wherein m = integer part of n / OSR, R n is the output value of the fourth register unit 290 at the n-th sampling clock signal time, that is, a first-order down-sampling operation is performed.

[0165] e n = R n-1 ;

[0166] wherein e0= 0.

[0167] E n = R n - e n ;

[0168] The sixth register unit 320 and the fourth adder unit 340 delay the integration result signal by one unit and perform a first-order difference operation.

[0169] f n = E (m*OSR) ;

[0170] wherein f n is the output value of the seventh register unit 350 at the n-th sampling clock signal time.

[0171] F n = E n - f n ;

[0172] wherein F n is the output value of the fifth adder unit 370 at the n-th sampling clock signal time, that is, a second-order down-sampling operation is performed on the integration result signal output by the accumulation module 200, and a second-order difference operation is performed.

[0173] g n = F (m*OsR) ;

[0174] wherein, g n is an output value of the eighth register unit 390 at the n th sampling clock signal moment.

[0175] G n = F n -g n ;

[0176] wherein, G n is an output value of the sixth adder unit 410 at the n th sampling clock signal moment.

[0177] The eighth register unit 390 and the sixth adder unit 410 perform a third-order down-sampling operation on the integral result signal output by the accumulation module 200, and perform a third-order difference operation.

[0178] h n = G (m*OSR) ;

[0179] wherein, h n is an output value of the ninth register unit 430 at the n th sampling clock signal moment, that is, a target filtering result, when the SincFast algorithm is selected, the order of the digital filtering circuit is three, therefore, from the 0 moment, the first valid value of h n appears at the 3*OSR+1 moment.

[0180] In some embodiments of the present application, the method further comprises:

[0181] Step S600: if the target order information is three;

[0182] Step S700: control the first input end of the first switch unit 240 to be in communication with the output end of the first switch unit 240, and control the first input end of the second switch unit 270 to be in communication with the output end of the second switch unit 270, and control the first input end of the third switch unit 380 to be in communication with the output end of the third switch unit 380, and control the first input end of the fourth switch unit 420 to be in communication with the output end of the fourth switch unit 420.

[0183] In the case where the target order information is three, the digital filtering circuit can also perform the Sinc3 algorithm, and the specific algorithm expression is as follows:

[0184]

[0185] wherein, A0=0, n is a natural number, and A nThe output value of the first adder unit 210 at the n th sampling clock signal time, that is, delayed by one unit through the first register unit 220, the first adder unit 210 accumulates the input bit stream signal, and the first adder unit 210 and the first register unit 220 jointly realize a first-order accumulation operation.

[0186] a n = A n-1 ;

[0187] Wherein, a0=0.

[0188]

[0189] Wherein, B0=0, B n The output value of the second adder unit 230 at the n th sampling clock signal time, that is, delayed by one unit through the second register unit 250, the second adder unit 230 performs a second-order accumulation operation on the bit stream signal.

[0190] b n =B n-1 ;

[0191] Wherein, b0=0.

[0192]

[0193] d n =D n-1 ;

[0194] Wherein, D0=0, d0=0, D n The output value of the third adder unit 260 at the n th sampling clock signal time.

[0195] The third adder unit 260 and the third register unit 280 perform a third-order accumulation operation on the bit stream signal, delayed by one unit through the third register unit 280, and the third adder unit 260 accumulates.

[0196] R n =D (m*OSR-1) ;

[0197] Wherein, R n The output value of the fourth register unit 290 at the n th sampling clock signal time, that is, a first-order down-sampling operation.

[0198] e n =R n-1 ;

[0199] Wherein, e0=0.

[0200] E n =Rn -e n ;

[0201] The sixth register unit 320 and the fourth adder unit 340 delay the integral result signal by one unit and perform a first-order difference operation.

[0202] f n = E (m*OSR) ;

[0203] Wherein, f n is the output value of the seventh register unit 350 at the n-th sampling clock signal moment.

[0204] F n = E n -f n ;

[0205] Wherein, F n is the output value of the fifth adder unit 370 at the n-th sampling clock signal moment, that is, a second-order down-sampling operation is performed on the integral result signal output by the accumulation module 200, and a second-order difference operation is performed.

[0206] g n = F (m*OSR) ;

[0207] Wherein, g n is the output value of the eighth register unit 390 at the n-th sampling clock signal moment.

[0208] G n = F n -g n ;

[0209] Wherein, G n is the output value of the sixth adder unit 410 at the n-th sampling clock signal moment.

[0210] The eighth register unit 390 and the sixth adder unit 410 perform a third-order down-sampling operation on the integral result signal output by the accumulation module 200, and perform a third-order difference operation.

[0211] h n = G (m*OSR) ;

[0212] Wherein, h n is the output value of the ninth register unit 430 at the n-th sampling clock signal moment, that is, the target filtering result, when the Sinc3 algorithm is selected, the order of the digital filtering circuit is three, therefore, from the 0 moment, the first valid value of h n appears at the 3*OSR+1 moment.

[0213] In addition, the embodiment of the present application provides a digital filter, comprising the digital filter circuit as described above.

[0214] The digital filter provided by the embodiment of the present application can realize the processes realized by the circuit embodiment and achieve the same beneficial effects. To avoid repetition, details are not described herein.

[0215] In addition, the embodiment of the present application provides an electronic device, comprising:

[0216] at least one processor;

[0217] at least one memory for storing at least one program;

[0218] The at least one program is executed by the at least one processor to implement the filter circuit control method as described above.

[0219] The electronic device provided by the embodiment of the present application can realize the processes realized by the method embodiment and achieve the same beneficial effects. To avoid repetition, details are not described herein.

[0220] In addition, the embodiment of the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a program executable by a processor, and the program executable by the processor is executed by the processor to implement the filter circuit control method as described above.

[0221] The computer readable storage medium provided by the embodiment of the present application can realize the processes realized by the method embodiment and achieve the same beneficial effects. To avoid repetition, details are not described herein.

[0222] The embodiments of the present application are described in detail above in combination with the drawings, but the present application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the purpose of the present application.

Claims

1. A digital filter circuit, characterized by, The application relates to a filter device for a digital signal, which comprises: a counting module for inputting a sampling clock signal of a modulator output and outputting a clock pulse signal according to the sampling clock signal and a preset oversampling rate; an accumulation module for receiving the clock pulse signal, a bit stream signal of the modulator output and the sampling clock signal, and performing accumulation operation and down-sampling operation on the bit stream signal based on the clock pulse signal, the sampling clock signal and target order information, and outputting an integration result signal; a calculation module for receiving the clock pulse signal, the sampling clock signal and the integration result signal, and performing difference operation on the integration result based on the clock pulse signal, the sampling clock signal and the target order information, so as to obtain a target filtering result.

2. The digital filter circuit of claim 1, wherein, The counting module comprises: an OSR counter unit, the input end of which is connected with the modulator for inputting the sampling clock signal, and the output end of which is connected with the accumulation module and the calculation module.

3. The digital filter circuit of claim 1, wherein, The accumulation module comprises: a first adder unit, the first input end of which is connected with the modulator for inputting the bit stream signal; a first register unit, the data input end of which is connected with the output end of the first adder unit, and the output end of which is connected with the second input end of the first adder unit; a second adder unit, the first input end of which is connected with the output end of the first register unit; a first switch unit, the first input end of which is connected with the output end of the second adder unit, and the second input end of which is connected with the output end of the first adder unit; a second register unit, the data input end of which is connected with the output end of the first switch unit, and the output end of which is connected with the second input end of the second adder unit; a third adder unit, the first input end of which is connected with the output end of the second register unit; a second switch unit, the first input end of which is connected with the output end of the third adder unit, the second input end of which is connected with the output end of the first adder unit, and the third input end of which is connected with the output end of the second adder unit; a third register unit, the data input end of which is connected with the output end of the second switch unit, and the output end of which is connected with the second input end of the third adder unit; the clock input ends of the first register unit, the second register unit and the third register unit are connected with the modulator for inputting the sampling clock signal. a fourth register unit, a data input terminal of the fourth register unit being connected to an output terminal of the second switch unit, a clock input terminal of the fourth register unit being connected to the counting module for inputting the clock pulse signal, and an output terminal of the fourth register unit being connected to the calculating module.

4. The digital filter circuit according to any one of claims 1 to 3, characterized by The calculating module comprises: a fifth register unit, a data input terminal of the fifth register unit being connected to an output terminal of the counting module, a clock input terminal of the fifth register unit being connected to the modulator for inputting the sampling clock signal; a sixth register unit, a data input terminal of the sixth register unit being connected to an output terminal of the accumulating module; a first value inversion unit, an input terminal of the value inversion unit being connected to an output terminal of the sixth register unit; a fourth adder unit, a first input terminal of the fourth adder unit being connected to an output terminal of the value inversion unit, and a second input terminal of the fourth adder unit being connected to an output terminal of the accumulating module; a seventh register unit, a data input terminal of the seventh register unit being connected to an output terminal of the fourth adder unit; a second value inversion unit, an input terminal of the second value inversion unit being connected to an output terminal of the seventh register unit; a fifth adder unit, a first input terminal of the fifth adder unit being connected to an output terminal of the second value inversion unit, and a second input terminal of the fifth adder unit being connected to an output terminal of the fourth adder unit; a third switch unit, a first input terminal of the third switch unit being connected to an output terminal of the fifth adder unit, and a second input terminal of the third switch unit being connected to an output terminal of the fourth adder unit; an eighth register unit, a data input terminal of the eighth register unit being connected to an output terminal of the third switch unit; a third value inversion unit, an input terminal of the third value inversion unit being connected to an output terminal of the eighth register unit; a sixth adder unit, a first input terminal of the sixth adder unit being connected to an output terminal of the third value inversion unit, and a second input terminal of the sixth adder unit being connected to an output terminal of the fifth adder unit; a fourth switch unit, a first input terminal of the fourth switch unit being connected to an output terminal of the sixth adder unit, a second input terminal of the fourth switch unit being connected to an output terminal of the fifth adder unit, and a third input terminal of the fourth switch unit being connected to an output terminal of the fourth adder unit; a ninth register unit, a data input terminal of the ninth register unit being connected to an output terminal of the fourth switch unit, and an output terminal of the ninth register unit being used for outputting a target filtering result. Clock input terminals of the sixth register unit, the seventh register unit, the eighth register unit and the ninth register unit are all connected to an output terminal of the fifth register unit.

5. A digital filter characterized by, The digital filtering circuit comprises the digital filtering circuit as claimed in claim 4.

6. A filter circuit control method characterized by, The method is applied to the digital filtering circuit as claimed in claim 4, and the method comprises: obtaining target order information; if the target order information is one order, controlling the second input end of the first switch unit to be in communication with the output end of the first switch unit, and controlling the second input end of the second switch unit to be in communication with the output end of the second switch unit, and controlling the second input end of the third switch unit to be in communication with the output end of the third switch unit, and controlling the third input end of the fourth switch unit to be in communication with the output end of the fourth switch unit; if the target order information is two orders, controlling the first input end of the first switch unit to be in communication with the output end of the first switch unit, and controlling the third input end of the second switch unit to be in communication with the output end of the second switch unit, and controlling the first input end of the third switch unit to be in communication with the output end of the third switch unit, and controlling the second input end of the fourth switch unit to be in communication with the output end of the fourth switch unit.

7. The filter circuit control method according to claim 6, wherein The method further comprises: if the target order information is fast three orders; controlling the first input end of the first switch unit to be in communication with the output end of the first switch unit, and controlling the third input end of the second switch unit to be in communication with the output end of the second switch unit, and controlling the first input end of the third switch unit to be in communication with the output end of the third switch unit, and controlling the first input end of the fourth switch unit to be in communication with the output end of the fourth switch unit.

8. The filter circuit control method according to claim 6, wherein The method further comprises: if the target order information is three orders; controlling the first input end of the first switch unit to be in communication with the output end of the first switch unit, and controlling the first input end of the second switch unit to be in communication with the output end of the second switch unit, and controlling the first input end of the third switch unit to be in communication with the output end of the third switch unit, and controlling the first input end of the fourth switch unit to be in communication with the output end of the fourth switch unit.

9. An electronic device, comprising: comprise: at least one processor; at least one memory for storing at least one program; when at least one of the programs is executed by the at least one processor, the filter circuit control method according to claim 6 is implemented.

10. A computer-readable storage medium, characterized in that, wherein the processor executable program is stored, and the processor executable program is executed by the processor to implement the filter circuit control method according to claim 6. wherein the processor executable program is stored, and the processor executable program is executed by the processor to implement the filter circuit control method according to claim 6.

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