Method and system for realizing mixed-precision low-resource digital control oscillator based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, specifically to a method and system for implementing a mixed-precision, low-resource digitally controlled oscillator based on FPGA. Background Technology

[0002] The digitally controlled oscillator (NCO) is the core module of a signal generator. It generates sine / cosine waves with adjustable frequency and phase through a phase accumulator and a waveform lookup table (LUT). It is widely used in communication, radar, measurement and control and other fields.

[0003] In FPGA implementations, the performance of NCOs is limited by three key technical bottlenecks:

[0004] Traditional full-precision phase accumulators (such as 32-bit unified accumulators) guarantee frequency resolution, but they do not distinguish between the main frequency control and dynamic compensation requirements, resulting in wasted logic resources and difficulty in timing convergence (critical path delay increases with bit width).

[0005] While symmetry-based ROM compression techniques (such as storing only the 0~π / 2 interval) reduce storage requirements, they rely on linear interpolation compensation, which leads to discontinuities in the second derivative and cannot effectively suppress high-frequency spurious signals.

[0006] Schemes that rely solely on distributed RAM (low latency) or block RAM (large capacity) fail to dynamically allocate storage resources based on frequency characteristics, resulting in high access latency in high-frequency scenarios and resource waste in low-frequency scenarios. Summary of the Invention

[0007] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the objective of this invention is to propose a method and system for implementing a hybrid precision, low-resource digitally controlled oscillator based on FPGA, in order to achieve efficient resource utilization.

[0008] To achieve the above objectives, a first aspect of the present invention proposes a method for implementing a hybrid precision low-resource digitally controlled oscillator based on FPGA, comprising the following steps:

[0009] The 32-bit phase accumulator is divided into a high-order 24-bit main frequency control segment and a low-order 8-bit dynamic compensation segment. Phase accumulation is performed in parallel through a dual carry chain. The high-order segment receives the high 24 bits of the frequency tuning word FTW to control the main frequency, and the low-order segment receives the low 8 bits of FTW and adds the overflow remainder to dynamically compensate for the phase error.

[0010] Based on the target signal frequency and the system clock frequency Through frequency threshold The system dynamically divides high-frequency and low-frequency bands. High-frequency waveform data is stored in distributed RAM to reduce access latency, while low-frequency data is stored in Block RAM to conserve resources. For distributed RAM address width;

[0011] In the phase transition interval, cubic spline interpolation or adaptive piecewise polynomial fitting algorithm is used. By pre-storing the node amplitude, first derivative and second derivative values, the polynomial function is calculated in parallel by the FPGA DSP module to compensate for waveform distortion.

[0012] The phase offset is calculated in real time during frequency switching and injected into the phase accumulator. At the same time, when the phase overflows, the remainder is retained and passed to the next cycle for accumulation to ensure phase continuity.

[0013] In some embodiments of the present invention, the high-order 24-bit main frequency control segment and the low-order 8-bit dynamic compensation segment optimize the logic delay through carry chain. The high-order segment accumulation result is used to determine the main address of the waveform lookup table, and the low-order segment accumulation result is used to generate the local offset of the interpolation calculation. Together, they constitute a 32-bit phase value.

[0014] In some embodiments of the present invention: the high-frequency band ( Distributed RAM is used to store high-bit phase quantization data in the range of 0 to π / 2, and full-cycle waveforms are generated through hardware symmetry mapping.

[0015] The low frequency band ( It uses Block RAM to store full-precision data in the range of 0 to π / 2, and divides the range into sub-intervals every π / 8 to store fundamental frequency data and second harmonic compensation coefficients.

[0016] In some embodiments of the present invention, the cubic spline interpolation algorithm pre-stores the amplitude of each node. First derivative and second derivative Through a cubic polynomial:

[0017] Calculate the interpolation point magnitude, where, It is uniquely determined by the node parameters.

[0018] In some embodiments of the present invention, when the phase accumulation result When the overflow flag is triggered, the remainder is retained. The initial phase of the next cycle is ;

[0019] During frequency switching, the phase increment difference is calculated based on the old and new FTW and injected into the accumulator to achieve glitch-free switching with a switching time of <10ns.

[0020] To achieve the above objectives, a second aspect of the present invention provides a hybrid precision low-resource digitally controlled oscillator system based on an FPGA, comprising:

[0021] Mixed-precision phase accumulation module: includes a high-order 24-bit accumulator and a low-order 8-bit compensator, which respectively receive the high 24 bits and low 8 bits of the frequency tuning word FTW, and generate a 32-bit phase value through parallel accumulation via a dual carry chain. The dual carry chain refers to the parallel carry logic based on the dedicated carry chain resources of the FPGA, which is used for independent accumulation of the high-order and low-order segments.

[0022] Hierarchical storage module: integrates distributed RAM and Block RAM, and dynamically schedules high-frequency and low-frequency data access through a frequency monitoring unit. The high-frequency segment uses folded address mapping, and the low-frequency segment uses segmented index storage.

[0023] Waveform reconstruction module: includes phase jump detection unit, interpolation calculation unit and symmetry mapping unit, supports cubic spline interpolation or adaptive piecewise polynomial fitting, and uses FPGA DSP module to calculate amplitude in parallel;

[0024] Phase compensation module: Includes an overflow remainder register and a phase offset injection unit to ensure phase continuity during frequency switching.

[0025] In some embodiments of the present invention, the dynamic scheduling logic of the hierarchical storage module is as follows:

[0026] The frequency monitoring unit compares the current output frequency with the preset threshold in real time. If the current frequency Then the memory access address will be pointed to a predefined address in the distributed RAM. And read the corresponding waveform data. ;

[0027] Otherwise, point the address to a predefined address in the Block RAM. And read the corresponding waveform data. .

[0028] In some embodiments of the present invention, the adaptive piecewise polynomial fitting algorithm is based on curvature. Dynamically adjust the segment granularity, where:

[0029] The high curvature region was fitted with a fourth-order polynomial with a segment interval Δφ=π / 128;

[0030] The low curvature region is fitted with a quadratic polynomial with a segment interval Δφ=π / 32.

[0031] In some embodiments of the present invention, the mixed-precision phase accumulation module supports dynamic switching of multiple waveforms, stores waveform data of sine waves, cosine waves and square waves through Block RAM, and adapts the symmetry and amplitude characteristics of different waveforms using phase mapping logic.

[0032] In some embodiments of the present invention, any one or more of AD are also included:

[0033] A. Hardware verification module: Real-time monitoring of Block RAM access conflicts and temporary storage of conflict addresses; Simultaneously, comparison of the theoretical and actual outputs of the phase accumulator; Dynamic calibration of the quantization error in the low-order compensation segment to ensure that the total harmonic distortion (THD) of the output signal is <0.1%.

[0034] B. Temperature / Voltage Adaptive Adjustment Module: Dynamically adjusts the storage partitioning threshold based on the real-time temperature and voltage of the FPGA. and parallelism parameters;

[0035] C. Multi-rate waveform generation module, which supports the output of two different rate signals from the same NCO core by sharing storage resources through time-division multiplexing;

[0036] D. On-chip verification IP module, which monitors BRAM access conflicts and phase accumulator errors in real time and dynamically calibrates compensation values.

[0037] To achieve the above objectives, a third aspect of the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory. When the computer program is executed by the processor, it implements the above-described method for implementing a mixed-precision low-resource digitally controlled oscillator based on an FPGA.

[0038] The present invention relates to a method and system for implementing a mixed-precision, low-resource digitally controlled oscillator based on FPGA. Through the synergistic innovation of mixed-precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction, and dynamic phase compensation, it systematically solves the core problems of traditional NCOs in terms of resource consumption, phase continuity, waveform accuracy, and timing performance, providing a reliable solution for implementing high-precision, low-resource digitally controlled oscillators on FPGA. Attached Figure Description

[0039] The disclosure of this invention is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this invention. In the drawings, the same reference numerals are used to refer to the same parts. Wherein:

[0040] Figure 1 This is a flowchart illustrating the implementation method of a hybrid precision low-resource digitally controlled oscillator based on FPGA provided by the present invention.

[0041] Figure 2 This is a schematic diagram of the phase error curve in the FPGA-based hybrid precision low-resource digital control oscillator implementation method provided by the present invention;

[0042] Figure 3 This is a schematic diagram comparing the storage resource usage in the FPGA-based hybrid precision low-resource digital control oscillator implementation method provided by the present invention.

[0043] Figure 4 This is a schematic diagram of the memory access latency comparison curve in the FPGA-based hybrid precision low-resource digital control oscillator implementation method provided by the present invention.

[0044] Figure 5 This is a schematic diagram of the time-domain waveform in the FPGA-based hybrid precision low-resource digital control oscillator implementation method provided by the present invention;

[0045] Figure 6 This is a waveform spectrum diagram of the FPGA-based hybrid precision low-resource digital control oscillator implementation method provided by the present invention.

[0046] Figure 7 This is a waveform diagram of the instantaneous frequency switching in the FPGA-based hybrid precision low-resource digital control oscillator implementation method provided by the present invention.

[0047] Figure 8 This is a schematic diagram of the FPGA-based hybrid precision low-resource digitally controlled oscillator system structure provided by the present invention;

[0048] Figure 9 This is a schematic diagram of the structure of other functional modules included in the FPGA-based hybrid precision low-resource digitally controlled oscillator system provided by the present invention;

[0049] Figure 10 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0050] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0051] The following description, with reference to the accompanying drawings, outlines an embodiment of the FPGA-based mixed-precision low-resource digitally controlled oscillator implementation method, system, and electronic device of the present invention.

[0052] Figure 1 This is a flowchart illustrating an embodiment of the present invention of a method for implementing a hybrid precision low-resource digitally controlled oscillator based on FPGA.

[0053] like Figure 1 As shown, the implementation method of a hybrid precision low-resource digitally controlled oscillator based on FPGA includes the following steps:

[0054] S1. Mixed-precision phase accumulation: In terms of hardware architecture design, the 32-bit phase accumulator is divided into a high-order 24-bit main frequency control segment and a low-order 8-bit dynamic compensation segment. Phase accumulation is performed in parallel through a dual carry chain. These two parts are deployed on dedicated carry chain resources of the FPGA, such as Xilinx's CARRY4 logic unit.

[0055] A dual-pipeline approach is used to perform the accumulation operation in parallel to improve computational efficiency. Specifically, the high 24 bits of the high-order receive frequency tuning word (FTW) control the main frequency, while the low 8 bits of the low-order receive frequency tuning word (FTW) are superimposed with the overflow remainder to dynamically compensate for phase errors.

[0056] High-order segment (master frequency control): The high 24 bits of the receiver frequency tuning word FTW (FTW[31:8]), whose accumulation formula is:

[0057]

[0058] The output is used to determine the main address of the waveform lookup table, corresponding to... The high 12 bits of the interval, such as phase_high[23:12].

[0059] Low-order segment (dynamic compensation): Receive the lower 8 bits of the FTW (FTW[7:0]) and add the overflow remainder from the previous cycle, overflow_remainder. The accumulation formula is:

[0060]

[0061] The output result serves as the local offset for interpolation calculation, such as phase_low[7:0] corresponding to The quantized value of the decimal part.

[0062] When the total 32-bit phase reaches or exceeds 2 to the power of 32, the overflow flag is triggered and the phase overflow remainder is extracted. The formula is:

[0063]

[0064] Where: the remainder of the high-order segment overflow_high= Used to update the initial value of the main frequency band in the next cycle; low-order segment remainder overflow_low= As the initial input for the dynamic compensation segment, it avoids the accumulation of phase truncation error.

[0065] It is important to note that the two accumulators execute synchronously using a pipelined architecture, avoiding the timing bottlenecks of traditional cascaded structures. Furthermore, a register is inserted at the end of each accumulation stage, reducing the critical path latency from four logic levels to two. This allows the architecture to support clock frequencies up to 500MHz, a significant improvement over the traditional full-precision accumulator's support of only 300MHz.

[0066] like Figure 2 The diagram illustrates the phase error over time for a conventional full-precision accumulator and the proposed solution under different frequency-tuned words (FTW). For each FTW value, two curves represent the conventional solution and the proposed solution, respectively. Figure 2 In the diagram, the traditional scheme's curve is represented by a dashed line, indicating significant phase error fluctuations, relatively high error values, and slow convergence speed. This reflects the difficulty of traditional full-precision accumulators in quickly and stably controlling the phase under different FTW conditions, resulting in persistent and unstable phase errors. In contrast, the curve of the proposed solution is represented by a solid line, showing smaller phase error fluctuations, significantly lower error values ​​than the traditional scheme, and faster convergence speed. This demonstrates the advantage of this solution in phase control, enabling it to quickly converge the phase error to a smaller value under different FTW conditions, ensuring system stability and high precision.

[0067] S2. Hierarchical Hybrid Storage: Based on the target signal frequency and the system clock frequency Through frequency threshold The system dynamically divides high-frequency and low-frequency bands; this threshold is calculated based on the system clock frequency and the address width of the distributed RAM. High-frequency waveform data is stored in distributed RAM to reduce access latency, while low-frequency data is stored in Block RAM to conserve resources. This refers to the address width of the distributed RAM.

[0068] At high frequencies, distributed RAM is used for data storage. Distributed RAM is constructed using LUTs built into the FPGA logic units, offering the advantage of a single-cycle access latency of no more than one clock cycle. It primarily stores high-order quantized data in the range of 0 to π / 2. Through a specific address mapping method, it can utilize hardware symmetry to generate full-cycle waveforms, significantly reducing storage requirements.

[0069] In the low-frequency range, Block RAM is used for data storage. Block RAM is a dedicated block RAM resource in the FPGA with a large storage depth. It stores full-precision data from 0 to π / 2, divided into four sub-intervals every π / 8. Each sub-interval stores the fundamental frequency data and the second harmonic compensation coefficient to support real-time waveform reconstruction in hardware.

[0070] To enable dynamic scheduling of storage resources, a frequency monitoring unit is integrated. This unit calculates the current frequency based on the current frequency tuning word and then switches the storage access path in real time according to this frequency. If the current frequency is higher than a threshold, distributed RAM is accessed; if it is lower than or equal to the threshold, Block RAM is accessed.

[0071] like Figure 3 , Figure 4 As shown, the storage resource usage and storage access latency of the traditional solution and the solution of this patent are simulated at different frequencies.

[0072] exist Figure 3 In the diagram, the traditional solution's curve is represented by the blue curve, which shows a roughly linear relationship with frequency, but fluctuates due to random noise. This means that the storage resource usage of the traditional solution increases steadily with frequency, and the increase is relatively stable. The curve for this new technology, represented by the red curve, shows that in the low-frequency range (below 200MHz), storage resource usage is similar to the traditional solution, but the growth rate is relatively slower; in the high-frequency range (above 200MHz), the growth rate of storage resource usage slows significantly. This demonstrates the high efficiency of this technology in resource utilization, especially in high-frequency scenarios, effectively controlling storage resource usage and avoiding the significant increase in resource consumption with increasing frequency seen in traditional solutions.

[0073] exist Figure 4 In the diagram, the traditional solution's curve is represented by the blue curve. It has a relatively high base latency, which increases significantly with increasing frequency. This indicates that the traditional solution experiences a noticeable slowdown in memory access when processing high-frequency signals because its memory access latency is highly dependent on frequency. Random noise causes fluctuations in the curve, simulating uncertainties in real-world systems. The curve for this technical solution, represented by the red curve, shows a lower base latency at low frequencies, indicating inherently faster memory access speeds in low-frequency scenarios. Even when the frequency exceeds 200MHz and enters the high-frequency band, the latency increase rate is much slower than the traditional solution. This highlights the advantage of this technical solution in memory access speed, enabling more efficient memory access operations at both low and high frequencies.

[0074] S3. High-order interpolation waveform reconstruction: In the phase transition interval, cubic spline interpolation or adaptive piecewise polynomial fitting algorithm is used. By pre-stored node amplitude, first derivative and second derivative values, and combined with the FPGA's DSP module, polynomial functions are calculated in parallel to compensate for waveform distortion.

[0075] As an example, a hardware implementation using cubic spline interpolation is shown:

[0076] The interval from 0 to π / 2 is divided into 256 nodes at equal intervals. For each node, the magnitude, first derivative, and second derivative need to be calculated and stored.

[0077] The amplitude is obtained by calculating a sine function and quantizing it into a 16-bit fixed-point number. The first derivative is approximated using the central difference method, but a special difference method is used for the first and last nodes to ensure accuracy. The second derivative is obtained by establishing cubic spline boundary conditions and solving the tridiagonal matrix equation, with the second derivatives at the first and last nodes set to 0.

[0078] During polynomial calculations, a three-stage pipeline architecture is employed for single-cycle interpolation. First, address generation is performed, determining the node and local offset based on the current phase. Next, the node coefficients are read in parallel from the BRAM. Finally, the cubic polynomial is calculated using the FPGA's DSP module. After calculation, the amplitude is further processed according to the quadrant of the phase to reconstruct the full-cycle waveform.

[0079] like Figure 5 , Figure 6 As shown, the time-domain waveform and waveform spectrum diagrams of the traditional solution and the present technical solution are presented.

[0080] exist Figure 5 In traditional methods, the time-domain waveform exhibits significant and complex fluctuations. This complexity implies that the signal generated by traditional methods contains substantial harmonic and noise interference, resulting in low signal purity. This reflects the difficulty of effectively suppressing harmonics and noise during signal generation, leading to poor signal quality and potentially impacting subsequent applications based on the signal. For example, signal transmission in communication systems may experience increased bit error rates. In contrast, the time-domain waveform of this proposed solution is relatively smooth with smaller fluctuations. While it also contains some harmonic components (second and third harmonics, with small amplitudes) and noise (noise figure of 0.05), their impact is significantly less compared to traditional methods. This demonstrates that this proposed solution effectively controls harmonic generation and suppresses noise, ensuring relative signal purity. This contributes to improved signal reliability and stability in various applications, such as providing more accurate signals in high-precision communication or measurement systems.

[0081] exist Figure 6In traditional schemes, besides a significant peak at the fundamental frequency (50Hz), the spectrum also shows high amplitude values ​​at multiple harmonic frequencies (such as 100Hz and 150Hz, corresponding to the second and third harmonics). This indicates that the signal generated by the traditional scheme contains rich harmonic components, suggesting that it cannot effectively control harmonic generation during signal generation, resulting in an impure signal spectrum. High harmonic content can cause interference between signals, degrading system performance. For example, in RF systems, it may generate out-of-band radiation, affecting signals in other frequency bands. In contrast, the spectrum of this technical solution shows a significant peak at the fundamental frequency, while the amplitude values ​​at harmonic frequencies are significantly lower than those of the traditional scheme. In particular, the amplitude of higher harmonics is almost negligible, fully demonstrating the advantage of this technical solution in reducing harmonic components. This means that this technical solution can generate a signal closer to an ideal sine wave, with a purer signal spectrum and lower total harmonic distortion. This advantage is of great significance for applications with high signal quality requirements, such as high-speed data communication and high-precision measurement, effectively improving system performance and stability.

[0082] S4. Dynamic phase continuous compensation: The phase offset is calculated in real time during frequency switching and injected into the phase accumulator. At the same time, when the phase overflows, the remainder is retained and passed to the next cycle for accumulation to ensure phase continuity.

[0083] When a frequency switching command is received, the phase increment difference between the old and new frequency tuning words is calculated. This difference is injected into the phase accumulator through a register cascade path to synchronize the phase of the high and low bits. This ensures that the phase increment remains continuous at the moment of frequency switching, greatly shortening the switching time and representing a significant improvement over traditional methods.

[0084] like Figure 7 The image shows the waveforms of the traditional solution and the proposed solution during frequency switching. Figure 7 In the traditional scheme, the waveform is represented by the blue curve. At the frequency switching moment (marked by the black dashed line in the figure), because the sine wave directly switches from one frequency to another without phase smoothing, a significant phase jump occurs, manifesting as glitches in the waveform. This indicates that the traditional scheme has poor signal continuity during frequency switching, which may adversely affect the system's stability and performance. The waveform of this technical solution is represented by the red curve. During frequency switching, by calculating the phase at the switching moment and applying it to the signal at the new frequency, phase continuity is ensured, resulting in a smoother transition without significant glitches. This demonstrates the stability advantage of this technical solution during frequency switching, better meeting the needs of applications with high signal stability requirements.

[0085] To avoid the phase jump problem caused by phase reset to 0 after overflow in traditional solutions, a remainder buffering and preloading method is adopted. When overflow occurs, the remainder is stored in a dual-port register. Before the next cycle accumulation, the remainder is preloaded into the low-order compensation segment to ensure that the phase continuity error is controlled within a very small range.

[0086] The above implementation scheme achieves a breakthrough optimization of digitally controlled oscillators on FPGAs through a four-dimensional collaborative approach of "hybrid precision architecture + hierarchical storage + high-order interpolation + dynamic compensation." In terms of resource efficiency, it significantly reduces BRAM usage and logic unit consumption compared to traditional full-precision schemes. Regarding accuracy improvement, cubic spline interpolation and adaptive piecewise fitting effectively reduce total harmonic distortion and high-frequency spurious emissions. In terms of real-time performance, the dual-carry pipeline and fast frequency switching capability meet the demands of demanding scenarios such as frequency-hopping communication and radar agility. Simultaneously, it deeply utilizes the heterogeneous characteristics of different FPGA modules to form an integrated architecture, demonstrating outstanding creativity and engineering value.

[0087] In some embodiments of the present invention, a hybrid storage strategy is adopted to address the signal characteristics of different frequency bands, namely, using distributed RAM for high-frequency bands and block RAM for low-frequency bands. This strategy fully utilizes the characteristics of different types of storage resources in the FPGA, effectively reducing resource consumption and improving the overall system performance while ensuring signal accuracy.

[0088] High-frequency distributed RAM storage solution:

[0089] ①Storing data content

[0090] High frequency band ( The system employs distributed RAM to store high-order phase quantization data in the 0~π / 2 interval. Specifically, 12-bit addresses are used to correspond to 4096 points. This means that the phase interval from 0 to π / 2 is divided into 4096 equal parts, with each point corresponding to a specific phase value and the quantization amplitude data under that phase. A full-cycle waveform is generated through hardware symmetry mapping.

[0091] ② Data Quantification and Accuracy

[0092] The data is represented using 16-bit fixed-point numbers (Q12 format), with 4 bits for the integer part and 12 bits for the fractional part. This quantization method ensures a certain level of precision while also being suitable for FPGA hardware processing. In actual calculations, the sine function value is obtained through high-precision floating-point calculations, and then quantized into Q12 format using FPGA development tools (such as MATLAB / Python), with the error controlled within 1LSB≈2⁻¹²≈0.00024.

[0093] ③ Hardware symmetry mapping generates full-cycle waveforms

[0094] By leveraging the symmetry of the sine function, only data in the range of 0 to π / 2 is stored; waveforms in other quadrants can be generated through hardware symmetry mapping. The specific mapping rules are as follows:

[0095] Second quadrant (π / 2 to π): For any phase φ in this quadrant, its amplitude y is equal to the amplitude of π-φ in the interval 0 to π / 2, and its sign is positive, i.e. In terms of hardware implementation, the phase in the range of 0 to π / 2 is obtained by performing simple logical operations on the phase, and then the corresponding amplitude data is read from the distributed RAM.

[0096] Third quadrant (π~3π / 2): For phase φ, its amplitude y is equal to the amplitude of φ-π in the interval 0~π / 2, but the sign is negative, i.e. Similarly, the phase is converted through hardware logic, and the data is read and then inverted.

[0097] Fourth quadrant (3π / 2~2π): For phase φ, its amplitude y is equal to the amplitude of 2π-φ in the interval 0~π / 2, and its sign is negative, i.e. The hardware implementation performs the corresponding phase conversion and amplitude inversion.

[0098] This symmetric mapping method greatly reduces the amount of data stored, achieving a compression rate of 75%, and only requires storing 1 / 4 of the cycle's data to generate a full-cycle waveform;

[0099] ④ Advantages of Distributed RAM

[0100] Distributed RAM is constructed using the built-in lookup tables (LUTs) of FPGA logic units (LEs), featuring a single-cycle access latency of ≤1 clock cycle. In high-frequency bands, signals change rapidly, requiring fast memory access speeds to ensure real-time signal generation. The high-speed access characteristics of distributed RAM perfectly meet this need, enabling the timely acquisition of the required amplitude data during high-frequency signal generation.

[0101] Low-frequency Block RAM storage solution:

[0102] ①Storing data content

[0103] The low-frequency band uses Block RAM to store full-precision data in the range of 0 to π / 2, using 16-bit addresses to correspond to 65,536 points. Compared to the high-frequency band, the low-frequency band stores more points, providing higher precision to meet the detail requirements of low-frequency signals.

[0104] Meanwhile, the interval from 0 to π / 2 is divided into four sub-intervals at π / 8 intervals, and each sub-interval stores the fundamental frequency data y=sinφ and the second harmonic compensation coefficient. =sin(2φ). This segmented storage and introduction of second harmonic compensation helps improve the waveform quality of low-frequency signals and reduce harmonic distortion.

[0105] ② Data accuracy and storage

[0106] The data is also stored in 16-bit fixed-point format (Q12 format) to ensure consistency with the data processing accuracy of the entire system. In practical applications, the fundamental wave data and second harmonic compensation coefficient of each point are obtained through high-precision calculations, and then quantized into Q12 format and stored in Block RAM.

[0107] ③ Waveform reconstruction

[0108] When generating low-frequency signals, the sub-interval is determined based on the current phase. Then, the fundamental frequency data and second harmonic compensation coefficient corresponding to that sub-interval are read from the Block RAM. The waveform is reconstructed in real-time via hardware, using the following formula:

[0109]

[0110] Where k is the compensation factor. The compensation factor can be adjusted according to actual needs to achieve the best waveform reconstruction effect.

[0111] ④ Advantages of Block RAM

[0112] Block RAM is a dedicated block RAM resource in FPGAs, featuring a large storage capacity (e.g., 36Kb per port). In low-frequency bands, where storing more data points and compensation coefficients is required, Block RAM can meet the storage needs. Furthermore, its storage structure and access methods are suitable for centralized storage and retrieval operations of large amounts of data.

[0113] Furthermore, to enable dynamic switching between high-frequency and low-frequency band storage, the system integrates a dynamic scheduling mechanism. The frequency of the current signal is calculated using the Frequency Tuning Word (FTW). The calculation formula is:

[0114]

[0115] when When this happens, the system automatically switches to a high-frequency distributed RAM storage access mode; when When this happens, switch to the low-frequency Block RAM storage access mode.

[0116] As an example, the dynamic scheduling mechanism is implemented through hardware logic, for example using the following Verilog code:

[0117] always @(posedge clk) begin

[0118] if (f_current > f_th) begin / / High-frequency access

[0119] dist_ram_addr <= phase_high[23:12];

[0120] data_out <= dist_ram[dist_ram_addr];

[0121] end else begin / / Low-frequency access

[0122] bram_subaddr <= phase_high[23:15]; / / Sub-interval index (π / 8 segments)

[0123] bram_addr <= {bram_subaddr, phase_high[14:12]}; / / Address within the sub-interval

[0124] data_out <= bram[bram_addr];

[0125] end

[0126] end

[0127] This dynamic scheduling mechanism enables the system to automatically select appropriate storage resources based on changes in signal frequency, further optimizing system performance and resource utilization.

[0128] In some embodiments of the present invention, the cubic spline interpolation algorithm pre-stores the amplitude of each node. First derivative and second derivative Through a cubic polynomial:

[0129] Calculate the interpolation point magnitude, where, It is uniquely determined by the node parameters, which include the node magnitude, first-order and second-order derivatives.

[0130] When implementing the above method through hardware, first pre-store the parameters: , , and coefficient , , , Pre-stored in the FPGA's Block RAM to avoid consuming resources during real-time computation;

[0131] Then parallel computing: a three-stage pipeline computing is implemented using the FPGA's DSP module;

[0132] Based on the current phase Determine the node ( and local offset ;

[0133] Parallel reading of nodes from Block RAM The four sets of coefficients;

[0134] Calculation via cascaded hardware multipliers , Then multiply by the coefficient and sum them up, where, and They are respectively Square and cube operations;

[0135] Finally, through symmetry mapping: based on the quadrant where the phase is located (e.g., determined by phase_high[23:13]), the interpolation result is inverted or its sign is flipped (e.g., amplitude = -result in the third quadrant, phase = ...). ), generating a full-cycle waveform.

[0136] As an example, to further improve the accuracy of waveform reconstruction, an adaptive piecewise polynomial fitting method can also be used. This involves calculating the curvature of three adjacent points in real time and dynamically adjusting the fitting order based on the magnitude of the curvature.

[0137] In high curvature regions, such as near π / 4, a fourth-order polynomial is used for fitting, and the segment interval is reduced to improve waveform detail. In low curvature regions, such as near 0, a second-order polynomial is used for fitting, while the segment interval is increased to reduce multiplier resource consumption.

[0138] When the phase crosses the segment boundary, a boundary self-calibration mechanism is triggered. A hardware comparator compares the amplitude and derivative of adjacent segments at the boundary point. If the error exceeds 1 LSB, a transition point is inserted in real time through BRAM dual-port mode, and the fitting coefficients are updated to ensure the continuity and accuracy of the waveform.

[0139] In some embodiments of the present invention, when the phase accumulation result When this happens, the overflow flag is triggered.

[0140] At this point, the remainder is calculated precisely. And split it into high-order remainders Remainder with lower segment By using a dual-port register to latch the remainder in real time, the initial phase of the next cycle is calculated through combinational logic as follows:

[0141]

[0142] In terms of specific hardware implementation, the remainder is generated in real time by combinational logic, and the register locks the remainder on the rising edge of the clock to ensure that the lower-order bits are locked first during the accumulation in the next cycle. Add the lower 8 bits of FTW, and perform the corresponding operation on the higher bits.

[0143] This mechanism avoids the phase jump caused by the phase reset to 0 after overflow in traditional schemes, ensuring phase continuity error <0.1° (at 32-bit precision), significantly improving the spectral purity and stability of the output signal, and meeting the requirements for high-precision signal generation.

[0144] When switching frequencies, the new frequency tuning word is calculated first. and old frequency tuning words Phase increment difference:

[0145]

[0146] And Divided into high 24 bits With the lower 8 bits , For the system clock cycle, .

[0147] Through a dedicated high-speed path, and The high and low bits of the phase accumulator are injected separately, and the entire process is completed within one clock cycle, achieving a switching time of <10ns. The hardware design employs synchronous reset logic to ensure that the injection timing is strictly synchronized with the system clock, avoiding metastability issues.

[0148] This mechanism meets the stringent requirements for rapid frequency switching in scenarios such as frequency hopping communication and radar agility, eliminates phase glitches, ensures the continuity and stability of the signal during the switching process, and improves the system's anti-interference capability and reliability.

[0149] like Figure 8 As shown, a hybrid precision low-resource digitally controlled oscillator system based on FPGA includes:

[0150] Mixed-precision phase accumulation module: It includes a high-order 24-bit accumulator and a low-order 8-bit compensator, which respectively receive the high 24 bits and low 8 bits of the frequency tuning word FTW, and generate a 32-bit phase value through parallel accumulation via a dual carry chain; by segmented accumulation, while maintaining 32-bit phase precision, it reduces the consumption of logic unit (LE), avoids the waste of resources in full-precision accumulation, and the carry chain optimization and pipeline design significantly reduce latency, meeting the real-time requirements of high-frequency signal generation;

[0151] Hierarchical storage module: Integrates distributed RAM and Block RAM, and dynamically schedules high-frequency and low-frequency data access through a frequency monitoring unit. High-frequency bands use folded address mapping, while low-frequency bands use segmented index storage. On-demand allocation of low latency in high-frequency bands and large capacity in low-frequency bands reduces BRAM usage, and distributed RAM resources are dynamically reused.

[0152] Waveform reconstruction module: Includes phase transition detection unit, interpolation calculation unit and symmetry mapping unit. It supports cubic spline interpolation or adaptive piecewise polynomial fitting. It uses the FPGA's DSP module to calculate the amplitude in parallel to meet the requirements of communication and radar for high-purity signals. It also stores sine / cosine / square wave data through Block RAM. The phase mapping logic adapts to different waveform symmetries (e.g., square waves only require sign judgment) and supports real-time waveform switching.

[0153] Phase compensation module: Includes an overflow remainder register and a phase offset injection unit to ensure phase continuity during frequency switching; fast frequency switching and overflow processing meet the glitch-free requirements of frequency hopping communication, radar agility and other scenarios, and enhance robustness. Hardware verification and environmental adaptation improve system stability and adapt to high-precision signal generation under complex working conditions.

[0154] In some embodiments of the present invention, the dynamic scheduling logic of the hierarchical storage module is as follows:

[0155] The frequency monitoring unit compares the current output frequency with the preset threshold in real time. If the current frequency This indicates that it is in a high-frequency range. At this time, the memory access address is pointed to a predefined address in the distributed RAM. The distributed RAM is constructed using LUTs built into the FPGA logic unit, featuring a single-cycle access latency of ≤1 clock cycle, enabling rapid reading of corresponding waveform data. This meets the stringent real-time requirements of high-frequency signals;

[0156] like If so, it is in the low-frequency range. The address is then set to a predefined address in the Block RAM. Read waveform data Block RAM is a dedicated block RAM resource for FPGAs, featuring large-capacity storage capabilities. It is suitable for storing low-frequency, full-precision data, saving logic resources.

[0157] This dynamic scheduling logic enables precise matching of storage resources. High-frequency bands utilize the high-speed characteristics of distributed RAM, while low-frequency bands utilize the large-capacity characteristics of Block RAM, reducing BRAM usage by more than 50%. At the same time, it ensures the efficiency and quality of signal generation in different frequency bands and improves the overall resource utilization of the system.

[0158] In some embodiments of the present invention, the adaptive piecewise polynomial fitting algorithm is based on curvature Dynamically adjust the segment granularity, where:

[0159] High curvature regions (such as) (Nearby area): The waveform changes drastically in this region. A fourth-order polynomial was used for fitting, with segmented intervals. A fourth-order polynomial can capture rapid changes in waveforms more precisely, such as in... Nearby, the slope of the sine wave varies considerably, and the fourth-order polynomial can be fitted by adjusting more parameters to reduce distortion;

[0160] In low curvature regions (such as near 0): the waveform changes relatively smoothly, and a quadratic polynomial fitting is used with segmented intervals. This reduces resource consumption, such as multipliers, from three DSP groups to one while maintaining a certain level of accuracy, achieving a balance between resources and accuracy.

[0161] By dynamically adjusting the segment granularity based on curvature, the fitting accuracy is improved in the high curvature region, reducing the total harmonic distortion (THD) to below 0.08%; while saving resources in the low curvature region, the system achieves both high performance and low power consumption, and enhances the algorithm's adaptability to different waveform regions.

[0162] In some embodiments of the present invention, the mixed-precision phase accumulation module supports dynamic switching of multiple waveforms, stores waveform data of sine waves, cosine waves and square waves through Block RAM, and adapts the symmetry and amplitude characteristics of different waveforms using phase mapping logic.

[0163] As an example, sine and cosine waves: utilizing their phase difference The characteristics of this can be achieved by adjusting the phase mapping relationship, such as... It enables rapid switching between generation without requiring a significant increase in storage.

[0164] As an example, consider a square wave: Based on the characteristic of a square wave's amplitude abruptly changing across different phase intervals, phase-based logic directly outputs a high or low level, eliminating the need for complex interpolation calculations. For instance, in the range of 0 to... The range outputs a high level. to The range output is low.

[0165] like Figure 9 As shown, in some embodiments of the present invention, the system further includes any one or more modules of the AD:

[0166] The hardware verification module uses dedicated monitoring logic to scan the address access queue of the Block RAM in real time. When it detects that the same address is requested multiple times within the same clock cycle, it immediately triggers a conflict response mechanism, temporarily storing the conflicting address in a First-In-First-Out (FIFO) register and rescheduling the access order through arbitration logic. Simultaneously, the module incorporates a high-precision phase comparator, comparing the theoretical phase value bit-by-bit with the actual phase accumulator output. It analyzes the error spectrum using digital filters and dynamically adjusts the quantization parameters of the low-order compensation segment, such as weighted correction of overflow remainders.

[0167] This module effectively avoids data errors caused by Block RAM access conflicts, minimizes phase accumulation errors, ensures that the total harmonic distortion (THD) of the output signal is less than 0.1%, significantly improves the purity of the signal spectrum, and meets the requirements of high-precision communication and radar systems.

[0168] B. Temperature / Voltage Adaptive Regulation Module: This module integrates a high-precision temperature sensor (such as the PT1000 type) and voltage monitoring circuitry to collect real-time temperature data from the FPGA chip. and power supply voltage .

[0169] When temperature When the threshold increases, the storage partitioning threshold is dynamically reduced using a lookup table. . The adjusted storage partitioning threshold, The original storage partitioning threshold before adjustment can be represented by the following formula:

[0170]

[0171] For temperature sensitivity coefficient, For reference temperature, The current temperature of the FPGA is monitored in real time;

[0172] Increase the proportion of high-frequency data stored in distributed RAM to reduce the impact of temperature drift on Block RAM access latency; when voltage When reducing power consumption, the number of multipliers in parallel computing is automatically reduced, thereby lowering system power consumption. For example, the number of parallel multipliers for cubic spline interpolation is reduced from 3 to 2. This enables the system to adapt to complex environmental changes, maintain stable operation under high temperature or low voltage conditions, extend the FPGA's lifespan, and optimize power consumption performance to meet the low power consumption requirements of portable devices.

[0173] C. Multi-rate waveform generation module: This module features a time-division multiplexing controller that divides the system clock cycle into multiple time slots. For example, the first half of the cycle processes high-frequency signals (e.g., 400MHz), quickly reading waveform data through distributed RAM; the second half of the cycle processes low-frequency signals (e.g., 100MHz), accessing full-precision data in Block RAM. Independent phase pointers control the phase accumulation of the two signals separately, ensuring phase alignment during time-division multiplexing time slot switching. Parallel generation of two signals at different rates is achieved on the same NCO core, eliminating the need for redundant hardware modules and increasing hardware area only slightly, while significantly improving system flexibility. This makes it suitable for scenarios such as multi-carrier communication and multi-band radar detection.

[0174] D. On-chip verification IP module, which monitors BRAM access conflicts and phase accumulator errors in real time, dynamically calibrates compensation values, realizes real-time monitoring and automatic calibration of BRAM access and phase accumulation, effectively improves system reliability, and ensures the stability and accuracy of output signals during long-term operation.

[0175] Corresponding to the above embodiments, the present invention also proposes an electronic device.

[0176] like Figure 10 The diagram shows a structural schematic of an electronic device according to the present invention. The electronic device 200 includes a processor 201 and a memory 203. The processor 201 and the memory 203 are connected, for example, via a bus 202. Optionally, the electronic device 200 may further include a transceiver 204. It should be noted that in practical applications, the transceiver 204 is not limited to one unit, and the structure of this electronic device 200 does not constitute a limitation on the embodiments of the present invention.

[0177] Processor 201 may be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. Processor 201 may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0178] Bus 202 may include a path for transmitting information between the aforementioned components. Bus 202 may be a PCI bus or an EISA bus, etc. Bus 202 may be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0179] The memory 203 stores a computer program corresponding to the FPGA-based mixed-precision low-resource digitally controlled oscillator implementation method of the above embodiments of the present invention. This computer program is executed under the control of the processor 201. The processor 201 executes the computer program stored in the memory 203 to implement the content shown in the aforementioned method embodiments.

[0180] Among them, electronic devices 200 include, but are not limited to: mobile terminals such as laptops and tablets, as well as fixed terminals such as desktop computers. Figure 10 The electronic device 200 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0181] The electronic device 200 of this invention systematically solves the core problems of traditional NCOs in terms of resource consumption, phase continuity, waveform accuracy and timing performance through the synergistic innovation of mixed-precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, providing a reliable solution for FPGA to realize high-precision, low-resource digital control oscillators.

[0182] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, digitally process, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0183] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0184] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0185] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0186] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for implementing a mixed-precision low-resource digitally controlled oscillator based on FPGA, characterized in that, The method comprises the following steps: 32-bit phase accumulator is divided into high 24-bit main frequency control segment and low 8-bit dynamic compensation segment, and phase accumulation is performed in parallel through double carry chain, wherein the high segment receives high 24 bits of frequency tuning word FTW to control main frequency, and the low segment receives low 8 bits of FTW and superimposes overflow remainder to dynamically compensate phase error; According to the target signal frequency and the system clock frequency , through the frequency threshold Dynamic division of high frequency band and low frequency band, high frequency band waveform data is stored in distributed RAM to reduce access delay, low frequency band data is stored in BlockRAM to save resources, wherein, is the address bit width of the distributed RAM; In the phase jump interval, a cubic spline interpolation or adaptive piecewise polynomial fitting algorithm is used, pre-stored node amplitude, first-order derivative and second-order derivative values are combined with the FPGA DSP module to calculate the polynomial function in parallel, and waveform distortion is compensated; When the frequency is switched, the phase offset is calculated in real time and injected into the phase accumulator, and when the phase overflows, the remainder is retained and transmitted to the next cycle accumulation, ensuring the continuity of the phase.

2. The method of claim 1, wherein, The high 24-bit main frequency control segment and the low 8-bit dynamic compensation segment are optimized in logic delay through the carry chain, wherein the high segment accumulation result is used to determine the main address of the waveform lookup table, and the low segment accumulation result is used to generate the local offset for interpolation calculation, and the two together constitute a 32-bit phase value.

3. The method of claim 1, wherein, The high-frequency segment uses distributed RAM to store high-bit phase quantization data in the 0~π / 2 interval, and generates a full-cycle waveform through hardware symmetry mapping; The low-frequency segment uses Block RAM to store full-precision data in the 0~π / 2 interval, and divides the sub-interval by every π / 8, stores the fundamental data and the second harmonic compensation coefficient.

4. The method of claim 1, wherein, The cubic spline interpolation algorithm pre-stores the amplitude of each node , the first derivative , and the second derivative The interpolation point amplitude is calculated by a cubic polynomial, as follows: wherein, uniquely determined by node parameters, the node parameters including a node amplitude, a first order derivative, and a second order derivative.

5. The method of claim 1, wherein, When the phase accumulation result , the overflow flag is triggered and the remainder is reserved , and the initial phase of the next cycle is ; When the frequency is switched, the phase increment difference is calculated according to the new and old FTW and injected into the accumulator.

6. A mixed-precision low-resource digital controlled oscillator system based on FPGA, characterized in that, It comprises: The mixed-precision phase accumulation module includes a high 24-bit accumulator and a low 8-bit compensator, which respectively receive high 24 bits and low 8 bits of the frequency tuning word FTW, and generate a 32-bit phase value through double carry chain parallel accumulation; The hierarchical storage module integrates distributed RAM and Block RAM, and dynamically schedules high-frequency segment and low-frequency segment data access through a frequency monitoring unit, the high-frequency segment uses folded address mapping, and the low-frequency segment uses segmented index storage; The waveform reconstruction module includes a phase jump detection unit, an interpolation calculation unit and a symmetry mapping unit, supports cubic spline interpolation or adaptive piecewise polynomial fitting, and uses the FPGA DSP module to calculate the amplitude in parallel; The phase compensation module includes an overflow remainder register and a phase offset injection unit to ensure the continuity of the phase when the frequency is switched.

7. The system of claim 6, wherein, The dynamic scheduling logic of the hierarchical storage module is: Comparing the current output frequency with a preset threshold value in real time by the frequency monitoring unit , if the current frequency , the storage access address is directed to a predefined address of the distributed RAM , and the corresponding waveform data is read ; Otherwise, point the address to the predefined address of the Block RAM , and read the corresponding waveform data .

8. The system of claim 6, wherein, The adaptive piecewise polynomial fitting algorithm is based on curvature dynamically adjusts the piecewise granularity, wherein: In the high-curvature region, a fourth-order polynomial fitting is used, and the segment interval Δφ=π / 128; In the low-curvature region, a second-order polynomial fitting is used, and the segment interval Δφ=π / 32.

9. The system of claim 6, wherein, The mixed-precision phase accumulation module supports multi-waveform dynamic switching, stores waveform data of sine wave, cosine wave and square wave through Block RAM, and adapts the symmetry and amplitude characteristics of different waveforms using phase mapping logic.

10. The system of claim 6, wherein, It also includes any one or more of A-D: A, the hardware verification module, which monitors Block RAM access conflicts in real time and temporarily stores conflict addresses, compares the theoretical output of the phase accumulator with the actual output, dynamically calibrates the quantization error of the low compensation segment, and ensures that the total harmonic distortion THD of the output signal is less than 0.1%. B. Temperature / voltage adaptive adjustment module, dynamically adjust the storage division threshold according to the real-time temperature and voltage of FPGA and parallelism parameters; C. Multi-rate waveform generation module, sharing storage resources by time division multiplexing, supporting two different rate signals output from the same NCO kernel; D. On-chip verification IP module, real-time monitoring BRAM access conflict and phase accumulator error, dynamic calibration compensation value.

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