Hardware acceleration calculation method and system based on post quantum cryptography algorithm

Abstract

The invention relates to a hardware acceleration calculation method and system based on a post quantum cryptography algorithm, and is applied to a chip. The method comprises the steps that hardware engines in a hardware acceleration engine array are adopted to execute post-quantum cryptographic algorithms of corresponding types, and the post-quantum cryptographic algorithms of the corresponding types comprise at least one of polynomial multiplication, multi-branch hash calculation, a tree structure and sparse polynomial operation; in the execution process, resources needed by the quantum cryptography algorithm after the hardware engines execute are dynamically adjusted based on the prediction mechanism and the fuzzy control logic, and the resources comprise at least one of the core number, the cache bandwidth, the voltage and the frequency. Namely, on one hand, a hardware engine is adopted to perform accelerated calculation on the post quantum cryptography algorithm, and on the other hand, resources required by calculation are dynamically adjusted during accelerated calculation, so that the resource utilization rate is increased, and calculation and energy efficiency regulation are optimized. Cooperative improvement of algorithm acceleration efficiency and performance can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and in particular to a hardware acceleration computing method and system based on a post-quantum cryptographic algorithm. BACKGROUND

[0002] With the rapid development of quantum computing technology, the traditional cryptographic algorithm is facing a huge risk of being cracked quickly, and the security of the existing encryption system relying on mathematical problems such as large number factorization and discrete logarithm is in great danger. In the chip application scenario, the security requirements of data transmission and storage are increasing, and once the encryption is broken, it will lead to serious consequences such as sensitive information leakage and system being attacked maliciously. At present, some researchers have applied post-quantum cryptographic algorithms to the preliminary encryption link of some specific field chip security protection, such as financial payment chip and Internet of Things communication chip. However, although the post-quantum cryptographic algorithm has the ability to resist quantum computing attacks, it has high algorithm complexity and large amount of calculation, and in the traditional software implementation mode, it will significantly reduce the data processing speed of the chip and the overall performance of the system, which is difficult to meet the needs of application scenarios with high real-time requirements. SUMMARY

[0003] Therefore, it is necessary to provide a hardware acceleration computing method and system based on a post-quantum cryptographic algorithm, which can improve the computing efficiency and performance of the post-quantum cryptographic algorithm.

[0004] In a first aspect, the present application provides a hardware acceleration computing method based on a post-quantum cryptographic algorithm, applied to a chip, wherein the chip includes a hardware acceleration engine array, and the hardware acceleration engine array includes hardware engines of different types, and the method includes: using each hardware engine in the hardware acceleration engine array to execute a corresponding type of post-quantum cryptographic algorithm, wherein the corresponding type of post-quantum cryptographic algorithm includes at least one of polynomial multiplication, multi-branch hash calculation, tree structure, and sparse polynomial operation; and during the execution, dynamically adjusting resources required by each hardware engine to execute the post-quantum cryptographic algorithm based on a prediction mechanism and fuzzy control logic, wherein the resources include at least one of core number, cache bandwidth, voltage, and frequency.

[0005] In one of the embodiments, the chip is also integrated with a side channel protection circuit, and the method further includes: performing security protection on the chip when a standard of the post-quantum cryptographic algorithm is updated or a firmware is upgraded.

[0006] In one of the embodiments, the using each hardware engine in the hardware acceleration engine array to execute a corresponding type of post-quantum cryptographic algorithm includes: determining different data processing stages of the post-quantum cryptographic algorithm; and in different data processing stages, using different types of hardware engines to execute a corresponding type of post-quantum cryptographic algorithm of the stage.

[0007] In one embodiment, the step of employing different hardware engines to execute the corresponding type of post-quantum cryptography algorithm at different data processing stages includes: determining that the hardware engine for the key generation, encryption, or decryption stage is a pipeline architecture and a modular multiplication algorithm unit, and decomposing the polynomial multiplication of the post-quantum cryptography algorithm into multiple pipeline stages based on the pipeline architecture, and performing single modular operations in each pipeline stage using the modular multiplication algorithm unit; determining that the hardware engine for the signature generation or signature verification stage is a parallel hash compression engine and a Merkle tree accelerator, and performing parallel computation of the multi-branch hash calculation of the post-quantum cryptography algorithm using the parallel hash compression engine, and verifying the tree structure of the post-quantum cryptography algorithm using the Merkle tree accelerator; and determining that the hardware engine for the key generation or signature generation stage is a parallel matrix multiplier, and performing computation of the sparse polynomial of the post-quantum cryptography algorithm using the parallel matrix multiplier at this stage.

[0008] In one embodiment, the dynamic adjustment of resources required by each hardware engine to execute the post-quantum cryptography algorithm based on a prediction mechanism and fuzzy control logic includes: collecting key resource indicator data of the computing units of the post-quantum cryptography algorithm, and predicting key resource indicator data for the next time period based on the key resource indicator data and a resource usage heatmap to obtain predicted values ​​of key resource indicator data; constructing membership functions and multi-condition coupled fuzzy logic inference rules based on fuzzy variables, wherein the fuzzy variables include load thresholds and cache conflict rates, and the multi-condition coupled fuzzy logic inference rules include membership degrees and corresponding resource adjustment actions. The resource regulation actions include adjustments to at least one of the following: number of cores, cache bandwidth, voltage, and frequency; fuzzy set membership degrees are obtained by substituting the predicted values ​​of the key resource indicator data into the membership function based on fuzzy mapping; a fuzzy output set of membership degrees for each resource regulation action is generated based on the fuzzy set membership degrees and the multi-condition coupled fuzzy logic reasoning rules; the centroid of the output fuzzy set is calculated based on the centroid method, and the resource requirements for the next time period are determined based on the centroid; and at least one of the following—number of cores, cache bandwidth, voltage, and frequency—required by each hardware engine after executing the quantum cryptography algorithm is adjusted based on the resource requirements for the next time period.

[0009] In one embodiment, the membership function is a trapezoidal membership function. The step of substituting the predicted value of the key resource indicator data into the membership function based on fuzzy mapping to obtain the fuzzy set membership degree includes: if the predicted value of the key resource indicator data is less than or equal to the left boundary starting point of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 0; if the predicted value of the key resource indicator data is greater than the left boundary starting point of the trapezoidal membership function and less than or equal to the left boundary ending point of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be a first membership degree value, where the first membership degree value is calculated based on the predicted value of the key resource indicator data, the left boundary ending point of the trapezoidal membership function, and the width parameter of the Gaussian curve. If the predicted value of the key resource indicator data is greater than the left boundary endpoint of the trapezoidal membership function and less than or equal to the right boundary starting point of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 1; if the predicted value of the key resource indicator data is greater than the right boundary starting point of the trapezoidal membership function and less than or equal to the right boundary endpoint of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be a second membership degree value, which is calculated based on the predicted value of the key resource indicator data, the right boundary starting point of the trapezoidal membership function, and the width parameter of the Gaussian curve; if the predicted value of the key resource indicator data is greater than the right boundary endpoint of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 0.

[0010] In one embodiment, the step of calculating the centroid of the output fuzzy set based on the centroid method and determining the resource demand for the next time period based on the centroid includes: extracting specific description information of each resource regulation action and its corresponding membership value from the fuzzy output set; using the extracted resource regulation action as a discrete point and its membership value as a weight, performing a weighted average processing according to the centroid method to obtain the centroid of the output fuzzy set; and determining the resource demand for the next time period based on the centroid.

[0011] In one embodiment, the security protection of the chip during standard updates or firmware upgrades of the post-quantum cryptography algorithm includes: during standard updates of the post-quantum cryptography algorithm, updating the circuit modules on the chip related to algorithm security adaptation through reconstruction technology; during firmware upgrades of the post-quantum cryptography algorithm, generating a unique root key for the chip based on a physically non-cloning function, performing digital signature verification on the upgraded firmware of the post-quantum cryptography algorithm based on the unique root key, and verifying each stage of the boot image step by step through a hardware security boot chain.

[0012] In one embodiment, the method further includes: collecting the operating status index parameters of the hardware acceleration engine array; evaluating the computing efficiency of the hardware acceleration engine based on the operating status index parameters; and optimizing the hardware resources of each hardware engine in the hardware acceleration engine according to the evaluation results.

[0013] Secondly, this application also provides a hardware-accelerated computing system based on post-quantum cryptography algorithms, applied to a chip. The chip includes a hardware acceleration engine array, which includes different types of hardware engines. The system includes: an execution module, used to execute corresponding types of post-quantum cryptography algorithms using each hardware engine in the hardware acceleration engine array, wherein the corresponding types of post-quantum cryptography algorithms include at least one of polynomial multiplication, multi-branch hash calculation, tree structure, and sparse polynomial operation; and an adjustment module, used to dynamically adjust the resources required by each hardware engine to execute the post-quantum cryptography algorithm during the execution process based on a prediction mechanism and fuzzy control logic, wherein the resources include at least one of core count, cache bandwidth, voltage, and frequency.

[0014] The aforementioned hardware-accelerated computing method and system based on post-quantum cryptography algorithms employs a hardware acceleration engine array where each hardware engine executes a corresponding type of post-quantum cryptography algorithm. This corresponding type of post-quantum cryptography algorithm includes at least one of polynomial multiplication, multi-branch hashing, tree structures, and sparse polynomial operations. During execution, the resources required by each hardware engine for executing the post-quantum cryptography algorithm are dynamically adjusted based on a prediction mechanism and fuzzy control logic. These resources include at least one of the number of cores, cache bandwidth, voltage, and frequency. In other words, on the one hand, the hardware engines accelerate the computation of post-quantum cryptography algorithms, improving their computational efficiency; on the other hand, the dynamic adjustment of resources required for computation based on the prediction mechanism and fuzzy control logic during accelerated computation improves resource utilization and optimizes computation and energy efficiency control. Thus, a synergistic improvement in algorithm acceleration efficiency and performance can be achieved. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is an application environment diagram of a hardware-accelerated computing method based on a post-quantum cryptography algorithm in one embodiment;

[0017] Figure 2This is a flowchart of a hardware-accelerated computing method based on a post-quantum cryptography algorithm in one embodiment;

[0018] Figure 3 In one embodiment Figure 2 A flowchart following step 202;

[0019] Figure 4 In one embodiment Figure 2 A flowchart illustrating step 201;

[0020] Figure 5 In one embodiment Figure 4 A flowchart illustrating step 402 in the middle section;

[0021] Figure 6 In one embodiment Figure 2 A flowchart illustrating step 202 in the middle section;

[0022] Figure 7 In one embodiment Figure 6 A flowchart illustrating step 605 in the middle section;

[0023] Figure 8 In one embodiment Figure 3 A flowchart illustrating step 301 in the middle section;

[0024] Figure 9 A flowchart of a hardware-accelerated computation method based on a post-quantum cryptography algorithm in a specific example;

[0025] Figure 10 This is a block diagram of a hardware-accelerated computing system based on a post-quantum cryptography algorithm in one embodiment. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0027] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0028] In related technologies, the software implementation of post-quantum cryptography algorithms significantly reduces the data processing speed of the chip and the overall system performance, making it difficult to meet the needs of application scenarios with high real-time requirements.

[0029] Therefore, in order to improve the performance of chips in various real-time application scenarios and ensure the efficient and stable operation of the system while ensuring chip data security, it is necessary to design a hardware-accelerated computing method based on post-quantum cryptography algorithms. By utilizing hardware acceleration technology to overcome the performance bottleneck of software implementation, and by using dynamic secure computing mechanisms to flexibly adapt to the security requirements of different scenarios, a dual optimization of chip security and performance can be achieved.

[0030] The hardware-accelerated computing method based on post-quantum cryptography provided in this application can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on another network server.

[0031] The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and drones. The server 104 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server providing cloud computing services.

[0032] In the embodiments of this application, such as Figure 2 As shown, a hardware-accelerated computing method based on post-quantum cryptography is provided. This method is applied to a chip, which includes a hardware acceleration engine array, comprising different types of hardware engines. The method is applied to... Figure 1 Taking server 104 as an example, the explanation includes the following steps 201 and 202. Wherein:

[0033] Step 201: Each hardware engine in the hardware acceleration engine array executes a corresponding type of post-quantum cryptography algorithm, wherein the corresponding type of post-quantum cryptography algorithm includes at least one of polynomial multiplication, multi-branch hash calculation, tree structure and sparse polynomial operation.

[0034] The hardware acceleration engine array integrates a coprocessor cluster adapted to post-quantum cryptography algorithms. During core algorithm computations, this coprocessor cluster achieves high-efficiency acceleration for lattice theory, hash signatures, and multivariable polynomial algorithms through a pipelined architecture with dedicated modular arithmetic, a parallel hash compression engine with Merkle tree accelerators, and parallel matrix multipliers. Specifically, the cluster incorporates three types of dedicated coprocessors: lattice theory, hash signatures, and multivariable polynomials. Each type of coprocessor is used to implement the core computations of its respective post-quantum algorithm, achieving high-efficiency acceleration of computationally intensive operations during critical stages of algorithm execution.

[0035] For example, different types of hardware engines are used to execute different types of post-quantum cryptography algorithms. Different types of hardware engines in the hardware acceleration engine array are used to accelerate polynomial multiplication (including high-dimensional polynomial multiplication), multi-branch hash calculation, tree structure and sparse polynomial operations of post-quantum cryptography algorithms.

[0036] Step 202: During execution, the resources required by each hardware engine for the quantum cryptography algorithm are dynamically adjusted based on the prediction mechanism and fuzzy control logic. The resources include at least one of the following: number of cores, cache bandwidth, voltage, and frequency.

[0037] During the acceleration of post-quantum cryptography algorithms, key resource indicators such as the utilization rate of computing units and cache bandwidth occupancy are first collected in real time. Combined with a resource usage heatmap, a comprehensive understanding of the system's operation and resource distribution during the current acceleration process is formed. Then, based on prediction mechanisms and fuzzy control logic, at least one of the resources required by the hardware engine to execute the post-quantum cryptography algorithm—namely, the number of cores, cache bandwidth, voltage, and frequency—is dynamically adjusted.

[0038] For example, in the post-quantum cryptography algorithm acceleration process, key resource indicators such as computing unit utilization and cache bandwidth occupancy are first collected in real time. Combined with a resource usage heatmap, this provides a comprehensive understanding of the system's operation and resource distribution during the current acceleration process. Then, a multi-objective resource scheduling algorithm based on fuzzy logic control and prediction mechanisms is employed to optimize the allocation of computing cores, cache bandwidth adjustment, and voltage frequency scaling. In the fuzzy logic control process, fuzzy variables such as load thresholds and cache conflict rates are defined based on the key resource indicator data and the spatial distribution characteristics of the resource usage heatmap. Membership functions and multi-condition coupled fuzzy logic inference rules are constructed based on these fuzzy variables, such as "increase the number of cores and increase the voltage when there is high load and high conflict," and "maintain the core allocation and increase the cache bandwidth allocation while maintaining voltage stability when there is medium load and medium cache conflict." In the prediction process, a time series model is constructed using historical load data. Based on the previously constructed membership functions and multi-condition coupled fuzzy logic inference rules, dynamic parameter adjustments and fuzzy mapping are used to predict the resource demand for the next period, enabling advance adjustment of core allocation and reducing real-time scheduling latency. Ultimately, by dynamically optimizing the allocation of computing cores, adjusting cache bandwidth, and scaling voltage and frequency, a synergistic optimization is achieved between algorithm acceleration efficiency and system energy efficiency, avoiding the trade-offs caused by optimizing a single performance or energy efficiency indicator.

[0039] The aforementioned hardware-accelerated computing method based on post-quantum cryptography algorithms first employs each hardware engine in a hardware acceleration engine array to execute a corresponding type of post-quantum cryptography algorithm. This corresponding type of post-quantum cryptography algorithm includes at least one of polynomial multiplication, multi-branch hashing, tree structures, and sparse polynomial operations. Then, during the acceleration process, the resources required by each hardware engine to execute the post-quantum cryptography algorithm are dynamically adjusted based on a prediction mechanism and fuzzy control logic. These resources include at least one of the number of cores, cache bandwidth, voltage, and frequency. In other words, this application, on the one hand, uses hardware engines to accelerate the computation of post-quantum cryptography algorithms, improving their computational efficiency; on the other hand, it dynamically adjusts the resources required for computation based on a prediction mechanism and fuzzy control logic during acceleration, improving resource utilization and optimizing computation and energy efficiency control. Thus, a synergistic improvement in algorithm acceleration efficiency and performance can be achieved.

[0040] To ensure the security of cryptographic operations, appropriate security measures can be implemented on the chip when updating the post-quantum cryptographic algorithm.

[0041] In one exemplary embodiment, a side-channel protection circuit is also integrated on the chip. This side-channel protection circuit is used to counter side-channel attacks, enabling power consumption analysis protection and electromagnetic leakage suppression.

[0042] like Figure 3As shown, the hardware-accelerated computing method based on post-quantum cryptography algorithms also includes step 301:

[0043] Step 301: Implement security protection for the chip during standard updates or firmware upgrades of post-quantum cryptography algorithms.

[0044] The standard for post-quantum cryptography algorithms can be understood as a protocol and specification that is resistant to quantum computing attacks, determined through a standardized process.

[0045] The firmware of a post-quantum cryptography algorithm can be understood as the software code required to execute the post-quantum cryptography algorithm.

[0046] For example, a combination of secure boot (including verification of firmware integrity based on PUF root key and secure boot chain) and dynamic reconfiguration mechanism (including partial reconfiguration to update protection logic and reserved resources to ensure performance) can be used to achieve rapid detection and deployment of protection strategies against side-channel attacks during chip runtime. At the same time, it can adapt to the protocol upgrade requirements of post-quantum cryptography algorithms, and finally form a synergy between physical layer protection and dynamic security response, ensuring the balance between algorithm reliability and system energy efficiency in hardware acceleration scenarios, and enhancing the dynamic response capability to security threats during chip runtime.

[0047] Therefore, this example enhances the chip's resistance to physical attacks and ensures the security of cryptographic operations by using side-channel protection circuits and dynamic reconstruction mechanisms.

[0048] In one exemplary embodiment, such as Figure 4 As shown, step 201 includes steps 401 and 402:

[0049] Step 401: Determine the different data processing stages of the post-quantum cryptography algorithm.

[0050] Step 402: At different data processing stages, different types of hardware engines are used to execute the post-quantum cryptography algorithm for that stage.

[0051] The data processing stages can include key generation, encryption, decryption, signature generation, and signature verification. Different stages correspond to different hardware engines, and these different hardware engines perform different types of computations within the quantum cryptography algorithm.

[0052] Furthermore, such as Figure 5 As shown, step 402 includes steps 501 to 503. Wherein:

[0053] Step 501: Determine the hardware engine for the key generation, encryption, or decryption stage as a pipeline architecture and a modular multiplication algorithm unit. In this stage, the polynomial multiplication of the post-quantum cryptography algorithm is decomposed into multiple pipelines based on the pipeline architecture, and a single modular operation in each pipeline is performed using the modular multiplication algorithm unit.

[0054] For example, in the key generation, encryption, or decryption stages, firstly, based on a pipelined architecture, the large-dimensional polynomial multiplication is decomposed into a three-stage pipeline of "coefficient extraction - modular reduction - carry propagation"; then, based on the pipelined modular multiplication (Montgomery) algorithm unit, through preset multiplication factors and parallel modular reduction channels, the single modular operation in each pipeline is pre-computed for multiplication factor conversion, parallel modular reduction channel processing, and dynamic carry prediction optimization, so as to achieve nanosecond-level latency acceleration of preset large-dimensional polynomial multiplication and lattice basis reduction.

[0055] As one possible implementation, the pipelined modular multiplication (Montgomery) algorithm unit performs a single modular operation through the following steps:

[0056] (a) Pre-calculate multiplication factor conversion. Specifically, when performing modular arithmetic, i.e., x mod m (the remainder when x is divided by m), the constant R is pre-calculated and stored. −1 mod m multiplies the input x with this pre-calculated constant, where R is a power of 2 greater than m. After some shift operations, the result is the same as direct division (i.e., the remainder). In other words, modulo reduction is converted into multiplication-shift operations, avoiding the overhead of division.

[0057] (b) Parallel modular reduction channel processing: Specifically, through an 8-channel parallel structure, the modular reduction of different data blocks is processed simultaneously. Combined with pipeline scheduling, the single-channel latency is compressed to 1.8ns, which improves throughput and reduces latency.

[0058] (c) Dynamic carry prediction optimization, specifically using a carry-retaining adder array and a local carry prediction circuit to eliminate cross-dimensional carry delay.

[0059] Therefore, by decomposing the large-dimensional polynomial through a pipeline structure and modular multiplication algorithm unit and then calculating the single modular operation in each pipeline stage during the key generation, encryption, and decryption stages, the computational efficiency of the large-dimensional polynomial can be improved.

[0060] Step 502: Determine that the hardware engine for the signature generation or signature verification stage is a parallel hash compression engine and a Merkle tree accelerator. In this stage, the parallel hash compression engine is used to perform parallel computation of the multi-branch hash calculation of the post-quantum cryptography algorithm, and the Merkle tree accelerator is used to verify the tree structure of the post-quantum cryptography algorithm.

[0061] The parallel hash compression engine is used to perform parallel calculations on multiple hashes to improve hash calculation efficiency.

[0062] Merkle tree accelerators are used to verify the tree structure of quantum cryptography algorithms.

[0063] For example, during the signature generation or signature verification stage, based on the parallel hash compression engine and Merkle tree accelerator, the throughput of multi-branch hash calculation and fast tree structure verification is improved through multi-channel parallel hash calculation and collision detection data reuse, path caching and sibling node pre-computation, and dynamic load balancing.

[0064] Step 503: Determine that the hardware engine for the key generation or signature generation stage is a parallel matrix multiplier, and use the parallel matrix multiplier to calculate the sparse polynomial of the post-quantum cryptography algorithm in this stage.

[0065] A sparse polynomial is a polynomial with sparse coefficients.

[0066] For example, in the key generation or signature generation stage, a parallel matrix multiplier is used to accelerate sparse polynomial inversion through the following techniques:

[0067] (a) The sparse polynomial matrix is ​​decomposed into n×n (the value of n can be set according to the adaptation requirements, and this application does not limit it) sub-blocks. For each sub-block, the storage space of the sparse sub-block is compressed by CSR (Compressed Sparse Row) / CSC (Compressed Sparse Column) format, and fast polynomial convolution transformation processing is performed by the Winograd algorithm (including pre-computing the transformation matrix required by the Winograd algorithm and converting polynomial multiplication into dot product operation in the transformation domain based on these transformation matrices; including dynamic neighborhood pruning and local transformation of non-zero elements located by CSR / CSC to skip the all-zero region; and including modular reduction acceleration, that is, directly processing the dot product result in the transformation domain through the modular reduction unit to reduce intermediate storage overhead) to reduce the amount of computation of sparse polynomial inversion. Parallel matrix multipliers are used to perform sparse polynomial inversion calculation. It should be noted that the CSR format uses a three-array structure (such as a value array, a column index array, and a row pointer array) to store sparse matrices. The CSC format is similar to the CSR storage format, but it is specifically stored by column compression.

[0068] (b) A dynamic scheduling algorithm based on hardware counters is adopted to monitor the computational load of each sub-block in real time. By reusing data across blocks and optimizing pipeline filling, critical path bottlenecks are eliminated to improve the parallelism utilization of linear transformation.

[0069] Therefore, using a parallel matrix multiplier to compute sparse polynomials during the key generation and signature generation stages can improve the computational efficiency of sparse polynomials.

[0070] In one exemplary embodiment, such asFigure 6 As shown, step 202 includes steps 601 to 606:

[0071] Step 601: Collect key resource indicator data of the computational unit of the post-quantum cryptography algorithm, and predict the key resource indicator data for the next period based on the key resource indicator data and the resource usage heatmap to obtain the predicted value of the key resource indicator data.

[0072] Key resource metrics include data such as computing unit utilization and cache bandwidth usage. A resource usage heatmap, used to display resource usage at different times, is collected through deployed monitoring tools.

[0073] For example, key resource indicator data of the computational units of the post-quantum cryptography algorithm are collected in real time and combined with a resource usage heatmap for prediction, resulting in predicted values ​​of key resource indicator data for the next time period. These predicted values ​​can be output by a time series model, which is a statistical model built based on historical load data and can output predicted values ​​of key resource indicator data for the next time period, such as predicted CPU utilization and memory usage.

[0074] Step 602: Construct membership functions and multi-condition coupled fuzzy logic reasoning rules based on fuzzy variables.

[0075] Among them, fuzzy variables include load threshold and cache conflict rate, and multi-condition coupled fuzzy logic reasoning rules include membership degree and corresponding resource regulation actions. Resource regulation actions include adjustment actions for at least one of the following: number of cores, cache bandwidth, voltage and frequency.

[0076] For example, firstly, load thresholds (high / medium / low) and cache conflict rates (high / medium / low) are defined as fuzzy variables, and their fuzziness is quantified using a trapezoidal membership function, with each fuzzy variable corresponding to a membership function. Then, membership functions and multi-condition coupled fuzzy logic reasoning rules are constructed based on the defined fuzzy variables, such as "increase the number of cores and increase the voltage when there is high load and high conflict" and "maintain the core allocation and increase the cache bandwidth allocation while maintaining voltage stability when there is medium load and medium cache conflict". The "increase the number of cores and increase the voltage" and "maintain the core allocation and increase the cache bandwidth allocation while maintaining voltage stability" are the resource regulation actions.

[0077] Step 603: Substitute the predicted values ​​of key resource indicator data into the membership function based on fuzzy mapping to obtain the fuzzy set membership degree.

[0078] For example, by combining trapezoidal membership functions and Gaussian curve segments, a flexible and smooth fuzzy mapping of input variables (predicted values ​​of key resource indicator data) can be achieved. This allows the input variables to be accurately mapped to different fuzzy sets according to preset rules, and the change process of membership is natural and smooth. This can better simulate the way humans perceive and process fuzzy concepts, providing a more reasonable and accurate input basis for subsequent fuzzy reasoning and decision-making.

[0079] In one possible implementation, the predicted values ​​of key resource indicators (such as predicted CPU utilization and memory usage) are first used as fuzzy input variables. Then, the fuzzy input variables are converted into corresponding fuzzy set membership degrees based on the fuzzy mapping through the previously constructed membership function (such as mapping 75% CPU utilization to "high" membership degree of 0.8 and mapping 60% memory usage to "medium" membership degree of 0.2).

[0080] Step 604: Generate a fuzzy output set of the membership degree of each resource regulation action based on the fuzzy set membership degree and the fuzzy logic reasoning rules of multi-condition coupling.

[0081] For example, after obtaining the membership degrees of the fuzzy sets, inference is performed using fuzzy logic reasoning rules coupled with multiple conditions to generate a fuzzy output set. During inference, for rules containing "AND" logic, such as "If CPU utilization is 'high utilization' and memory usage is 'high memory usage,' then significantly increase resources," the smaller of the membership degrees of "CPU utilization is 'high utilization'" and "memory usage is 'high memory usage'" is taken as the overall membership degree of the rule's antecedent; for rules containing "OR" logic, such as "If CPU utilization is 'medium-low utilization' or memory usage is 'low memory usage,' then no resources are increased," the larger of the corresponding membership degrees is taken as the overall membership degree of the rule's antecedent.

[0082] Furthermore, based on pre-defined implication relationships (such as product implication) and combined with the overall membership degree of the rule antecedents, the impact of the rule on the output fuzzy sets such as "significantly increase resources" and "do not increase resources" is calculated. Finally, methods such as maximum-product synthesis are used to integrate all rule results and generate a fuzzy output set containing the membership degree of each resource regulation action, providing a basis for resource allocation decisions.

[0083] It should be noted that, during the inference process, considering that the dynamic fluctuations of the real-time load may cause the static membership function to fail, this application also minimizes the mean square error of the historical prediction error through the gradient descent method, so as to dynamically optimize the threshold and shape parameters of the membership function, so that the dynamic optimization of the membership function and the time series prediction model form a closed loop, and corrects the impact of the prediction error on fuzzy inference through gradient descent backpropagation.

[0084] Step 605: Calculate the centroid of the output fuzzy set based on the centroid method, and determine the resource requirements for the next time period based on the centroid.

[0085] The centroid method is a defuzzification method that obtains a precise output value by calculating the centroid (i.e., weighted average) of the fuzzy set. For the fuzzy output set, each element (resource regulation action) has a corresponding membership degree. By multiplying these element values ​​by their membership degrees, summing the results, and then dividing by the sum of the membership degrees, the precise value corresponding to the centroid can be obtained. This precise value can be used to determine the resource demand for the next time period.

[0086] Step 606: Based on the resource requirements of the next time period, adjust at least one of the following: the number of cores, cache bandwidth, voltage, and frequency required for each hardware engine to execute the quantum cryptography algorithm.

[0087] For example, regarding core allocation, the analysis is based on the type and scale of the computational tasks in the resource requirements. If the task is computationally intensive and requires high parallel processing capabilities, the number of cores is increased to improve computation speed, taking into account the current system's core utilization efficiency and load balancing. If the task is relatively simple or has low parallel requirements, the number of cores is appropriately reduced to avoid resource waste. For cache bandwidth adjustment, it is determined based on the frequency and pattern of data access in the resource requirements. If a large number of frequent data read / write operations are predicted in the next period, the cache bandwidth is increased to ensure fast data transmission and reduce data access latency. Conversely, if the data access volume is small, the cache bandwidth is reduced to save energy and resources. Regarding voltage and frequency scaling, both resource requirements and system power consumption constraints are considered. When resource requirements are high, the voltage and frequency are appropriately increased to improve processor performance and meet computational requirements. When resource requirements are low, the voltage and frequency are reduced to reduce power consumption and heat generation, achieving efficient energy utilization. By comprehensively balancing these three aspects, the optimal allocation of system resources is achieved, improving overall system performance and energy efficiency.

[0088] Therefore, based on the prediction mechanism and fuzzy control logic, a fuzzy output set of the membership degree of each resource regulation action is generated. Then, based on the fuzzy output set, the resource demand for the next period is obtained. According to the resource demand, the number of cores, cache bandwidth, voltage and frequency are dynamically adjusted in advance, which can reduce or avoid resource waste, improve resource utilization, and thus optimize the overall computing energy efficiency.

[0089] Further, step 603 includes: performing fuzzy mapping using the following formula:

[0090]

[0091] Where x represents the input variable, Let x represent the membership degree of fuzzy set A, and let a, b, c, and d represent the left boundary start point, left boundary end point, right boundary start point, and right boundary end point of the trapezoidal membership function, respectively. , This parameter controls the width of the Gaussian curve.

[0092] Based on the above formula, it should be noted that the trapezoidal structure defined by the four points a, b, c, and d determines the boundary and core region of the fuzzy set. Where: 1) 1) The region outside the left boundary has a membership degree of 0, indicating that the input value does not belong to the fuzzy set A at all; 2) [a,b] represents the first transition region, and the membership degree of this region is determined by the Gaussian curve segment. Calculations show that as x approaches b, the membership degree gradually increases, achieving a smooth transition from 0 to 1; 3) [b,c] represents the core region, where the membership degree is always 1, indicating that the input value completely belongs to the fuzzy set A, forming the core region of the fuzzy set; 4) [c,d] represents the second transition region, where the membership degree is determined by a Gaussian curve segment. Calculations show that as x moves further away from c, the membership degree gradually decreases, achieving a smooth transition from 1 to 0; 5) This represents the region outside the right boundary. The membership degree of this region is 0, indicating that the input value x does not belong to the fuzzy set A at all.

[0093] It should be noted that using Gaussian curve segments to calculate membership degrees in the transition region makes the changes in membership degrees smoother and more natural. Through this piecewise mapping, the input variable x is transformed into a membership degree value. This represents the degree to which x belongs to the fuzzy set A. This fuzzification process can convert precise input values ​​into fuzzy concepts, facilitating subsequent fuzzy reasoning and decision-making.

[0094] From the above formula, we can derive:

[0095] If the predicted value of the key resource indicator data is less than or equal to the starting point 'a' of the left boundary of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 0, that is, the prediction does not belong to the fuzzy set.

[0096] If the predicted value of the key resource indicator data is greater than the starting point 'a' of the left boundary of the trapezoidal membership function and less than or equal to the ending point 'b' of the left boundary of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined as the first membership degree value. The first membership value is determined based on the predicted value x of the key resource indicator data, the left boundary endpoint b of the trapezoidal membership function, and the width parameter of the Gaussian curve. Calculated.

[0097] If the predicted value of the key resource indicator data is greater than the left boundary endpoint b of the trapezoidal membership function and less than or equal to the right boundary starting point c of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 1.

[0098] If the predicted value of the key resource indicator data is greater than the starting point of the right boundary of the trapezoidal membership function and less than or equal to the ending point of the right boundary of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined as the second membership degree value. The second membership value is based on the predicted value x of the key resource indicator data, the starting point c of the right boundary of the trapezoidal membership function, and the width parameter of the Gaussian curve. Calculated;

[0099] If the predicted value of the key resource indicator data is greater than the right boundary endpoint of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 0, that is, the predicted value does not belong to the fuzzy set.

[0100] Therefore, fuzzification can convert precise input values ​​into fuzzy concepts, which facilitates subsequent fuzzy reasoning and decision-making.

[0101] In one possible implementation, such as Figure 7 As shown, step 605 may include steps 701 to 703. Wherein:

[0102] Step 701: Extract the specific description information of each resource regulation action and its corresponding membership value from the fuzzy output set.

[0103] Step 702: Using the extracted resource regulation actions as discrete points and their membership values ​​as weights, perform weighted averaging according to the centroid method to obtain the centroid of the output fuzzy set.

[0104] For example, each resource control action is first assigned a numerical representation (e.g., "slightly increase the number of computing cores" is represented as 1, "maintain the current number of computing cores" as 0, "slightly decrease the number of computing cores" as -1, etc.), and then the weighted average of these discrete points is calculated according to the centroid method formula to obtain the centroid value. This centroid value reflects the system's overall resource control tendency under the current fuzzy inference results.

[0105] Step 703: Determine the resource requirements for the next time period based on the centroid.

[0106] For example, in addition to the centroid value, this example also considers several related factors, such as the current task load type of the system (compute-intensive, data-intensive, etc.), task priority, and the system's energy budget. By assigning corresponding weights to each related factor, a weighted comprehensive evaluation method is used to determine the extent of resource adjustments. For example, for compute-intensive tasks, when the centroid value indicates that additional resources are needed, the number of compute cores will be increased first; while for data-intensive tasks, the focus is more on increasing cache bandwidth. At the same time, if the system's energy budget is tight, energy-saving resource adjustment schemes will be selected as much as possible while meeting basic performance requirements. By combining all the above factors and their corresponding weights with the centroid value, the resource requirements for the next time period are finally determined.

[0107] Therefore, determining the resource demand for the next period by using the centroid value can improve the accuracy of resource demand determination.

[0108] When performing accelerated computing, it is also necessary to ensure the safe operation of the chip and adapt to the protocol upgrade requirements of the post-quantum cryptography algorithm, namely step 301, to provide security protection for the chip when the standard of the post-quantum cryptography algorithm is updated or the firmware is upgraded.

[0109] In one exemplary embodiment, such as Figure 8 As shown, step 301 includes steps 801 and 802:

[0110] Step 801: During the standard update of the post-quantum cryptography algorithm, the circuit modules on the chip related to algorithm security adaptation are updated through reconstruction technology.

[0111] For example, when the standard for post-quantum cryptography algorithms (a specification for cryptographic algorithms designed to resist quantum computer attacks) is updated, partial reconstruction techniques and dynamic reconstruction engines are used to locate and update circuit modules directly related to algorithm security adaptation. This allows only the circuit modules related to algorithm security adaptation to be updated, without requiring a full system restart. Examples include: adjusting the protection level of the modular arithmetic unit (e.g., increasing the noise injection strength to protect the key generation phase of the new algorithm); modifying the bus encoding rules (e.g., switching from fixed encoding to randomized encoding to adapt to the data transmission characteristics of the new algorithm); and updating side-channel protection parameters (e.g., adjusting the frequency-selective surface of the electromagnetic shielding layer to suppress electromagnetic leakage during the computation phase of the new algorithm).

[0112] Step 802: During the firmware upgrade of the post-quantum cryptography algorithm, a unique root key for the chip is generated based on the physical non-cloning function, and the upgraded firmware of the post-quantum cryptography algorithm is digitally signed and verified based on the unique root key. The various stages of the boot image are verified step by step through the hardware security boot chain.

[0113] For example, during the protocol upgrade process, a unique root key for the chip is generated based on a physically unclonable function. Specifically, this utilizes random physical characteristics introduced during chip manufacturing (such as gate delay and transistor threshold voltage differences) and is generated via a PUF arbitrator. The upgraded new algorithm firmware (such as the Kyber signature library) is signed by a trusted party (such as NIST) using the public key portion of the root key. Upon chip startup, the private key portion of the root key is used to decrypt and verify the new algorithm firmware and its signature file. If the signature matches, the firmware's origin is confirmed to be trustworthy and untampered; if it does not match, loading is refused and a security alarm is triggered. The hardware security boot chain then verifies each stage of the boot image process step-by-step, such as Boot ROM (Read-Only Memory) → Secure Monitor → OS (Operating System). Each level uses the key of the previous level for decryption and integrity verification, forming a chain of trust transfer to ensure that the new protocol's code is not maliciously injected from the bottom layer to the application layer.

[0114] This ensures that the code of the new protocol has not been tampered with, prevents malicious code injection attacks, and enhances the chip's dynamic response capability to security threats during operation through secure boot and dynamic reconfiguration mechanisms.

[0115] The above describes the process of hardware-accelerated computing based on post-quantum cryptography algorithms applied to chips. It is implemented using a hardware acceleration engine array. In practical applications, the performance of the hardware acceleration engine array can be monitored and analyzed.

[0116] In one exemplary embodiment, the method further includes collecting operational status index parameters of the hardware acceleration engine array; evaluating the computational efficiency of the hardware acceleration engine based on the operational status index parameters; and optimizing the hardware resources of each hardware engine in the hardware acceleration engine based on the evaluation results.

[0117] For example, when the hardware acceleration engine array executes the post-quantum cryptography algorithm, the operational status parameters of the hardware acceleration engine array are monitored in real time. These operational status parameters include the number of computation cycles, cache hit rate, and instruction parallelism. Based on these operational status parameters, a performance evaluation model is constructed to assess the computational efficiency of the engines. The hardware resource allocation strategy for each hardware engine is then optimized based on the evaluation results. This performance evaluation model is a comprehensive weighted model that takes the operational status parameters—computation cycles, cache hit rate, and instruction parallelism—as input parameters and assigns different weights to each parameter. Through weighted comprehensive calculation, a performance evaluation score reflecting the engine's computational efficiency is obtained.

[0118] It's important to note that different operational metrics during the operation of the hardware acceleration engine array reflect the utilization of hardware resources. For example, a long computation cycle count may indicate excessive load on computing units, while a low cache hit rate may suggest insufficient cache resources. By constructing a performance evaluation model and comprehensively analyzing these metrics to obtain a computational efficiency assessment result, hardware resource allocation can be optimized in a targeted manner. For instance, idle cache resources can be allocated to engines with low cache hit rates, or computing cores can be added to engines with long computation cycles, thereby improving overall computational efficiency and resource utilization.

[0119] Therefore, by monitoring the operating status of the hardware acceleration engine in real time and optimizing its computing resources, the computing efficiency and resource utilization of the hardware acceleration engine array are improved through dynamic optimization, achieving a synergistic improvement in computing efficiency and performance.

[0120] In a specific application, such as Figure 9 As shown, the hardware-accelerated computing method based on post-quantum cryptography algorithms may include the following steps:

[0121] Step 901: The hardware engines in the hardware acceleration engine array are used to perform polynomial multiplication, multi-branch hash calculation, tree structure and sparse polynomial operation of the post-quantum cryptography algorithm.

[0122] Step 902: During the accelerated processing, the number of cores, cache bandwidth, voltage and frequency required by each hardware engine to execute the quantum cryptography algorithm are dynamically adjusted based on the prediction mechanism and fuzzy control logic.

[0123] Step 903: Integrate side-channel attack protection circuitry, and provide security protection for the chip through secure boot and dynamic reconstruction mechanisms during standard updates or firmware upgrades of post-quantum cryptography algorithms.

[0124] Step 904: Collect the operating status indicators of the hardware acceleration engine array.

[0125] Step 905: Evaluate the computational efficiency of the hardware acceleration engine based on the running status index parameters, and optimize the hardware resources of each hardware engine in the hardware acceleration engine according to the evaluation results.

[0126] Steps 901 to 905 above correspond to the corresponding steps mentioned above and have been described in detail, so they will not be repeated here.

[0127] In this application, on the one hand, by integrating a hardware acceleration engine array adapted to post-quantum cryptography algorithms, combined with pipelined architecture, modular arithmetic, and parallel computing engines, the computational efficiency of post-quantum cryptography algorithms such as lattice theory, hash signatures, and multivariable polynomials is significantly improved. On the other hand, based on real-time load and fuzzy logic control, the allocation of computing cores and energy efficiency regulation are optimized, achieving a synergistic improvement in algorithm acceleration efficiency and system energy efficiency. Simultaneously, the chip's resistance to physical attacks is enhanced based on side-channel protection circuits and dynamic reconstruction mechanisms, ensuring the security of cryptographic operations. In summary, this application, while ensuring efficient post-quantum cryptography processing, also considers low-power operation and proactive security protection, providing a comprehensive solution with high performance, high energy efficiency, and high security to address quantum computing threats, meeting the needs of application scenarios with high real-time requirements.

[0128] Based on the same inventive concept, this application also provides a hardware-accelerated computing system based on a post-quantum cryptography algorithm for implementing the aforementioned hardware-accelerated computing method based on post-quantum cryptography algorithms. The solution provided by this system is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more system embodiments provided below can be found in the limitations of the hardware-accelerated computing method based on post-quantum cryptography algorithms described above, and will not be repeated here.

[0129] In one exemplary embodiment, such as Figure 10 As shown, a hardware-accelerated computing system based on a post-quantum cryptography algorithm is provided, including: an execution module 1001 and an adjustment module 1002. Wherein:

[0130] The execution module 1001 is used to execute the corresponding type of post-quantum cryptography algorithm using each hardware engine in the hardware acceleration engine array, wherein the corresponding type of post-quantum cryptography algorithm includes at least one of polynomial multiplication, multi-branch hash calculation, tree structure and sparse polynomial operation.

[0131] The adjustment module 1002 is used to dynamically adjust the resources required by each hardware engine for the quantum cryptography algorithm after execution based on the prediction mechanism and fuzzy control logic during the execution process. The resources include at least one of the following: number of cores, cache bandwidth, voltage and frequency.

[0132] In one embodiment, the chip also integrates a side-channel protection circuit, and the system further includes a security protection module for providing security protection for the chip during standard updates or firmware upgrades of post-quantum cryptography algorithms.

[0133] In one embodiment, the execution module 1001 includes a determining unit and an execution unit. The determining unit is used to determine different data processing stages of the post-quantum cryptography algorithm; the execution unit is used to execute the corresponding type of post-quantum cryptography algorithm for each data processing stage using a different type of hardware engine.

[0134] In one embodiment, the execution unit is specifically configured to: determine that the hardware engine for the key generation, encryption, or decryption stage is a pipeline architecture and a modular multiplication algorithm unit, and in this stage, decompose the polynomial multiplication of the post-quantum cryptography algorithm into multiple pipelines based on the pipeline architecture, and use the modular multiplication algorithm unit to perform a single modular operation in each pipeline; determine that the hardware engine for the signature generation or signature verification stage is a parallel hash compression engine and a Merkle tree accelerator, and in this stage, use the parallel hash compression engine to perform parallel computation of the multi-branch hash computation of the post-quantum cryptography algorithm, and use the Merkle tree accelerator to verify the tree structure of the post-quantum cryptography algorithm; determine that the hardware engine for the key generation or signature generation stage is a parallel matrix multiplier, and in this stage, use the parallel matrix multiplier to compute the sparse polynomial of the post-quantum cryptography algorithm.

[0135] In one embodiment, the execution module 1002 includes: a prediction unit, a construction unit, a mapping unit, a generation unit, a determination unit, and an adjustment unit. The system comprises: a prediction unit, used to collect key resource indicator data of the computational unit of the post-quantum cryptography algorithm, and predict the key resource indicator data for the next period based on the key resource indicator data and resource usage heatmap, obtaining predicted values ​​of the key resource indicator data; a construction unit, used to construct membership functions and multi-condition coupled fuzzy logic inference rules based on fuzzy variables, where fuzzy variables include load threshold and cache conflict rate, and multi-condition coupled fuzzy logic inference rules include membership degrees and corresponding resource control actions, where resource control actions include adjustments to at least one of the number of cores, cache bandwidth, voltage, and frequency; a mapping unit, used to substitute the predicted values ​​of key resource indicator data into the membership function based on fuzzy mapping to obtain fuzzy set membership degrees; a generation unit, used to generate fuzzy output sets of membership degrees for each resource control action based on fuzzy set membership degrees and multi-condition coupled fuzzy logic inference rules; a determination unit, used to calculate the centroid of the output fuzzy set based on the centroid method, and determine the resource requirements for the next period based on the centroid; and an adjustment unit, used to adjust at least one of the number of cores, cache bandwidth, voltage, and frequency required by each hardware engine to execute the post-quantum cryptography algorithm based on the resource requirements for the next period.

[0136] In one embodiment, the security protection module includes an update unit and a verification unit. Specifically: the update unit is used to update the circuit modules on the chip related to algorithm security adaptation using reconstruction technology during standard updates of the post-quantum cryptography algorithm; the verification unit is used to generate a unique root key for the chip based on a physically non-cloning function during firmware upgrades of the post-quantum cryptography algorithm, perform digital signature verification on the upgraded firmware of the post-quantum cryptography algorithm based on the unique root key, and verify each stage of the boot image step-by-step through a hardware secure boot chain.

[0137] In one embodiment, the system further includes a data acquisition module and an optimization module, wherein: the data acquisition module is used to acquire the operating status index parameters of the hardware acceleration engine array; the optimization module is used to evaluate the computational efficiency of the hardware acceleration engine based on the operating status index parameters, and optimize the hardware resources of each hardware engine in the hardware acceleration engine according to the evaluation results.

[0138] The modules in the aforementioned hardware-accelerated computing system based on post-quantum cryptography algorithms can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

Claims

1. A hardware-accelerated computing method based on post-quantum cryptography algorithms, applied to a chip, characterized in that, The chip includes a hardware acceleration engine array, which includes different types of hardware engines. The method includes: Each hardware engine in the hardware acceleration engine array executes a corresponding type of post-quantum cryptographic algorithm, wherein the corresponding type of post-quantum cryptographic algorithm includes at least one of polynomial multiplication, multi-branch hash calculation, tree structure and sparse polynomial operation; During the execution process, the resources required by each hardware engine to execute the quantum cryptography algorithm are dynamically adjusted based on the prediction mechanism and fuzzy control logic. The resources include at least one of the following: number of cores, cache bandwidth, voltage, and frequency.

2. The method according to claim 1, characterized in that, The chip also integrates a side-channel protection circuit, and the method further includes: The chip is protected against standard updates or firmware upgrades in post-quantum cryptography algorithms.

3. The method according to claim 1, characterized in that, The execution of corresponding types of post-quantum cryptography algorithms by each hardware engine in the hardware acceleration engine array includes: The different data processing stages of the post-quantum cryptography algorithm are determined; Different types of hardware engines are used to execute the corresponding type of post-quantum cryptography algorithm at different data processing stages.

4. The method according to claim 1, characterized in that, The process of using different hardware engines to execute corresponding types of post-quantum cryptography algorithms at different data processing stages includes: The hardware engine for the key generation, encryption, or decryption stage is determined to be a pipeline architecture and a modular multiplication algorithm unit. In this stage, the polynomial multiplication of the post-quantum cryptography algorithm is decomposed into multi-stage pipelines based on the pipeline architecture, and the modular multiplication algorithm unit is used to perform a single modular operation in each stage of the pipeline. The hardware engine for the signature generation or signature verification stage is determined to be a parallel hash compression engine and a Merkle tree accelerator. In this stage, the parallel hash compression engine is used to perform parallel computation of the multi-branch hash calculation of the post-quantum cryptography algorithm, and the Merkle tree accelerator is used to verify the tree structure of the post-quantum cryptography algorithm. The hardware engine for the key generation or signature generation stage is determined to be a parallel matrix multiplier, and the parallel matrix multiplier is used to compute the sparse polynomial of the post-quantum cryptography algorithm in this stage.

5. The method according to claim 1, characterized in that, The dynamic adjustment of resources required by each hardware engine to execute the quantum cryptography algorithm based on prediction mechanisms and fuzzy control logic includes: After collecting the key resource indicator data of the computing unit of the quantum cryptography algorithm, the key resource indicator data for the next period is predicted based on the key resource indicator data and the resource usage heatmap, and the predicted value of the key resource indicator data is obtained. The fuzzy logic reasoning rules are constructed based on membership functions and multi-condition coupling, wherein the fuzzy variables include load threshold and cache conflict rate, and the multi-condition coupling fuzzy logic reasoning rules include membership degree and corresponding resource adjustment actions, and the resource adjustment actions include adjustment actions for at least one of the following: number of cores, cache bandwidth, voltage and frequency. Based on fuzzy mapping, the predicted values ​​of the key resource indicator data are substituted into the membership function to obtain the fuzzy set membership degree; Based on the fuzzy set membership degree and the fuzzy logic reasoning rule of multi-condition coupling, a fuzzy output set of membership degree for each resource regulation action is generated; The centroid of the output fuzzy set is calculated based on the centroid method, and the resource requirements for the next time period are determined based on the centroid. Based on the resource requirements of the next time period, at least one of the following factors is adjusted for each hardware engine: number of cores, cache bandwidth, voltage, and frequency required to execute the quantum cryptography algorithm.

6. The method according to claim 5, characterized in that, The membership function is a trapezoidal membership function. The step of substituting the predicted values ​​of the key resource indicator data into the membership function based on fuzzy mapping to obtain the fuzzy set membership includes: If the predicted value of the key resource indicator data is less than or equal to the starting point of the left boundary of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 0. If the predicted value of the key resource indicator data is greater than the starting point of the left boundary of the trapezoidal membership function and less than or equal to the ending point of the left boundary of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined as the first membership degree value. The first membership degree value is calculated based on the predicted value of the key resource indicator data, the ending point of the left boundary of the trapezoidal membership function, and the width parameter of the Gaussian curve. If the predicted value of the key resource indicator data is greater than the left boundary endpoint of the trapezoidal membership function and less than or equal to the right boundary starting point of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 1. If the predicted value of the key resource indicator data is greater than the starting point of the right boundary of the trapezoidal membership function and less than or equal to the ending point of the right boundary of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined as the second membership degree value. The second membership degree value is calculated based on the predicted value of the key resource indicator data, the starting point of the right boundary of the trapezoidal membership function, and the width parameter of the Gaussian curve. If the predicted value of the key resource indicator data is greater than the right boundary endpoint of the trapezoidal membership function, then the fuzzy set membership degree of the predicted value of the key resource indicator data is determined to be 0.

7. The method according to claim 5, characterized in that, The process of calculating the centroid of the output fuzzy set based on the centroid method, and determining the resource requirements for the next time period based on the centroid, includes: Extract the specific description information of each resource regulation action and its corresponding membership value from the fuzzy output set; Using the extracted resource regulation actions as discrete points and their membership values ​​as weights, a weighted average is performed according to the centroid method to obtain the centroid of the output fuzzy set. The resource requirements for the next time period are determined based on the centroid.

8. The method according to claim 2, characterized in that, The security protection for the chip during post-quantum cryptography algorithm standard updates or firmware upgrades includes: During the standard update of post-quantum cryptography algorithms, the circuit modules on the chip related to algorithm security adaptation are updated through reconstruction technology. During firmware upgrades for post-quantum cryptography algorithms, a unique root key for the chip is generated based on a physically non-cloning function. The upgraded firmware is then digitally signed and verified using this unique root key. Finally, the boot image is verified step-by-step through a hardware security boot chain.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: Collect the operating status parameters of the hardware acceleration engine array; The computational efficiency of the hardware acceleration engine is evaluated based on the aforementioned operational status indicators, and the hardware resources of each hardware engine within the hardware acceleration engine are optimized based on the evaluation results.

10. A hardware-accelerated computing system based on post-quantum cryptography algorithms, applied to a chip, characterized in that, The chip includes a hardware acceleration engine array, which includes different types of hardware engines; the system includes: An execution module is used to execute a corresponding type of post-quantum cryptographic algorithm using each hardware engine in the hardware acceleration engine array, wherein the corresponding type of post-quantum cryptographic algorithm includes at least one of polynomial multiplication, multi-branch hash calculation, tree structure and sparse polynomial operation; An adjustment module is used to dynamically adjust the resources required by each hardware engine for the quantum cryptography algorithm after execution, based on a prediction mechanism and fuzzy control logic, during the execution process. The resources include at least one of the following: number of cores, cache bandwidth, voltage, and frequency.

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