High-on-off-ratio inverted ferroelectric capacitive memory based on silicon-on-insulator substrate and preparation method of high-on-off-ratio inverted ferroelectric capacitive memory
By thinning the top silicon channel and forming a heavily doped N+ region in an inverse ferroelectric capacitor memory, the problem of low capacitor on/off ratio is solved, realizing a memory structure with high capacitance ratio and low power consumption, which is suitable for high-precision, high-density in-memory computing chips.
Patent Information
- Application Number
- CN202511136942.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2025-11-18
AI Technical Summary
The capacitance switching ratio of existing inverse ferroelectric capacitor memory is generally low, which affects the distinguishability and reliability of the stored state and limits its practical application in high-precision, high-density memory-computing fusion chips.
A high on/off ratio inverse ferroelectric capacitor memory structure based on silicon-on-insulator substrate is adopted. By reducing the thickness of the top silicon channel from 10 micrometers to 10 nanometers and forming a heavily doped N+ region below the ferroelectric layer, combined with high-temperature annealing to form ohmic contacts, a significant difference between the high capacitance state and the low capacitance state is achieved, and the capacitance ratio is increased to over 4000.
It significantly improves the capacitor switching ratio, achieving low power consumption, nanosecond-level operation speed and high integration, and is suitable for high-density multi-value storage and high-energy-efficiency multiply-accumulate operation chips.
Smart Images
Figure CN120980891A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of semiconductors, and particularly relates to a high on-off ratio anti-ferroelectric capacitor type memory based on a silicon-on-insulator substrate and a preparation method. BACKGROUND
[0002] Under the drive of information technology such as the Internet of Things, massive data processing poses a severe challenge to traditional computing architecture. Developing new computing and storage devices and chip technologies with high integration density, low power consumption, high computing power, and high energy efficiency for non-Von Neumann architecture has become a key to breaking through the existing technical bottlenecks.
[0003] At present, a memristor with storage and computing fusion capability is one of the important technical paths to achieve this goal. However, the inherent read current or leakage current of the memristor will inevitably cause static power consumption, which seriously restricts its energy efficiency performance and limits large-scale integrated applications.
[0004] To overcome the problem of static power consumption, researchers have proposed a capacitor type memory as a promising alternative. Based on the charge storage mechanism of the capacitor, there is no direct current path in the non-reading and writing state in theory, thereby basically eliminating static power consumption and providing the possibility of ultra-low power storage and computing. Among them, the anti-ferroelectric capacitor type memory is attracting the research community to accelerate its engineering landing due to its excellent operating speed, high energy efficiency, good reliability, excellent scalability, and high compatibility with advanced CMOS processes.
[0005] However, the current research on anti-ferroelectric capacitor type memory is still in the relatively early stage, and the achievements are limited. In particular, the existing anti-ferroelectric capacitor type memory has a generally low capacitance on-off ratio, which seriously affects the distinguishability and reliability of the storage state and becomes a major obstacle to its practical application in high-precision and high-density computing and storage integrated chips.
[0006] Conventional ferroelectric capacitor type memories mainly adopt two structures of MFM (metal-ferroelectric-metal) or MFS (metal-ferroelectric-semiconductor). The MFM unit has a limited change in ferroelectric dielectric constant, and the capacitance on-off ratio is usually compressed between 1-2, which is difficult to meet the needs of multi-value storage and high-precision multiplication and addition operations; the MFS structure can output high and low capacitances by means of the anti-type and depletion states of the semiconductor channel, and obtain an observable capacitance window at 0V by relying on the shift of the C-V curve of the ferroelectric polarization, but the high capacitance is limited by the physical limit of the equivalent oxide layer thickness of the gate dielectric, and the improvement space is limited, resulting in a low capacitance ratio.
[0007] In summary, whether it is an MFM structure or a conventional MFS structure, the existing ferroelectric capacitor type memory has the technical bottlenecks of low capacitance switching ratio and insufficient capacitance window resolution, which seriously limits its large-scale application and industrialization landing in the field of high-precision, high-density, low-power consumption storage and computing chip. SUMMARY
[0008] In order to overcome the deficiencies of the prior art, the purpose of the present application is to provide a high switching ratio inverted ferroelectric capacitor type memory based on a silicon-on-insulator substrate and a preparation method, which precisely compresses the low capacitance state with an ultra-thin top layer of silicon, breaks through the EOT limit, and significantly improves the capacitance ratio, while considering high integration and low power consumption, which is significantly better than existing MFM and conventional MFS devices, and provides a feasible path for multi-value storage and high-energy-efficient storage and computing chips.
[0009] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is:
[0010] A high switching ratio inverted ferroelectric capacitor type memory based on a silicon-on-insulator substrate, comprising a bottom buried oxygen layer and a top channel layer covering the top of the bottom buried oxygen layer, a ferroelectric layer covering the top left side of the top channel layer, a top electrode covering the top of the ferroelectric layer, a bottom electrode covering the top right side of the top channel layer, and the ferroelectric layer and the bottom electrode not being in contact;
[0011] The top channel layer below the bottom electrode is a heavily doped N + region formed after ion implantation, with a doping peak concentration of 1x10 20 cm -3 The top channel layer below the ferroelectric layer is a lightly doped thin silicon, uniformly doped, with a doping concentration of 1x10 15 cm -3 .
[0012] The thickness of the top silicon of the top channel layer is changed from 10 microns to 10 nanometers.
[0013] The bottom buried oxygen layer and the top channel layer form a silicon-on-insulator, the material of the bottom buried oxygen layer is SiO2, and the top channel layer is any one of Si, Ge, SiC, SiGe, GaN;
[0014] The ferroelectric material of the ferroelectric layer is any one of Hf 0.5 Zr 0.5 O2(HZO), HAO, HYO, HSO, PZT, BFO, AlScN;
[0015] The top electrode and the bottom electrode use any one of tungsten, titanium, platinum, aluminum, titanium nitride, tantalum nitride, titanium carbide, tantalum carbide, and tungsten carbide.
[0016] The top channel below the bottom electrode forms N through self-aligned implantation of arsenic or phosphorus ions by the top electrode. + The heavily doped region forms an ohmic contact between the top channel and the bottom electrode after high-temperature annealing;
[0017] The top channel and the ferroelectric layer are connected by a conformal interface formed by atomic layer deposition (ALD); the ferroelectric layer and the top electrode are connected by a Schottky contact formed by magnetron sputtering; the bottom electrode and the top electrode are isolated by photolithography-dry etching to prevent the formation of parasitic conductive paths. The ferroelectric layer and the top channel constitute a high on / off ratio inverse ferroelectric capacitor structure. Under 0V bias, when the ferroelectric polarization direction of the ferroelectric layer is upward, a strong inversion (electron accumulation) is formed on the surface of the top channel, and the device is in a high capacitance state HCS (≈C). FE When the polarization direction reverses downwards, the depletion layer at the interface between the light P-type dopant and the heavy N+ type dopant widens, and the device is in an extremely low capacitance state (LCS≈C). dep +C ov ≈C dep Through ultra-thin top-layer channels, the LCS is compressed to less than 1 / 40 of its original value, while the HCS remains essentially unchanged, achieving C ratio A high switching ratio of >4000; this structure enables non-volatile high and low capacitance readings at 0V, exhibiting ultra-high switching ratio characteristics.
[0018] The thickness of the ultrathin top channel is 10 nanometers.
[0019] A method for fabricating a high on / off ratio inverse ferroelectric capacitor memory based on a silicon-on-insulator substrate, wherein the substrate material is selected from, but not limited to, silicon (Si), includes the following steps;
[0020] Step 1): Select an SOI wafer with a top channel containing a buried oxide layer and lightly doped thin silicon as the substrate;
[0021] Step 2): A ferroelectric layer is deposited on top of the top trench using a deposition process;
[0022] Step 3): Deposit electrode material on the surface of the ferroelectric layer by magnetron sputtering to form the top electrode required for subsequent operations;
[0023] Step 4): The top electrode and the underlying ferroelectric layer are patterned using photolithography and dry etching, retaining only the predetermined area on the left and completely removing the rest, thereby defining the geometric contour of the top electrode of the device.
[0024] Step 5): Use ion implantation to introduce a high dose of doping under the top channel silicon layer that is not covered by the top electrode to construct a heavily doped region;
[0025] Step 6): electrode material is deposited on the exposed top channel on the right side again by a sputtering process to form a bottom electrode; finally, rapid thermal annealing is performed in an inert atmosphere, on the one hand to induce crystallization of the ferroelectric layer, and on the other hand, after high-energy ion implantation, most of the ions are in interstitial positions and have low electrical activity, rapid thermal annealing makes impurity atoms move into substitutional sites, the electrical activity is increased, and the contact resistance is significantly reduced to ensure ohmic contact, thereby completing the preparation of the high-capacitance-ratio reverse-type ferroelectric capacitor.
[0026] In the step 5), the high-dose doping is specifically: using arsenic ions (As + ) or phosphorus ions (P + ) implantation, the dose is 1×10 15 ~1×10 16 cm -2 , the energy is 20~50keV, the implantation angle is 7°, so as to form a heavily doped N + region with a square resistance of <100Ω-1 under the top channel silicon layer not covered by the top electrode.
[0027] In the step 6), the limited conditions of rapid thermal annealing in an inert atmosphere are: the annealing atmosphere is N2, Ar or a mixed gas thereof, the oxygen content is <1ppm; the heating rate is ≥50℃ / s -1 , the peak temperature is 600~900℃, the peak holding time is 100~300s, and then it is cooled to room temperature at a rate of ≥30℃ / s -1 , so as to ensure that the ferroelectric layer is fully crystallized and ohmic contact is formed between the bottom electrode and the channel by ion implantation activation.
[0028] The beneficial effects of the present application are:
[0029] The present application precisely thins the SOI top layer silicon channel from microns to 10 nanometers, and for the first time realizes a capacitance switching ratio of more than 4000 in the MFS reverse-type capacitor structure, far exceeding the level of 2~200 switching ratio of existing MFM or conventional MFS devices.
[0030] The preparation process only adds one step of SOI thinning and one step of ion implantation, which is fully compatible with the CMOS back-end process and has high wafer-level uniformity.
[0031] The structure has no direct current leakage, sub-fJ level write energy consumption, nanosecond level operation speed and 10nm scalability, and provides a feasible new path for high-density multi-value storage and high-energy-efficient multiplication and addition operation chips. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 The physical mechanism of the reverse-type ferroelectric capacitor type memory of the present application in the high-capacitance state and the low-capacitance state.
[0033] Figure 2To verify through simulation that as the substrate thickness decreases, the depletion capacitance decreases, and the capacitance ratio of the inverse ferroelectric capacitor memory increases.
[0034] Figure 3 Schematic diagram and simulation verification for achieving extremely low capacitance by reducing substrate thickness.
[0035] Figure 4 This describes the fabrication process of the high capacitance ratio inverse ferroelectric capacitor memory of the present invention. Detailed Implementation
[0036] The present invention will now be described in further detail with reference to the accompanying drawings.
[0037] Figure 1 The physical mechanism of the inverse ferroelectric capacitor of the present invention under high capacitance state (HCS) and low capacitance state (LCS);
[0038] Combination Figure 4 (f) illustrates the device structure. When the ferroelectric layer 102 is polarized downwards, the high-capacitance state HCS is determined by the intrinsic capacitance C of the ferroelectric layer 102. FE C, the heavily doped overlap region under the top electrode 103 ov Parallel connection, because C ov Numerically significantly smaller than C FE In the high-capacitance state, HCS is mainly composed of C FE The thickness of the ferroelectric layer 102 directly determines the C when the ferroelectric layer 102 is polarized upwards. The top channel 101 of the ultrathin SOI channel is completely depleted under the influence of the ferroelectric field of the ferroelectric layer 102. dep And C dep Also much smaller than C FE In the low-capacitance state, the capacitance of the LCS is approximately equal to C. dep With C ov The sum. Therefore, increasing the capacitor switching ratio C ratio (C ratio There are two paths to improving the capacitance (HCS / LCS): one is to increase the high-capacitance HCS, which theoretically can be achieved by using ferroelectric materials with higher dielectric constants. However, this approach is limited by the equivalent oxide thickness (EOT), resulting in a limited increase in HCS. The other is to reduce the low-capacitance LCS. Given these limitations, this invention employs methods to control the SOI substrate thickness to significantly compress the capacitance (C). dep With C ov This significantly reduces LCS, thereby achieving a capacitance ratio C ratio Significant improvement.
[0039] Figure 2The simulation results verify the amplification effect of the SOI top layer silicon thickness modulation scheme on the capacitance ratio. The normalized capacitance window corresponding to different top layer silicon thicknesses under 0V bias is given. The ferroelectric layer 102 and the top electrode 103 are stacked on the 10nm ultra-thin SOI channel top layer 101 in turn, the buried oxide layer 100 is below the top layer 101, and the heavily doped N + region and the bottom electrode 104 form ohmic contact. Due to this structure, when the SOI thickness is reduced from 10μm to 10nm, the depletion region is longitudinally limited by the buried oxide layer 100 and transversely widened by the ferroelectric field of the ferroelectric layer 102, C dep is reduced, while C ov is sharply reduced to 0 under the influence of the ferroelectric field in the ultra-thin top layer channel 101, and the high capacitance state HCS is still dominated by C FE , so the normalized capacitance window jumps from less than 100 to more than 4000 at 0V, directly proving the key role of the ultra-thin SOI top layer silicon layer in precisely suppressing the low capacitance state.
[0040] Figure 3 The physical context of the compression of the low capacitance state when the SOI top layer silicon thickness is reduced from 10μm to 10nm is clarified. When the top layer silicon top layer channel 101 thickness is reduced from the traditional 10μm to 70nm, the longitudinal expansion of the depletion layer is limited by the SiO2 layer below, resulting in a significant reduction in the equivalent capacitance area A dep of the depletion layer, thereby reducing the depletion capacitance C dep . Further reducing the substrate to 10nm, the equivalent capacitance area A dep of the depletion layer continues to decrease, and to balance the channel surface potential change caused by the ferroelectric layer 102, the depletion region widens in the transverse direction, increasing the equivalent plate distance d of the depletion capacitance. These two factors together cause C dep to be further significantly reduced. In addition, due to the ferroelectric polarization effect, a large number of holes will accumulate on the surface of the top layer channel 101. In the 10nm ultra-thin channel, the high concentration of holes almost occupies the entire area below the top electrode, while the electrons are completely expelled outside the top electrode. Due to the expulsion of electrons, the L overlap on which the overlapping capacitance C ov depends tends to zero, resulting in C ov which can be almost ignored. This phenomenon can be verified by simulation: in the 70nm SOI structure, the low capacitance state increases linearly with the increase of L overlap , while in the 10nm SOI structure, even if L overlap increases, the low capacitance state can still be maintained at a very low level.
[0041] Figure 4The overall preparation process of the anti-type ferroelectric capacitor type memory of the present application is shown in a continuous profile:
[0042] Step 1): as shown in Figure 4 (a), select an SOI wafer containing a buried oxygen layer 100 and a lightly doped thin silicon top layer channel 101 as a substrate;
[0043] Step 2): as shown in Figure 4 (b), a layer of ferroelectric layer 102 is deposited on the top layer channel 101 by deposition process;
[0044] Step 3): as shown in Figure 4 (c), the electrode material is deposited on the surface of the ferroelectric layer 102 by magnetron sputtering to form the top electrode 103 required subsequently;
[0045] Step 4): as shown in Figure 4 (d), the top electrode 103 and the ferroelectric layer 102 below it are patterned by photolithography and dry etching, only the left side of the predetermined area is reserved, and the rest is completely removed. The purpose and effect of this step is to define the top electrode geometry profile of the device, and to prepare for the subsequent self-aligned ion implantation;
[0046] Step 5): as shown in Figure 4 (e), high-dose doping is introduced into the silicon layer top layer channel 101 below the top electrode by ion implantation, and a heavily doped region is constructed. The purpose and effect of this step is to form a heavily doped N + region, which is an essential part of the device structure;
[0047] Step 6): as shown in Figure 4 (f), the bottom electrode 104 is formed by depositing electrode material on the right side of the exposed silicon layer 101 by sputtering process. Finally, rapid thermal annealing is performed in an inert atmosphere. The purpose and effect of this step is to induce crystallization of the ferroelectric phase in the 102 ferroelectric layer on the one hand, and to move the implanted ions from the interstitial site to the substitutional site on the other hand, to complete the activation of the implanted ions to ensure the formation of ohmic contact between the interfaces, thereby completing the preparation of high-capacitance ratio anti-ferroelectric capacitor.
[0048] The present application significantly reduces the low capacitance state at 0V by precisely thinning the thickness of the top layer silicon of SOI, thereby greatly increasing the capacitance ratio under the premise of almost unchanged high capacitance state, providing a feasible and easily integrated technical path for low-power, high-density capacitor type computing chips.
Claims
1. A high on / off ratio inverse ferroelectric capacitor memory based on silicon-on-insulator substrate, characterized in that, It includes a bottom buried oxygen layer (100) and a top top channel (101) covering it. The top left side of the top top channel (101) is covered by a ferroelectric layer (102), the top of the ferroelectric layer (102) is covered by a top electrode (103), and the top right side of the top top channel (101) is covered by a bottom electrode (104). The ferroelectric layer (102) and the bottom electrode (104) are not in contact. The top channel (101) below the bottom electrode (104) is heavily doped with N. + In the region, the top channel (101) below the ferroelectric layer (102) is a lightly doped thin silicon; the peak doping concentration is 1×10⁻⁶. 20 cm -3 The top channel (101) below the ferroelectric layer is a thin, lightly doped silicon layer with uniform doping and a doping concentration of 1×10⁻⁶. 15 cm -3 .
2. The high on / off ratio inverse ferroelectric capacitor memory based on silicon-on-insulator substrate according to claim 1, characterized in that, The thickness of the top silicon layer of the top channel (101) is changed from 10 micrometers to 10 nanometers. The bottom buried oxide layer (100) and the top channel (101) constitute silicon-on-insulator. The bottom buried oxide layer (100) is made of SiO2. The top channel (101) is any one of Si, Ge, SiC, SiGe, and GaN.
3. The high on / off ratio inverse ferroelectric capacitor memory based on silicon-on-insulator substrate according to claim 1, characterized in that, The ferroelectric material of the ferroelectric layer (102) is Hf. 0.5 Zr 0.5 Any one of the following: O2 (HZO), HAO, HYO, HSO, PZT, BFO, AlScN; The top electrode (103) and bottom electrode (104) are made of any one of tungsten, titanium, platinum, aluminum, titanium nitride, tantalum nitride, titanium carbide, tantalum carbide, or tungsten carbide.
4. A high on / off ratio inverse ferroelectric capacitor memory based on a silicon-on-insulator substrate according to claim 1, characterized in that, The top channel (101) below the bottom electrode (104) forms N through self-aligned implantation of arsenic or phosphorus ions by the top electrode (103). + The heavily doped region forms an ohmic contact between the top channel (101) and the bottom electrode (104) after high-temperature annealing.
5. A high on / off ratio inverse ferroelectric capacitor memory based on a silicon-on-insulator substrate according to claim 1, characterized in that, The top channel (101) and the ferroelectric layer (102) are connected by a conformal interface formed by atomic layer deposition (ALD); the ferroelectric layer (102) and the top electrode (103) are connected by a Schottky contact formed by magnetron sputtering; the bottom electrode (104) and the top electrode (103) are isolated by photolithography-dry etching to avoid the formation of parasitic conductive paths.
6. A high on / off ratio inverse ferroelectric capacitor memory based on a silicon-on-insulator substrate according to claim 1, characterized in that, The ferroelectric layer (102) and the top channel (101) constitute a high on / off ratio inverting ferroelectric capacitor structure. Under 0V bias, when the ferroelectric polarization direction of the ferroelectric layer (102) is upward, a strong inversion is formed on the surface of the top channel (101), and the device is in a high capacitance state HCS (≈C). FE When the polarization direction reverses downwards, the depletion layer at the interface between the light P-type dopant and the heavy N+ type dopant widens, and the device is in an extremely low capacitance state (LCS≈C). dep +C ov ≈C dep Through the ultra-thin top-layer channel (101), the LCS is compressed to less than 1 / 40 of its original value, while the HCS remains basically unchanged, achieving C ratio A high switching ratio of >4000; this structure enables non-volatile high and low capacitance readings at 0V and features an ultra-high switching ratio.
7. A high on / off ratio inverse ferroelectric capacitor memory based on a silicon-on-insulator substrate according to claim 6, characterized in that, The thickness of the ultrathin top channel (101) is 200nm to 10nm, and the thickness of the bottom buried oxide layer (100) is 220nm.
8. A method for fabricating a high on / off ratio inverse ferroelectric capacitor memory based on a silicon-on-insulator substrate according to any one of claims 1-7, characterized in that, Includes the following steps; Step 1): Select an SOI wafer with a buried oxide layer (100) and a top channel (101) of lightly doped thin silicon as the substrate; Step 2): A ferroelectric layer (102) is deposited on top of the top channel (101) using a deposition process; Step 3): Electrode material is deposited on the surface of the ferroelectric layer (102) by magnetron sputtering to form the top electrode (103) required for subsequent processing; Step 4): The top electrode (103) and the underlying ferroelectric layer (102) are patterned by photolithography and dry etching, retaining only the predetermined area on the left and completely removing the rest, thus defining the geometric contour of the top electrode (103) of the device. Step 5): High-dose doping is introduced under the silicon layer of the top channel (101) not covered by the top electrode (103) by ion implantation to construct a heavily doped region; Step 6): Electrode material is deposited again on the exposed top channel (101) on the right side by sputtering process to form bottom electrode (104); finally, rapid thermal annealing is carried out in an inert atmosphere to induce crystallization of ferroelectric layer (102) on the one hand, and significantly reduce contact resistance to ensure ohmic contact on the other hand, thereby completing the preparation of high capacitance ratio inverse ferroelectric capacitor.
9. The method for fabricating a high on / off ratio inverse ferroelectric capacitor memory on a silicon-on-insulator substrate according to claim 8, characterized in that, In step 5), high-dose doping specifically involves using arsenic ions (As... + ) or phosphate ions (P + Injection, dose is 1×10 15 ~1×10 16 cm -2 Energy of 20–50 keV and injection tilt of 7° are used to form heavily doped N-type silicon with a sheet resistance of <100 Ω⁻¹ below the top channel (101) silicon layer not covered by the top electrode (103). + district.
10. The method for fabricating a high on / off ratio inverse ferroelectric capacitor memory on a silicon-on-insulator substrate according to claim 8, characterized in that, In step 6), the limiting conditions for rapid thermal annealing in an inert atmosphere are: the annealing atmosphere is N2, Ar, or a mixture thereof, with an oxygen content <1ppm; and the heating rate is ≥50℃s. -1 Peak temperature 600–900℃, peak holding time 100–300s, followed by a decrease of ≥30℃ for s. -1 The ferroelectric layer is cooled to room temperature at a rate that ensures full crystallization and ion implantation activation to form an ohmic contact between the bottom electrode and the channel.