Update unit, neuromorphic circuit including same, and method of operating neuromorphic circuit

Abstract

An update unit, a neuromorphic circuit including the same, and a method of operating the neuromorphic circuit are disclosed. The disclosed neuromorphic circuit may include an update cell array, which may include: a plurality of word lines; a plurality of bit lines crossing the plurality of word lines; and a plurality of update units disposed at a plurality of intersections of the plurality of word lines and the plurality of bit lines, respectively, the update units may include: a capacitor including a first electrode and a second electrode; a switching transistor including a first node connected to the second electrode, a second node connected to the bit line, and a gate connected to the word line; and a charge / discharge circuit unit connected to the capacitor and configured to charge and discharge the capacitor. A comparison circuit section connected to each of the plurality of bit lines may also be provided, and the comparison circuit section may be configured to output a first signal, a second signal, and a third signal separately based on a positive (+) threshold voltage and a negative (-) threshold voltage.

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