Multi-stage fully differential class AB amplifier

Abstract

A fully differential amplifier is provided that includes one or more stages and a class AB output stage. The one or more stages amplify a pair of differential input signals to produce an amplified pair of differential signals, and the class AB output stage further amplifies the amplified pair of differential signals to produce a pair of differential output signals. The class AB output stage includes a pair of differential outputs. For a respective one of the pair of differential outputs, the class AB output stage includes a folded transistor grid and a feedback circuit. Transistors of the folded transistor grid form a control amplifier to regulate a control input of a pair of output transistors, and the feedback circuit drives the control amplifier. The folded transistor grid biases a pair of output transistors in class AB.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to fully differential amplifiers, and in particular to multi-stage, fully differential class AB amplifiers. BACKGROUND

[0002] Differential amplifiers are electronic amplifiers that take two input signals and amplify the difference between them while rejecting any common-mode signals. They are used to amplify small signals in a wide range of applications, including analog front-end (AFE) systems, which are responsible for amplifying, filtering, and converting analog signals to digital signals for further processing.

[0003] Differential amplifiers are commonly used in AFE systems to amplify small signals from sensors and other devices, such as microphones and thermocouples. They are also used in analog-to-digital converters (ADCs) and other data acquisition systems. Differential amplifiers are used in medical imaging systems, such as MRI and CT scanners, to amplify signals from sensors. They are also used in telecommunications systems to amplify signals from antennas and other devices.

[0004] Differential amplifiers can be implemented in various ways, including very large scale integration (VLSI) circuits, which are commonly used for high-speed, high-performance applications. VLSI circuits are typically composed of transistors and other electronic components connected on a single chip. This reduces the size and cost of the circuit while increasing its speed and reliability.

[0005] The transistors used in VLSI circuits are typically created with a focus on digital circuits rather than analog circuits, and some device types' threshold voltage selection can not be available. Therefore, it is challenging to design an amplifier for operation from a typical supply voltage to as low as half of the typical supply voltage, considering the available devices. For example, most conventional complementary metal-oxide-semiconductor (CMOS) class AB operational amplifier designs can operate with a standard Monticelli-type biasing circuit at least two threshold voltages plus two drain-source voltage drops (2V TH + 2V DSat ). For class AB operational amplifier designs with a standard Monticelli-type biasing circuit, the threshold voltage of many CMOS devices does not allow for a supply voltage lower than about 2 volts.

[0006] Therefore, it is desirable to have a system and method that takes into account at least some of the issues discussed above, as well as possibly other issues. SUMMARY

[0007] Example implementations of the present disclosure relate to a fully differential amplifier, and more specifically, to a fully differential class AB amplifier. The fully differential amplifier can be a multi-stage amplifier having one or more stages and a class AB output stage. The class AB output stage can be implemented in a fully differential configuration and can be designed to operate at voltages as low as one threshold voltage plus two drain-source voltage drops (IV TH + 2V DSat ). In this regard, the fully differential amplifier can be used at lower voltages (e.g., 0.4 to 0.9 volts lower) than what would otherwise be possible with conventional processes and typical class AB designs.

[0008] The fully differential amplifier can be useful in several applications, such as part of an AFE system for amplifying signals from a sensor. In a more specific example, the fully differential amplifier can be used as a front-end amplifier for a high-resolution ADC. In this regard, the fully differential amplifier can provide high bandwidth, low power, high common-mode rejection, and low voltage operation.

[0009] The present disclosure thus includes, without limitation, the following example implementations.

[0010] Some example implementations provide a fully differential amplifier comprising: one or more stages for amplifying a pair of differential input signals to produce a pair of amplified differential signals; and a class AB output stage for further amplifying the pair of amplified differential signals to produce a pair of differential output signals, the class AB output stage comprising a pair of differential outputs, the class AB output stage comprising, for a respective differential output of the pair of differential outputs: a pair of output transistors coupled to the respective differential output of the pair of differential outputs and to a respective power rail of a first power rail and a second power rail; a folded transistor grid for biasing the pair of output transistors in class AB, and wherein transistors in the folded transistor grid form a control amplifier to regulate a control input of the pair of output transistors; and a feedback circuit for driving the control amplifier.

[0011] Some example implementations provide a fully differential amplifier including one or more stages to amplify a pair of differential input signals to produce a pair of amplified differential signals, the one or more stages including a folded cascode (FC) amplification stage including, for a respective input signal of the pair of differential input signals: a first pair of current sources; a second pair of current sources; and a pair of input transistors to conduct current from or to a respective summing node of the second pair of current sources, the second pair of current sources to provide current to the FC stage.

[0012] Some example implementations provide a fully differential amplifier including one or more stages to amplify a pair of differential input signals to produce a pair of amplified differential signals, the one or more stages including an amplification stage having a common mode feedback (CMFB) input for a CMFB control signal; and a CMFB control circuit to measure a midpoint of the pair of differential output signals and to generate the CMFB control signal to drive the midpoint of the pair of differential output signals to a common mode setpoint, the CMFB control circuit including a CMFB amplifier circuit including: a pair of diode-connected devices; and a pair of input transistors to input a respective one of the common mode setpoint and the midpoint of the pair of differential output signals, the pair of input transistors to conduct current through the pair of diode-connected devices, the pair of diode-connected devices to generate the CMFB control signal.

[0013] These and other features, aspects, and advantages of the present disclosure will become evident to those skilled in the art from a reading of the following detailed description, together with the appended claims and drawings. The present disclosure includes any combination of two, three, four, or more of the features or elements set forth in the present disclosure, whether or not explicitly set forth in a particular example implementation described herein. The present disclosure is intended to be read altogether, such that any separable feature or element of the present disclosure should be considered combinable in any aspect and example implementation thereof, unless the context of the present disclosure clearly dictates otherwise.

[0014] Accordingly, it will be appreciated that this Summary is provided merely for purposes of summarizing some example implementations so as to provide a basic understanding of some aspects of the disclosure. Accordingly, it will be appreciated that the above-described example implementations are merely examples and should not be construed as limiting the scope or spirit of the disclosure in any way. Other example implementations, aspects, and advantages will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of some of the described example implementations. BRIEF DESCRIPTION OF DRAWINGS

[0015] Accordingly, having generally described an example implementation of the disclosure, a specific example implementation will now be described with reference to the following drawings, which are not necessarily to scale, and wherein:

[0016] Figure 1 is a block diagram of a fully differential amplifier according to some example implementations of the disclosure;

[0017] Figure 2 is a block diagram of a fully differential amplifier according to some more specific example implementations, which can correspond to the fully differential amplifier of Figure 1 ;

[0018] Figure 3 is a circuit diagram of one end of the fully differential amplifier of Figure 2 according to some example implementations;

[0019] Figure 4 is a circuit diagram of one end of the fully differential amplifier of Figure 2 according to some example implementations;

[0020] Figure 5 is a portion of the circuit diagram of Figure 4 according to some example implementations, in which one of the plurality of stages includes a set of transconductance control circuits;

[0021] Figure 6 is another portion of the circuit diagram of Figure 4 according to some example implementations, in which another of the plurality of stages includes another set of transconductance control circuits; and

[0022] Figure 7 is a circuit diagram of a common mode feedback (CMFB) control circuit for a fully differential amplifier according to some example implementations. DETAILED DESCRIPTION

[0023] Some embodiments of the disclosure will now be described below with reference to the accompanying drawings, in which some but not all embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure can be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0024] Unless otherwise specified or clear from context, references to first, second, etc. should not be construed as implying a particular order. A feature described as on top of another feature (unless otherwise specified or clear from context) can instead be on bottom, and vice versa; and similarly, a feature described as on the left of another feature can instead be on the right, and vice versa. Additionally, while reference can be made herein to quantitative measures, values, geometric relationships, etc., unless otherwise stated, any one or more of these quantitative measures, values, geometric relationships, etc. (if not all) can be absolute or approximate, to account for acceptable variations that can arise, such as due to engineering tolerances, etc.

[0025] As used herein, unless otherwise specified or clear from context, an "or" of a set of operands is an "inclusive or," and thereby true if and only if one or more of the operands is true, as opposed to an "exclusive or," which is false if all of the operands are true. Thus, for example, "[A] or [B]" is true if [A] is true, or if [B] is true, or if both [A] and [B] are true. Also, unless otherwise specified or clear from context to refer to a singular form, the article "a" means "one or more." Further, it is to be understood that the terms "data," "content," "digital content," "information," and like terms can be used interchangeably.

[0026] Example embodiments of the disclosure relate generally to fully differential amplifiers, and in particular to multi-stage, fully differential class-AB amplifiers for low voltage applications. As understood by those skilled in the art, different types of amplifiers can be classified into amplifier classes that indicate characteristics and performance of the amplifiers. A class-A amplifier can be characterized as having an output stage that is always on. A class-B amplifier can be characterized as having an output stage made up of a pair of output devices, each of which is on only half or less of the input cycle. A class-AB amplifier combines characteristics of class-A and class-B amplifiers. In a class-AB amplifier, both output devices can be on together for some portion of the input cycle, such as when the input cycle is near zero degrees.

[0027] Figure 1 is a block diagram of a fully differential amplifier 100 according to some example implementations of the present disclosure. A fully differential amplifier is an electronic voltage amplifier that has differential inputs and differential outputs. A fully differential amplifier can amplify a difference between two input signals and provide an amplified positive output and an amplified negative output, both referenced to a common-mode voltage.

[0028] As shown, the fully differential amplifier 100 amplifies a differential input signal pair V IN+ , V IN- to produce a differential output signal pair V OUT+ , V OUT- . As also shown, the fully differential amplifier can be a multi-stage amplifier having multiple stages for amplifying the differential input signal pair. These stages can include one or more stages 102 for amplifying the differential input signal pair to produce an amplified differential signal pair and an AB class output stage 104 for further amplifying the amplified differential signal pair to produce the differential output signal pair V OUT+ , V OUT- .

[0029] As also shown, the AB class output stage 104 includes a pair of differential outputs for outputting the differential output signal pair V OUT+ , V OUT- , either of which can be more generally referred to as V OUT+ / - . For a respective differential output of the pair of differential outputs, the AB class output stage includes a pair of output transistors 106, a folded transistor grid 108, and a feedback circuit 110. The pair of output transistors 106 are coupled to the respective differential output of the pair of differential outputs V OUT+ / - and to respective power rails of a first power rail V DD and a second power rail V SS . The folded transistor grid 108 biases the pair of output transistors 106 in the AB class. The transistors of the folded transistor grid 108 form a control amplifier to regulate a control input of the pair of output transistors 106, and the feedback circuit 110 drives the control amplifier.

[0030] Figure 2 is a block diagram of a fully differential amplifier 200 according to some more specific example implementations, which can correspond to the fully differential amplifier 100 of Figure 1 . As Figure 2More specifically shown, in some examples, the one or more stages include, but are not limited to, an input stage 202 and an amplification stage 204. The fully differential amplifier 200 is also shown as having an AB class output stage 206; and in some examples, the fully differential amplifier 200 includes a compensation network 208 (illustrated as a pair of capacitors) for providing frequency compensation for the fully differential amplifier 200. And as also shown, the fully differential amplifier can include a common mode feedback (CMFB) control circuit 210.

[0031] In some more specific examples, the input stage 202 can be implemented as a fully balanced differential difference amplifier (FBDDA) stage, and the amplification stage 204 can be implemented as a single stage fully differential amplifier. A differential difference amplifier (DDA) is an operational amplifier having four inputs for two differential signal pairs, such as a differential input signal pair V IN+ , V IN- and a differential feedback signal pair V INFB+ , V INFB- from a feedback network. The DDA compares the two differential signal pairs and amplifies the difference between the two differential signal pairs, i.e., (V IN+ -V IN- )-(V ONFB+ -V ONFB- ). An FBDDA is a version of a DDA that provides both a positive output and a negative output of the amplification. However, it should be understood that the fully differential amplifier 200 can include one or more additional or alternative stages, fewer stages than shown, and can include appropriate support circuitry. Other examples of suitable stages include followers, current mirrors, buffers, and other voltage or current amplification stages.

[0032] Figure 3 is a circuit diagram of a fully differential amplifier 300 having a plurality of stages that can correspond to those of the fully differential amplifier 200 of Figure 2 . The fully differential amplifier 300 can be implemented in a plurality of transistors and other electronic components (such as resistors and capacitors) arranged in a complementary or differential configuration. In some examples, the transistors are metal oxide semiconductor field effect transistors (MOSFETs), and include a combination of n-channel MOSFET (NMOS) transistors and p-channel MOSFET (PMOS) transistors. In this regard, the fully differential amplifier 300 includes an NMOS side and a PMOS side. However, it should be understood that the NMOS side and the PMOS side can be reversed with only slight modifications to the connections between the transistors.

[0033] In some examples, the fully differential amplifier 300 is symmetric and includes an arrangement of transistors and resistors for amplifying a differential input signal pair VIN+ V IN- The corresponding input signal in V is used to generate a differential output signal. OUT+ V OUT- The corresponding output signal in the [process]. To further illustrate and describe the fully differential amplifier 300, Figure 4 It is a fully differential amplifier 300 used for the positive output signal V. OUT+ The circuit diagram for one end of the amplifier. The following description also applies to the fully differential amplifier for the negative output signal V. OUT- The other end.

[0034] Similarly, as shown in the figure, the fully differential amplifier 300 has multiple stages, including an FBDDA stage 402, a folded cascode (FC) amplification stage 404, and a Class AB output stage 406, which can correspond to... Figure 2 The fully differential amplifier 200 comprises one of its input stage 202, amplification stage 204, and Class AB output stage 206. Starting with the output, the Class AB output stage 406 includes multiple components for corresponding differential outputs in a pair of differential outputs, which are used to output differential output signal pairs, where only V is shown. OUT+ These components include a pair of output transistors (with a first output transistor M). 401 Second output transistor M 402 ), which is coupled to the pair of differential outputs V OUT+ / - The corresponding differential output, especially V OUT+ And coupled to the first power rail V DD Second power rail V SS The corresponding power rail in the system.

[0035] The fully differential amplifier 300 may include a pair of differential outputs V OUT+ / - The corresponding differential output compensation network 408 in the diagram corresponds to compensation network 208. In this respect, the compensation network can provide frequency compensation for the fully differential amplifier 300. As shown, compensation network 408 includes R... M1 C M1 and R M2 C M2 They are connected to the pair of output transistors and the pair of differential outputs V. OUT+ / - The corresponding differential outputs in the circuit are used, and the compensation network provides frequency compensation for the fully differential amplifier 300 using Miller compensation. More generally, the compensation network can use any combination of compensation capacitors, resistors, current feedback, or circuitry operated to provide frequency compensation to compensate the fully differential amplifier 300.

[0036] The Class AB output stage 406 includes transistor M. 403 M 404 M405 , M 406 folded grid of transistors M 401 , M 402 . In the folded grid, transistors M 403 , M 404 are cascode devices with their gates and sources connected in parallel and their drains independent of one another. Also in the folded grid, transistors M 405 , M 406 form a control amplifier 410 to regulate the control inputs of the pair of output transistors M 401 , M 402 . The class-AB output stage includes a feedback circuit 412 to drive the control amplifier 410 formed by transistors M 405 , M 406 .

[0037] The feedback loop regulates the quiescent current flowing through the class-AB output stage 406, which includes the feedback circuit 412, the folded grid of transistors M 403 , M 404 , M 405 , M 406 (including the control amplifier 410), and the output transistors M 401 , M 402 . In various example implementations described in more detail below, the feedback circuit 412 uses a minimum selector circuit and the control amplifier 410 to control the quiescent current flowing through the class-AB output stage 406, which allows for lower voltage operation than other class-AB output stages, such as those using the Monticelli biasing system.

[0038] In some more particular examples, the feedback circuit 412 includes a minimum selector circuit 414 (e.g., a minimum current selector circuit) that includes a current mirror 416 with transistors M 407 , M 408 and a first sense transistor M 409 . The feedback circuit 412 also includes a second sense transistor M 410 and a rectifier 418 coupled to the first sense transistor M 409 . The second sense transistor M 410 senses the current flowing through the second output transistor M 402 and conducts a current proportional to the current of the second output transistor M 402 . This current is mirrored by the current mirror 416 to the first sense transistor M 409 , which senses the current flowing through the first output transistor M 401 .

[0039] First sensing transistor M 409 Conducting and the first output transistor M 401 Second output transistor M 402 The current is proportional to the smaller of the currents. The first sensing transistor M 409 The current flows through rectifier 418 and is guided by transistor M 405 M 406 The control amplifier 410 is formed. Along with the first sensing transistor M... 409 Transistor M conducts less current. 406 The gate voltage on the second output transistor M decreases. 402 The gate voltage at the point increases, and the first output transistor M... 401 The gate voltage at the point is reduced to allow the output transistor M to... 401 M 402 Conducting more quiescent current. With the first sensing transistor M... 409 Transistor M conducts more current 406 As the gate voltage increases, the second output transistor M... 402 The gate voltage at the point decreases, and the first output transistor M 401 The gate voltage at point M is increased to reduce the output transistor M. 401 M 402 The quiescent current. The steady-state quiescent current is proportional to the feedback current, and thus proportional to the voltage generated on rectifier 418.

[0040] In some examples (not shown), rectifier 418 is a transistor M connected to a diode. 411 This is achieved through [the following]. In other examples, rectifier 418 is implemented using a transistor connected to a common-source cascode diode, shown in the diagram as a resistor R1 and transistor M. 411 M 412 This indicates that the transistor connected to the cascode diode can be used to match the cascode voltage of the main bias generator circuit (not shown). The main bias generator circuit generates a bias voltage for the current source and the cascode device; and in one example, the main bias generation circuit for the NMOS side of the fully differential amplifier 300 can be similar to that consisting of R1, M 411 M 412 The transistor is formed by a common-source cascode diode. A resistor in the main bias generation circuit provides a voltage drop, thereby generating a common-source cascode bias voltage relative to the main bias voltage. To balance the bias voltage generated by M... 405 and M 406 The generated differential pair, transistor M 406 The static voltage level is required to be close to M. 405 The NMOS common-source common-gate voltage is presented above. Therefore, the rectifier 418 can be constructed similarly to the NMOS common-source common-gate voltage.405 A main bias voltage generator circuit that provides a voltage.

[0041] In some examples, the feedback circuit 412 of the class AB output stage 406 includes a resistor R2 coupled between the second sense transistor M 410 and the current mirror M 407 , M 408 . The resistor R2 prevents the current mirror M 407 , M 408 from conducting an excessive current in the event that the second output transistor M 402 is fully or almost fully on.

[0042] In some examples, the feedback circuit 412 of the class AB output stage 406 includes one or more source degeneration resistors R3, R4, R5 for controlling the transconductance of the feedback circuit 412. The one or more source degeneration resistors R3, R4, R5 can include a first source degeneration resistor R3 and a second source degeneration resistor R4 coupled between the transistors of the current mirror M 407 , M 408 and the first supply rail V DD , and a third source degeneration resistor R5 coupled between the second sense transistor M 410 and the second supply rail V SS .

[0043] Prior to the class AB output stage 406, the fully differential amplifier 300 has one or more stages, including the FBDDA stage 402 and the FC amplifier stage 404. In some examples, the fully differential amplifier 300 is connected as a current feedback amplifier, and the FBDDA stage 402 includes multiple pairs of inputs. In this regard, the FBDDA stage 402 includes a first pair of inputs for receiving one of a pair of differential input signals and an opposite one of a pair of differential input feedback signals, e.g., V IN+ , V INFB- , and a second pair of inputs for receiving the other of the pair of differential input signals and the opposite other of the pair of differential input feedback signals, e.g., V IN- , V INFB+ .

[0044] The FBDDA stage 402 includes: a first pair of current sources 420, 426, which provide tail current for a first pair of inputs; and a second pair of current sources 422, 424, which provide tail current for a second pair of inputs. In some examples, current sources 420, 422, 424, 426 may be implemented as a source-and-cascode transistor pair, but in other examples a single transistor may also be used as the corresponding current source. For the corresponding differential output in this pair of differential outputs, the FBDDA stage 402 includes a signal V for outputting a signal V. IN-ASN V IN-ASP ("ASN" and "ASP" refer to the amplification stage, NMOS side, and PMOS side, respectively) output node and its symmetrical pair V TN+ASN and V IN+ASP The corresponding output nodes. Additionally, for each output, the FBDDA 402 includes load resistors R6 and R7, which are coupled to the output node and the first power rail V. DD Second power rail V SS The corresponding power rails in the circuit. Load resistors R6 and R7 can be selected to provide DC bias levels to the next stage (e.g., FC amplifier stage 404), thereby allowing the desired performance. As described above, V IN-ASN V IN-ASP and V IN+ASN V IN+ASP This refers to the negative-side and positive-side voltage inputs of the next stage of the corresponding devices on the NMOS and PMOS sides. Other signals indicated include the shared amplifier stage current source tail (AS) for both the NMOS and PMOS sides. NTAIL AS PTAIL ), Main current source bias (V shown only for the PMOS side) BIASP ) and current source cascode bias (V CASN V CASP ).

[0045] like Figure 5 As shown, in some examples, the FBDDA stage 402 includes a set of transconductance control circuitry (g m CTRL)502. In some examples, this set of transconductance control circuitry 502 can act as an electronic implementation of a Zener diode because it allows the tail current conductance to balance the transconductance of the input device. In another example, this set of transconductance control circuitry can act as a current switch for either the first pair of inputs or the second pair of inputs. Specifically, for example, this set of transconductance control circuitry can allow the tail current conductance to balance the transistor (M) of the first pair of inputs. 422 M 423 ), (M 424 M 425 ) and the second pair of input transistors (M) 426, M 427 ), (M 428 , M 429 ) transistors.

[0046] Returning to Figure 4 , the fully differential amplifier 300 in the illustrated implementation includes an FC amplification stage 404 between the FBDDA stage 402 and the class-AB output stage 406. Similar to the other stages, the FC amplification stage 404 includes a number of components for respective input signals in the differential input signal pair V IN+ , V IN- . The FC amplification stage 404 includes a first pair of current sources 428, 430 and a second pair of current sources 432, 434, which includes transistors (M 434 , M 403 , M 404 ), (M 435 , M 405 , M 406 ), respectively. In some examples, the current sources 428, 430 can be implemented as source and cascode transistor pairs, but a single transistor can also be used for the respective current source in other examples. The FC amplification stage 404 also includes an input transistor pair M 436 , M 437 . The first pair of current sources 428, 430 provides respective tail currents for the input transistor pair M 436 , M 437 . The input transistor pair M 436 , M 437 conducts current from or to respective summing nodes 436, 438 of the second pair of current sources 432, 434, which provide current to the FC amplification stage 404. In some examples, as shown, the current provided by the second pair of current sources 432, 434 can be in a cascode configuration.

[0047] In the illustrated implementation, the second pair of current sources 432, 434 are implemented with transistors that include a folded transistor grid of transistors M 403 , M 404 , M 405 , M 406 . The bidirectional arrows between M 403 and M 404 and between M 405 and M 406 indicate devices that have been split to create the folded transistor grid. The transistors M 403 and M 404 can still act as cascode devices; but as indicated above, the transistors M 405 , M 406The FBDDA stage 402 has become a controlled amplifier 410 (differential amplifier) to control the class AB quiescent current while still remaining a cascode device for the FC amplification path.

[0048] Similar to the FBDDA stage 402, in some examples, the FC amplification stage 404 includes a transconductance control circuit for acting as an electronic implementation of a Zener diode or as a current switch for the input transistor pair M 436 , M 437 as the input of the FC amplification stage. Figure 6 A transconductance control circuit (g m CTRL) 602 for one end of the fully differential amplifier 300 is illustrated.

[0049] Returning to Figure 4 , as also shown, one of the current sources in the first pair of current sources 428, 430 or the second pair of current sources 432, 434 of the FC amplification stage 404 includes a CMFB input for a common mode feedback (CMFB) control signal V CMFB . In the illustrated implementation, the CMFB input is coupled to the control input of the transistor M 435 on the NMOS side of the fully differential amplifier 300. However, as indicated above, in other implementations, the CMFB input can be coupled to the PMOS side of the fully differential amplifier. In some of these implementations, the CMFB input can be coupled to the control input of the transistor M 434 on the PMOS side of the fully differential amplifier if the circuit is so reconfigured. As will be appreciated by those skilled in the art, such reconfiguration of the CMFB input can also include reconnection of various ones of the other transistors. In other examples, the tail current source 428 or 430 of the FC amplification stage 404 can include a CMFB input for a CMFB control signal V CMFB . In yet other examples, the first pair of current sources 420, 422 or the second pair of current sources 424, 426 of the FBDDA stage 402 can include a CMFB input for a CMFB control signal V CMFB .

[0050] Figure 7 is a circuit diagram of a CMFB control circuit 700, which can correspond to the CMFB control circuit 210 of the fully differential amplifier 200 of Figure 2 , and can provide a CMFB control signal V Figure 2 and Figure 3 to the CMFB input of the FC amplification stage 404 of the fully differential amplifier 300 of CMFBIn some examples, as shown, the CMFB control circuit 700 is a rail-to-rail symmetrical current mirror that provides low gain and high bandwidth for stability without the need for additional compensation components. In other examples, the CMFB circuit can provide CMFB control signals to other stages of the amplifier when necessary. The rail-to-rail CMFB circuit 700 allows for low-voltage operation to complement the low-voltage capability of the fully differential amplifier 300.

[0051] Similar to the fully differential amplifier 300, the CMFB control circuit 700 may include an NMOS side and a PMOS side; and as shown in the figure, the CMFB control circuit 700 provides the CMFB output signal, i.e., the CMFB control signal V, to the NMOS side of the fully differential amplifier (as the CMFB input of the FC amplification stage). CMFB However, it should also be understood that the NMOS and PMOS sides can be reversed with only a slight modification to the connections between the transistors. In this case, the CMFB control circuit 700 can alternately use the CMFB output signal as the CMFB control signal V. CMFB It is provided to the PMOS side of the fully differential amplifier.

[0052] The CMFB control circuit 700 typically measures the differential output signal relative to V. OUT+ V OUT- midpoint V MID And generate CMFB control signal V CMFB To drive the midpoint of the differential output signal pair to the common-mode setpoint V CM (also Figure 2 (As shown in the diagram). In various examples, the common mode setpoint V CM It can be set by the user, such as the first power rail V. DD Half of it. The CMFB control circuit 700 can drive its output (V CMFB ) to balance V MID and V CM The amplifier acts as a control signal. In some examples, the CMFB control signal V... CMFB It can be biased to a value higher than the second power rail V. SS A gate-source voltage (V Gs And change as needed to achieve balance V MID and V CM Its function.

[0053] As shown in the figure, in some examples, the CMFB control circuit 700 may include a resistor divider circuit 702 and a CMFB amplifier circuit 704. The resistor divider circuit with two equal resistors outputs a differential signal to V. OUT+ V OUT-at the midpoint of the resistive divider circuit, which can include a capacitor for added stability. The CMFB amplifier circuit includes a pair of diode-connected devices 706, 708, which respectively include common-source common-gate diode-connected transistors (M 701 , M 702 ), (M 703 , M 704 ). The CMFB circuit also includes a pair of input transistors M 705 , M 706 . The pair of input transistors M 705 , M 706 input respective ones of the common-mode setpoint V CM and the midpoint V MID of the differential output signal pair and conduct current through the pair of diode-connected devices 706, 708. The diode-connected device 708 generates a CMFB control signal V CMFB that directs the fully differential amplifier 300 to drive V MID to V CM . The other diode-connected device 706 functions to maintain load symmetry in the differential amplifier.

[0054] In some examples, the CMFB control circuit 700 includes a pair of current mirrors 710, 712, which respectively include transistors (M 707 , M 708 , M 709 , M 710 ), (M 711 , M 712 , M 713 , M 714 ). The CMFB control circuit also includes a second pair of input transistors M 715 , M 716 . In some examples, as shown, the pair of current mirrors 710, 712 is a pair of common-source common-gate current mirrors. In other examples, the pair of current mirrors can not be common-source common-gate. The second pair of input transistors M 715 , M 716 input respective ones of the common-mode setpoint V CM and the midpoint V MID of the differential output signal pair and conduct current through the pair of current mirrors 710, 712 of the CMFB control circuit 700. The pair of current mirrors 710, 712 then conduct current through the pair of diode-connected devices 706, 708 to generate the output common-mode feedback voltage V CMFB .

[0055] As also shown, for example, the CMFB control circuit includes current sources 714, 716. In some examples, the current sources 714, 716 can be implemented as source and common-gate transistor pairs, although a single transistor can also be used for the respective current source in other examples. These current sources provide tail currents to respective input transistors M 705 、M 706 and M 715 、M 716 of the second pair of input transistors, and are biased from the same bias and common-gate voltage rails as the fully differential amplifier 300.

[0056] As explained above and reiterated below, the present disclosure includes, without limitation, the following example implementations.

[0057] Clause 1. A fully differential amplifier, comprising: one or more stages to amplify a pair of differential input signals to produce a pair of amplified differential signals; and an AB class output stage to further amplify the pair of amplified differential signals to produce a pair of differential output signals, the AB class output stage comprising a pair of differential outputs, the AB class output stage comprising, for a respective differential output of the pair of differential outputs: a pair of output transistors coupled to the respective differential output of the pair of differential outputs and to a respective power rail of a first power rail and a second power rail; a folded transistor grid to bias the pair of output transistors in AB class, and wherein transistors in the folded transistor grid form a control amplifier to regulate a control input of the pair of output transistors; and a feedback circuit to drive the control amplifier.

[0058] Clause 2. The fully differential amplifier of clause 1, wherein the fully differential amplifier comprises, for a respective differential output of the pair of differential outputs: a compensation network to provide frequency compensation for the fully differential amplifier.

[0059] Clause 3. The fully differential amplifier of clause 1 or clause 2, wherein the pair of output transistors includes a first output transistor and a second output transistor, and the feedback circuit includes: a minimum selector circuit including a current mirror and a first sense transistor; a second sense transistor for sensing a current flowing through the second output transistor, the second sense transistor for conducting a current flowing through the current mirror of the minimum selector circuit to the first sense transistor, the first sense transistor for sensing the current flowing through the first output transistor; and a rectifier coupled to the first sense transistor, the first sense transistor for conducting a current flowing through the rectifier and directing the current to the control amplifier.

[0060] Clause 4. The fully differential amplifier of clause 3, wherein the rectifier is implemented with a diode-connected transistor.

[0061] Clause 5. The fully differential amplifier of clause 3 or clause 4, wherein the rectifier is implemented with a cascode diode-connected transistor.

[0062] Clause 6. The fully differential amplifier of any of clauses 3 to 5, wherein the feedback circuit includes a resistor coupled between the second sense transistor and the current mirror to prevent the current mirror from conducting an excessive current in the event that the second output transistor is fully on or near fully on.

[0063] Clause 7. The fully differential amplifier of any of clauses 3 to 6, wherein the feedback circuit includes one or more source degeneration resistors for controlling a transconductance of the feedback circuit.

[0064] Clause 8. The fully differential amplifier of clause 7, wherein the source degeneration resistors include a first source degeneration resistor and a second source degeneration resistor coupled between the current mirror and the first supply rail, and a third source degeneration resistor coupled between the second sense transistor and the second supply rail.

[0065] Clause 9. The fully differential amplifier of any of clauses 1 to 8, wherein the one or more stages include a fully balanced differential difference amplifier (FBDDA) stage.

[0066] Clause 10. The fully differential amplifier of clause 9, wherein the fully differential amplifier is connected as a current feedback amplifier, and the FBDDA stage includes a plurality of pairs of inputs, including a first pair of inputs and a second pair of inputs, the first pair of inputs to receive one of the differential input signal pair and an opposite one of a differential input feedback signal pair, and the second pair of inputs to receive the other of the differential input signal pair and the opposite other of the differential input feedback signal pair.

[0067] Clause 11. The fully differential amplifier of clause 10, wherein the FBDDA stage includes: a first pair of current sources to provide tail currents for the first pair of inputs; and a second pair of current sources to provide tail currents for the second pair of inputs.

[0068] Clause 12. The fully differential amplifier of clause 10 or clause 11, wherein for a respective differential output of the pair of differential outputs, the FBDDA stage includes: an output node; and a load resistor coupled to the output node and a respective one of the first supply rail and the second supply rail.

[0069] Clause 13. The fully differential amplifier of any of clauses 9-12, wherein the FBDDA stage includes a set of transconductance control circuits to act as electronic implementations of Zener diodes or as current switches for the first pair of inputs or the second pair of inputs.

[0070] Clause 14. The fully differential amplifier of any of clauses 1-13, wherein the one or more stages include a folded cascode (FC) amplification stage.

[0071] Clause 15. The fully differential amplifier of clause 14, wherein the FC amplification stage includes, for a respective one of the differential input signal pair: a first pair of current sources to provide tail currents for a pair of input transistors, the pair of input transistors to conduct current from or to a respective summing node of a second pair of current sources, the second pair of current sources to provide current to the FC amplification stage.

[0072] Clause 16. The fully differential amplifier of clause 15, wherein the second pair of current sources are implemented with transistors, the transistors including the transistors of the folded grid of transistors.

[0073] Clause 17. The fully differential amplifier of clause 15 or clause 16, wherein one of the current sources in the first pair of current sources or the second pair of current sources comprises a common mode feedback (CMFB) input for a CMFB control signal.

[0074] Clause 18. The fully differential amplifier of any of clauses 15-17, wherein the FC amplification stage comprises a set of transconductance control circuits to function as an electronic implementation of a Zener diode or as a current switch for the input transistor pair.

[0075] Clause 19. The fully differential amplifier of any of clauses 1-18, wherein one of the one or more stages comprises an amplification stage having a common mode feedback input for a common mode feedback (CMFB) control signal, and the fully differential amplifier comprises: a CMFB control circuit to measure a midpoint of the differential output signal pair and to generate the CMFB control signal to drive the midpoint of the differential output signal pair to a common mode setpoint.

[0076] Clause 20. The fully differential amplifier of clause 19, wherein the CMFB control circuit comprises a resistive voltage divider circuit to generate a signal at the midpoint of the differential output signal pair.

[0077] Clause 21. The fully differential amplifier of clause 19 or clause 20, wherein the CMFB control circuit comprises a CMFB amplifier circuit comprising: a pair of diode-connected devices; and a pair of input transistors to input respective ones of the common mode setpoint and the midpoint of the differential output signal pair, the pair of input transistors to conduct current through the pair of diode-connected devices, the pair of diode-connected devices to generate the CMFB control signal.

[0078] Clause 22. The fully differential amplifier of clause 21, wherein the CMFB control circuit comprises: a pair of current mirrors; and a second pair of input transistors to input respective ones of the common mode setpoint and the midpoint of the differential output signal pair, the second pair of input transistors to conduct current through the pair of current mirrors of the CMFB control circuit, the pair of current mirrors to conduct current through the pair of diode-connected devices.

[0079] Clause 23. The fully differential amplifier of clause 22, wherein the CMFB control circuit comprises a current source to provide a tail current to respective ones of the pair of input transistors and the second pair of input transistors.

[0080] Clause 24. A fully differential amplifier, the fully differential amplifier comprising: one or more stages for amplifying a pair of differential input signals to produce a pair of amplified differential signals, the one or more stages comprising a folded common-source- common-gate (FC) amplification stage, the folded common-source-common-gate (FC) amplification stage comprising, for respective input signals of the pair of differential input signals: a first pair of current sources for providing tail currents for a pair of input transistors, the pair of input transistors for conducting current from or to respective summing nodes of a second pair of current sources, the second pair of current sources providing current to the FC amplification stage.

[0081] Clause 25. The fully differential amplifier of clause 24, wherein the fully differential amplifier comprises an AB class output stage for further amplifying the pair of amplified differential signals to produce a pair of differential output signals, and the AB class output stage comprises a folded transistor grid for biasing a pair of output transistors in AB class, and wherein the second pair of current sources is implemented with transistors including the transistors of the folded transistor grid.

[0082] Clause 26. The fully differential amplifier of clause 24 or clause 25, wherein one of the current sources of the first pair of current sources or the second pair of current sources comprises a common mode feedback (CMFB) input for a CMFB control signal.

[0083] Clause 27. The fully differential amplifier of clause 26, wherein the fully differential amplifier comprises: a CMFB control circuit for measuring a midpoint of the pair of differential output signals, and producing the CMFB control signal to drive the midpoint of the pair of differential output signals to a common mode setpoint.

[0084] Clause 28. The fully differential amplifier of clause 27, wherein the CMFB control circuit comprises a resistive voltage divider circuit for producing a signal at the midpoint of the pair of differential output signals.

[0085] Clause 29. The fully differential amplifier of clause 27 or clause 28, wherein the CMFB control circuit comprises a CMFB amplifier circuit comprising: a pair of diode-connected devices; and a pair of input transistors for inputting respective ones of the common mode setpoint and the midpoint of the differential output signal pair, the pair of input transistors for conducting current through the pair of diode-connected devices, the pair of diode-connected devices generating the CMFB control signal.

[0086] Clause 30. The fully differential amplifier of clause 29, wherein the CMFB control circuit comprises: a pair of current mirrors; and a second pair of input transistors for inputting respective ones of the common mode setpoint and the midpoint of the differential output signal pair, the second pair of input transistors for conducting current through the pair of current mirrors of the CMFB control circuit, the pair of current mirrors conducting current through the pair of diode-connected devices.

[0087] Clause 31. The fully differential amplifier of clause 30, wherein the CMFB control circuit comprises a current source for providing a tail current to respective ones of the pair of input transistors and the second pair of input transistors.

[0088] Clause 32. A fully differential amplifier comprising: one or more stages for amplifying a differential input signal pair to generate an amplified differential signal pair, the one or more stages comprising an amplification stage having a common mode feedback (CMFB) input for a CMFB control signal; and a CMFB control circuit for measuring a midpoint of the differential output signal pair and generating the CMFB control signal to drive the midpoint of the differential output signal pair to a common mode setpoint, the CMFB control circuit comprising a CMFB amplifier circuit comprising: a pair of diode-connected devices; and a pair of input transistors for inputting respective ones of the common mode setpoint and the midpoint of the differential output signal pair, the pair of input transistors for conducting current through the pair of diode-connected devices, the pair of diode-connected devices generating the CMFB control signal.

[0089] Clause 33. The fully differential amplifier of clause 32, wherein the CMFB control circuit comprises a resistive voltage divider circuit for generating a signal at the midpoint of the differential output signal pair.

[0090] Clause 34. The fully differential amplifier of clause 32 or clause 33, wherein the CMFB control circuit comprises: a pair of current mirrors; and a second pair of input transistors for inputting respective ones of the common mode setpoint and the midpoint of the differential output signal pair, the second pair of input transistors for conducting current through the pair of current mirrors of the CMFB control circuit, the pair of current mirrors conducting current through the pair of diode-connected devices.

[0091] Clause 35. The fully differential amplifier of clause 34, wherein the CMFB control circuit comprises a current source for providing a tail current to respective ones of the pair of input transistors and the second pair of input transistors.

[0092] Clause 36. The fully differential amplifier of any of clauses 32 to 35, wherein the amplification stage is a folded cascode (FC) amplification stage.

[0093] Clause 37. The fully differential amplifier of clause 36, wherein the FC amplification stage comprises, for respective ones of the differential input signal pair: a first pair of current sources; a second pair of current sources; and a pair of input transistors, the first pair of current sources for providing a tail current for the pair of input transistors, the pair of input transistors for conducting current to respective summing nodes of the second pair of current sources, the second pair of current sources providing current to the FC amplification stage.

[0094] Clause 38. The fully differential amplifier of clause 37, wherein the fully differential amplifier comprises an AB class output stage for further amplifying the amplified differential signal pair to produce a differential output signal pair, and the AB class output stage comprises a folded transistor grid for biasing a pair of output transistors in AB class, and wherein the second pair of current sources are implemented with transistors including the folded transistor grid.

[0095] Clause 39. The fully differential amplifier of clause 37 or clause 38, wherein one of the current sources of the first pair of current sources or the second pair of current sources comprises a CMFB input for the common mode feedback (CMFB) control signal.

[0096] Many modifications and other specific embodiments of the present disclosure set forth herein will be apparent to those of ordinary skill in the art upon benefiting from the teachings presented in the foregoing descriptions and the associated drawings. Accordingly, the present disclosure is not limited to the specific embodiments set forth for purposes of exemplification alone, and it is therefore understood that the scope of the present disclosure is not limited to the specific examples described and techniques presented and / or components and described herein. Further, it should be understood that the specific embodiments set forth in the foregoing description and illustrated in the associated drawings are not intended to be limiting of the present disclosure, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing description has been described in the context of particular examples, it should be appreciated that the description set forth herein is a description of example embodiments and is not intended to limit the claims. Also, for example, where an element or component is said to be included in even one of multiple embodiments or configurations, such element or component would also, where possible and practicable, be included in and / or perform the functions of the other embodiments and configurations. Additionally, it should be understood that where the foregoing description has described one or more example embodiments, the description has not identified either expressly or implicitly all of the embodiments that would be relied upon to support the patentability of the present disclosure.

Claims

1. A fully differential amplifier, the fully differential amplifier comprising: One or more stages, the one or more stages being used to amplify differential input signal pairs to produce amplified differential signal pairs; and An AB-class output stage is provided for further amplifying the amplified differential signal pair to generate a differential output signal pair. The AB-class output stage includes a pair of differential outputs, and for each differential output in the pair of differential outputs, the AB-class output stage includes: A pair of output transistors, the pair of output transistors being coupled to a corresponding differential output of the pair of differential outputs, and coupled to a corresponding power rail of the first power rail and the second power rail; A folded transistor grid, the folded transistor grid being used to bias the pair of output transistors in Class AB, and wherein the transistors in the folded transistor grid form a control amplifier to regulate the control input of the pair of output transistors; and A feedback circuit is provided to drive the control amplifier.

2. The fully differential amplifier of claim 1, wherein the fully differential amplifier comprises, for each differential output of the pair of differential outputs: A compensation network is provided to provide frequency compensation for the fully differential amplifier.

3. The fully differential amplifier of claim 1, wherein the pair of output transistors includes a first output transistor and a second output transistor, and the feedback circuit includes: A minimum selector circuit, the minimum selector circuit including a current mirror and a first sensing transistor; The second sensing transistor is used to sense the current flowing through the second output transistor. The second sensing transistor is used to conduct the current flowing through the current mirror of the minimum selector circuit to the first sensing transistor. The first sensing transistor is used to sense the current flowing through the first output transistor. and a rectifier, the rectifier being coupled to the first sensing transistor, the first sensing transistor being used to conduct current flowing through the rectifier and directing the control amplifier.

4. The fully differential amplifier according to claim 3, wherein the rectifier is implemented using a diode-connected transistor.

5. The fully differential amplifier of claim 3, wherein the rectifier is implemented using a transistor connected with a common-source cascode diode.

6. The fully differential amplifier of claim 3, wherein the feedback circuit includes a resistor coupled between the second sensing transistor and the current mirror to prevent the current mirror from conducting excessive current when the second output transistor is fully or nearly fully turned on.

7. The fully differential amplifier of claim 3, wherein the feedback circuit includes one or more source degradation resistors for controlling the transconductance of the feedback circuit.

8. The fully differential amplifier of claim 7, wherein the source degradation resistor comprises a first source degradation resistor and a second source degradation resistor coupled between the current mirror and the first power rail, and a third source degradation resistor coupled between the second sensing transistor and the second power rail.

9. The fully differential amplifier of claim 1, wherein the one or more stages comprise a fully balanced differential amplifier (FBDDA) stage.

10. The fully differential amplifier of claim 9, wherein the fully differential amplifier is connected as a current feedback amplifier, and the FBDDA stage includes a plurality of pairs of inputs, including: The first pair of inputs is used to receive one input signal from the differential input signal pair and the opposite input feedback signal from the differential input feedback signal pair; And a second pair of inputs, the second pair of inputs being used to receive another input signal in the differential input signal pair and the opposite input feedback signal in the differential input feedback signal pair.

11. The fully differential amplifier of claim 10, wherein the FBDDA stage comprises: The first pair of current sources is used to provide tail current for the first pair of inputs; and a second pair of current sources, which are used to provide tail current for the second pair of inputs.

12. The fully differential amplifier of claim 10, wherein for a corresponding differential output in the pair of differential outputs, the FBDDA stage comprises: Output node; and A load resistor, which is coupled to the output node and a corresponding power rail in the first and second power rails.

13. The fully differential amplifier of claim 9, wherein the FBDDA stage includes a set of transconductance control circuitry, the set of transconductance control circuitry serving as an electronic embodiment of a Zener diode or as a current switch for the first pair of inputs or the second pair of inputs.

14. The fully differential amplifier of claim 1, wherein one or more stages comprise a folded cascode (FC) amplification stage.

15. The fully differential amplifier of claim 14, wherein the FC amplification stage comprises, for each corresponding input signal in the differential input signal pair: The first pair of current sources; The second pair of current sources; and Input transistor pairs, The first pair of current sources is used to provide tail current to the input transistor pair, the input transistor pair is used to conduct current to the corresponding summing node of the second pair of current sources, and the second pair of current sources provides current to the FC amplifier stage.

16. The fully differential amplifier of claim 15, wherein the second pair of current sources is implemented using transistors, the transistors comprising the transistors of the folded transistor grid.

17. The fully differential amplifier of claim 15, wherein one of the current sources in the first pair of current sources or the second pair of current sources includes a CMFB input for a common-mode feedback (CMFB) control signal.

18. The fully differential amplifier of claim 15, wherein the FC amplification stage includes a set of transconductance control circuitry, the set of transconductance control circuitry serving as an electronic embodiment of a Zener diode or as a current switch for the input transistor pair.

19. The fully differential amplifier of claim 1, wherein one of the one or more stages includes an amplification stage having a common-mode feedback input for a common-mode feedback (CMFB) control signal, and the fully differential amplifier includes: A CMFB control circuit is used to measure the midpoint of the differential output signal pair and generate the CMFB control signal to drive the midpoint of the differential output signal pair to a common-mode setpoint.

20. The fully differential amplifier of claim 19, wherein the CMFB control circuit includes a resistor divider circuit for generating a signal at the midpoint of the differential output signal pair.

21. The fully differential amplifier according to claim 19, wherein the CMFB control circuit includes a CMFB amplifier circuit, the CMFB amplifier circuit comprising: A device with a pair of diodes connected together; and A pair of input transistors, the pair of input transistors being used to input one of the common-mode setpoint and the midpoint of the differential output signal pair, the pair of input transistors being used to conduct current flowing through the device connected to the pair of diodes, the device connected to the pair of diodes generating the CMFB control signal.

22. The fully differential amplifier of claim 21, wherein the CMFB control circuit comprises: A pair of current mirrors; and The second pair of input transistors is used to input one of the common-mode setpoint and the midpoint of the differential output signal pair, and is used to conduct current through the pair of current mirrors of the CMFB control circuit, which conduct current through the device connected to the pair of diodes.

23. The fully differential amplifier of claim 22, wherein the CMFB control circuit includes a current source for providing tail current to a corresponding input transistor in the pair of input transistors and the second pair of input transistors.

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