High power supply rejection low dropout linear regulator based on level feed-forward ripple elimination
By introducing a level shifting circuit and an AEA error amplifier into the LDO loop, power supply fluctuation information is directly loaded onto the gate of the power transistor, solving the problem of insufficient power supply suppression capability in the intermediate frequency range of traditional LDOs, and achieving effective suppression of power supply ripple and improved stability.
Patent Information
- Application Number
- CN202511097173.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-06
- Publication Date
- 2025-11-21
AI Technical Summary
Traditional low-dropout linear regulators (LDOs) have insufficient power supply rejection capability in the mid-frequency range, and feedforward ripple elimination technology consumes a lot of hardware resources and is difficult to achieve stability.
The level feedforward ripple elimination technology is adopted. By introducing a level shifting circuit and an AEA error amplifier into the LDO loop, and combining it with the Mp power transistor, the power supply fluctuation information is directly loaded onto the gate of the power transistor to eliminate ripple, simplify the circuit structure and improve stability.
It effectively suppresses power ripple in the intermediate frequency range, reduces hardware resource consumption, and improves the stability and power suppression capability of the LDO loop.
Smart Images
Figure CN120994010A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of power electronics, and particularly relates to a high power-supply rejection low-dropout linear regulator based on level feed-forward ripple elimination. BACKGROUND
[0002] Low-dropout linear regulators LDO of power management chips are increasingly applied to portable electronic devices because of their ability to suppress power ripples, small static power consumption and small area; especially circuits such as analog-to-digital converters and high-precision amplifiers, which require the power chip LDO to be able to suppress power ripple interference in a higher frequency range. The power supply rejection capability of traditional LDOs is mainly concentrated in the low frequency range, such as 1KHz-100KHz, and cannot suppress power ripples in the medium frequency range, such as 1MHz-10MHz. In recent years, in order to improve the power supply rejection capability of LDO in the medium frequency range, some scholars have proposed a feed-forward ripple cancellation technology FFRC, which collects the fluctuations on the power supply through a ripple collection circuit, and then loads the power supply ripple to the power tube gate through an adding amplifier, so as to achieve the suppression of the power supply ripple in the medium frequency range. Figure 8 As shown in FIG. 1, it is a traditional LDO based on feed-forward ripple cancellation, mainly including a feed-forward amplifier, an adding amplifier and a feedback loop, etc. This technology needs to use three amplifiers AFF, AEA, AS, and needs large feedback resistors RFF1, RFF2, RS1, RS2, RS3 and capacitors CFF1, which consumes a lot of hardware resources; in addition, the traditional feed-forward ripple cancellation technology also has high requirements for stability, and it is difficult to achieve stability. SUMMARY
[0003] The present application provides a high power-supply rejection low-dropout linear regulator based on level feed-forward ripple elimination, which sets a level shift circuit into the loop of the low-dropout linear regulator, and simultaneously sets an AEA error amplifier and an Mp power tube, to achieve the elimination of the feed-forward ripple of the power supply voltage.
[0004] Technical solution: To achieve the above-mentioned purpose, the high power supply rejection low dropout linear voltage regulator based on level feedforward ripple elimination of the application comprises an AEA error amplifier, a level shift circuit and an Mp power tube; the output end of the AEA error amplifier is electrically connected to the input end of the level shift circuit through a zero point follow-up circuit, the output end of the level shift circuit is electrically connected to the gate of the Mp power tube, and the source of the Mp power tube is electrically connected to the VDD power supply; the drain of the Mp power tube is electrically connected to one end of the R1 resistor, the other end of the R1 resistor is grounded through the R2 resistor, and the other end of the R1 resistor is electrically connected to the positive input end of the AEA error amplifier; the drain of the Mp power tube is grounded through the CL capacitor, and the drain of the Mp power tube serves as the output end of the high power supply rejection low dropout linear voltage regulator, and outputs the voltage eliminating feedforward ripple.
[0005] Further, the level shift circuit comprises an ADC amplifier and an Md power tube; the negative input end of the ADC amplifier serves as the input end of the level shift circuit, and the output end of the ADC amplifier is electrically connected to the gate of the Md power tube; the drain of the Md power tube is grounded through the R3 resistor, and the drain of the Md power tube is electrically connected to the positive input end of the ADC amplifier; the source of the Md power tube is electrically connected to the VDD power supply through the R4 resistor, and the source of the Md power tube serves as the output end of the level shift circuit.
[0006] Further, the AEA error amplifier is an amplifier of NMOS current mirror.
[0007] Further, the AEA error amplifier comprises an input circuit and an NMOS tube current mirror circuit; the input circuit comprises MN1 transistor, MN2 transistor and MN3 transistor; the gate of the MN1 transistor serves as the positive input end of the AEA error amplifier, the gate of the MN2 transistor serves as the negative input end of the AEA error amplifier, and the VREF reference voltage is input; the source of the MN1 transistor and the source of the MN2 transistor are both electrically connected to the drain of the MN3 transistor, and the source of the MN3 transistor is grounded; the source of the MN1 transistor and the source of the MN2 transistor are grounded through the Iadp current source.
[0008] Further, the NMOS transistor current mirror circuit comprises MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, MN4 transistor, MN5 transistor, MN6 transistor and MN7 transistor; the drain of the MP1 transistor is electrically connected with the drain of the MN2 transistor and the source of the MP3 transistor, the drain of the MP2 transistor is electrically connected with the drain of the MN1 transistor and the source of the MP4 transistor; the drain of the MP3 transistor is electrically connected with the drain of the MN6 transistor and the gate of the MN4 transistor, the source of the MN6 transistor is electrically connected with the drain of the MN4 transistor; the drain of the MP4 transistor is electrically connected with the gate of the MN7 transistor, the source of the MN7 transistor is electrically connected with the drain of the MN5 transistor; the gates of the MP1 transistor and the MP2 transistor are interconnected, the gates of the MP3 transistor and the MP4 transistor are interconnected, the gates of the MN6 transistor and the MN7 transistor are interconnected, the gates of the MN4 transistor and the MN5 transistor are interconnected; the drain of the MP4 transistor is used as the output terminal of the AEA error amplifier.
[0009] Further, the zero point following circuit comprises MN8 transistor and Cc capacitor; the gate of the MN8 transistor is electrically connected with the output terminal of the AEA error amplifier, the drain of the MN8 transistor is electrically connected with the input terminal of the level shift circuit through the Cc capacitor, and the source of the MN8 transistor is grounded.
[0010] Further, the R4 resistor in the level shift circuit is a resistor array, which is used for changing the resistance value of the R4 resistor.
[0011] Further, the load adaptive adjustment circuit is further comprised; the load adaptive adjustment circuit compares the current of the Mp power transistor with the preset current value, and adjusts the resistance value of the R4 resistor according to the comparison result; in the initial state, the current of the Mp power transistor is smaller than the preset current value, and the load adaptive adjustment circuit controls the resistance value of the R4 resistor to remain unchanged; when the current of the Mp power transistor is greater than the preset current value, the load adaptive adjustment circuit automatically controls the resistance value of the R4 resistor to become larger.
[0012] Beneficial effects: the high power suppression low-dropout linear regulator based on the level feedforward ripple elimination of the application can realize the elimination of the power voltage feedforward ripple by setting the level shift circuit into the loop of the low-dropout linear regulator, and simultaneously setting the AEA error amplifier and the Mp power transistor; the level shift circuit is used for directly collecting the fluctuation on the power supply and loading to the gate of the power transistor, and the circuit structure is simple and the hardware cost is small; the level shift circuit can isolate the high impedance output by the first-stage error amplifier and the large capacitance of the gate of the power transistor, split the pole point, and is helpful to realize high stability. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 It is a circuit diagram of the high power suppression low-dropout linear regulator.
[0014] Figure 2 Circuit diagram of level shift circuit;
[0015] Figure 3 Conceptual diagram of level shift in level shift circuit;
[0016] Figure 4 Circuit stage topology diagram of high power supply rejection low dropout linear regulator;
[0017] Figure 5 Idea diagram of adaptive adjustment circuit;
[0018] Figure 6 Circuit diagram of load adaptive adjustment circuit;
[0019] Figure 7 Effect comparison diagram of level feedforward ripple cancellation;
[0020] Figure 8 LDO circuit diagram based on traditional feedforward ripple cancellation technology. DETAILED DESCRIPTION
[0021] The application will be further described below with reference to the drawings.
[0022] As Figure 1 shown, the high power supply rejection low dropout linear regulator based on level feedforward ripple cancellation includes an AEA error amplifier 1, a level shift circuit 2 and an Mp power tube 3; the output end of the AEA error amplifier 1 is electrically connected to the input end of the level shift circuit 2 through a zero point follower circuit, the output end of the level shift circuit 2 is electrically connected to the gate of the Mp power tube 3, and the source of the Mp power tube 3 is electrically connected to a VDD power supply; the drain of the Mp power tube 3 is electrically connected to one end of an R1 resistor, the other end of the R1 resistor is grounded through an R2 resistor, and the other end of the R1 resistor is electrically connected to the positive input end of the AEA error amplifier 1; the drain of the Mp power tube 3 is grounded through a CL capacitor, and the drain of the Mp power tube 3 serves as the output end of the high power supply rejection low dropout linear regulator, outputting a voltage eliminating feedforward ripple. The drain of the Mp power tube 3 is electrically connected to a VSS through the CL capacitor; the VDD power supply is a power supply with a voltage of VDD, and the input voltage VIN of the LDO low dropout linear regulator is the voltage VDD of the VDD power supply; the Mp power tube 3 is a PMOS tube.
[0023] In the actual application process of the LDO low dropout linear regulator, there is a ripple on the VDD power supply voltage, which is derived from the previous DCDC circuit. After adopting the level shift circuit, the ripple of the output voltage of the LDO low dropout linear regulator is greatly reduced, as Figure 3As shown in the figure, the image shows that the output voltage ripple is reduced after using the level shift circuit. In the level shift circuit, the ripple on the power supply voltage is directly subtracted by a fixed level voltage to obtain a signal VGATE, which includes the fluctuation information of the power supply ripple; the obtained signal VGATE is directly loaded to the gate of the Mp power tube, and the fluctuation of the power supply voltage at the source of the Mp power tube is offset, so as to achieve the effect of power supply ripple suppression. In addition, the level shift circuit is directly embedded in the LDO loop, without the need for an additional summing amplifier, and the level shift circuit can isolate the high impedance of the first-stage AEA error amplifier and the large capacitance of the gate of the Mp power tube, which helps to improve the stability of the LDO loop.
[0024] As shown in the figure, Figure 2 The level shift circuit 2 includes an ADC amplifier 21 and an Md power tube 22; the negative input end of the ADC amplifier 21 is used as the input end of the level shift circuit 2, the output end of the ADC amplifier 21 is electrically connected to the gate of the Md power tube 22, and the power supply end of the ADC amplifier 21 is electrically connected to the VDD power supply; the drain of the Md power tube 22 is connected to the ground through the R3 resistor, and the drain of the Md power tube 22 is electrically connected to the positive input end of the ADC amplifier 21; the source of the Md power tube 22 is electrically connected to the VDD power supply through the R4 resistor, and the source of the Md power tube 22 is used as the output end of the level shift circuit 2; the Md power tube 22 is a PMOS tube.
[0025] As shown in the figure, Figures 2-3 The drain of the Md power tube 22 is electrically connected to the positive input end of the ADC amplifier 21, forming an internal loop; the voltage at the drain of the Md power tube 22 is VDC1 voltage, and the voltage input at the negative input end of the ADC amplifier 21 is VDC voltage, and due to the formed internal loop, the VDC1 voltage is equal to the VDC voltage; at this time, the voltage output by the level shift circuit 2 is the VGATE voltage, and the VGATE voltage is equal to the power supply voltage VDD minus the voltage on the R4 resistor. Assuming that the VDC voltage is a fixed level, therefore the VDC1 voltage is also a fixed level, and again assuming that the resistance value of the R4 resistor is equal to the resistance value of the R3 resistor, at this time the VGATE voltage is equal to the power supply voltage VDD minus the VDC1 voltage; from the above analysis, it can be seen that the VGATE voltage contains the ripple information of the power supply voltage; when the ripple information on the VGATE voltage is consistent with the voltage at the source of the Mp power tube 3, that is, when the voltage of the VDD power supply input at the source of the Mp power tube 3 is the same as the gate voltage of the Mp power tube 3, the influence of the power supply voltage ripple on the Mp power tube will be eliminated, the power supply suppression will be enhanced, and the effect of feedforward ripple elimination will be achieved.
[0026] As shown in the figure, Figure 4As shown, the AEA error amplifier 1 is an amplifier of NMOS current mirror; the AEA error amplifier 1 comprises an input circuit and an NMOS tube current mirror circuit; the input circuit comprises MN1 transistor, MN2 transistor and MN3 transistor; the gate of the MN1 transistor is the positive input terminal of the AEA error amplifier 1, the gate of the MN2 transistor is the negative input terminal of the AEA error amplifier 1, and the VREF reference voltage is input; the source of the MN1 transistor and the source of the MN2 transistor are both electrically connected to the drain of the MN3 transistor, the source of the MN3 transistor is grounded, that is, the source of the MN3 transistor is electrically connected to VSS; the source of the MN1 transistor and the source of the MN2 transistor are grounded through the Iadp current source, that is, the source of the MN1 transistor and the source of the MN2 transistor are electrically connected to VSS through the Iadp current source.
[0027] As shown in the figure, Figure 4 the NMOS tube current mirror circuit comprises MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, MN4 transistor, MN5 transistor, MN6 transistor and MN7 transistor; the drain of the MP1 transistor is electrically connected to the drain of the MN2 transistor and the source of the MP3 transistor, and the drain of the MP2 transistor is electrically connected to the drain of the MN1 transistor and the source of the MP4 transistor; the drain of the MP3 transistor is electrically connected to the drain of the MN6 transistor and the gate of the MN4 transistor, and the source of the MN6 transistor is electrically connected to the drain of the MN4 transistor; the drain of the MP4 transistor is electrically connected to the gate of the MN7 transistor, and the source of the MN7 transistor is electrically connected to the drain of the MN5 transistor; the gates of the MP1 transistor and the MP2 transistor are interconnected, that is, the gate of the MP1 transistor is electrically connected to the gate of the MP2 transistor; the gates of the MP3 transistor and the MP4 transistor are interconnected, that is, the gate of the MP3 transistor is electrically connected to the gate of the MP4 transistor; the gates of the MN6 transistor and the MN7 transistor are interconnected, that is, the gate of the MN6 transistor is electrically connected to the gate of the MN7 transistor; the gates of the MN4 transistor and the MN5 transistor are interconnected, that is, the gate of the MN4 transistor is electrically connected to the gate of the MN5 transistor; and the drain of the MP4 transistor is the output terminal of the AEA error amplifier 1. The sources of the MP1 transistor and the MP2 transistor are both electrically connected to the VDD power supply, and the sources of the MN4 transistor and the MN5 transistor are both grounded, that is, the sources of the MN4 transistor and the MN5 transistor are both electrically connected to VSS.
[0028] The gate of the MN3 transistor, the gate of the MP1 transistor and the gate of the MP2 transistor input Vpbias bias voltage, the gate of the MP3 transistor and the gate of the MP4 transistor input Vpcas common mode voltage, and the gate of the MN6 transistor and the gate of the MN7 transistor input Vncas differential mode voltage; the MP1 transistor, the MP2 transistor, the MP3 transistor and the MP4 transistor are PMOS transistors, and the MN1 transistor, the MN2 transistor, the MN3 transistor, the MN4 transistor, the MN6 transistor and the MN7 transistor are NMOS transistors.
[0029] The level shift circuit 2 needs a fixed DC voltage, that is, VDC voltage; in an actual circuit, a fixed DC voltage cannot be obtained, and the fixed DC voltage cannot adjust the feedback loop; therefore, the level shift circuit 2 is directly placed in the loop of the LDO low-dropout linear voltage regulator, and the AEA error amplifier 1 and the Mp power tube 3 are added; the input end of the level shift circuit 2 is connected to the P2 connection point, in order to make the voltage of the P2 connection point approximate to a fixed DC voltage, the AEA error amplifier 1 is selected as an NMOS current mirror amplifier; according to impedance analysis, the NMOS current mirror amplifier can resist power voltage ripple interference, therefore, the ripple of the output voltage of the AEA error amplifier 1 is small, is attenuated by about 100 times, and can be approximately regarded as a fixed DC voltage, which meets the offset condition of the level shift circuit 2.
[0030] The zero point follower circuit includes an MN8 transistor and a Cc capacitor; the gate of the MN8 transistor is electrically connected to the output end of the AEA error amplifier 1, the drain of the MN8 transistor is electrically connected to the input end of the level shift circuit 2 through the Cc capacitor, and the source of the MN8 transistor is grounded; the MN8 transistor is an NMPS transistor. Another possibility is that the zero point follower circuit can also be only a Cc capacitor, and the output end of the AEA error amplifier 1 is grounded through the Cc capacitor. In order to maintain the stability of the LDO low-dropout linear voltage regulator, a compensation circuit, that is, a zero point follower circuit, is added at the output position of the first-stage AEA error amplifier 1; in addition, a compensation circuit, that is, an R3 resistor, is added at the position of the drain of the Mp power tube in the loop of the level shift circuit 2; the two together guarantee the stability of the loop of the LDO low-dropout linear voltage regulator. At the same time, due to the use of the level shift circuit 2, the large impedance at the output position of the first-stage AEA error amplifier 1 and the large capacitor at the gate of the Mp power tube 3 are split, avoiding the formation of a lower pole to maintain the normal operation of the circuit.
[0031] As Figure 5As shown, the LDO low-dropout linear regulator also needs to consider the impact of load changes on the level shift circuit. When the load current increases, the voltage at the gate of the Mp power tube 3 will decrease. Therefore, when the load current continuously increases, the voltage at the gate of the Mp power tube 3 will continuously decrease, causing the current flowing through the R4 resistor in the level shift circuit 2 to increase. The current flowing through the R4 resistor will flow to the R3 resistor, thereby causing the voltage VDC1 at the drain of the Md power tube 22 to continuously increase. This will cause the drain-source voltage VDS of the Md power tube 22 to continuously decrease, resulting in the circuit being unable to work.
[0032] The R4 resistor in the level shift circuit 2 is a resistance array used to change the resistance value of the R4 resistor. To solve the problem of the operating voltage of the Md power tube 22, a load adaptive adjustment circuit is used. The MPC1 transistor in the load adaptive adjustment circuit copies the current of the Mp power tube 3 in proportion, and then compares the proportionally copied current with a preset current value to obtain a comparison result. The overall resistance value of the resistance array of the R4 resistor is then changed based on the comparison result. The greater the load current, the greater the overall resistance value of the resistance array of the R4 resistor. When the resistance value of the R4 resistor increases, the VDC1 voltage does not continuously increase and is maintained at the original voltage value, and the drain-source voltage VDS of the Md power tube 22 does not decrease and is maintained at the original voltage value, thereby ensuring the normal operation of the level shift circuit.
[0033] The load adaptive adjustment circuit 4 compares the current of the Mp power tube 3 with a preset current value and adjusts the resistance value of the R4 resistor based on the comparison result. In the initial state, the current of the Mp power tube 3 is less than the preset current value, and the load adaptive adjustment circuit 4 controls the resistance value of the R4 resistor to remain unchanged. When the current of the Mp power tube 3 is greater than the preset current value, the load adaptive adjustment circuit 4 automatically controls the resistance value of the R4 resistor to increase. When the current of the Mp power tube 3 changes from being greater than the preset current value to being less than the preset current value, the load adaptive adjustment circuit 4 controls the resistance value of the R4 resistor to decrease to the resistance value of the R4 resistor in the initial state.
[0034] As Figure 6As shown, the load adaptive adjustment circuit 4 comprises an AEA1 error amplifier 41, an AMP operational amplifier 42, an MPC1 transistor, an MP11 transistor, an MP12 transistor, an MN11 transistor, an MN12 transistor, an MN13 transistor, an MN14 transistor and a Schmitt trigger 43; the output end of the AEA1 error amplifier 41 is electrically connected to the gate of the MP11 transistor and the gate of the MPC1 transistor, the source of the MP11 transistor and the source of the MPC1 transistor are electrically connected to the VDD power supply, the drain of the MP11 transistor is electrically connected to the positive input end of the AEA1 error amplifier 41, and the negative input end of the AEA1 error amplifier 41 inputs a VREF reference voltage, which can be set according to actual needs; the drain of the MP11 transistor is connected to the ground through an RL resistor, the drain of the MP11 transistor is electrically connected to the positive input end of the AMP operational amplifier 42, and the drain of the MPC1 transistor is electrically connected to the negative input end of the AMP operational amplifier 42; the drain of the MPC1 transistor is electrically connected to the source of the MP12 transistor, the output end of the AMP operational amplifier 42 is electrically connected to the gate of the MP12 transistor, the drain of the MP12 transistor is electrically connected to the drain and the gate of the MN11 transistor, and the source of the MN11 transistor is connected to the ground. Through the connection of the circuit, the MPC1 transistor proportionally replicates the current of the Mp power tube 3, then the current of the MPC1 transistor is compared with the preset current value, and the resistance value of the resistance array of the R4 resistor is adjusted.
[0035] The drain of the MP12 transistor is electrically connected to the gate of the MN12 transistor and the gate of the MN13 transistor, the source of the MN12 transistor is connected to the ground, and the drain of the MN12 transistor and the drain of the MN13 transistor are both electrically connected to the VDD power supply through an Ib current source, and the drain of the MN12 transistor and the drain of the MN13 transistor are both electrically connected to the input end of the Schmitt trigger 43, and the output end of the Schmitt trigger 43 serves as the output end of the load adaptive adjustment circuit 4. The source of the MN13 transistor is electrically connected to the drain of the MN14 transistor, the source of the MN14 transistor is connected to the ground, and the gate of the MN14 transistor is electrically connected to the output end of the Schmitt trigger 43. The output end of the Schmitt trigger 43 outputs a control signal to control the resistance value change of the resistance array of the R4 resistor, and adjusts the resistance value of the resistance array of the R4 resistor according to the control signal. The MP11 transistor, the MP12 transistor and the MPC1 transistor are all PMOS tubes; the MN11 transistor, the MN12 transistor, the MN13 transistor and the MN14 transistor are all NMOS tubes, and the MN14 transistor is an enhancement mode N-channel metal oxide semiconductor field effect transistor.
[0036] As Figure 4As shown, the high power supply rejection low dropout linear regulator mainly includes the first-stage AEA error amplifier 1, the zero-point follower circuit, the ADC amplifier 21 in the level shifting circuit 2, and the power stage circuit; the power stage circuit is the circuit where the Mp power transistor 3 is located. The first-stage AEA error amplifier 1 uses a folded cascode amplifier with an NMOS current mirror, which can suppress the power supply ripple on the first-stage amplifier, making the output of the first-stage AEA error amplifier 1 approximately DC voltage, thus satisfying the precondition for level feedforward ripple elimination.
[0037] like Figure 7 As shown in the figure, the simulation results of the circuit built based on the present invention are as follows: the upper waveform is the PSR waveform without level ripple cancellation technology, and the lower waveform is the PSR waveform with level ripple cancellation. The comparison results show that the technology proposed in this invention can enhance the power supply ripple by 32dB at 1KHz and by about 20dB at 1MHz, and the power supply suppression effect is obvious.
[0038] The above description is merely a preferred embodiment of the present invention. Those skilled in the art can make several modifications and optimizations based on the above disclosure without departing from the basic principles described above. These modifications and optimizations should be considered within the scope of protection as understood by the present invention.
Claims
1. A high power-supply rejection low-dropout linear voltage regulator based on level feed-forward ripple cancellation, characterized by: It comprises an AEA error amplifier (1), a level shift circuit (2) and an Mp power tube (3); the output end of the AEA error amplifier (1) is electrically connected to the input end of the level shift circuit (2) through a zero point follow-up circuit, the output end of the level shift circuit (2) is electrically connected to the gate of the Mp power tube (3), and the source of the Mp power tube (3) is electrically connected to a VDD power supply; The drain of the Mp power tube (3) is electrically connected to one end of an R1 resistor, the other end of the R1 resistor is grounded through an R2 resistor, and the other end of the R1 resistor is electrically connected to the positive input end of the AEA error amplifier (1); the drain of the Mp power tube (3) is grounded through a CL capacitor, and the drain of the Mp power tube (3) serves as an output end of a high power supply to suppress a low voltage difference linear voltage stabilizer, and outputs a voltage for eliminating feedforward ripple.
2. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 1, wherein: The level shift circuit (2) comprises an ADC amplifier (21) and an Md power tube (22); the negative input end of the ADC amplifier (21) serves as the input end of the level shift circuit (2), and the output end of the ADC amplifier (21) is electrically connected to the gate of the Md power tube (22); the drain of the Md power tube (22) is grounded through an R3 resistor, and the drain of the Md power tube (22) is electrically connected to the positive input end of the ADC amplifier (21); The source of the Md power tube (22) is electrically connected to a VDD power supply through an R4 resistor, and the source of the Md power tube (22) serves as the output end of the level shift circuit (2).
3. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 1, wherein: The AEA error amplifier (1) is an NMOS current mirror amplifier.
4. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 3, wherein: The AEA error amplifier (1) comprises an input circuit and an NMOS tube current mirror circuit; the input circuit comprises MN1, MN2 and MN3 transistors; the gate of the MN1 transistor serves as the positive input end of the AEA error amplifier (1), the gate of the MN2 transistor serves as the negative input end of the AEA error amplifier (1), and a VREF reference voltage is input; the source of the MN1 transistor and the source of the MN2 transistor are both electrically connected to the drain of the MN3 transistor, and the source of the MN3 transistor is grounded; the source of the MN1 transistor and the source of the MN2 transistor are grounded through an Iadp current source.
5. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 4, wherein: The NMOS transistor current mirror circuit comprises MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, MN4 transistor, MN5 transistor, MN6 transistor and MN7 transistor; the drain of the MP1 transistor is electrically connected with the drain of MN2 transistor and the source of MP3 transistor, the drain of the MP2 transistor is electrically connected with the drain of MN1 transistor and the source of MP4 transistor; the drain of the MP3 transistor is electrically connected with the drain of MN6 transistor and the gate of MN4 transistor, the source of MN6 transistor is electrically connected with the drain of MN4 transistor; the drain of MP4 transistor is electrically connected with the gate of MN7 transistor, the source of MN7 transistor is electrically connected with the drain of MN5 transistor; the gates of MP1 transistor and MP2 transistor are interconnected, the gates of MP3 transistor and MP4 transistor are interconnected, the gates of MN6 transistor and MN7 transistor are interconnected, the gates of MN4 transistor and MN5 transistor are interconnected; the drain of MP4 transistor is the output terminal of the AEA error amplifier (1).
6. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 1, wherein: The zero point following circuit comprises MN8 transistor and Cc capacitor; the gate of the MN8 transistor is electrically connected with the output terminal of the AEA error amplifier (1), the drain of the MN8 transistor is electrically connected with the input terminal of the level shift circuit (2) through the Cc capacitor, and the source of the MN8 transistor is grounded.
7. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 2, wherein: The R4 resistor in the level shift circuit (2) is a resistor array, which is used to change the resistance value of the R4 resistor.
8. The high power-supply rejection low-dropout linear voltage regulator based on level- feedforward ripple cancellation of claim 7, wherein: The load adaptive adjustment circuit (4) is further comprised; the load adaptive adjustment circuit (4) compares the current of the Mp power transistor (3) with the preset current value, and adjusts the resistance value of the R4 resistor according to the comparison result; in the initial state, the current of the Mp power transistor (3) is less than the preset current value, and the load adaptive adjustment circuit (4) controls the resistance value of the R4 resistor to remain unchanged; when the current of the Mp power transistor (3) is greater than the preset current value, the load adaptive adjustment circuit (4) automatically controls the resistance value of the R4 resistor to become larger.