Chip testing method and device, equipment, storage medium and program product

Abstract

The invention provides a chip testing method and device, equipment, a storage medium and a program product. The method comprises the steps that operator codes, comprising multiple chip interface instructions, of a target operator are obtained, the target operator and a reference operator have the same calculation function, the chip interface instructions are used for achieving at least one hardware operation of a chip, and the hardware operations combining the multiple chip interface instructions are used for achieving the calculation function; analyzing the operator code to obtain a machine code file of the chip; test data are obtained, the test data and the machine code file are transmitted to chip simulation equipment, the chip simulation equipment is used for executing the machine code file on the test data, and a simulation calculation result of the target operator for the test data is obtained; obtaining a simulation calculation result from chip simulation equipment, and obtaining a reference calculation result of the reference operator for the test data; and generating a test result of the chip based on the simulation calculation result and the reference calculation result. According to the invention, the chip test progress can be accelerated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a chip testing method, device, equipment, storage medium and program product. BACKGROUND

[0002] Chip design involves million lines of hardware and software code, and function verification is a key link to ensure the correctness of chip design, which needs to be realized through multi-stage testing such as software simulation, hardware simulation and prototype verification. However, after the completion of chip hardware design, the development of software stack is often lagging behind the hardware progress, and the incompleteness of software stack leads to the delay of prototype verification of the chip, which slows down the chip testing progress. SUMMARY

[0003] The embodiments of the present application provide a chip testing method, device, electronic equipment, computer readable storage medium and computer program product, which can accelerate the chip testing progress.

[0004] The technical scheme of the embodiments of the present application is implemented as follows: The embodiments of the present application provide a chip testing method, comprising: obtaining operator code of a target operator comprising a plurality of chip interface instructions, wherein the target operator and a benchmark operator have the same computing function, the chip interface instruction is used to realize at least one hardware operation of the chip, and the hardware operation of the plurality of chip interface instructions is used to realize the computing function; parsing the operator code to obtain a machine code file of the chip; obtaining test data and transmitting the test data and the machine code file to a chip simulation device, wherein the chip simulation device is used to execute the machine code file on the test data to obtain a simulation computing result of the target operator for the test data; obtaining the simulation computing result from the chip simulation device and obtaining a benchmark computing result of the benchmark operator for the test data; generating a test result of the chip based on the simulation computing result and the benchmark computing result.

[0005] The embodiments of the present application also provide a chip testing device, comprising: a first obtaining module, configured to obtain operator code of a target operator comprising a plurality of chip interface instructions, wherein the target operator and a benchmark operator have the same computing function, the chip interface instruction is used to realize at least one hardware operation of the chip, and the hardware operation of the plurality of chip interface instructions is used to realize the computing function; a parsing module, configured to parse the operator code to obtain a machine code file of the chip; The transmission module is configured to acquire test data and transmit the test data and the machine code file to a chip simulation device, where the chip simulation device is configured to execute the machine code file on the test data to obtain a simulation calculation result of the target operator on the test data; The second acquisition module is configured to acquire the simulation calculation result from the chip simulation device and acquire a benchmark calculation result of the benchmark operator on the test data. The generation module is configured to generate a test result of the chip based on the simulation calculation result and the benchmark calculation result.

[0006] Embodiments of the present application also provide an electronic device, comprising: A memory configured to store computer executable instructions; A processor configured to execute the computer executable instructions stored in the memory to implement the chip test method provided by the embodiments of the present application.

[0007] Embodiments of the present application also provide a computer readable storage medium storing computer executable instructions or a computer program, and the computer executable instructions or the computer program are executed by a processor to implement the chip test method provided by the embodiments of the present application.

[0008] Embodiments of the present application also provide a computer program product comprising computer executable instructions or a computer program, and the computer executable instructions or the computer program are executed by a processor to implement the chip test method provided by the embodiments of the present application.

[0009] The embodiments of the present application have the following beneficial effects: The operator code of the target operator (having the same calculation function as the benchmark operator) is implemented by combining the chip interface instructions. Since the chip interface instructions can implement at least one hardware operation of the chip, the machine code file of the chip can be obtained by parsing the operator code. Thus, the machine code file is run on the chip simulation device to obtain the simulation calculation result. Finally, the test result of the chip is generated by combining the simulation calculation result and the benchmark calculation result. In this way, the operator code is implemented based on the chip interface instructions, and the operator simulation is performed in combination with the chip simulation device. Thus, the chip test can be implemented in advance from the operator level, without waiting for the software stack to be developed completely, thereby accelerating the chip test progress. Moreover, the test result is generated by combining the simulation calculation result and the benchmark calculation result, thereby ensuring the completeness of the chip test. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is an architecture schematic diagram of the chip test system provided by the embodiments of the present application; Figure 2 is a structure schematic diagram of the electronic device provided by the embodiments of the present application; Figure 3 is a first flowchart of a chip testing method provided by an embodiment of the present application; Figure 4 is a second flowchart of a chip testing method provided by an embodiment of the present application; Figure 5 is a third flowchart of a chip testing method provided by an embodiment of the present application; Figure 6 is a fourth flowchart of a chip testing method provided by an embodiment of the present application; Figure 7 is a fifth flowchart of a chip testing method provided by an embodiment of the present application.

[0011] It should be noted that the above-mentioned "first", "second" are only used to distinguish different schemes, and do not represent the advantages or disadvantages of the schemes or the priority in the implementation process. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be described in more detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0013] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0014] In the following description, the terms "first\second\third" are only used to distinguish similar objects, and do not represent the specific order of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0015] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as processing circuit or memory) or combination thereof. Similarly, one processor (or multiple processors or memory) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that includes the functions of the module or unit.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the application belong. The terminology used in the description of embodiments of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0017] The relevant data collection processing in the embodiments of the application should be strictly in accordance with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and within the scope of authorization of laws and regulations and the personal information subject, carry out subsequent data use and processing behavior.

[0018] Before further detailing the embodiments of the application, the terms and phrases involved in the embodiments of the application are explained, and the terms and phrases involved in the embodiments of the application are applicable to the following explanations.

[0019] 1) Target operator, refers to the basic functional unit in the chip to realize the specific computing function (such as matrix multiplication, attention mechanism algorithm, activation function, etc. in deep learning). Its core feature is: based on at least one chip instruction encapsulated chip interface instruction (API instruction) for coding implementation, the interface and the computing function need to be consistent with the benchmark operator in the deep learning framework (such as Torch), which is the basic functional unit of the chip for accelerated computing, and needs to realize its computing logic through the operator code. The target operator is the test object in the prototype verification stage, and the execution logic of the target operator is run on the chip simulation device to verify the correctness and completeness of the chip hardware design, and the test scene is close to the actual running situation of the product.

[0020] 2) Chip interface instruction, namely API instruction, based on at least one chip instruction pre-encapsulated application programming interface (i.e. upper interface of chip instruction), each API instruction is used to realize one or a group of basic hardware operations of the chip (such as data loading, thread configuration, operation execution, etc.), but the details of the underlying binary instruction are shielded, and a more concise function or interface form is presented. In this way, the API instruction simplifies the direct operation of the chip underlying hardware instruction, provides a more user-friendly programming interface for the developer, so that the developer does not need to directly process the binary instruction, but only needs to call the interface to realize the control of the hardware, which is convenient for the software level coding of the operator. Using API instructions, operator code that implements specific computing functions (such as convolution, pooling, etc. in deep learning) is written, that is: combining multiple API instructions can realize specific computing functions.

[0021] 3) Chip instruction, which is a set of bottom-layer operation rules that can be directly recognized and executed by chip hardware, is the basic specification of chip design. It defines the basic hardware operations (such as data transmission, operation, logical judgment, etc.) that can be completed by the chip, operation code (binary code identifying specific operations), operand format (such as register address, memory address), addressing mode, and other core contents, which is the "bottom-layer language" for the interaction between hardware and software. Chip instruction is the basis for API instruction encapsulation and the basis for the compiler or emulator to parse API instructions in the operator code, that is, API instructions are parsed into binary instructions (0, 1 sequence) conforming to the chip instruction set, which can be executed by chip hardware.

[0022] 4) Chip emulation device, i.e. Emulator device, which is a special test platform for chip prototype verification stage. It is used to simulate the running environment of the chip and verify the function and performance of the chip hardware design before the actual chip production. Specifically, the hardware design of the chip (such as instruction set, operator execution logic, storage format, etc.) needs to be tested through the Emulator device to verify the correctness, completeness and performance of the chip hardware design. In summary, the Emulator device is a "simulation carrier" for chip prototype verification, and the hardware design of the chip is verified through the simulation test of the Emulator device, thereby accelerating the process from chip design to chip production.

[0023] The embodiments of the present application provide a chip testing method and device, electronic equipment, computer readable storage medium and computer program product, which can accelerate the chip testing progress. Next, based on the above description of the terms and terms involved in the embodiments of the present application, the embodiments of the present application will be described in detail.

[0024] The chip testing system provided by the embodiments of the present application is described below. Referring to Figure 1 , Figure 1 is the architecture schematic diagram of the chip testing system provided by the embodiments of the present application. To realize one exemplary application, the chip testing system 100 includes a terminal 200 and a chip emulation device 300.

[0025] The terminal 200 obtains operator code of a target operator including a plurality of chip interface instructions in response to a chip test instruction (e.g., triggered by a user on the terminal 200), wherein the target operator and the reference operator have the same calculation function, the chip interface instructions are used to implement at least one hardware operation of the chip, and the hardware operations of the plurality of chip interface instructions are used to implement the calculation function; the operator code is parsed to obtain a machine code file of the chip; test data is obtained and transmitted to the chip simulation device 300 together with the machine code file; the chip simulation device 300 receives the test data and the machine code file sent by the terminal 200; the test data is executed by the machine code file to obtain a simulation calculation result of the target operator for the test data; the terminal 200 obtains the simulation calculation result from the chip simulation device 300 and obtains a reference calculation result of the reference operator for the test data; and a test result of the chip is generated based on the simulation calculation result and the reference calculation result.

[0026] In some embodiments, the chip test method provided by the embodiments of the present application is implemented by an electronic device. For example, the chip test method can be implemented by a terminal alone, implemented by a server alone, or implemented by a terminal and a server cooperatively. The electronic device implementing the chip test method provided by the embodiments of the present application can be various types of terminals or servers. The server can be a standalone physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud service, cloud database, cloud computing, cloud function, cloud storage, network service, cloud communication, middleware service, domain name service, security service, content delivery network (CDN), and big data and artificial intelligence platform. The terminal can be a notebook computer, a tablet computer, a desktop computer, etc., but is not limited thereto. The terminal and the server can be connected directly or indirectly through wired or wireless communication, and the embodiments of the present application do not limit this.

[0027] The electronic device implementing the chip test method provided by the embodiments of the present application is described below. Referring to Figure 2 , Figure 2 FIG. 1 is a structural schematic diagram of an electronic device provided by the embodiments of the present application. The electronic device 500 provided by the embodiments of the present application can be a terminal or a server. As shown in Figure 2 , the electronic device 500 includes at least one processor 510, a memory 550, at least one network interface 520, and a user interface 530. The various components in the electronic device 500 are coupled together through a bus system 540. It can be understood that the bus system 540 is used to realize the connection and communication between the components. In addition to the data bus, the bus system 540 also includes a power bus, a control bus, and a status signal bus. However, for the purpose of clear illustration, only the data bus is shown in Figure 2The various buses are together referred to as bus system 540.

[0028] Processor 510 can be an integrated circuit chip having signal processing capabilities, such as a general purpose processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like. The general purpose processor can be a microprocessor, or any conventional processor, or the like.

[0029] User interface 530 includes one or more output devices 531 that enable presentation of media content, including one or more speakers and / or one or more visual display screens. User interface 530 also includes one or more input devices 532 that facilitate user input, such as a keyboard, a mouse, a microphone, a touch screen display, a camera, other input buttons and controls, and the like.

[0030] Memory 550 can be removable, non-removable, or a combination thereof. Memory 550 can include one or more memory devices physically located in proximity to processor 510. Memory 550 includes volatile memory or non-volatile memory, and can include both volatile and non-volatile memory. Non-volatile memory can be read only memory (ROM), and volatile memory can be random access memory (RAM). The memory 550 described in embodiments of the present application is intended to include any suitable type of memory.

[0031] In some embodiments, memory 550 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or a subset or superset thereof, which are illustratively described below. Among these are an operating system 551, including system programs for handling various basic system services and performing hardware dependent tasks, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and handling hardware-dependent tasks; a network communication module 552 for communicating to other electronic devices via one or more network interfaces 520 (wired or wireless), examples of which include Bluetooth, Wireless Fidelity (Wi-Fi), Universal Serial Bus (USB), and the like; a presentation module 553 for enabling presentation of information via one or more output devices 531 associated with user interface 530 (e.g., a display screen, a speaker, and the like) (e.g., a user interface for operating peripheral devices and displaying content and information); and an input processing module 554 for detecting and interpreting one or more user inputs or interactions from one or more input devices 532.

[0032] In some embodiments, the chip testing apparatus provided by the embodiments of the present application can be implemented in a software manner, Figure 2 A chip testing apparatus 555 stored in the memory 550 is shown, which can be software in the form of programs and plug-ins, etc., including the following software modules: a first obtaining module 5551, an analyzing module 5552, a transmitting module 5553, a second obtaining module 5554 and a generating module 5555, which are logical, and thus can be combined or further split according to the implemented functions, and the functions of the modules will be described below.

[0033] The chip testing method provided by the embodiments of the present application will be described below. As described above, the chip testing method provided by the embodiments of the present application is implemented by an electronic device, for example, can be implemented by a server or a terminal alone, or by a server and a terminal cooperatively. Therefore, the execution subject of each step will not be repeated below. Referring to Figure 3 , Figure 3 is a first flowchart of the chip testing method provided by the embodiments of the present application, and the chip testing method provided by the embodiments of the present application includes: Step 101: obtaining operator code of a target operator including a plurality of chip interface instructions.

[0034] The target operator and the reference operator have the same computing function, the chip interface instruction is used to implement at least one hardware operation of a chip, and the hardware operation of combining the plurality of chip interface instructions is used to implement the computing function.

[0035] For step 101, the operator code of the target operator is first obtained, which can be obtained by programming in advance. The operator code includes a plurality of chip interface instructions. The operator code implements the same computing function as the reference operator by combining the hardware operations of the plurality of chip interface instructions. It should be noted that the operator has a clear input / output format, function definition and behavior logic. Here, the target operator is required to completely match the reference operator in terms of interface (such as input data type, quantity, output result format) and computing function. The chip interface instruction is a pre-packaged application program interface (i.e., the upper interface of the chip instruction) based on at least one chip instruction. Each API instruction is used to implement one or a group of basic hardware operations (such as data loading, thread configuration, operation execution, etc.) of a chip. The chip instruction is a bottom layer operation rule set that can be directly recognized and executed by the chip hardware, and is a basic specification of the chip design.

[0036] In some embodiments, the number of chip interface instructions is M, M is an integer greater than 1; based on the step 101 of "obtaining the operator code of the target operator including a plurality of chip interface instructions" being performed before, the following steps can also be performed: obtaining N chip instructions, each chip instruction being used to implement a hardware operation of a chip, N being an integer greater than or equal to M; packaging the N chip instructions to obtain the M chip interface instructions, each chip interface instruction including at least one chip instruction.

[0037] Here, first, N chip instructions are obtained, the N chip instructions being a chip instruction set. The chip instruction is a set of bottom layer operation rules that can be directly recognized and executed by chip hardware, and by packaging the N chip instructions, M chip interface instructions are obtained, each chip interface instruction including at least one chip instruction. Since the chip instruction is a set of bottom layer operation rules that can be directly recognized and executed by chip hardware, the chip interface instruction is also a hardware instruction that can be directly recognized and executed by chip hardware, so as to ensure that the operator code programmed based on the chip interface instruction is also supported by chip hardware recognition and execution, providing a basis for subsequent operator simulation based on the operator code by the chip simulation device, so as to implement verification and testing of the chip.

[0038] By applying the above embodiments, 1) the development threshold is reduced: without directly operating the bottom layer hardware instruction (i.e., the chip instruction), the developer can quickly implement the operator function through the high layer API instruction, reduce the dependence on the details of the chip instruction, and improve the development efficiency of the operator code. 2) The code compatibility is enhanced: the API instruction as an intermediate layer can shield the differences between different chip instruction sets, so that the operator code is reused on multiple hardware platforms, and the cross-platform adaptation cost is reduced. 3) The implementation correctness is guaranteed: the API instruction encapsulates the verified hardware operation logic, reduces the errors that may occur when directly writing the operator code, and indirectly improves the correctness of the operator function. 4) The testing and iteration are facilitated: the operator code based on the API instruction can be quickly self-tested in the simulator, and when modified, only the API instruction calling logic needs to be adjusted, without the need to reconstruct the bottom layer instruction, so as to accelerate the iteration process. 5) The software and hardware collaboration is supported: the API instruction establishes a standardized interface for the software operator and the chip instruction set, so that the software development and hardware design can be promoted in parallel, and the overall chip research and development period is shortened.

[0039] In some embodiments, referring to Figure 4The "obtaining N chip instructions" can be implemented by performing the following steps: step 201, obtaining an instruction description file of N chip instructions to be generated, the instruction description file including: domain segment definition information of a plurality of instruction domain segments included in each chip instruction to be generated, and a combination format of the plurality of instruction domain segments; step 202, for each chip instruction to be generated, generating a domain segment parameter of each instruction domain segment based on the domain segment definition information of each domain segment included in the chip instruction to be generated; and step 203, for each chip instruction to be generated, combining the domain segment parameters of the plurality of instruction domain segments included in the chip instruction to be generated according to the combination format of the plurality of instruction domain segments to obtain the chip instruction.

[0040] For step 201, each chip instruction to be generated includes a plurality of instruction domain segments, and the domain segment definition information of each instruction domain segment included in the instruction description file and the combination format of the instruction domain segments. For example, (1) the domain segment definition information: clearly defines the specific rules of the plurality of instruction domain segments (such as the operation code domain, the address code domain, the data domain, etc.) contained in each chip instruction to be generated, for example, the bit width (such as 8 bits) of the operation code domain, the value range (such as 00H-FFH corresponding to different operations), the addressing mode (such as direct addressing, indirect addressing) of the address code domain, etc., to ensure that the subsequent generated domain segment parameters meet the hardware recognizable standard. (2) The domain segment combination format: specifies the splicing order and overall structure of the plurality of instruction domain segments, such as the fixed order of "operation code domain (8 bits) + address code domain (16 bits) + data domain (32 bits)", to ensure that the finally generated chip instruction meets the binary format specification of the chip instruction set, and provides a premise for subsequent hardware parsing and execution.

[0041] For step 202, according to the domain segment definition information, a legal specific parameter value is generated for each instruction domain segment. For example, if the domain segment definition information of the instruction domain segment "operation code domain" defines "01H corresponding to addition operation", the domain segment parameter "01H" is generated for the operation code domain of the addition instruction; if the domain segment definition information of the instruction domain segment "address code domain" defines "16-bit direct addressing, value range 0000H-FFFFH", the domain segment parameter "1234H" is generated for the address code domain. It should be noted that the generation process of the domain segment parameter needs to strictly follow the rules of the bit width, value constraints, etc. of the domain segment, to avoid the parameter exceeding the hardware recognizable range, and to ensure the independence and legality of the domain segment parameter of each instruction domain segment.

[0042] For step 203, the domain segment parameters of the plurality of instruction domain segments included in the chip instruction to be generated are combined according to the combination format of the plurality of instruction domain segments to obtain the chip instruction. For example, the combination format of the chip instruction to be generated is "operation code (8 bits) + address code (16 bits) + data domain (32 bits)", and if the domain segment parameters of the respective instruction domain segments are 01H (8 bits), 1234H (16 bits), and 56789ABC (32 bits), respectively, the combination format is 01 12 34 56 78 9A BC (binary format). After combination, a complete chip instruction is formed, which conforms to the instruction analysis logic of the chip hardware and can be directly used for subsequent simulation testing, realizing the conversion from "hardware rules to hardware instructions".

[0043] By applying the above embodiment, 1) the instruction generation normativity is guaranteed: step 201 clearly defines the domain segment definition information and the combination format, providing a unified standard for chip instruction generation, avoiding the situation that the hardware cannot parse due to format confusion; and steps 202 and 203 generate and combine the parameters according to the rules, ensuring that the chip instruction conforms to the chip instruction set specification and laying a correct instruction foundation for subsequent simulation testing. 2) The instruction generation efficiency is improved: through the standardized process of "defining according to the description file -> generating parameters -> combining instructions", N chip instructions can be generated in batches without defining the format and parameters one by one, reducing manual operation and repetitive work, and adapting to the multi-instruction scene demand in chip testing. 3) The test flexibility and controllability are enhanced: different types and functions of chip instructions can be quickly generated by modifying the instruction description file (such as adjusting the domain segment definition and the combination format), flexibly adapting to diversified testing needs (such as operator testing and abnormal testing), and it is convenient to trace the instruction generation logic, reducing the problem troubleshooting difficulty.

[0044] Step 102: parsing the operator code to obtain a machine code file of the chip.

[0045] For step 102, the operator code is supported for parsing, and by means of a simulator or a compiler, the operator code is parsed to obtain a machine code file that can be run by the chip, so that the chip simulation device of the chip can run the machine code file to simulate the target operator, and thus the design correctness of the chip is verified based on the simulation calculation result.

[0046] In some embodiments, before performing step 102 "parsing the operator code to obtain a machine code file of the chip", the following step can also be performed: obtaining the test code of the target operator. Based on this, step 102 "parsing the operator code to obtain a machine code file of the chip" can be implemented by performing the following steps: parsing the test code to obtain the control logic of the target operator; based on the control logic, parsing the operator code to obtain the calculation logic of the target operator; and integrating the control logic and the calculation logic to obtain the machine code file.

[0047] Here, test code is also written for the target operator. The test code can also be parsed together with the operator code. Specifically, first, the test code is parsed to obtain the control logic of the target operator, for example, the control logic can include: a calling statement of the target operator, result comparison logic, an operator name and parameters of the target operator (such as an address of input data obtained when the machine code is executed, an address of output data, etc.). Then, based on the control logic, the operator code is parsed to obtain the calculation logic of the target operator. For example, based on the operator calling information (such as the calling statement, the operator name and parameters, the input data address, the output data address, etc.) in the control logic, the operator code of the target operator to be parsed is located, so that the operator code is parsed to obtain the calculation logic of the target operator, for example, the calculation logic can include: called API instructions (such as data reading API instructions, operation API instructions, result storage API instructions), a calculation flow (such as loop logic of matrix multiplication, judgment logic of an activation function, etc.), resources required for operator calculation (such as temporary storage space, register usage, etc.). Finally, the control logic and the calculation logic are integrated to obtain a machine code file of the target operator, and the machine code file is a chip instruction stream, and the chip instruction stream (all machine codes) includes but is not limited to: an operator execution process, a storage address of data required for operator calculation on a chip, a storage address of the chip instruction stream on the chip, a storage address of output data after operator execution is completed, etc.

[0048] By applying the above embodiments, 1) hardware execution is adapted: high-level code (i.e., operator code and test code) is converted into binary chip instruction streams that can be directly run on a chip, realizing mapping of software logic to hardware operation, and enabling the operator function to be executed on a chip simulation platform. 2) Test closed loop is opened: the chip instruction stream integrates the control logic of the test code and the calculation logic of the operator code, ensuring that the whole process of test data loading, operator calling, result output, etc. is completely reproduced on the hardware level, providing a basis for subsequent result verification. 3) Performance analysis is supported: the execution process of the chip instruction stream is directly reflected in the hardware timing, providing accurate instruction-level granularity basis for extracting performance data such as calculation time consumption and resource utilization, and assisting architecture optimization.

[0049] In some embodiments, the number of target operators is multiple; based on this, refer to Figure 5The step 102 of "parsing the operator code to obtain the machine code file of the chip" can be implemented by performing the following steps 1021-1024: step 1021, obtaining the dependency relationship between the plurality of target operators, and constructing a topology graph with the target operators as nodes and the dependency relationship as directed edges; step 1022, determining the execution order of the plurality of target operators according to the topology graph; step 1023, parsing the operator code to obtain the execution instruction of each target operator; and step 1024, integrating the execution instructions of the plurality of target operators based on the execution order of the plurality of target operators to obtain the machine code file of the chip.

[0050] For step 1021, the dependency relationship between the plurality of target operators is obtained, and the plurality of target operators combined together can implement more complex operator functions than a single operator, such as a specific machine learning model composed of a plurality of target operators, an image recognition model, etc. The dependency relationship can include: 1) data dependency relationship: if the input of operator B is the output of operator A (such as "the output feature map of the convolution operator as the input of the activation operator"), a one-way dependency of "operator A→operator B" is formed; 2) timing dependency relationship: if operator C must be started after operators A and B are both executed (such as "the pooling operator needs to wait for the completion of the convolution and activation operators"), a multi-source dependency of "operator A, operator B→operator C" is formed; 3) no dependency relationship: if the input and output of operator D and operator E are independent of each other (such as two parallel convolution branches), it is determined that the two operators have no dependency relationship and can be executed in parallel. The dependency relationship can be extracted in combination with the data transmission logic between the target operators in the operator code (such as the binding of the output address and the input address).

[0051] Thus, a topology graph is constructed with the target operators as nodes and the dependency relationship as directed edges (representing the dependency direction of the dependency relationship). Each node corresponds to a target operator and can include the operator name, function (such as convolution, activation), input / output data address, and required hardware resources (such as operation unit, register); the directed edge represents the dependency direction of the dependency relationship, such as the edge of "convolution operator→activation operator" marked as "data transmission: convolution output address→activation input address"; for nodes with no dependency relationship (such as operator D and operator E), "parallel" is marked in the topology graph, which provides a basis for subsequent thread allocation.

[0052] For step 1022, the execution order of the plurality of target operators is determined according to the topology graph. For example, 1) serial execution: for an operator chain with one-way dependency, the execution is performed in the order of the path of the topology graph, and the output address of the previous operator is automatically used as the input address of the next operator; (2) parallel execution: for operators without dependency, the operators are assigned to different threads for parallel execution, and the number of threads and the instruction fetch address are configured through the chip running configuration file to ensure that the resources do not conflict; (3) for multi-source dependency (such as operator A, operator B→operator C), operator A and operator B are executed in parallel first, and after both of them are completed (triggered through a synchronization instruction), operator C is executed in series.

[0053] For step 1023, the execution instructions of each target operator are determined from the operator code by parsing the operator code. For step 1024, the execution instructions of the plurality of target operators are integrated according to the execution order of the plurality of target operators to obtain a machine code file of the chip. In this way, when the machine code file is executed, the target operators can be executed according to the execution order of the plurality of target operators.

[0054] By applying the above embodiments, 1) the correctness of the test logic is ensured: the operator dependency and the execution order are determined through the topology graph, the distortion of the test result caused by out-of-order execution is avoided, the test flow on the chip simulation device is ensured to comply with the operator function logic, and a reliable basis is provided for subsequent result verification. 2) The test efficiency is improved: the redundant operations are reduced by sequentially parsing and integrating the instructions, the generation of the machine code file is accelerated, and thus the operator test is carried out in advance, the prototype verification pace is accelerated, and the test period is shortened. 3) The test completeness is enhanced: the multi-operator collaborative scenario is completely covered, the real running environment is simulated through the ordered integration of the instructions, the dependency conflict problems that are difficult to be found in single-operator testing are exposed, and the prototype verification of the chip design is facilitated.

[0055] Step 103: Obtain test data, and transmit the test data and the machine code file to the chip simulation device.

[0056] The chip simulation device is configured to execute the machine code file on the test data to obtain the simulation calculation result of the target operator for the test data.

[0057] For step 103, first, test data is obtained, which can be pre-generated, and the test data is used to calculate the benchmark calculation result of the benchmark operator as a comparison benchmark. For example, the test data can be generated in the following ways: 1) generating basic test data: generating standardized input data (such as matrices, vectors, scalars, etc.) according to the calculation function and interface of the target operator, covering normal scenarios (such as typical numerical ranges) and basic boundary values (such as zero values, maximum values, and minimum values). For example, for an addition operator, generate positive and negative integers and small arrays to ensure that the basic function is covered. 2) Constructing boundary and extreme test data: generating extreme data manually or through scripts for limit scenarios that the hardware may face, such as large-dimension matrices, precision critical values (such as the smallest positive value of a floating-point number), and abnormal format data (such as non-aligned address data). Such data is used to verify the hardware's ability to handle boundary conditions and expose potential overflow, precision loss, or address access errors. 3) Reusing real business scenario data: extracting real data (such as actual image pixel matrices and speech signal feature vectors) from chip target application scenarios (such as AI inference and image processing), and converting them into test data. This type of data is closer to actual usage scenarios and can more realistically verify the hardware's performance in a product environment, improving the practicality of the verification. 4) Random data expansion test coverage: generate a large amount of unexpected data through random number generation algorithms (such as pseudo-random number generators) to increase the randomness and coverage of the test. Random data can be combined with the data generated in the above directed manner to find occasional hardware logic vulnerabilities or data dependency issues in large-scale simulations.

[0058] After obtaining the test data, the test data and the machine code file are transmitted to the chip simulation device. Specifically, the chip simulation device has a corresponding data loading method, and the chip simulation device provides a corresponding loading path for the data loading method. The test data and the machine code file are loaded into (or imported into) the chip simulation device through the loading path corresponding to the data loading method (i.e., a debugging interface or a special loading channel reserved by the chip simulation device). In this way, the chip simulation device obtains and stores the test data and the machine code file.

[0059] The chip simulation device executes the machine code file on the test data to execute the calculation function of the target operator on the test data, thereby obtaining the simulation calculation result of the target operator on the test data. In actual applications, the chip simulation device can reset the state of the chip simulation device (such as emptying the registers, memory address space, and thread state) before executing the machine code file, clear the interference state of the environment before executing the machine code file, ensure the purity of the environment of this simulation (i.e., executing the machine code file on the test data), and improve the correctness of the simulation calculation result.

[0060] In some embodiments, the following steps can also be performed: obtaining a chip running configuration file of the chip; based on this, the step of "transmitting the test data and the machine code file to the chip simulation device" can be implemented by the following steps: transmitting the chip running configuration file, the test data and the machine code file to the chip simulation device, wherein the chip running configuration file is used for the chip simulation device to execute the machine code file on the test data based on the chip running configuration file to obtain the simulation calculation result.

[0061] Here, the chip running configuration file is an executable file obtained by being pre-written and compiled, and is used for configuring chip running parameters (such as execution mode, thread number, instruction fetch address), adding synchronization instructions, and controlling the start, running and end of the test flow. The chip running configuration file includes the following configurations: (1) configuring chip execution mode; (2) configuring chip instruction fetch mode; (3) configuring thread instruction fetch starting address; (4) setting the number of start threads; (5) adding synchronization instructions, and the program exits after all threads are executed. Thus, the chip running configuration file, the test data and the machine code file are transmitted to the chip simulation device, based on which the chip simulation device executes the machine code file on the test data according to the chip running configuration file to obtain the simulation calculation result.

[0062] Specifically, (1) initialization loading: the chip simulation device first loads the chip running configuration file to the starting address of the instruction area, and loads the test data and the machine code file to the data area and the instruction area (the machine code file follows the chip running configuration file); at the same time, the state of the chip simulation device is reset, the program counter (PC) points to the starting address of the chip simulation device, and the thread state and bus signal are reset.

[0063] (2) environment configuration execution: the PC reads and executes the chip running configuration file in sequence, and completes the configuration of the chip running parameters: sets the execution and instruction fetch mode (such as single / multi-thread, sequential instruction fetch); configures the thread number, allocates the starting address of the instruction stream to each thread and writes the private PC of the thread; writes the base address of the test data in the data area and the storage address of the simulation calculation result into the corresponding registers to establish the data access association.

[0064] (3) thread start and machine code file execution: when the "thread start" instruction is executed, the PC of each thread jumps to the starting address of the machine code file, reads the calculation instruction of the target operator from the instruction area, and the thread state is updated to "running". The thread operates according to the machine code file: loads the test data from the data area to the operation unit, executes the calculation (intermediate result is stored in the temporary address in the data area), and finally writes the final simulation calculation result to the specified output address; if it is a synchronization mode, the thread sends a "ready signal" after completion, and all threads are ready to trigger global synchronization.

[0065] (4) Ending and result derivation: after the synchronization signal is activated, the chip running configuration file executes ending instructions: activates the result write back enable to lock the output data, configures the waveform capture parameters, and triggers the simulation end signal. The chip simulation device stops the clock driving, reads the simulation calculation result from the specified address in the data area and converts the format, which is provided for subsequent comparison and verification with the benchmark calculation result.

[0066] By using the above embodiments, 1) controllability of testing is improved: by uniformly configuring the execution mode, thread parameters, etc. through the chip running configuration file, it is ensured that the simulation process is executed according to the preset rules, hardware resource conflicts or disordered operations are avoided, and the testing complexity is reduced. 2) verification efficiency is accelerated: the chip running configuration file directly associates the instruction stream and the data area address, the manual configuration link is saved, and the testing scene (such as single / multi-thread, different operators) can be quickly switched through parameters, thereby shortening the verification period. 3) completeness of testing is enhanced: by means of the synchronization control and waveform capture configuration of the chip running configuration file, the hardware state can be recorded comprehensively, and by combining the output result comparison, not only the functional correctness is verified, but also the performance bottleneck (such as thread cooperation efficiency) can be analyzed. 4) close to actual scene: by simulating the program starting and execution logic of the real chip, the testing result is more valuable, and reliable basis is provided for the design optimization before the chip is put into production.

[0067] In some embodiments, the step of "transmitting the chip running configuration file, the test data and the machine code file to the chip simulation device" can be implemented by the following steps: converting the storage format of the chip running configuration file from the current first storage format to the chip storage format of the chip, converting the storage format of the test data from the current second storage format to the chip storage format, and converting the machine code file from the current third storage format to the chip storage format; transmitting the chip running configuration file, the test data and the machine code file in the chip storage format to the chip simulation device.

[0068] Here, first, the storage format of each of the chip running configuration file, the test data and the machine code file is converted into the chip storage format, so that the chip running configuration file, the test data and the machine code file can be successfully loaded and stored to the chip simulation device. Specifically, the storage format of the chip running configuration file is converted from the current first storage format to the chip storage format of the chip; the storage format of the test data is converted from the current second storage format to the chip storage format; and the machine code file is converted from the current third storage format to the chip storage format. Thus, the chip running configuration file, the test data and the machine code file in the chip storage format are transmitted to the chip simulation device.

[0069] In practical applications, when performing storage format conversion, the essence is to first ensure that the data format of the to-be-transmitted data (i.e., the chip running configuration file, the test data, and the machine code file) meets the parsing requirements of the chip hardware, and then arrange the layout of the to-be-transmitted data in the chip hardware according to the rules of the chip storage format. For example: converting the data format of the to-be-transmitted data into a data format that can be directly parsed by the chip hardware (such as a 32-bit binary floating-point number format); on the basis of correct data format, adjusting the storage mode of the data according to the physical layout rules of the chip hardware. It should be noted that the core of the chip storage format is a binary format that adapts to the hardware architecture, and its specific rules (bit width, byte order, address mapping, etc.) are determined by the hardware design of the chip, and there is no unified "general format", but all aim to "enable the chip hardware to efficiently and correctly read and process data". The chip storage format is the physical layout rule of data in the hardware storage medium (register, memory, cache), which defines "how data is placed in hardware", and is directly related to the hardware architecture. For example: bit width alignment (such as data in a 32-bit chip must be aligned by 4 bytes, and 0 is added if necessary); byte order (big-endian / little-endian, such as the storage order of multi-byte data); address mapping (the starting address of data in memory, partitioning, such as instructions stored at 0x0000~0xFFFF, and data stored at 0x10000~0xFFFFF); storage unit multiplexing (such as data isolation layout when multiple threads share memory).

[0070] By converting the storage formats of the chip running configuration file, the test data, and the machine code file respectively into the chip storage format, the above embodiments can ensure that the chip running configuration file, the test data, and the machine code file can be successfully loaded and stored into the chip simulation device, and also ensure that the chip simulation device can correctly read and parse the chip running configuration file, the test data, and the machine code file, implement simulation calculation of the target operator, and ensure correct execution of the target operator.

[0071] In some embodiments, the machine code file includes: first storage addresses of the chip running configuration file, the test data, and the machine code file in the chip simulation device, and a second storage address of the simulation calculation result in the chip simulation device; based on this, "transmitting the chip running configuration file, the test data, and the machine code file to the chip simulation device" can be implemented by performing the following steps: transmitting the chip running configuration file, the test data, and the machine code file to the respective first storage addresses in the chip simulation device; based on this, obtaining the simulation calculation result from the chip simulation device includes: obtaining the simulation calculation result from the second storage address in the chip simulation device.

[0072] Here, the machine code file includes: the chip running configuration file, the test data and the first storage address of the machine code file in the chip simulation device. The first storage addresses of different data (i.e., the chip running configuration file, the test data and the machine code file) can be different. For example, (1) the chip running configuration file belongs to control program code, which can be stored in the instruction area of the chip simulation device, such as being mapped to the preset low address segment (such as 0x0000_0000-0x000F_FFFF) of the chip simulation device. When the simulation is started, the instruction fetching and execution are started from the starting address of the chip running configuration file, triggering the subsequent process. (2) The test data belongs to data information, which can be stored in the data area of the chip simulation device, such as being mapped to the high address segment (such as 0x0100_0000-0xFFFF_FFFF), for the "data loading instruction" in the machine code file. (3) The machine code file belongs to computing program code, which can also be stored in the instruction area and can be adjacent and continuous to the address segment of the chip running configuration file. In actual application, the chip running configuration file will explicitly configure the starting address of the machine code file. When the chip running configuration file executes to the "start thread" instruction, the starting address of the machine code file will be loaded into the program counter of the thread. The thread starts to read and execute the specific computing instructions (such as data loading, operation, result storage, etc.) of the target operator from this address. Based on this, the chip running configuration file, the test data and the machine code file are transmitted to the first storage address of each in the chip simulation device.

[0073] Similarly, the machine code file can also include the second storage address of the simulation computing result in the chip simulation device. The simulation computing result also belongs to data information and can also be stored in the data area of the chip simulation device. Based on this, when the simulation computing result is obtained from the chip simulation device, the simulation computing result is obtained from the second storage address of the chip simulation device.

[0074] By setting the storage addresses of different data (the chip running configuration file, the test data and the machine code file, and the simulation computing result) according to the above embodiment, the hardware design safety principle is met, the interference risk of each module is reduced, the address association rule is clear, the collaborative access of various data is guaranteed, and the simulation execution efficiency and stability are improved.

[0075] Step 104: Obtain the simulation computing result from the chip simulation device, and obtain the benchmark computing result of the benchmark operator for the test data.

[0076] For step 104, after the chip simulation device obtains the simulation calculation result, the simulation calculation result is obtained from the chip simulation device, that is, the simulation calculation result is exported from the second storage address of the chip simulation device for storing the simulation calculation result. At the same time, the benchmark calculation result of the benchmark operator for the test data is obtained. The benchmark operator can be a standard operator built in a deep learning framework, such as a benchmark operator built in the deep learning framework Torch. The benchmark calculation result is obtained by calculating the test data by the benchmark operator. In actual application, the benchmark operator is developed based on the hardware environment and software stack of general CPU / GPU, and depends on the underlying interface of the general computing framework. The calculation process of the benchmark operator can be implemented in the hardware environment of general CPU / GPU. Therefore, since the simulation calculation result is exported from the chip simulation device, the storage format of the simulation calculation result is the chip storage format. At this time, the simulation calculation result needs to be converted from the chip storage format to a format suitable for CPU processing (including storage, reading, result comparison, etc.) in order to be compared with the benchmark calculation result.

[0077] Step 105: generating a test result of the chip based on the simulation calculation result and the benchmark calculation result.

[0078] For step 105, after obtaining the simulation calculation result calculated by the chip simulation device and obtaining the benchmark calculation result calculated based on the benchmark operator, the simulation calculation result and the benchmark calculation result are compared to obtain the test result of the chip.

[0079] In some embodiments, the test result is a first test result or a second test result. Based on this, step 105 "generating a test result of the chip based on the simulation calculation result and the benchmark calculation result" can be implemented by performing the following steps: in the case that the simulation calculation result and the benchmark calculation result are the same, generating a first test result, the first test result indicating that the chip verification passes; in the case that the simulation calculation result and the benchmark calculation result are different, generating a second test result, the second test result indicating that the chip verification fails.

[0080] Here, after comparing the simulation calculation result and the benchmark calculation result, if the simulation calculation result and the benchmark calculation result are the same, a first test result is generated, which indicates that the chip verification passes, specifically, the accuracy verification of the chip passes; if the simulation calculation result and the benchmark calculation result are different, a second test result is generated, which indicates that the chip verification fails, specifically, the accuracy verification of the chip fails.

[0081] Applying the above embodiments, 1) anchor function correctness benchmark: the benchmark calculation result is the theoretically correct value, which can directly judge whether the target operator implementation and hardware execution of the chip conform to the functional design by comparison, excluding logical errors; 2) improve verification rigor: the benchmark calculation result is independent of the standard result of the chip hardware, which can avoid the "self-verification correct" deviation caused by the inherent defects of the hardware, and ensure the objectivity of the verification; 3) accelerate problem positioning: the difference result can accurately point to the loopholes of the hardware design (such as operation unit, data path) or operator implementation, reducing the troubleshooting cost; 4) ensure the adaptability of the actual scene: the benchmark calculation result is close to the real application demand, and the comparison means that the chip can output reliable results in actual business, laying a foundation for subsequent chip testing and marketization, and accelerating the chip testing pace.

[0082] In some embodiments, when the test result is the first test result, referring to Figure 6 The following steps 301-303 can also be performed: step 301, injecting an exception instruction into the machine code file to obtain a target machine code file; step 302, transmitting the target machine code file to a chip simulation device, wherein the chip simulation device is configured to execute the target machine code file on the test data to obtain a target simulation calculation result of the target operator on the test data; and step 303, analyzing the fault tolerance capability of the chip based on the target simulation calculation result and the simulation calculation result to obtain a fault tolerance capability analysis result.

[0083] For step 301, an exception instruction is first injected into the machine code file to obtain a target machine code file. In actual application, the correct instruction in the machine code file can be modified to an error instruction to obtain the target machine code file. For example, for a correct instruction of memory access, the corresponding position is modified to be out of bounds, such as modifying the address of the correct instruction from 18xx to 19xx to obtain an error instruction of memory access out of bounds.

[0084] For step 302, the target machine code file is transmitted to the chip simulation device; the chip simulation device executes the target machine code file on the test data to obtain a target simulation calculation result of the target operator on the test data. In this way, the chip simulation device executes the target machine code file including the exception instruction to obtain the target simulation calculation result.

[0085] For step 303, based on the target simulation calculation result and the simulation calculation result, the fault tolerance capability of the chip is analyzed to obtain a fault tolerance capability analysis result. The target simulation calculation result and the simulation calculation result are compared. If the target simulation calculation result and the simulation calculation result are the same, a first fault tolerance capability analysis result is obtained, which represents that the fault tolerance capability of the chip is effective. If the target simulation calculation result and the simulation calculation result are not the same, a second fault tolerance capability analysis result is obtained, which represents that the fault tolerance capability of the chip is not effective, and there is a problem with the fault tolerance capability. The fault tolerance capability analysis result includes the first fault tolerance capability analysis result and the second fault tolerance capability analysis result.

[0086] By applying the above embodiment, 1) early exposure of chip hardware defects: injecting exceptions in the chip simulation stage, without actual hardware, early discovery of vulnerabilities in chip design fault tolerance mechanisms (such as exception detection, error recovery), avoiding cost loss due to insufficient fault tolerance after chip deployment, and meeting the goals of early verification and early optimization of chips. 2) Accurate evaluation of fault tolerance capability: By comparing the target simulation calculation result after exception injection with the normal simulation calculation result, the influence of exceptions on chip execution can be directly quantified, and it can be determined whether the fault tolerance mechanism is effective in intercepting and repairing exceptions, avoiding the limitations of relying on theoretical analysis to judge fault tolerance performance. 3) Guarantee the correctness of the function bottom line: Combined with the comparison of the previous and benchmark calculation results, this process can verify the fault tolerance capability while confirming that the chip can still maintain the correctness of the core calculation function (or handle errors as expected) under abnormal scenarios, ensuring the reliability of the chip in complex environments and laying a foundation for subsequent actual hardware testing.

[0087] In some embodiments, the following steps can also be performed: obtaining a signal waveform diagram from the chip simulation device, the signal waveform diagram being generated based on hardware signals collected during execution of the machine code file; analyzing the signal waveform diagram according to at least one running state analysis dimension to obtain a running state of the chip; and analyzing the signal waveform diagram according to at least one performance analysis dimension to obtain performance data of the chip.

[0088] Here, the signal waveform chart is obtained from the chip simulation device, and the hardware signals are captured based on the pre-set waveform capture condition during the execution of the machine code file, so as to generate the signal waveform chart based on the captured hardware signals. For example, the waveform capture condition can be: 1) the hardware signal capture operation (start recording) is triggered when the "input data load signal (load_en)" becomes high, to capture the process of loading data from the memory to the operation unit. 2) the hardware signal capture operation is triggered when the "operation unit start signal (calc_start)" becomes high, to capture the signal change of the calculation process. 3) the hardware signal capture operation (stop recording) is no longer performed when the "output result write back signal (write_back)" becomes high, to avoid recording subsequent irrelevant operations. For example, the hardware signals include but are not limited to: 1) control signals such as data load enable (load_en), operation unit start (calc_start), synchronization signal (sync), result write back (write_back), etc., reflecting the trigger and end of hardware operation. 2) data signals such as data bus (data_bus), result bus (result_bus), etc., recording the specific data values (such as matrix elements, intermediate calculation results) transmitted. 3) status signals such as operation unit status (alu_status, 0=idle / 1=calculating), thread status (thread_state, 0=not started / 1=running / 2=ended), etc., reflecting the real-time working mode of the hardware components.

[0089] In some embodiments, the signal waveform chart is analyzed according to at least one running state analysis dimension to obtain the running state of the chip, including: performing at least one of the following operations: obtaining the trigger sequence of the control signal from the signal waveform chart, and determining the running state in combination with the trigger sequence and the expected trigger sequence; obtaining the numerical value of the data signal based on the signal waveform chart, and determining the running state in combination with the numerical value and the expected numerical value; obtaining the duration and switching time point of the status signal based on the signal waveform chart, and determining the running state in combination with the duration and the switching time point.

[0090] Here, the running state analysis dimension includes: control signal analysis dimension, data signal analysis dimension and state signal analysis dimension. (1) The trigger sequence of the control signal is obtained from the signal waveform diagram, and the running state is determined in combination with the trigger sequence and the expected trigger sequence. For example, check whether the trigger sequence of the control signal conforms to the expected trigger sequence, such as whether the process of data loading→calculation start→result write back is strictly executed in sequence. Specific operation: a) Observe whether load_en (data loading enable) becomes high level before calc_start (calculation start): if calc_start triggers when load_en is not activated, it means that "calculation is earlier than data preparation", there is a timing error, and the running state is abnormal. B) Confirm whether the sync (synchronization signal) is triggered after the thread_state of all threads becomes "end": if the synchronization signal is triggered in advance, it means that the thread is terminated without completing the calculation, there is a synchronization logic error, and the running state is abnormal.

[0091] (2) Based on the signal waveform diagram, the numerical value of the data signal is obtained, and the running state is determined in combination with the numerical value and the expected numerical value. For example, check whether the numerical value of the data signal is consistent with the expected input / output, and ensure that there is no error in the storage, operation and transmission of data. Specific operation: Extract the numerical value of data_bus during load_en=1, and compare it with the expected value (such as test data): if the numerical value does not match, it means that there is a transmission error (such as bus failure, address mapping error) when the data is loaded from the memory to the operation unit, and the running state is abnormal.

[0092] (3) Based on the signal waveform diagram, the duration and switching time point of the state signal are obtained, and the running state is determined in combination with the duration and switching time point. For example, monitor whether the duration and switching time point of the state signal meet the execution requirements of the target operator, and troubleshoot deadlocks, interruptions and other abnormalities. Specific operation: Observe whether alu_status becomes "1 (in calculation)" immediately after calc_start=1, and remains "1" before result_bus starts transmission. If alu_status suddenly jumps to "0 (idle)", it means that the operation unit abnormally exits in the middle, and there may be abnormal situations such as deadlock or resource conflict. b) Check the thread state thread_state: if the thread_state of a thread remains "1 (running)" for a long time without switching to "2 (end)", it means that the thread is blocked, and there is a running state abnormality.

[0093] In some embodiments, the signal waveform diagram is analyzed according to at least one performance analysis dimension to obtain performance data of the chip, including: performing at least one of the following operations: obtaining the execution duration of each execution stage of the machine code file from the signal waveform diagram, and determining the performance data based on the execution duration of each execution stage; determining the execution duration of the calculation stage of the machine code file and the total execution duration of the machine code file based on the signal waveform diagram, and determining the performance data.

[0094] Here, the performance analysis dimension includes a stage time consumption dimension and a resource utilization rate dimension. (1) The stage time consumption dimension: the execution duration of each execution stage of the machine code file is obtained from the signal waveform diagram, and the performance data (such as whether the execution duration of each execution stage is overtime, execution efficiency, etc.) is determined based on the execution duration of each execution stage. For example, a) delay of the data loading stage: the time difference from when load_en becomes high (data starts to load) to when calc_start becomes high (calculation starts). b) time consumption of the calculation stage: the time difference from when calc_start is activated (calculation starts) to when result_bus first outputs data (calculation ends). c) total execution duration: the time difference from when load_en is activated (data loading starts) to when write_back is activated (result writing back is completed).

[0095] (2) The resource utilization rate dimension: the execution duration of the calculation stage of the machine code file and the total execution duration of the machine code file are determined based on the signal waveform diagram, and the performance data (such as operation unit utilization rate and thread parallel efficiency) is determined. For example, a) the proportion of the time when the operation unit is in “calculating (alu_status=1)” to the total execution duration, which can be considered as the operation unit utilization rate. b) In the multi-thread scenario, the ratio of the total time when all threads are “running (thread_state=1)” to the total execution duration, which can be considered as the thread parallel efficiency. The resource utilization rate includes the operation unit utilization rate and the thread parallel efficiency.

[0096] By applying the above embodiments of the present application, the operator code of the target operator (having the same calculation function as the benchmark operator) is implemented by combining the chip interface instructions. Since the chip interface instructions can implement at least one hardware operation of the chip, the machine code file of the chip can be obtained by parsing the operator code, so that the machine code file is run by simulating the chip through the chip simulation device to obtain the simulation calculation result. Finally, the test result of the chip is generated by combining the simulation calculation result and the benchmark calculation result. In this way, only the operator code needs to be implemented based on the chip interface instructions, and then the operator simulation is performed in combination with the chip simulation device, so that the test of the chip can be implemented in advance from the operator level, without waiting for the software stack to be developed completely, thereby accelerating the chip test progress; and the test result is generated by combining the simulation calculation result and the benchmark calculation result, thereby ensuring the completeness of the chip test.

[0097] The following describes an exemplary application of the embodiments of the present application in an actual application scenario. Chip design involves a million lines of hardware and software code, and function verification is a key link to ensure the correctness of chip design. In the related art, multi-stage testing such as software simulation, hardware simulation, and prototype verification needs to be implemented. However, after the chip hardware design is completed, the development of the software stack often lags behind the hardware progress. The incompleteness of the software stack causes the chip prototype verification to be unable to be carried out in time, which slows down the chip testing progress and delays the chip production and marketing cycle.

[0098] Based on this, the embodiments of the present application provide a chip testing method, which can carry out chip testing from the operator level without waiting for the development of the chip software stack to be complete, test the completeness of the chip hardware, and accelerate the prototype verification of the chip. In this way, 1) the chip testing rhythm is accelerated, and the prototype verification testing of the operator level can be carried out in advance for a long time; 2) the testing of the operator level is close to the actual running scene of the product, which increases the completeness of the chip prototype verification; 3) the performance data obtained by the prototype verification of the operator level can be used for the architecture to understand the actual running performance of the chip, and the implementation scheme of the operator can also be optimized. Next, a detailed description is given.

[0099] In the embodiments of the present application, the implementation basis of chip testing is: a) the API instruction encapsulated by the chip instruction set; and b) a compiler or simulator is provided, which can parse the encapsulated API instruction into chip hardware instructions represented by 0 and 1.

[0100] (1) Software operators are programmed based on the encapsulated API instructions to obtain operator code of a target operator, the target operator and a benchmark operator (such as a Torch operator) having the same interface and calculation function; and operator self-test code (i.e., the above-mentioned test code) of the target operator is written.

[0101] (2) The operator self-test code and the operator code are parsed into a chip instruction stream file capable of running on the chip hardware through a chip simulator or a compiler. The chip instruction stream file includes: an operator execution process, a storage address of data required for operator calculation, a storage address of the chip instruction stream, and a storage address of output data (such as the above-mentioned simulation calculation result) after the operator execution ends.

[0102] (3) A main function for starting the chip configuration is written, and a binary file (i.e., the above-mentioned chip running configuration file) is obtained by compiling. The binary file includes the following settings: a) setting the chip execution mode; b) configuring the chip instruction fetching mode; c) configuring the first address of thread instruction fetching; d) setting the number of starting threads; and e) adding a synchronization instruction, and the program exits after all threads are executed.

[0103] (4) Data preparation: convert the data format of the input data of the target operator (i.e., the test data described above), the chip instruction stream file, and the binary file obtained by compiling the chip configuration main function into a data format suitable for the storage format of the chip; load the input data obtained after the data format conversion, the chip instruction stream file, and the binary file obtained by compiling the chip configuration main function into the Emulator simulation device through the data loading method provided by the Emulator simulation device.

[0104] (5) Run the Emulator simulation device for simulation, and capture the waveform diagram according to the pre-set capture waveform condition during the simulation, so as to obtain the hardware running state and performance data by analyzing the waveform diagram.

[0105] (6) Result acquisition: the storage address of the simulation calculation result is specified in the chip instruction stream file, so the simulation calculation result is exported from the storage address of the Emulator simulation device in the same way, and then the data format conversion is performed on the simulation calculation result, so that the converted data format supports CPU reading and comparison.

[0106] (7) Result comparison: run the benchmark operator (such as the Torch operator) on the test data through the CPU platform or the GPU platform to obtain the benchmark calculation result, and compare the benchmark calculation result with the simulation calculation result to obtain the chip verification result (i.e., the test result described above). Specifically, if the benchmark calculation result and the simulation calculation result are the same, the chip verification result indicates that the correctness verification of the chip design is passed; if the benchmark calculation result and the simulation calculation result are different, the chip verification result indicates that the correctness verification of the chip design is not passed.

[0107] Referring to Figure 7 , Figure 7 is a fifth flowchart of a chip testing method provided by the embodiment of the present application. Here, the chip testing method comprises: 1) obtaining operator code and operator self-test code; 2) obtaining a chip instruction stream file by analyzing the operator code and the operator self-test code through a simulator or a compiler; 3) obtaining a chip configuration main function; 4) obtaining a binary file by compiling the chip configuration main function; 5) obtaining input data required for chip testing; 6) obtaining a target file in a storage format suitable for the chip by performing format conversion on the chip instruction stream file, the binary file, and the input data; 7) loading the target file into an Emulator simulation device; 8) running the Emulator simulation device; 9) triggering a synchronization signal, executing all threads, and ending the simulation; 10) storing a simulation calculation result; 11) capturing a waveform diagram and analyzing the waveform diagram to obtain a hardware running state and performance data; and 12) running a benchmark operator on test data to obtain a benchmark calculation result, and comparing the simulation calculation result with the benchmark calculation result to obtain a chip verification result.

[0108] The specific implementation process of the present application can be as follows: based on the encapsulated API instructions, the operator library operator of the chip is developed, and the operator self-test code is written on the simulator to verify and ensure the correctness of the operator writing. Based on this, without waiting for the subsequent software stack to be perfected, the following processing is carried out to carry out prototype verification of the operator on the Emulator simulation platform. Specifically, the operator code and the operator self-test code are executed on the simulator, and the simulator parses the operator code and the operator self-test code into instruction streams and redirects the instruction streams into an instruction stream file as one of the input files of the Emulator simulation platform. After obtaining the instruction stream file, a startup program (i.e., a chip configuration main function) is written to configure: starting a thread, configuring the number of threads, configuring the thread execution starting address, etc. These are also configured through the encapsulated API instructions. After writing, it is compiled into a binary file, which is also one of the input files of the Emulator simulation platform. Finally, the data file, the operator randomly generates input data during self-test, and inputs the same input data into the developed operator and the torch operator respectively to verify the correctness of the operator. Here, the input data and the output data that pass the self-test result are saved in binary format. A data format conversion script is developed, and two conversion scripts are written for the storage form of the chip: one is to convert the instruction stream file to adapt to the storage format of the chip; the other is to convert the binary file to adapt to the storage format of the chip. The Emulator simulation platform has a backdoor loading operation, and through the backdoor loading path provided by the Emulator machine, the above three converted files are loaded into the corresponding storage space of the Emulator simulation platform. Then the test of the Emulator simulation platform is started, and after the data is loaded, the state of the Emulator simulation platform is reset to clear the interference state before this run to ensure the purity of this simulation. Before that, the waveform graph grabbing signal and the grabbing time can be added. After the execution is completed, the simulation calculation result address space data can be exported through the backdoor export method provided by the Emulator platform, so as to verify the correctness of the simulation calculation result by comparing the simulation calculation result with the benchmark calculation result.

[0109] By applying the above embodiments of the present application, 1) the chip test pace is accelerated, and the operator level prototype verification test can be carried out much earlier; 2) the operator level test is close to the actual running scene of the product, increasing the completeness of the chip prototype verification; 3) the performance data of the operator level prototype verification can be used for architecture to understand the actual running performance of the chip, and the operator implementation scheme can also be optimized.

[0110] The following continues to illustrate an exemplary structure of the chip testing device 555 implementation as a software module provided by the embodiments of the present application. In some embodiments, as shown in FIG. 6, the chip testing device 555 includes a chip testing module 601, a chip testing data module 602, a chip testing result module 603, a chip testing data format conversion module 604, and a chip testing data format conversion module 605. Figure 2As shown, the software modules stored in the chip test device 555 of the memory 550 can include: a first obtaining module 5551 configured to obtain operator code of a target operator, the operator code including a plurality of chip interface instructions, wherein the target operator and a reference operator have the same computing function, and the chip interface instructions are used to implement at least one hardware operation of the chip, and the hardware operations of the plurality of chip interface instructions are used to implement the computing function; an analyzing module 5552 configured to analyze the operator code to obtain a machine code file of the chip; a transmitting module 5553 configured to obtain test data and transmit the test data and the machine code file to a chip simulation device, wherein the chip simulation device is configured to execute the machine code file on the test data to obtain a simulation computing result of the target operator for the test data; a second obtaining module 5554 configured to obtain the simulation computing result from the chip simulation device and obtain a reference computing result of the reference operator for the test data; and a generating module 5555 configured to generate a test result of the chip based on the simulation computing result and the reference computing result.

[0111] In some embodiments, the first obtaining module 5551 is further configured to, before the analyzing module 5552 analyzes the operator code to obtain the machine code file of the chip, obtain test code of the target operator; the analyzing module 5552 is further configured to analyze the test code to obtain control logic of the target operator, analyze the operator code based on the control logic to obtain computing logic of the target operator, and integrate the control logic and the computing logic to obtain the machine code file.

[0112] In some embodiments, the first obtaining module 5551 is further configured to obtain a chip running configuration file of the chip; and the transmitting module 5553 is further configured to transmit the chip running configuration file, the test data, and the machine code file to the chip simulation device, wherein the chip running configuration file is used to enable the chip simulation device to execute the machine code file on the test data based on the chip running configuration file to obtain the simulation computing result.

[0113] In some embodiments, the transmitting module 5553 is further configured to convert a storage format of the chip running configuration file from a current first storage format to a chip storage format of the chip, convert a storage format of the test data from a current second storage format to the chip storage format, and convert the machine code file from a current third storage format to the chip storage format; and transmit the chip running configuration file, the test data, and the machine code file in the chip storage format to the chip simulation device.

[0114] In some embodiments, the machine code file includes: the chip running configuration file, the test data and the machine code file are respectively at a first storage address of the chip simulation device, and the simulation calculation result is at a second storage address of the chip simulation device; the transmission module 5553 is further configured to transmit the chip running configuration file, the test data and the machine code file to the first storage address of the chip simulation device respectively; and the second acquisition module 5554 is further configured to acquire the simulation calculation result from the second storage address of the chip simulation device.

[0115] In some embodiments, the number of chip interface instructions is M, and M is an integer greater than 1; the first acquisition module 5551 is further configured to acquire N chip instructions before acquiring the operator code of the target operator including a plurality of chip interface instructions, each of the chip instructions being used to implement one of the hardware operations of the chip, and N is an integer greater than or equal to M; and the N chip instructions are encapsulated to obtain M chip interface instructions, each of the chip interface instructions including at least one chip instruction.

[0116] In some embodiments, the first acquisition module 5551 is further configured to acquire an instruction description file of N to-be-generated chip instructions, the instruction description file including: domain segment definition information of a plurality of instruction domain segments included in each of the to-be-generated chip instructions, and a combination format of the plurality of instruction domain segments; for each of the to-be-generated chip instructions, generating a domain segment parameter of each of the instruction domain segments based on each of the domain segment definition information included in the to-be-generated chip instruction; and for each of the to-be-generated chip instructions, combining the domain segment parameters of the plurality of instruction domain segments included in the to-be-generated chip instruction according to the combination format of the plurality of instruction domain segments to obtain the chip instruction.

[0117] In some embodiments, the test result is a first test result or a second test result; the generation module 5555 is further configured to generate the first test result in a case where the simulation calculation result and the benchmark calculation result are the same, the first test result indicating that the chip passes the verification; and generate the second test result in a case where the simulation calculation result and the benchmark calculation result are not the same, the second test result indicating that the chip fails the verification.

[0118] In some embodiments, when the test result is the first test result, the generation module 5555 is further configured to inject an exception instruction into the machine code file to obtain a target machine code file; and transmit the target machine code file to the chip simulation device, where the chip simulation device is configured to execute the target machine code file on the test data to obtain a target simulation calculation result of the target operator on the test data; and analyze the fault tolerance capability of the chip based on the target simulation calculation result and the simulation calculation result to obtain a fault tolerance capability analysis result.

[0119] In some embodiments, the generation module 5555 is further configured to obtain a signal waveform diagram from the chip simulation device, where the signal waveform diagram is generated based on hardware signals collected during execution of the machine code file; analyze the signal waveform diagram according to at least one running state analysis dimension to obtain a running state of the chip; and analyze the signal waveform diagram according to at least one performance analysis dimension to obtain performance data of the chip.

[0120] In some embodiments, the generation module 5555 is further configured to perform at least one of the following: obtain a trigger sequence of a control signal from the signal waveform diagram, and determine the running state in combination with the trigger sequence and an expected trigger sequence; obtain a value of a data signal based on the signal waveform diagram, and determine the running state in combination with the value and an expected value; obtain a duration and a switching time point of a state signal based on the signal waveform diagram, and determine the running state in combination with the duration and the switching time point; and the generation module 5555 is further configured to perform at least one of the following: obtain an execution duration of each execution phase of the machine code file from the signal waveform diagram, and determine the performance data based on the execution duration of each execution phase; determine an execution duration of a calculation phase of the machine code file and a total execution duration of the machine code file based on the signal waveform diagram, and determine the performance data.

[0121] In some embodiments, the number of target operators is a plurality, the analysis module 5552 is further configured to obtain a dependency relationship between the plurality of target operators, and construct a topology graph with the target operators as nodes and the dependency relationship as directed edges; determine an execution order of the plurality of target operators according to the topology graph; analyze the operator code to obtain an execution instruction of each target operator; and integrate the execution instructions of the plurality of target operators based on the execution order of the plurality of target operators to obtain a machine code file of the chip.

[0122] It should be noted that the description of the device embodiments in the present application is similar to the description of the method embodiments described above, and has similar beneficial effects as the method embodiments, which will not be described here. For the technical details not described in the chip testing device provided by the embodiments of the present application, it can be understood based on the description of the technical details in the method embodiments.

[0123] The embodiments of the present application also provide a computer program product, which includes computer executable instructions or computer programs stored in a computer readable storage medium. The processor of the electronic device reads the computer executable instructions or computer programs from the computer readable storage medium, and the processor executes the computer executable instructions or computer programs, so that the electronic device executes the chip testing method provided by the embodiments of the present application.

[0124] The embodiments of the present application also provide a computer readable storage medium, which stores computer executable instructions or computer programs. When the computer executable instructions or computer programs are executed by the processor, the processor will execute the chip testing method provided by the embodiments of the present application.

[0125] In some embodiments, the computer readable storage medium can be RAM, ROM, flash memory, magnetic surface memory, optical disc, or CD-ROM memory, etc. It can also be various devices including one or any combination of the above storage.

[0126] In some embodiments, the computer executable instructions can be in the form of programs, software, software modules, scripts or codes, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as independent programs or being deployed as modules, components, subroutines or other units suitable for use in computing environments.

[0127] As an example, the computer executable instructions can but not necessarily correspond to files in the file system, can be stored in part of a file storing other programs or data, for example, stored in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program in question, or stored in multiple cooperative files (for example, files storing one or more modules, subroutines or code portions).

[0128] As an example, the computer executable instructions can be deployed to execute on one electronic device, or on multiple electronic devices located in one place, or on multiple electronic devices distributed in multiple places and interconnected through a communication network.

[0129] The above merely provides an example of the present application, but is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, and improvement made within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. A method of testing a chip, characterized by, The method comprises: acquiring operator code of a target operator comprising a plurality of chip interface instructions, wherein the target operator and a benchmark operator have the same computing function, and the chip interface instructions are used to implement at least one hardware operation of the chip, and the hardware operations of the plurality of chip interface instructions are used to implement the computing function; parsing the operator code to obtain a machine code file of the chip; acquiring test data and transmitting the test data and the machine code file to a chip simulation device, wherein the chip simulation device is used to execute the machine code file on the test data to obtain a simulation computing result of the target operator for the test data; acquiring the simulation computing result from the chip simulation device and acquiring a benchmark computing result of the benchmark operator for the test data; generating a test result of the chip based on the simulation computing result and the benchmark computing result.

2. The method of claim 1, wherein, Before the parsing the operator code to obtain the machine code file of the chip, the method further comprises: acquiring test code of the target operator; the parsing the operator code to obtain the machine code file of the chip comprises: parsing the test code to obtain control logic of the target operator; based on the control logic, parsing the operator code to obtain computing logic of the target operator; integrating the control logic and the computing logic to obtain the machine code file.

3. The method of claim 1 or 2, wherein, The method further comprises: acquiring a chip running configuration file of the chip; the transmitting the test data and the machine code file to the chip simulation device comprises: transmitting the chip running configuration file, the test data and the machine code file to the chip simulation device, wherein the chip running configuration file is used for the chip simulation device to execute the machine code file on the test data based on the chip running configuration file to obtain the simulation computing result.

4. The method of claim 3, wherein, The transmitting the chip running configuration file, the test data and the machine code file to the chip simulation device comprises: converting a storage format of the chip running configuration file from a current first storage format to a chip storage format of the chip, converting a storage format of the test data from a current second storage format to the chip storage format, and converting the machine code file from a current third storage format to the chip storage format; transmitting the chip running configuration file, the test data and the machine code file in the chip storage format to the chip simulation device.

5. The method of claim 3, wherein, The machine code file comprises: first storage addresses of the chip running configuration file, the test data and the machine code file in the chip simulation device, and a second storage address of the simulation computing result in the chip simulation device; the transmitting the chip running configuration file, the test data and the machine code file to the chip simulation device comprises: transmitting the chip running configuration file, the test data and the machine code file to the first storage addresses in the chip simulation device, respectively; the transmitting the chip running configuration file, the test data and the machine code file to the chip simulation device comprises: transmitting the chip running configuration file, the test data and the machine code file to the first storage addresses in the chip simulation device, respectively; The obtaining the simulation calculation result from the chip simulation device comprises: Obtaining the simulation calculation result from the second storage address of the chip simulation device.

6. The method of claim 1, wherein, The number of the chip interface instructions is M, and M is an integer greater than 1; before obtaining the operator code of the target operator comprising a plurality of chip interface instructions, the method further comprises: Obtaining N chip instructions, each of which is used to implement one of the hardware operations of the chip, and N is an integer greater than or equal to M; Packaging the N chip instructions to obtain M chip interface instructions, each of which comprises at least one chip instruction.

7. The method of claim 6, wherein, The obtaining N chip instructions comprises: Obtaining an instruction description file of N to-be-generated chip instructions, the instruction description file comprising: domain segment definition information of a plurality of instruction domain segments included in each of the to-be-generated chip instructions, and a combination format of the plurality of instruction domain segments; For each of the to-be-generated chip instructions, generating a domain segment parameter of each of the instruction domain segments based on each of the domain segment definition information included in the to-be-generated chip instruction; For each of the to-be-generated chip instructions, combining the domain segment parameters of the plurality of instruction domain segments included in the to-be-generated chip instruction according to the combination format of the plurality of instruction domain segments to obtain the chip instruction.

8. The method of claim 1, wherein, The test result is a first test result or a second test result; The generating the test result of the chip based on the simulation calculation result and the benchmark calculation result comprises: In the case that the simulation calculation result and the benchmark calculation result are the same, generating the first test result, the first test result indicating that the chip passes the verification; In the case that the simulation calculation result and the benchmark calculation result are not the same, generating the second test result, the second test result indicating that the chip fails the verification.

9. The method of claim 8, wherein, When the test result is the first test result, the method further comprises: Injecting an exception instruction into the machine code file to obtain a target machine code file; Transmitting the target machine code file to the chip simulation device, wherein the chip simulation device is configured to execute the target machine code file on the test data to obtain a target simulation calculation result of the target operator on the test data; Based on the target simulation calculation result and the simulation calculation result, analyzing the fault tolerance capability of the chip to obtain a fault tolerance capability analysis result.

10. The method of claim 1, wherein, The method further comprises: Obtaining a signal waveform diagram from the chip simulation device, the signal waveform diagram being generated based on a hardware signal collected during execution of the machine code file; Analyzing the signal waveform diagram according to at least one running state analysis dimension to obtain a running state of the chip; Analyzing the signal waveform diagram according to at least one performance analysis dimension to obtain performance data of the chip.

11. The method of claim 10, wherein, The analyzing the signal waveform diagram according to at least one running state analysis dimension to obtain a running state of the chip comprises: Performing at least one of the following operations: acquire a trigger sequence of the control signal from the signal waveform diagram, and determine the running state by combining the trigger sequence and an expected trigger sequence; acquire a value of the data signal based on the signal waveform diagram, and determine the running state by combining the value and an expected value; acquire a duration and a switching time point of the state signal based on the signal waveform diagram, and determine the running state by combining the duration and the switching time point; the performance data of the chip is obtained by analyzing the signal waveform diagram according to at least one performance analysis dimension, including: at least one of the following operations is performed: the execution duration of each execution phase of the machine code file is acquired from the signal waveform diagram, and the performance data is determined based on the execution duration of each execution phase; the execution duration of the calculation phase of the machine code file and the total execution duration of the machine code file are determined based on the signal waveform diagram, and the performance data is determined.

12. The method of claim 1, wherein, the number of target operators is multiple, and the machine code file of the chip is obtained by analyzing the operator code, including: acquiring a dependency relationship between multiple target operators, and constructing a topology graph by taking the target operators as nodes and the dependency relationship as directed edges; determining the execution order of multiple target operators according to the topology graph; analyzing the execution instructions of each target operator from the operator code; integrating the execution instructions of multiple target operators based on the execution order of multiple target operators to obtain the machine code file of the chip.

13. A chip testing apparatus characterized by comprising: The device includes: a first acquisition module configured to acquire operator code of a target operator including a plurality of chip interface instructions, wherein the target operator and a reference operator have the same calculation function, and the chip interface instructions are used to implement at least one hardware operation of the chip, and the hardware operation of the plurality of chip interface instructions is used to implement the calculation function; an analysis module configured to analyze the operator code to obtain a machine code file of the chip; a transmission module configured to acquire test data and transmit the test data and the machine code file to a chip simulation device, wherein the chip simulation device is configured to execute the machine code file on the test data to obtain a simulation calculation result of the target operator for the test data; a second acquisition module configured to acquire the simulation calculation result from the chip simulation device and acquire a reference calculation result of the reference operator for the test data; a generation module configured to generate a test result of the chip based on the simulation calculation result and the reference calculation result.

14. An electronic device, comprising: The electronic device includes: a memory configured to store computer executable instructions; a processor configured to execute the computer executable instructions stored in the memory to implement the chip test method in any one of claims 1 to 12.

15. A computer-readable storage medium storing computer-executable instructions or a computer program, wherein the computer-executable instructions or the computer program comprise the steps of: The computer executable instructions or computer programs are executed by the processor to implement the chip test method in any one of claims 1 to 12. ​ 16. A computer program product comprising computer-executable instructions or a computer program, characterized in that, The computer executable instructions or computer programs are executed by the processor to implement the chip test method in any one of claims 1 to 12.

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