Heavy load efficiency improvement control method for asynchronous parallel soft switching inverter

Abstract

The invention discloses a control method for improving the heavy load efficiency of an asynchronous parallel soft switching inverter, and the method comprises the following steps: S1, constructing a topological structure of the asynchronous parallel inverter, generating a DPWM modulation wave through zero-sequence component injection in a QCM mode, and enabling a power tube not to act in a specific interval in a fundamental wave period; s2, adjusting a clamping interval of a DPWM1 strategy by correcting the injected zero-sequence component; s3, calculating a phase shift angle, and generating carrier waves of a leading bridge arm and a lagging bridge arm; s4, when the power tube enters or exits from the non-action interval, transition interval control is carried out, so that the differential mode inductance circulating current is reduced to 0; and S5, generating a driving signal of a hybrid control strategy based on DPWM modulation, and controlling a switching tube to act according to the optimized clamping interval and transition logic. According to the method, the current stress and on-state loss of the power tube of the asynchronous parallel inverter under the heavy load are reduced, and the current stress minimization of the power tube and the efficiency maximization of the inverter are realized.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, and in particular to a control method for improving the heavy-load efficiency of asynchronous parallel soft-switching inverters. Background Technology

[0002] In high-frequency applications, SiC power devices exhibit high switching losses. Therefore, to further improve the system's power density and carrier ratio, and to increase the system switching frequency to several hundred kHz, it is necessary to employ soft-switching technology to reduce system switching losses and thermal stress on power devices. Existing two-level asynchronous parallel inverters use phase shifting to control the differential-mode inductor circulating current ripple, thereby achieving soft switching. Because the inductor current waveform approximates a quadrilateral, this operating mode is called quadrilateral current mode (QCM). However, when this topology operates in QCM, the parallel bridge arms experience significant current ripple, resulting in high current stress and conduction losses in the power transistors under heavy loads. To improve system efficiency and reliability, it is necessary to reduce the power transistor current stress and conduction losses in the QCM mode of the two-level asynchronous parallel inverter.

[0003] Existing two-level asynchronous parallel inverters add a differential-mode inductor to the parallel half-bridge and employ a phase-shifting control scheme to generate a circulating current in the differential-mode inductor. The current shape of the parallel inductor is quadrilateral, thereby enabling all power transistors to achieve zero-voltage switching (ZVS). In this operating mode, the amplitude variation range of the power transistor current is i. ZVS ~i O +i ZVS , where i O i represents the output phase current amplitude. ZVS To achieve the valley current required for soft switching of the power transistors, the current stress and conduction losses of the power transistors are relatively high under heavy load conditions. Other technologies have optimized this operating mode for heavy load applications, adaptively switching between soft-switching QCM mode and hard-switching CCM mode within one fundamental cycle based on the instantaneous load current. When operating in CCM mode, the maximum current amplitude of each power transistor is 0.5i. O This reduces current stress, thus enabling high efficiency across the entire load range. However, when operating in hard-switching CCM mode, the power transistor switching losses increase significantly, making it difficult to apply at higher frequencies. Therefore, reducing power transistor current stress and conduction losses under heavy load in asynchronous parallel inverters at high frequencies, while avoiding increased switching losses, has become a core challenge that urgently needs to be addressed in this field. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a control method for improving the heavy-load efficiency of asynchronous parallel soft-switching inverters. In quadrilateral current mode, a discontinuous pulse width modulation (DPWM) strategy is used instead of a continuous space vector pulse width modulation (SVM) strategy. By modifying the injected zero-sequence component to adjust the clamping interval of the DPWM1 strategy, the power transistor current stress and conduction losses of the asynchronous parallel inverter under heavy load are reduced. Furthermore, transition interval control ensures rapid current balancing of the parallel bridge arms within the clamping interval, thereby minimizing power transistor current stress and maximizing inverter efficiency.

[0005] A control method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter, specifically including the following steps:

[0006] Step S1: Construct an asynchronous parallel inverter topology. In the quadrilateral current mode (QCM), a discontinuous pulse width modulation (DPWM) strategy is adopted. A DPWM modulation wave is generated by injecting zero-sequence components, so that the power transistor does not operate in a specific interval within one fundamental cycle.

[0007] Step S2: Collect the three-phase output current, identify the electrical angle range where the current peak is located, correct the injected zero-sequence component, and adjust the clamping range of the DPWM1 strategy by correcting the injected zero-sequence component so that the clamping range coincides with the 60° range symmetrical to the left and right of the current peak.

[0008] Step S3: Calculate the phase shift angle based on the three-phase output current, and then generate the carrier waves for the leading and lagging bridge arms based on the phase shift angle.

[0009] Step S4: Design a transition range control strategy. When the power transistor enters or exits the inactive range, perform transition range control. By adjusting the modulation amplitude and phase shift angle, reduce the differential mode inductor circulating current to 0 to ensure the current balance of the parallel bridge arms.

[0010] Step S5: Compare the modulated wave after zero-sequence component correction and transition interval control with the carrier wave to generate a drive signal based on the hybrid control strategy of DPWM modulation. Output the drive signal to the gate of the power transistor to control the switching transistor to operate according to the optimized clamping interval and transition logic, thereby reducing conduction loss while achieving soft switching.

[0011] Furthermore, in step S1, the zero-sequence component u in different DPWM strategies z The unified representation is:

[0012] u z =(2k-1)-ku max -(1-k)u min

[0013] Where k is the DPWM clamping interval selection coefficient, u max and u minLet be the maximum and minimum values ​​of the three-phase reference voltage at any given time, respectively, and be expressed as:

[0014]

[0015] Among them, u a u b and u c This is the three-phase reference voltage.

[0016] Furthermore, in step S2, the zero-sequence component k of the DPWM1 strategy is represented as:

[0017]

[0018] When the phase voltage v x With output current i x There is a phase difference When k is changed to k*, k* is represented as:

[0019]

[0020] Among them, i max and i min Let be the maximum and minimum values ​​of the three-phase output current at any given moment, respectively, and be expressed as:

[0021]

[0022] Among them, i a i b and i c This is the three-phase output current.

[0023] Furthermore, in step S2, the corrected k* is substituted into the zero-order component u. z The corrected zero-order component u is obtained. z *, when the phase voltage v x With output current i x phase difference satisfy At that time, the clamping interval coincides with the 60° interval symmetrical to the left and right of the current peak.

[0024] Furthermore, in step S4, the transition interval control strategy is as follows: when entering the transition interval, the modulation wave maintains the amplitude of the previous switching cycle, and the phase shift angle becomes half of the previous switching cycle, specifically including the following steps:

[0025] Step S4-1: Enter the transition interval and determine whether the modulation wave changes. If the modulation wave changes, proceed to step S4-2; if the modulation wave does not change, proceed to step S3-6.

[0026] Step S4-2: Determine whether the modulation wave jumps to 1 or 0. If the modulation wave jumps to 1 or 0, proceed to step S4-3. If the modulation wave does not jump to 1 or 0, proceed to step S3-4.

[0027] Step S4-3: Latch the current modulation amplitude value;

[0028] Step S4-4: Update the phase shift angle to half of the current phase shift angle;

[0029] Step S4-5: Determine if it is the second switch of the power transistor within the transition interval. If it is, proceed to step S4-6. If it is not, wait for the next power transistor switch time and repeat step S4-5.

[0030] Step S4-6: End the transition interval.

[0031] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0032] (1) The proposed method for improving the efficiency of asynchronous parallel soft-switching inverters under heavy load reduces the power tube current stress and conduction loss of the asynchronous parallel inverters under heavy load by modifying the clamping range of the DPWM1 strategy by adjusting the injected zero-sequence component.

[0033] (2) The method for improving the heavy-load efficiency of asynchronous parallel soft-switching inverter proposed in this invention will not increase the switching loss of power transistors and can be applied in high-frequency applications.

[0034] (3) The asynchronous parallel soft-switching inverter heavy load efficiency improvement control method proposed in this invention can adjust the clamping interval according to the power factor of the load. The added transition interval enables the parallel bridge arm current in the clamping interval to be quickly balanced, thereby minimizing the power tube current stress and maximizing the inverter efficiency. Attached Figure Description

[0035] Figure 1 This is a flowchart of a control method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter proposed in this invention.

[0036] Figure 2 This is an asynchronous parallel inverter topology diagram proposed in this invention.

[0037] Figure 3 It is the modulated wave and current waveform after injecting the corrected zero-sequence component.

[0038] Figure 4 This is a comparison of the instantaneous on-state losses of the power transistor in QCM mode and DPWM hybrid mode.

[0039] Figure 5 This is a timing diagram of the transition interval.

[0040] Figure 6 This is a flowchart of the transition interval control strategy.

[0041] Figure 7 This is a waveform diagram of the current of a parallel differential-mode inductor. Detailed Implementation

[0042] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. The technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Combination Figure 1 This invention proposes a control method for improving the heavy-load efficiency of asynchronous parallel soft-switching inverters, which specifically includes the following steps:

[0044] Step S1, construct as follows Figure 2 The asynchronous parallel inverter topology shown adopts a discontinuous pulse width modulation strategy, i.e., DPWM strategy, in quadrilateral current mode, i.e. QCM mode. DPWM modulation wave is generated by zero-sequence component injection, so that the power transistor does not operate in a specific interval within one fundamental cycle.

[0045] Step S2: Collect the three-phase output current, identify the electrical angle range where the current peak is located, correct the injected zero-sequence component, and adjust the clamping range of the DPWM1 strategy by correcting the injected zero-sequence component so that the clamping range coincides with the 60° range symmetrical to the left and right of the current peak.

[0046] Step S3: Calculate the phase shift angle based on the three-phase output current, and then generate the carrier waves for the leading and lagging bridge arms based on the phase shift angle.

[0047] Step S4: Design a transition range control strategy. When the power transistor enters or exits the inactive range, perform transition range control. By adjusting the modulation amplitude and phase shift angle, reduce the differential mode inductor circulating current to 0 to ensure the current balance of the parallel bridge arms.

[0048] Step S5: Compare the modulated wave after zero-sequence component correction and transition interval control with the carrier wave to generate a drive signal based on the hybrid control strategy of DPWM modulation. Output the drive signal to the gate of the power transistor to control the switching transistor to operate according to the optimized clamping interval and transition logic, thereby reducing conduction loss while achieving soft switching.

[0049] Furthermore, in step S1, the zero-sequence component u in different DPWM strategies z The unified representation is:

[0050] u z =(2k-1)-ku max -(1-k)u min

[0051] Where k is the DPWM clamping interval selection coefficient, u max and u min Let be the maximum and minimum values ​​of the three-phase reference voltage at any given time, respectively, and be expressed as:

[0052]

[0053] Among them, u a u b and u c This is the three-phase reference voltage.

[0054] Furthermore, in step S2, the zero-sequence component k of the DPWM1 strategy is represented as:

[0055]

[0056] When the phase voltage v x With output current i x There is a phase difference When k is changed to k*, k* is represented as:

[0057]

[0058] Among them, i max and i min Let be the maximum and minimum values ​​of the three-phase output current at any given moment, respectively, and be expressed as:

[0059]

[0060] Among them, i a i b and i c This is the three-phase output current.

[0061] Furthermore, in step S2, the corrected k* is substituted into the zero-order component u. z The corrected zero-order component u is obtained. z *,like Figure 3 As shown, when the phase voltage v x With output current i x phase difference satisfy- At that time, the clamping interval coincides with the 60° interval symmetrical to the left and right of the current peak.

[0062] Furthermore, the on-state loss of a single-phase power transistor is expressed as:

[0063]

[0064] Among them, D x R is the duty cycle of phase x, where phase x is any one of phase a, phase b, or phase c. ds,on t is the on-resistance of the power transistor, T is the fundamental period of the phase current, and i(t) is the phase current.

[0065] Taking phase A as an example, the duty cycle D under the DPWM1 strategy is... A The expressions are shown in Table 1, where ωt is the electrical angle and M is the modulation ratio:

[0066] Table 1 shows the duty cycle of phase A under the DPWM1 strategy. A expression

[0067]

[0068] Correspondingly, the duty cycle of phase A under the SVPWM strategy is:

[0069]

[0070] Taking phase A as an example, analyzing the instantaneous conduction loss of the power transistor within the interval [-π / 2, π / 2], the conduction loss of the upper transistor of the leading arm in one switching cycle under QCM mode can be expressed as:

[0071]

[0072] Where T shift For phase shift time, I ZVS V is the valley current required for soft switching. dc For DC voltage, L c T is the resonant inductance value. S For the switching period, i ao The output phase current is m, and the modulation amplitude is m.

[0073] The on-state loss of the lower tube of the advanced bridge arm can be expressed as:

[0074]

[0075] The on-state loss of the upper tube of the hysteresis bridge arm can be expressed as:

[0076]

[0077] The on-state loss of the lower tube of the hysteresis bridge arm can be expressed as:

[0078]

[0079] The on-state loss of the power transistor during one switching cycle within the clamping interval can be expressed as:

[0080]

[0081] When the inverter input is 540V and the output is 6kW, the instantaneous on-state loss of the power transistor in the QCM mode and DPWM hybrid mode within half a fundamental cycle is as follows: Figure 4 As shown, the combination of clamping mode and QCM under the DPWM modulation strategy can effectively reduce the conduction loss of the power transistor.

[0082] Furthermore, in step S4, the control timing of the transition interval is as follows: Figure 5 As shown; Figure 6 As shown, the transition interval control strategy is as follows: when entering the transition interval, the modulated wave maintains the amplitude of the previous switching cycle, and the phase shift angle becomes half of the previous switching cycle. Specifically, it includes the following steps:

[0083] Step S4-1: Enter the transition interval and determine whether the modulation wave changes. If the modulation wave changes, proceed to step S4-2; if the modulation wave does not change, proceed to step S3-6.

[0084] Step S4-2: Determine whether the modulation wave jumps to 1 or 0. If the modulation wave jumps to 1 or 0, proceed to step S4-3. If the modulation wave does not jump to 1 or 0, proceed to step S3-4.

[0085] Step S4-3: Latch the current modulation amplitude value;

[0086] Step S4-4: Update the phase shift angle to half of the current phase shift angle;

[0087] Step S4-5: Determine if it is the second switch of the power transistor within the transition interval. If it is, proceed to step S4-6. If it is not, wait for the next power transistor switch time and repeat step S4-5.

[0088] Step S4-6: End the transition interval.

[0089] Parallel differential mode inductor current such as Figure 7 As shown, where I LA I LB and I LC The parallel differential mode inductor currents for phases a, b, and c are respectively. It can be seen that in the non-switching range, after adopting the asynchronous parallel soft-switching inverter heavy load efficiency improvement control method proposed in this invention, the current stress of the parallel bridge arms is small, and the current is evenly distributed among the parallel bridge arms.

[0090] The above descriptions are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A control method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter, characterized in that, Includes the following steps: Step S1: Construct an asynchronous parallel inverter topology. In the quadrilateral current mode (QCM), a discontinuous pulse width modulation (DPWM) strategy is adopted. A DPWM modulation wave is generated by injecting zero-sequence components, so that the power transistor does not operate in a specific interval within one fundamental cycle. Step S2: Collect the three-phase output current, identify the electrical angle range where the current peak is located, correct the injected zero-sequence component, and adjust the clamping range of the DPWM1 strategy by correcting the injected zero-sequence component so that the clamping range coincides with the 60° range symmetrical to the left and right of the current peak. Step S3: Calculate the phase shift angle based on the three-phase output current, and then generate the carrier waves for the leading and lagging bridge arms based on the phase shift angle. Step S4: Design a transition range control strategy. When the power transistor enters or exits the inactive range, perform transition range control. By adjusting the modulation amplitude and phase shift angle, reduce the differential mode inductor circulating current to 0 to ensure the current balance of the parallel bridge arms. Step S5: Compare the modulated wave after zero-sequence component correction and transition interval control with the carrier wave to generate a drive signal based on the hybrid control strategy of DPWM modulation. Output the drive signal to the gate of the power transistor to control the switching transistor to operate according to the optimized clamping interval and transition logic, thereby reducing conduction loss while achieving soft switching.

2. The method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter according to claim 1, characterized in that: In step S1, the zero-sequence component u in different DPWM strategies z The unified representation is: u z =(2k-1)-stand max -(1-k)u min Where k is the DPWM clamping interval selection coefficient, u max and u min Let be the maximum and minimum values ​​of the three-phase reference voltage at any given time, respectively, and be expressed as: Among them, u a u b and u c This is the three-phase reference voltage.

3. The method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter according to claim 1, characterized in that: In step S2, the zero-sequence component k of the DPWM1 strategy is represented as: When the phase voltage v x With output current i x There is a phase difference When k is changed to k*, k* is represented as: Among them, i max and i min Let be the maximum and minimum values ​​of the three-phase output current at any given moment, respectively, and be expressed as: Among them, i a i b and i c This is the three-phase output current.

4. The method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter according to claim 3, characterized in that: In step S2, the corrected k* is substituted into the zero-order component u. z The corrected zero-order component u is obtained. z *, when the phase voltage v x With output current i x phase difference satisfy At that time, the clamping interval coincides with the 60° interval symmetrical to the left and right of the current peak.

5. The method for improving the heavy-load efficiency of an asynchronous parallel soft-switching inverter according to claim 1, characterized in that: In step S4, the transition interval control strategy is as follows: when entering the transition interval, the modulation wave maintains the amplitude of the previous switching cycle, and the phase shift angle becomes half of the previous switching cycle. Specifically, it includes the following steps: Step S4-1: Enter the transition interval and determine whether the modulation wave changes. If the modulation wave changes, proceed to step S4-2; if the modulation wave does not change, proceed to step S3-6. Step S4-2: Determine whether the modulation wave jumps to 1 or 0. If the modulation wave jumps to 1 or 0, proceed to step S4-3. If the modulation wave does not jump to 1 or 0, proceed to step S3-4. Step S4-3: Latch the current modulation amplitude value; Step S4-4: Update the phase shift angle to half of the current phase shift angle; Step S4-5: Determine if it is the second switch of the power transistor within the transition interval. If it is, proceed to step S4-6. If it is not, wait for the next power transistor switch time and repeat step S4-5. Step S4-6: End the transition interval.

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