Dynamic on-resistance test circuit based on gallium nitride transistor and test method thereof

Abstract

The application discloses a dynamic on-resistance test circuit based on a gallium nitride transistor and a test method thereof, and belongs to the technical field of power electronics.The circuit comprises a DPT test circuit, a switching state switching circuit and a clamping circuit; the test method is to obtain the on-resistance of the to-be-tested tube by monitoring the voltage between test points on the clamping circuit and the current on the coaxial resistor; and the switching between hard switching and soft switching tests is realized by changing the switching interface.The gallium nitride transistor and the clamping circuit are introduced on the traditional double-pulse test circuit, and the dynamic on-resistance test functions in the soft switching and hard switching modes are integrated.Compared with the traditional test circuit, the clamping circuit of the application can capture the dynamic on-resistance within nanosecond time delay, greatly reduces the peak of the clamping voltage, improves the test precision, and realizes the fast and accurate measurement of the dynamic on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and in particular relates to a dynamic on-resistance test circuit and test method based on gallium nitride transistors. Background Technology

[0002] Gallium nitride (GaN) devices are widely used in industry for high-efficiency and high-power-density converter designs due to their low on-resistance, high breakdown voltage, and fast switching speed. However, the reliability of high-voltage GaN devices in practical applications remains an issue. Under dynamic conditions, GaN high-electron-mobility transistors experience on-resistance degradation, which is a significant challenge for GaN researchers and developers.

[0003] Dynamic on-resistance degradation is a serious problem limiting the large-scale application of gallium nitride (GaN) power devices. It is caused by the trapping effect, specifically manifested as an increase in the on-resistance between the source and drain of a GaN device after a period of stress, followed by a return to its original static value after a sufficiently long time. Considering that GaN devices typically operate at high switching frequencies in practical power electronic applications, the extremely short on-time is insufficient to recover the resistance, thus generating more conduction losses and causing the device to operate at higher junction temperatures, resulting in lower efficiency. Dynamic on-resistance degradation increases the uncertainty in assessing the power conduction losses of GaN devices and also increases the difficulty of base converter design. Therefore, characterizing the dynamic on-resistance of GaN devices is of great significance.

[0004] To accurately measure dynamic on-resistance, the oscilloscope needs a sufficient measurement range to simultaneously display the high voltage of the device under test (DUT) in its off-state and the low voltage in its on-state. Otherwise, the portion exceeding the measurement range will cause overdrive of the oscilloscope, resulting in inaccurate measurement of the DUT's drain-source voltage. Increasing the oscilloscope's measurement range, however, leads to insufficient measurement resolution, significantly reducing measurement accuracy. Many studies have addressed this issue by introducing clamping circuits. However, the high voltage spikes introduced by clamping circuits make the clamping effect less than ideal. Furthermore, the charging and discharging of internal capacitors and the introduction of passive components introduce other problems such as test response delay and leakage current. Therefore, a fast and accurate clamping circuit is needed to clamp the high drain-source voltage of the DUT to a lower value when it is on, while minimizing the negative impacts of oscillation and delay introduced by the clamping circuit. Summary of the Invention

[0005] Purpose of the invention: To address the technical problems existing in measuring the dynamic on-resistance of gallium nitride transistors, the purpose of this invention is to provide a dynamic on-resistance test circuit and test method based on gallium nitride transistors, which can effectively clamp high voltage, reduce the output capacitance in the clamping circuit, reduce oscillations caused by rapid voltage changes of the device under test, and at the same time have a low response delay.

[0006] Technical Solution: This invention provides a dynamic on-resistance test circuit based on gallium nitride transistors (GaN transistors), comprising a DPT test circuit, a switch state switching circuit, and a clamping circuit. The DPT test circuit generates dual-pulse or multi-pulse test signals to control the on / off state of the device under test (DUT) and the accompanying device. The switch state switching circuit can switch between hard-switching and soft-switching states via a switching unit after changing the input gate signal. The clamping circuit clamps the high voltage at the drain-source terminal of the DUT to a lower level when it is off, and simultaneously declamps it promptly and accurately measures the on-state voltage when the DUT is on. The DPT test circuit includes a DC power supply, a first capacitor, a coaxial resistor, a control signal, a gate drive, a first GaN device, and a second GaN device.

[0007] The DC power supply is connected to one end of the first capacitor, one end of the switch state switching circuit, and the drain of the first gallium nitride device, respectively. The other end of the switch state switching circuit is connected to one end of the coaxial resistor, the other end of the DC power supply, and the other end of the first capacitor, respectively. The source of the first gallium nitride device is connected to the drain of the second gallium nitride device, the output of the switch state switching circuit, and one end of the clamping circuit, respectively. The source of the second gallium nitride device is grounded to the other end of the clamping circuit and the other end of the coaxial resistor, respectively. The gate drive is connected to the gate of the first gallium nitride device and the gate of the second gallium nitride device, respectively. The clamping circuit is connected in parallel across the second gallium nitride device to measure its drain-source voltage.

[0008] Furthermore, the switch state switching circuit includes a second capacitor, a third capacitor, a first resistor, a second resistor, a switch unit, and a load inductor;

[0009] One end of the second capacitor is connected to one end of the first resistor and one end of the switching unit; the other end of the second capacitor is connected to the other end of the first resistor, one end of the third capacitor, one end of the second resistor, and one end of the switching unit; the other end of the third capacitor is connected to the other end of the second resistor; one end of the switching unit is connected to one end of the load inductor; switching the switching unit to end 2 and end 3 can respectively put the test circuit under soft switching and hard switching test conditions.

[0010] Furthermore, the second capacitor and the third capacitor of the switching state switching circuit are of the same size; the first resistor and the second resistor are of the same size; connecting a resistor of the same size in parallel with the capacitor providing pre-voltage stress can control the waveform duty cycle during multi-pulse testing to 50%.

[0011] Furthermore, the clamping circuit includes a third gallium nitride device, a second voltage source, a Schottky diode, a Zener diode, and a fourth resistor;

[0012] The drain of the third gallium nitride device is connected to the drain of the second gallium nitride device; the source of the third gallium nitride device is connected to the negative terminal of the Zener diode; the positive terminal of the Zener diode is connected to one end of the fourth resistor and the negative terminal of the Zener diode; the positive terminal of the second voltage source is connected to the gate of the third gallium nitride device; the negative terminal of the second voltage source is connected to the positive terminal of the Schottky diode and the other end of the fourth resistor, respectively, to the source of the second gallium nitride device.

[0013] Furthermore, the withstand voltage of the third gallium nitride device in the clamping circuit should be greater than or equal to the withstand voltage of the second gallium nitride device to prevent the third gallium nitride device from being broken down when testing high-voltage operating conditions.

[0014] Furthermore, the third gallium nitride device is an enhancement-mode gallium nitride device and its on-resistance is much smaller than that of the second gallium nitride device, so as to reduce the influence of the third gallium nitride device on the on-voltage drop during testing.

[0015] A method for testing the dynamic on-resistance of gallium nitride transistors includes:

[0016] S1. The DC power supply supplies power to the first capacitor and the load inductor;

[0017] S2. The control signals PWM1 and PWM2 of the first gallium nitride device and the second gallium nitride device generate different pulse waveforms when the switching unit is switched to different ports to control the second gallium nitride device to be in a soft switching or hard switching test state.

[0018] When terminal 1 of the switching unit is connected to terminal 2, the control signal causes the test system to be in hard-switching test mode. Specifically, from the third to the fourth time, PWM2 controls the second gallium nitride device to be in the on state; from the fourth to the seventh time, PWM2 controls the second gallium nitride device to be in the off state; and from the seventh to the eighth time, PWM2 controls the second gallium nitride device to be in the on state.

[0019] When terminal 1 of the switching unit is connected to terminal 3, the control signal puts the test system into a soft-switching test mode. Specifically, from the first to the second moment, PWM1 controls the first gallium nitride (GaN) device to be in the ON state; from the second to the fifth moment, PWM1 controls the first GaN device to be in the OFF state; from the fifth to the sixth moment, PWM1 controls the first GaN device to be in the ON state; from the third to the fourth moment, PWM2 controls the second GaN device to be in the ON state; from the fourth to the seventh moment, PWM2 controls the second GaN device to be in the OFF state; and from the seventh to the eighth moment, PWM2 controls the second GaN device to be in the ON state. By applying a narrow pulse to the device under test (DUT) before the DUT is turned on, the DUT can discharge the load inductor before being turned on, thereby achieving zero-voltage turn-on to meet the soft-switching test requirements.

[0020] S3. When the third gallium nitride device is turned off, the voltage between test points A and B can be determined by V. CC -V TH Calculations show that by selecting a suitable second voltage source, the measured V on the oscilloscope will be... AB The size is sufficient to meet the measurement accuracy requirements. When the third gallium nitride device is turned on, since the on-resistance of the third gallium nitride device is much smaller than that of the second gallium nitride device, the negative terminal of the Zener diode and the positive terminal of the Schottky diode are selected as two test points. The voltage difference between the test points is equal to the on-state voltage of the second gallium nitride device. The voltage measured between the seventh and eighth moments is selected as the required on-state voltage V of the device under test. AB ;

[0021] S4. Calculate the current flowing through the device under test (DUT) based on the voltage drop across the coaxial resistor, V. AB The ratio of this to the dynamic on-resistance is the dynamic on-resistance.

[0022] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0023] 1. This invention can clamp the voltage value of the test point to within 5V, while controlling the voltage spike introduced by the clamping circuit to a low level, allowing the oscilloscope to display the conduction voltage more accurately without distortion of the internal amplifier, thereby improving the measurement accuracy of dynamic conduction resistance.

[0024] 2. This invention can realize soft-switching test and hard-switching test of dynamic on-resistance respectively. By using zero-voltage and zero-current technology, it overcomes the resonance phenomenon that may be caused by the loop inductance and the output capacitance of the test tube, which greatly reduces the oscillation during the switching process of the device under test and improves the test accuracy.

[0025] 3. The clamping circuit used in this invention significantly reduces the parasitic capacitance of the Zener diode in the clamping circuit by connecting the Schottky diode and the Zener diode in series, thereby reducing the charging and discharging time and effectively reducing the test response delay. Simultaneously, the series resistor after the Zener diode avoids overheating of the Zener diode due to the large current during frequent switching transitions in multi-pulse testing, resulting in a more stable test system. Attached Figure Description

[0026] Figure 1 A schematic diagram of a dynamic on-resistance test circuit based on gallium nitride transistors is provided for an embodiment of this application.

[0027] Figure 2 A schematic diagram of a clamping circuit for a dynamic on-resistance test circuit based on a gallium nitride transistor, provided for an embodiment of this application;

[0028] Figure 3 A schematic diagram showing the on-state voltage of the device under test after introducing a clamping circuit;

[0029] Figure 4 The timing diagrams of the control signals required for hard switching and soft switching tests respectively;

[0030] Figure 5 This is the equivalent circuit diagram for hard switching and soft switching tests in this invention;

[0031] Figure 6 This is a schematic diagram of the zero-voltage conduction waveform in this invention;

[0032] Figure 7 This is a simulation test result of dynamic on-resistance.

[0033] The labels in the attached diagram are as follows: DC, DC power supply; Vcc, second voltage source; C1, first capacitor; C2, second capacitor; C3, third capacitor; R1, first resistor; R2, second resistor; R3, coaxial resistor; R4, fourth resistor; Q1, first gallium nitride device; Q2, second gallium nitride device; Q3, third gallium nitride device; D1, Schottky diode; Dz, Zener diode; L, load inductance. Detailed Implementation

[0034] The present invention will be further explained and described in detail below with reference to the accompanying drawings, so that those skilled in the art can understand the present invention more deeply and be able to implement it. However, the following examples are only used to explain the present invention and are not intended to limit the present invention.

[0035] like Figure 1As shown, a dynamic on-resistance test circuit based on gallium nitride transistors (GaN transistors) includes a DPT test circuit, a switch state switching circuit, and a clamping circuit. The DPT test circuit includes a DC power supply (DC), a first capacitor C1, a coaxial resistor R3, a control signal, a gate drive, a first GaN device Q1, and a second GaN device Q2. The DC power supply (DC) is used to charge the first capacitor C1 (the bus capacitor) to maintain a stable test voltage. The first GaN device Q1 is a secondary test transistor (DUT), providing a freewheeling path for the load inductor L when the DUT is turned off. The second GaN device Q2 is the DUT itself, with a clamping circuit connected in parallel across its terminals for testing the on-voltage. The coaxial resistor R3 is used to measure the current flowing through the DUT.

[0036] A DC power supply (DC) is connected to one end of the first capacitor C1, one end of the switching circuit, and the drain of the first gallium nitride (GaN) device Q1. The other end of the switching circuit is connected to one end of the coaxial resistor R3, the other end of the DC power supply (DC), and the other end of the first capacitor C1. The source of the first GaN device Q1 is connected to the drain of the second GaN device Q2, the output of the switching circuit, and one end of the clamping circuit. The source of the second GaN device Q2 is grounded to the other end of the clamping circuit and the other end of the coaxial resistor R3. The gate drive is connected to the gate of the first GaN device Q1 and the gate of the second GaN device Q2. The input of the clamping circuit is connected to the drain of the second GaN device Q2. The output of the clamping circuit is connected to the source of the second GaN device Q2.

[0037] The switching state switching circuit includes a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a switching unit S, and a load inductor L. One end of the second capacitor C2 is connected to one end of the first resistor R1 and one end of the switching unit S. The other end of the second capacitor C2 is connected to the other end of the first resistor R1, one end of the third capacitor C3, one end of the second resistor R2, and one end of the switching unit S. The other end of the third capacitor C3 is connected to the other end of the second resistor R2. One end of the switching unit S is connected to one end of the load inductor L. Because the second capacitor C2 and the third capacitor C3 are connected in series, the output capacitor is already charged to its initial value before the gate signal arrives. Therefore, it can be forced to operate in pulse mode but in a steady state without requiring an initial pre-charging process for the output capacitor.

[0038] The second capacitor C2 and the third capacitor C3 in the switch state switching circuit have the same value; the first resistor R1 and the second resistor R2 have the same value. The voltage drop across the second and third capacitors can be determined by the first resistor R1 and the second resistor R2, allowing the switch state switching circuit to directly enter a stable state with different duty cycles in multi-pulse test mode. The first resistor R1 and the second resistor R2 are chosen to be the same to match a 50% duty cycle.

[0039] The clamping circuit includes a third gallium nitride device Q3, a second voltage source Vcc, a Schottky diode D1, a Zener diode Dz, and a fourth resistor R4. The drain of the third gallium nitride device Q3 is connected to the drain of the second gallium nitride device Q2. The source of the third gallium nitride device Q3 is connected to the cathode of the Zener diode Dz. The anode of the Zener diode Dz is connected to one end of the fourth resistor R4 and the cathode of the Schottky diode D1. The anode of the second voltage source Vcc is connected to the gate of the third gallium nitride device Q3. The cathode of the second voltage source Vcc is connected to the anode of the Schottky diode D1 and the other end of the fourth resistor R4, respectively, to the source of the second gallium nitride device Q2.

[0040] The withstand voltage of the third gallium nitride device Q3 in the clamping circuit should be greater than or equal to the withstand voltage of the second gallium nitride device Q2.

[0041] The third gallium nitride device Q3 is an enhancement-mode gallium nitride device, and its on-resistance is much smaller than that of the second gallium nitride device Q2.

[0042] The operating state of the clamping circuit can be divided into two processes: the off state and the on state of the device under test (DUT). When the DUT is in the off state, the voltage Vcc applied to the gate of the third gallium nitride (GaN) device by the second voltage source causes the third GaN device to turn on, and the source voltage of the third GaN device begins to rise. When the source voltage rises to the point that the gate-source voltage is lower than the threshold voltage, the third GaN device will turn off again, thus establishing voltage balance. The clamping voltage V... AB The difference between the second voltage source Vcc and the threshold voltage of the third gallium nitride device, such as... Figure 2 As shown. When the device under test (DUT) is turned on, the voltage across the DUT drops. The gate-source voltage of the third gallium nitride (GaN) device is greater than the threshold voltage, and the transistor is fully turned on. Since the on-resistance of the selected third GaN device is much smaller than that of the second GaN device, the voltage drop across the third GaN device can be ignored. At this time, the voltage between measurement points A and B is the turn-on voltage of the DUT. The Zener diode can reduce the clamping voltage spike caused by the drain-source parasitic capacitance of the third GaN device. In traditional clamping circuits, this spike may even be several times the clamping voltage, such as... Figure 3 As shown. Meanwhile, the fourth resistor connected in series after the Zener diode avoids overheating of the Zener diode due to the large current during frequent switching transitions in multi-pulse testing, making the test system more stable. Furthermore, the series connection of the Schottky diode and the Zener diode further reduces the charging and discharging time of the Zener diode's internal capacitor, thereby significantly reducing the test response delay.

[0043] A method for testing the dynamic on-resistance of gallium nitride transistors includes the following steps:

[0044] S1, DC power supply supplies power to the first capacitor C1 and the load inductor L.

[0045] S2, the control signals PWM1 and PWM2 of the first gallium nitride device Q1 and the second gallium nitride device Q2, when switched to different ports by the switching unit S, are respectively as follows: Figure 4 The pulse waveform shown is used to control the second gallium nitride device Q2 to be in a soft-switching or hard-switching test state.

[0046] When terminal 1 of the switching unit S is connected to terminal 2, the control signal puts the test system into a hard-switching test mode. Specifically, from the third to the fourth time point, PWM2 controls the second gallium nitride device Q2 to be in the on state; from the fourth to the seventh time point, PWM2 controls the second gallium nitride device Q2 to be in the off state; and from the seventh to the eighth time point, PWM2 controls the second gallium nitride device Q2 to be in the on state. A schematic diagram of the hard-switching equivalent is shown below. Figure 5 As shown in (a), the device under test provides a reverse conduction path as a freewheeling tube when the device under test is turned off.

[0047] When terminal 1 of the switching unit S is connected to terminal 3, the control signal causes the test system to be in a soft-switching test mode. Specifically, from the first to the second moment, PWM1 controls the first gallium nitride device Q1 to be in the on state; from the second to the fifth moment, PWM1 controls the first gallium nitride device Q1 to be in the off state; from the fifth to the sixth moment, PWM1 controls the first gallium nitride device Q1 to be in the on state; from the third to the fourth moment, PWM2 controls the second gallium nitride device Q2 to be in the on state; from the fourth to the seventh moment, PWM2 controls the second gallium nitride device Q2 to be in the off state; and from the seventh to the eighth moment, PWM2 controls the second gallium nitride device Q2 to be in the on state.

[0048] The equivalent diagram of soft switching is as follows: Figure 5 As shown in (b). During the period t1–t2, a narrow pulse gate signal is provided to the first gallium nitride device Q1. Q1 is turned on for a short period of time, the load inductor charges, and the load current I... L Increase to a smaller value. During the dead time t2–t3, the parasitic capacitance of Q2 discharges to the load inductance, so the drain-source voltage of Q2 begins to decrease. When the drain-source voltage drops to zero, the channel of Q2 begins to conduct in reverse, and a small reverse current flows through the device under test. The waveform diagram is shown below. Figure 6 As shown. Subsequently, Q2 can be turned on with zero voltage at time t3, thereby realizing the soft switching of the device under test.

[0049] S3. When the third gallium nitride device Q3 is turned off, the voltage between test points A and B can be determined by V. CC -V THCalculations show that a suitable DC voltage source V is selected. CC This makes the V measured on the oscilloscope... AB The size is sufficient to meet the measurement accuracy requirements. When the third gallium nitride device Q3 is turned on, since the on-resistance of the third gallium nitride device Q3 is much smaller than that of the second gallium nitride device Q2, a Zener diode D is selected. Z The negative terminal of the diode and the positive terminal of the Schottky diode D1 are used as two test points. The voltage difference between the test points is equal to the conduction voltage of the second gallium nitride device Q2. The voltage V measured during the second conduction period of the device under test, t7-t8, is selected. AB As the on-state voltage of the device under test.

[0050] S4. Calculate the current flowing through the device under test (DUT) based on the voltage drop across coaxial resistor R3. Then, use Ohm's law to obtain the dynamic on-resistance of the device. The simulation test delay effect is shown in the figure below. Figure 7 As shown.

[0051] Compared to traditional test circuits, this invention utilizes an improved clamping circuit to clamp the on-state voltage of the device under test (DUT) to a lower value while significantly reducing additional voltage spikes caused by active devices. This allows the oscilloscope to display the on-state voltage more accurately without distortion from the internal amplifier, thereby improving the measurement accuracy of dynamic on-resistance. Furthermore, while most traditional test circuits still use hard-switching conditions, this invention can achieve both soft-switching and hard-switching tests for dynamic on-resistance. Zero-voltage technology significantly reduces oscillations during the switching process of the DUT, improving test accuracy. The innovation of this invention lies in connecting a Schottky diode and a Zener diode in series in the clamping circuit, greatly reducing the parasitic capacitance of the Zener diode in the clamping circuit, thereby reducing charging and discharging time and effectively reducing test response delay. Simultaneously, the series resistor after the Zener diode avoids overheating of the Zener diode due to the large current during frequent switching during multi-pulse testing, making the test system more stable.

[0052] The specific implementation schemes described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific implementation schemes of the present invention and are not intended to limit the scope of the present invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention should fall within the scope of protection of the present invention.

Claims

1. A dynamic on-resistance testing circuit based on gallium nitride transistors, characterized in that, It includes a DPT test circuit, a switch state switching circuit, and a clamping circuit; wherein the DPT test circuit includes a DC power supply (DC), a first capacitor (C1), a coaxial resistor (R3), a control signal, a gate drive, a first gallium nitride device (Q1), and a second gallium nitride device (Q2); The DC power supply is connected to one end of the first capacitor (C1), one end of the switch state switching circuit, and the drain of the first gallium nitride device (Q1); the other end of the switch state switching circuit is connected to one end of the coaxial resistor (R3), the other end of the DC power supply, and the other end of the first capacitor (C1); the source of the first gallium nitride device (Q1) is connected to the drain of the second gallium nitride device (Q2), the output of the switch state switching circuit, and one end of the clamping circuit; the source of the second gallium nitride device (Q2) is grounded to the other end of the clamping circuit and the other end of the coaxial resistor (R3); the gate drive is connected to the gate of the first gallium nitride device (Q1) and the gate of the second gallium nitride device (Q2); wherein the first gallium nitride device is a device under test, and the second gallium nitride device is a device under test; the input of the clamping circuit is connected to the drain of the second gallium nitride device (Q2); the output of the clamping circuit is connected to the source of the second gallium nitride device (Q2); The clamping circuit includes a third gallium nitride device (Q3), a second voltage source (Vcc), a Schottky diode (D1), a Zener diode (Dz), and a fourth resistor (R4); The drain of the third gallium nitride device (Q3) is connected to the drain of the second gallium nitride device (Q2); the source of the third gallium nitride device (Q3) is connected to the negative terminal of the Zener diode (Dz); the positive terminal of the Zener diode (Dz) is connected to one end of the fourth resistor (R4) and the negative terminal of the Schottky diode (Dz); the positive terminal of the second voltage source (Vcc) is connected to the gate of the third gallium nitride device (Q3); the negative terminal of the second voltage source (Vcc) is connected to the positive terminal of the Schottky diode (D1) and the other end of the fourth resistor (R4) to the source of the second gallium nitride device (Q2).

2. The dynamic on-resistance testing circuit based on gallium nitride transistors according to claim 1, characterized in that, The switching state switching circuit includes a second capacitor (C2), a third capacitor (C3), a first resistor (R1), a second resistor (R2), a switching unit (S), and a load inductor (L); One end of the second capacitor (C2) is connected to one end of the first resistor (R1) and the second end of the switching unit (S); the other end of the second capacitor (C2) is connected to the other end of the first resistor (R1), one end of the third capacitor (C3), one end of the second resistor (R2), and the third end of the switching unit (S); the other end of the third capacitor (C3) is connected to the other end of the second resistor (R2); and one end of the switching unit (S) is connected to one end of the load inductor (L).

3. The dynamic on-resistance testing circuit based on gallium nitride transistors according to claim 2, characterized in that, The second capacitor (C2) and the third capacitor (C3) of the switching state switching circuit have the same value; the first resistor (R1) and the second resistor (R2) have the same value to match the 50% duty cycle during multi-pulse testing.

4. The dynamic on-resistance testing circuit based on gallium nitride transistors according to claim 3, characterized in that, The withstand voltage of the third gallium nitride device (Q3) in the clamping circuit is greater than or equal to the withstand voltage of the second gallium nitride device (Q2).

5. The dynamic on-resistance testing circuit based on gallium nitride transistors according to claim 3, characterized in that, The third gallium nitride device (Q3) is an enhancement-mode gallium nitride device and its on-resistance is much smaller than that of the second gallium nitride device (Q2).

6. A test method based on the dynamic on-resistance test circuit of a gallium nitride transistor according to any one of claims 1-5, characterized in that, Includes the following steps: S1, DC power supply supplies power to the first capacitor (C1), load inductor (L), and other components; S2. The control signals PWM1 and PWM2 of the first gallium nitride device (Q1) and the second gallium nitride device (Q2) generate different pulse waveforms when they are switched to different ports by the switching unit (S) to control the second gallium nitride device (Q2) to be in a soft-switching or hard-switching test state. S3. When the third gallium nitride device (Q3) is turned off, the voltage between test points A and B is determined by V. CC -V TH Calculations show that a preset DC voltage source (V) is selected. CC This causes the V measured on the oscilloscope to... AB The size meets the measurement accuracy requirements; when the third gallium nitride device (Q3) is turned on, since the on-resistance of the third gallium nitride device (Q3) is much smaller than that of the second gallium nitride device (Q2), a Zener diode (D) is selected. Z The negative terminal of the first test device (Q1) and the positive terminal of the second test device (Q2) are used as two test points. The voltage difference between the test points is equal to the turn-on voltage of the second gallium nitride device (Q2). The voltage measured during the second turn-on period of the second gallium nitride device (Q2) from time t7 to t8 is selected as the required turn-on voltage V of the device under test. AB ; S4. Calculate the current flowing through the device under test (DUT) based on the voltage drop across the coaxial resistor (R3). The V measured in step S3 is... AB The ratio of this to the dynamic on-resistance is the dynamic on-resistance.

7. The test method for the dynamic on-resistance test circuit based on gallium nitride transistors according to claim 6, characterized in that, Step S2 specifically involves the following steps: When terminal 1 of the switching unit (S) is connected to terminal 2, the control signal causes the test system to enter a hard-switching test mode. Specifically, time t3 is the first turn-on time of the second gallium nitride device (Q2), time t4 is the turn-off time after the first turn-on of the second gallium nitride device (Q2), and the time from t3 to t4 is the current build-up time. During this period, PWM2 controls the second gallium nitride device (Q2) to remain in the on state. Time t7 is the second turn-on time of the second gallium nitride device (Q2), and the time from t4 to t7 is the time for the inductor current to flow through the first gallium nitride device (Q1) in reverse freewheeling. During this period, PWM2 controls the second gallium nitride device (Q2) to remain in the off state. Time t8 is the turn-off time after the second turn-on of the second gallium nitride device (Q2), and the time from t7 to t8 is the dynamic on-resistance test time. During this period, PWM2 controls the second gallium nitride device (Q2) to remain in the on state. When terminal 1 of the switching unit (S) is connected to terminal 3, the control signal puts the test system into a soft-switching test mode. Here, time t1 is the first turn-on time of the first gallium nitride device (Q1), time t2 is the turn-off time of the first gallium nitride device (Q1) after its first turn-on, and PWM1 controls the first gallium nitride device (Q1) to be in the on state from time t1 to t2; time t5 is the second turn-on time of the first gallium nitride device (Q1), and PWM1 controls the first gallium nitride device (Q1) to be in the off state from time t2 to t5; time t6 is the turn-off time of the first gallium nitride device (Q1) after its second turn-on, and PWM1 controls the first gallium nitride device (Q1) to be in the off state from time t5 to t6. The first gallium nitride device (Q1) is turned on; time t3 is the first time the second gallium nitride device (Q2) is turned on, time t4 is the time the second gallium nitride device (Q2) is turned off after the first turn-on, and PWM2 controls the second gallium nitride device (Q2) to be turned on from time t3 to time t4; time t7 is the second time the second gallium nitride device (Q2) is turned on, and PWM2 controls the second gallium nitride device (Q2) to be turned off from time t4 to time t7; time t8 is the time the second gallium nitride device (Q2) is turned off after the second turn-on, and PWM2 controls the second gallium nitride device (Q2) to be turned on from time t7 to time t8.

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