Interference suppression and adaptive demodulation method and system for power frequency communication of low-voltage power line

Abstract

The invention discloses a low-voltage power line power frequency communication interference suppression and adaptive demodulation method and system, and the method comprises the steps: firstly, detecting the voltage zero crossing of a power grid in real time, and dynamically calibrating a communication time slot based on an actually measured power frequency, thereby achieving the precise power frequency synchronization; injecting a pilot signal into the synchronous time slot window, and judging line topology mutation through coupling of pilot response and a preset signal-to-noise ratio threshold, thereby completing topology perception and verification; triggering channel reestimation in combination with a topological change result, rejecting fundamental wave and multi-order harmonic interference from channel response of least square estimation, and updating a channel model by adopting a time-varying smoothing algorithm; then, a low-noise time window is determined according to the corrected zero cross point, key data packets are scheduled preferentially, and high-reliability anti-interference transmission is achieved; and finally, dynamically and cooperatively adjusting the transmitting power, the receiving filter and the phase compensation based on the newest channel and topology state to form closed-loop self-adaption. According to the scheme, the intelligent degree is high, and the communication stability and the system maintainability are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of low-voltage power line communication, and in particular to a low-voltage power line communication interference suppression and adaptive demodulation method and system. BACKGROUND

[0002] Low-voltage power line carrier (PLC) communication has been widely used in smart meter reading, power distribution automation, building Internet of Things, etc. due to its advantages of no additional wiring, wide coverage, low cost, etc. However, the power line is not designed for communication, and the power frequency (50 / 60 Hz) harmonic, switching burst noise, load switching transient and line topology change interference can easily cause distortion of the carrier signal, affecting the communication reliability.

[0003] The existing PLC system usually adopts fixed frequency or spread spectrum to resist interference, and relies on experience threshold, static notch or single adaptive filtering technology, which has the following technical defects: 1. Static notch can filter out a certain fixed harmonic component, but cannot follow the power grid frequency deviation and multi-harmonic change; 2. The topology or load mutation is determined by relying on the experience threshold, which has no scientific theory support and has the risk of misjudgment or omission; 3. Fixed frame time slot and hard-coded power allocation need to be manually reconfigured under power grid frequency drift or sudden load change, which has high operation and maintenance cost and slow communication recovery.

[0004] Therefore, how to realize the full-link adaptation of zero-crossing synchronization, interference identification, channel compensation and transmission scheduling when the power grid frequency slightly drifts, greatly fluctuates or the topology is reconfigured, becomes a key technical problem to improve the robustness and maintainability of the PLC system. SUMMARY

[0005] This section aims to summarize some aspects of the embodiments of the present application and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of the specification to avoid obscuring the purpose of this section, abstract and title, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0006] Therefore, in order to solve the above technical problems, the present application provides the following technical scheme: a low-voltage power line communication interference suppression and adaptive demodulation method, comprising the following specific steps: S1: real-time detection of power grid voltage zero-crossing point, dynamic calibration of period offset based on measured power frequency, construction of power grid power frequency synchronization reference and generation of corrected communication time slot alignment position; S2: Based on the constructed power grid frequency synchronization reference injection pilot signal, the topology mutation event is determined through the coupling relationship between the impedance change amount and the preset signal-to-noise ratio tolerance, and topology change perception and verification are realized; S3: The results of topology change perception and verification are used to trigger channel reestimation, and the current power frequency harmonic component is removed from the least square estimation channel response, and harmonic associated channel modeling is completed; S4: According to the constructed power grid frequency synchronization reference, a low-noise time window is determined, high-priority data packets are preferentially scheduled near the modified zero-crossing point, and anti-interference transmission scheduling is realized; S5: Based on the results of harmonic associated channel modeling and the topology state obtained by topology change perception and verification, the transmit power allocation strategy, the receive filter cutoff frequency and the carrier phase compensation amount are dynamically and cooperatively adjusted to realize closed-loop parameter adaptation.

[0007] As a preferred scheme of the low-voltage power line power frequency communication interference suppression and adaptive demodulation method, wherein the step S1 of constructing the power grid frequency synchronization reference comprises: The power grid voltage signal is sampled and the actual operating frequency is extracted; The period deviation amount of the actual frequency and the nominal frequency is calculated; The detected zero-crossing points are compensated for cumulative deviation, and a synchronization time slot control signal is generated.

[0008] As a preferred scheme of the low-voltage power line power frequency communication interference suppression and adaptive demodulation method, wherein the topology change perception and verification in step S2 comprises: The pilot signal is injected in the synchronization time slot window; The impedance change threshold is dynamically calculated according to the nominal impedance and the communication quality threshold; If the impedance change amount of the last two times exceeds the threshold, it is determined that there is an effective topology change.

[0009] As a preferred scheme of the low-voltage power line power frequency communication interference suppression and adaptive demodulation method, wherein the harmonic associated channel modeling in step S3 comprises: The harmonic amplitude and phase characteristics associated with the fundamental frequency are extracted; The harmonic interference component is removed from the channel estimation value; The time-varying smoothing coefficient is used to update the channel model parameters.

[0010] As a preferred scheme of the low-voltage power line power frequency communication interference suppression and adaptive demodulation method, wherein the parameter closed-loop adaptation in step S5 comprises: Power allocation: the total power is allocated in proportion to the inverse of the subcarrier channel gain; Filter adjustment: resetting cutoff frequency according to noise spectrum peak position offset; Phase compensation: generating real-time compensation by referring to subcarrier phase error.

[0011] As a preferred scheme of the low-voltage power line power frequency communication interference suppression and adaptive demodulation method, the method further comprises an exception handling mechanism. When the impedance variation exceeds the safety tolerance or the channel modeling fails, switch to a robust communication mode; The robust communication mode includes order reduction modulation, enhanced error correction coding and transmission rate limitation.

[0012] The low-voltage power line power frequency communication interference suppression and adaptive demodulation system is used to realize any of the low-voltage power line power frequency communication interference suppression and adaptive demodulation methods described above, and comprises: A synchronization reference modeling module performs voltage zero-crossing detection and dynamic time slot calibration; A topology-aware verification module realizes impedance mutation decision based on pilot signals; A channel modeling module generates a harmonic-compensated channel response model; A transmission scheduling module controls data priority allocation in a low-noise window; A parameter coordination optimization module adjusts power, filter and phase parameters in linkage.

[0013] As a preferred scheme of the low-voltage power line power frequency communication interference suppression and adaptive demodulation system, the synchronization reference modeling module comprises: A zero-crossing detection unit samples the voltage signal at a rate of 10 kHz or higher; A frequency offset compensation unit dynamically calculates power frequency cycle offset; A time slot controller outputs an enable signal of the calibrated communication window.

[0014] A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of any of the methods described above when executing the computer program.

[0015] A computer-readable storage medium having a computer program stored thereon, characterized in that the computer program is executed by a processor to implement the steps of any of the methods described above.

[0016] The beneficial effects of the present application are: The present application proposes an interference suppression and adaptive demodulation method and system integrating dynamic power frequency calibration, topology awareness based on signal-to-noise ratio coupling, multi-order harmonic correlation modeling, zero-crossing window priority scheduling and closed-loop parameter coordination.

[0017] The method can correct power frequency deviation in real time, generate accurate communication time slots, accurately identify line topology changes combined with dynamic threshold, further remove fundamental wave and high-order harmonic interference components, preferentially use voltage zero-crossing low-noise period to transmit key data, and automatically adjust transmission power, receiving filter and phase compensation according to the channel model and topology state, so as to realize rapid response and autonomous management to power grid state changes.

[0018] The whole process is intelligently and adaptively operated, without the need for on-site manual parameter adjustment or program upgrade, thereby significantly improving the robustness and reliability of the system and reducing the operation and maintenance cost, and providing stable and efficient communication guarantee for smart grid and related Internet of Things applications. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. Among them: Fig. 1 The workflow diagram of the present application.

[0020] Fig. 2 The system architecture diagram of the present application.

[0021] Fig. 3 The structural schematic diagram of the computer device of the present application. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings of the specification.

[0023] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0024] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. In this specification, "in one embodiment" appearing in different places does not mean the same embodiment, nor is it an independent or selective embodiment that excludes other embodiments.

[0025] Embodiment 1 Reference Figs. 1-3This is the first embodiment of the present invention, which provides a method for suppressing and adaptively demodulating low-voltage power line frequency communication interference. The specific implementation steps of the method are as follows: S1: Construct a power grid frequency synchronization benchmark; Step 1.1: Voltage sampling and frequency extraction; Sampling settings: Use a 16-bit ADC (such as AD7606) kHz sampling grid voltage ; Zero-crossing count: within the time window length Inside, count the number of times it crosses zero. (The total number of zero crossings counted within a fixed time window, including one positive and one negative zero crossing), while counting positive and negative zero crossings separately to improve robustness; Calculate the actual power frequency: The actual power frequency (Hz) of the power grid is calculated using this formula. (Sampling start and end time interval, i.e., window length); For example: if 10 zero crossings are counted within 0.1 seconds, then ; In this formula, the current power grid frequency is estimated quickly and robustly by statistically counting the number of zero crossings, ensuring accurate correction of the period offset in the future; molecular This represents the number of times the grid voltage actually crosses the zero level within this time window; denominator Because the voltage needs to cross zero twice to complete one cycle from the positive half-cycle to the negative half-cycle and then back to positive, therefore, divide by 2. To obtain the number of cycles per second.

[0026] Step 1.2: Calculate the period offset; The offset formula is as follows: ; Among them, in the formula Step 1.1 Calculate the actual power grid frequency (Hz); 50Hz: Nominal power frequency; The zero-crossing time offset half-cycle amount (s) of a single cycle is used to accumulate and compensate for time slot drift. Half-cycle factor: The denominator "2" comes from the symmetry of the grid voltage poles, and only half-cycle phase shift needs to be compensated; The above formula can be used to quantify the time slot drift caused by the power grid frequency offset, and then accumulate corrections during subsequent alignment. item : difference between actual period and nominal period; : multiply by : with voltage symmetry, only half period phase drift needs to be compensated to achieve zero-crossing alignment.

[0027] Step 1.3: zero-crossing correction and time slot generation; Zero-crossing time correction: the kth detected zero-crossing time is corrected as follows: Cumulative compensation, the calculation formula is as follows: ; : the kth original detected zero-crossing time (s); : single period half period offset (s) calculated in step 1.2; : the kth corrected zero-crossing time (s); In this step, each detected zero-crossing time is cumulatively compensated for power grid frequency deviation by the above formula, ensuring that the kth time slot is always synchronized with the actual power grid; Cumulative term : with the increase of period number, the offset accumulates, otherwise the frequency deviation error will increase linearly; Time slot alignment: In this step, take , and take and its integer multiples as the starting time of communication time slot; Note: this structure can be realized by the timing controller in FPGA, and the 4ms width time slot enable signal is output; Example: when (3rd period), : Original → After correction: ; S2: topology change perception and verification; Step 2.1: pilot signal injection; Chirp signal: a kind of linear frequency modulation signal, whose frequency is linearly scanned from the initial frequency to ; Transmitted Chirp pilot signal: ; Wherein, the former : fundamental phase, through this term, a sinusoidal wave reference with constant frequency is generated, which provides a known fundamental phase starting point for Chirp signal, which is convenient for comparison with at the receiving end to complete preliminary channel estimation; The latter For linear frequency phase, the frequency increases linearly with time until The channel frequency response is measured with a wider frequency band, thereby improving the measurement accuracy and spectral resolution; The PLC subcarriers are usually distributed in the range of 10 kHz-500 kHz, and in this example, the lower limit of 10 kHz is selected to avoid the harmonic concentration area of the power grid; In a 4 ms window, the frequency is swept from 10 kHz to 20 kHz, which can cover multiple subcarriers and is sufficient to obtain the multi-frequency response of the channel. At the same time, the bandwidth should not be too large to avoid exceeding the window or circuit bandwidth limit; Power and duration: the transmission power does not exceed 1 W, and the pulse width (ensure ≤4 ms window), which is slightly smaller than the total width of the ±2 ms zero-crossing window 4 ms, to ensure that the Chirp signal is completely located in the low-noise window, while leaving enough time for receiving processing (FFT, filtering, etc.); Receiving processing: in window, receive , use Hanning window to do N=1024 point FFT (frequency resolution ≈9.8 Hz), and obtain .

[0028] Step 2.2: adaptive threshold calculation; Nominal impedance: read from the line parameter library (examples 50 Ω).

[0029] SNR threshold: ; Threshold calculation formula: ; Through the above formula, the communication quality (SNR) requirement is linked with the impedance change, avoiding the uncertainty brought by the empirical threshold; In the above formula: : nominal line impedance (Ω), derived from design or line parameter library; : minimum acceptable signal-to-noise ratio threshold (dB), for example, 10 dB; : impedance change threshold, used to determine topology or load mutation; Term : convert the SNR in decibels to a linear gain change ratio, and then multiply it by the nominal impedance to get the corresponding impedance change boundary.

[0030] Step 2.3: topology mutation determination; Impedance calculation: , ; ; The above formula is used to calculate and measure the line impedance change by quantizing the pilot signal. The threshold is then used to determine whether a structural change (such as feeder switching) has occurred. , This time, the frequency point is the same as the last time. Complex impedance (Ω) measured at 100kHz. The absolute difference between two measurements (Ω); Absolute value: Focus on amplitude changes, no need to consider phase sign; Continuous determination: If two measurements are obtained This triggers the topology mutation flag and feeds it back to the closed-loop control.

[0031] S3: Harmonic correlation channel modeling; Step 3.1: Harmonic component extraction; PLL capture: Utilizing a phase-locked loop to generate a fundamental frequency signal in phase with the power grid. ; Coefficient calculation: , ; The above formula is mainly used to separate and quantize the power frequency harmonic components of each order in the received signal, in preparation for subsequent frequency domain compensation. Integral multiplied by cosine: Using orthogonal projection, The amplitude of the harmonic is obtained by taking the inner product over the basis functions that are in phase and have the same frequency as the harmonic. : The time-domain waveform of the received signal; : Duration of one power grid cycle (s); Harmonic order, with a value range of 1-5; The phase of the nth harmonic is obtained synchronously from the PLL output; : Amplitude estimation of the nth harmonic component (combined with phase to form a complete harmonic); Overall objective: To separate and quantize the power frequency harmonic components of the received signal, in preparation for subsequent frequency domain compensation.

[0032] Step 3.2: Channel response correction; Original estimate: ; sinc function: using , for reconstructing the spectral shape of harmonics.

[0033] Compensation formula: ; : frequency-domain least square channel estimation value : calculated by step 3.2 above : channel model after eliminating harmonic interference, the calculation purpose of which is to directly subtract the impact of harmonic main lobe and its sidelobe leakage on other subcarriers in the frequency domain, thereby improving channel estimation accuracy : analog harmonic diffusion shape in the frequency domain, which is accurately deducted

[0034] Step 3.3: Smooth update Dynamic rules:

[0035] Smooth formula: ; In the above formula: : time-varying smoothing coefficient, which is adaptively selected in the range [0.1, 0.3] according to impedance change ; when the impedance changes little (the environment is stable), it tends to update quickly; when the impedance changes greatly, it increases inertia to protect historical information.

[0036] : channel model after update at the last time : final channel model at the current time, the calculation purpose of which is mainly to balance new estimation and historical estimation, suppress estimation noise caused by short-time mutation, and maintain model timeliness

[0037] S4, Anti-interference transmission scheduling Low-noise window definition: , ; Through calculation by the above formula, the period with the lowest noise in the power grid voltage waveform is determined to improve the transmission reliability of critical data packets wherein, : current corrected zero-crossing time : half-width of zero-crossing low-noise time window, used for priority scheduling The scheduling strategy is as follows: High-priority data packets (control commands) are forced to be sent within W Normal data packets are sent outside the window Technical effect: The noise power in the window is reduced by about 12dB compared with the outside of the window.

[0038] S5, closed loop parameter adaptation; Step 5.1: power allocation; Formula: ; Implementation: C code embedded in MCU, loop calculation of subcarrier power; : total system transmit power (W); : estimated channel gain of subcarrier : total number of subcarriers; Through the above formula, power is allocated according to the inverse square of the channel, and more power is allocated to weak channels to balance the SNR of each subcarrier; Inverse square: amplify and compensate for subcarriers with small channel gains.

[0039] Step 5.2: filter cutoff frequency adjustment; Noise spectrum estimation: collect in the non-signal time window, and use sliding average filtering to remove narrowband signal interference; Cutoff frequency: ; : estimated noise power spectrum density; : filter cutoff frequency (Hz); In the above formula, first locate the strongest noise frequency point , and then slightly shift it outward by 1kHz to ensure better preservation of signal components outside the main noise band.

[0040] Step 5.3, phase compensation; Reference subcarrier: select (out-of-band subcarrier with low interference); Compensation amount: ; Through the above formula, the phase deviation caused by carrier phase shift is eliminated to ensure phase synchronization required for demodulation.

[0041] In the above formula: Negative sign: "reverse" the measured phase shift to correct the phase reference of the receiver demodulator; : reference subcarrier frequency point (example 80kHz); ​The complex channel estimation ratio of this carrier is used to estimate the complex response of the channel at this frequency, where the phase angle is the channel-introduced phase offset of this subcarrier; in, : Represents the received signal spectrum value at the corresponding frequency point obtained by the receiver after FFT; : Indicates that the transmitting end is at the reference subcarrier frequency point The frequency domain value of the known pilot signal at the location (usually obtained through a preset chirp signal or a fixed amplitude and phase pilot); Real-time phase compensation (rad); Moving average: for Perform a 5-sample moving average to suppress measurement noise.

[0042] S6, Exception handling mechanism; Triggering conditions: ; The above formula is used to calculate and set a more stringent security boundary (1.5 times the threshold) and a maximum acceptable bit error rate. Once the boundary is exceeded, robust mode is triggered.

[0043] A low-voltage power line power frequency communication interference suppression and adaptive demodulation system, used to implement any of the above-described low-voltage power line power frequency communication interference suppression and adaptive demodulation methods, characterized in that it includes: The synchronous reference construction module performs voltage zero-crossing detection and dynamic time slot calibration. The topology-sensing verification module implements impedance change decision-making based on pilot signals; The channel modeling module generates a harmonic-compensated channel response model. The transmission scheduling module controls the data priority allocation within the low-noise window; The parameter co-optimization module adjusts the power, filter, and phase parameters in a coordinated manner.

[0044] As a preferred embodiment of the low-voltage power line frequency communication interference suppression and adaptive demodulation system of the present invention, the synchronization reference construction module includes: Zero-crossing detection unit samples voltage signals at a rate of 10kHz or higher; Frequency offset compensation unit dynamically calculates the power frequency cycle offset; The time slot controller outputs the enable signal for the calibrated communication window.

[0045] The above-mentioned unit modules can be embedded in the processor of the computer device in hardware form or independent of it, or they can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of the above modules.

[0046] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Fig. 3 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements an SFC (Start-up Control Switching) method that adapts to different main connection methods. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device casing, or an external keyboard, touchpad, or mouse.

[0047] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the above-described low-voltage power line frequency communication interference suppression and adaptive demodulation method.

[0048] Example 2 As a second embodiment of the present invention, a method and system for suppressing and adaptively demodulating low-voltage power line frequency communication interference are provided. In order to verify the beneficial effects of the present invention, comparative experiments are conducted for scientific demonstration.

[0049] Table 1. Bit error rate and handover recovery time records for each test scenario.

[0050] In this embodiment, the parameters of the three major modules—power frequency cycle offset compensation, signal-to-noise ratio coupling threshold, and multi-order harmonic compensation—were combined and tested under various power grid conditions.

[0051] Test scenarios 1-3 (steady state / mild / severe frequency deviation): set thresholds for each scenario. ( Take 50Ω, Different in (=10dB) Value, observation The effect of time slot alignment recovery and bit error rate (BER) changes were investigated. Results show that even with a frequency offset of ±1.5 Hz, the cumulative drift correction after half-cycle compensation can control the BER within a certain range. The order of magnitude is 10-6, and the switching recovery time is less than or equal to 60 ms.

[0052] Test scenarios 4-5 (third-order harmonic interference): comparison and The BER changes before and after compensation are compared for two harmonic compensation orders. The single-order compensation effect is limited ( ), and the third-order compensation is , which proves the significant advantage of the multi-order harmonic correlation modeling.

[0053] Test scenarios 6-7 (load switching and frequency offset superposition): when the instantaneous exceeds the threshold, the system triggers topology reevaluation and resampling, and the recovery time is observed. The results show that the pure load switching recovery time is approximately 28 ms, and the recovery time is approximately 68 ms when superimposed with severe frequency offset, verifying the efficiency of the cooperative closed-loop adaptive logic.

[0054] The second embodiment of the present application scientifically demonstrates the following beneficial effects of the present application by comparing the performance data under different power grid disturbance combinations: High accuracy of frequency offset drift correction: BER≤2.8×10 -5 within ±1.5 Hz, and the maximum window drift is less than 0.1 ms; Significant multi-order harmonic suppression: harmonic insight and compensation can reduce the BER under interference environment by more than 90%; Agile topology adaptation: load mutation recovery time is less than or equal to 28 ms, which is much better than the traditional static scheme; Robust cooperative optimization: when frequency offset and topology, harmonics exist at the same time, the overall recovery time is less than or equal to 70 ms, ensuring uninterrupted communication.

[0055] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and they should be included in the scope of the claims of the present application.

[0056] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In one embodiment, the present application can be implemented in software and can be stored on a computer readable medium, which can include random access memory (RAM), read only memory (ROM), magnetic disk or optical disk, or the like. The software implementation can comprise one or more computer program components embodied on one or more computer readable medium(s). The computer readable medium can be resident within the computing device or external to the computing device. The computer program components can also be downloaded into the computing device from an external computer or external storage device.

[0057] The present application is described in reference to the flowchart illustrations and / or block diagrams according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing device or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Fig. 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Fig. 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0058] These computer program instructions can also be stored in a computer readable medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Fig. 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Fig. 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0059] These computer program instructions can also be loaded onto a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Fig. 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Fig. 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0060] While the preferred embodiments of the application have been described, additional variations and modifications can be employed by those skilled in the art. Therefore, the appended claims are intended to cover all such variations and modifications as falling within the scope of the application.

[0061] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method for suppressing and adaptively demodulating low-voltage power line frequency communication interference, characterized in that: The specific steps include the following: S1: Real-time detection of the grid voltage zero crossing point, dynamic calibration cycle offset based on the measured power frequency, construction of the power frequency synchronization benchmark, and generation of the corrected communication time slot alignment position; S2: Based on the constructed power grid frequency synchronization benchmark, inject pilot signals and determine topology change events by the coupling relationship between impedance change and preset signal-to-noise ratio tolerance, thereby realizing topology change perception and verification; S3: Trigger channel re-estimation using the results of topology change sensing and verification, eliminate the current power frequency harmonic components from the least squares estimated channel response, and complete harmonic-correlated channel modeling. S4: Determine the low-noise time window based on the constructed power grid frequency synchronization benchmark, and prioritize scheduling high-priority data packets in the period near the corrected zero-crossing point to achieve anti-interference transmission scheduling; S5: Based on the harmonic correlation channel modeling results and the topology state obtained from topology change perception and verification, the transmit power allocation strategy, receive filter cutoff frequency and carrier phase compensation amount are dynamically and collaboratively adjusted to achieve closed-loop parameter self-adaptation.

2. The low-voltage power line frequency communication interference suppression and adaptive demodulation method as described in claim 1, characterized in that: The step of constructing the power grid frequency synchronization reference in step S1 includes: Sample the grid voltage signal and extract the actual operating frequency; Calculate the period deviation between the actual frequency and the nominal frequency; Accumulated deviation compensation is performed on the detected zero-crossing points to generate a synchronous time slot control signal.

3. The low-voltage power line frequency communication interference suppression and adaptive demodulation method as described in claim 2, characterized in that: The topology change sensing and verification in step S2 includes: Inject pilot signals within the synchronization time slot window; The impedance change threshold is dynamically calculated based on the nominal impedance and the communication quality threshold. If the impedance changes exceed the threshold twice consecutively, it is considered a valid topology change.

4. The low-voltage power line frequency communication interference suppression and adaptive demodulation method as described in claim 3, characterized in that: The harmonic correlation channel modeling in step S3 includes: Extract the amplitude and phase characteristics of harmonics associated with the fundamental power frequency; Remove harmonic interference components from the channel estimate; The channel model parameters are updated using time-varying smoothing coefficients.

5. The low-voltage power line frequency communication interference suppression and adaptive demodulation method as described in claim 4, characterized in that: The parameter closed-loop adaptive step S5 includes: Power allocation: The total power is allocated according to the inverse ratio of the subcarrier channel gain; Filter adjustment: Reset the cutoff frequency based on the offset of the noise spectrum peak position; Phase compensation: Real-time compensation is generated by referencing the subcarrier phase error.

6. The low-voltage power line frequency communication interference suppression and adaptive demodulation method as described in claim 5, characterized in that: This method also includes an exception handling mechanism: When the impedance change exceeds the safety tolerance or the channel modeling fails, switch to robust communication mode; The robust communication mode includes down-order modulation, enhanced error correction coding, and transmission rate limiting.

7. A low-voltage power line frequency communication interference suppression and adaptive demodulation system, used to implement the low-voltage power line frequency communication interference suppression and adaptive demodulation method according to any one of claims 1 to 6, characterized in that: include: The synchronous reference construction module performs voltage zero-crossing detection and dynamic time slot calibration. The topology-sensing verification module implements impedance change decision-making based on pilot signals; The channel modeling module generates a harmonic-compensated channel response model. The transmission scheduling module controls the data priority allocation within the low-noise window; The parameter co-optimization module adjusts the power, filter, and phase parameters in a coordinated manner.

8. The low-voltage power line frequency communication interference suppression and adaptive demodulation method as described in claim 7, characterized in that: The synchronization benchmark construction module includes: Zero-crossing detection unit samples voltage signals at a rate of 10kHz or higher; Frequency offset compensation unit dynamically calculates the power frequency cycle offset; The time slot controller outputs the enable signal for the calibrated communication window.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-6.

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