LDMOS process TVS device and manufacturing method thereof

Abstract

The invention provides an LDMOS process TVS (Transient Voltage Suppressor) device and a manufacturing method thereof, and belongs to the technical field of TVS semiconductor preparation. Comprising a P-type silicon substrate, the surface of the P-type silicon substrate is provided with a deep N well, the deep N well is used for providing isolation for a source / drain high-voltage N + region and preventing punch-through or premature breakdown between the deep N well and the P-type substrate, the deep N well is used as a collector region of a parasitic NPN BJT, and a P-type body region is arranged in the deep N well. According to the invention, the inherent high-voltage capability of an LDMOS and a parasitic BJT structure are utilized to realize rapid triggering and low clamping, the manufacturing process is highly compatible with a standard CMOS / BCD process, key parameters such as breakdown voltage, clamping voltage, capacitance, surge capability and the like can be optimized by accurately designing a drift region, a P body region, a deep N well and layout, various harsh circuit protection requirements are met, and the reliability of the device is improved. The method is particularly applied to applications requiring low capacitance, high integration level and high reliability.

Description

Technical Field

[0001] This invention relates to the field of TVS semiconductor fabrication technology, and in particular to an LDMOS process TVS device and its manufacturing method. Background Technology

[0002] Traditional TVS devices (such as silicon avalanche diodes and Zener diodes) rely on the PN junction avalanche breakdown principle for clamping, but they have the following problems: High clamping voltage: The clamping coefficient (the ratio of clamping voltage to breakdown voltage) is generally between 1.2 and 1.4, which is difficult to meet the precision protection requirements of low-voltage circuits; Limited response speed: Although the nanosecond-level response (0.3 to 1 ps) is better than that of gas discharge tubes, it is still insufficient for the fast surges of high-frequency interfaces (such as USB 4.0); Large parasitic capacitance: The junction capacitance can reach 1000 pF (power supply level), which seriously affects the quality of RF signal transmission.

[0003] LDMOS has become the mainstream choice for high-voltage TVS due to its drift region design, which can withstand high voltages (such as 700V to 1200V). Therefore, this application provides an LDMOS process TVS device and its manufacturing method to meet the requirements. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an LDMOS process TVS device and its manufacturing method to solve the existing problems.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: An LDMOS TVS device and its manufacturing method are disclosed, comprising: a P-type silicon substrate, wherein a deep N-well is formed on the surface of the P-type silicon substrate, the deep N-well being used to provide isolation for the high-voltage N+ regions of the source / drain, preventing punch-through or premature breakdown between the deep N-type substrate and the P-type substrate, and serving as the collector region for a parasitic NPN BJT; a P-type body region is disposed within the deep N-well by implantation; a heavily doped N+ source region is disposed within the P-type body region; a heavily doped N+ drain region is disposed outside the P-type body region; a drift region is disposed in a lightly doped N-type region between the P-type body region and the N+ drain region; a gate is covered on the surface of the P-type body region and the drift region, the gate being located on the surface of a polysilicon layer; an anode is disposed on the side of the N+ drain region; and a cathode is disposed between the N+ source region and the gate, wherein both the anode and the cathode are made of metal.

[0006] In one possible implementation, the N+ source region serves as the emitter region of the parasitic NPN BJT and also as an electrode of the TVS, with the wire of the N+ source region grounded.

[0007] In one possible implementation, the N+ drain region serves as another electrode of the TVS to withstand surge voltage, and the N+ drain region is also part of the collector region of the parasitic NPN BJT.

[0008] In one possible implementation, there is a gate oxide layer below the gate, the gate is directly connected to the source, the channel below the gate is in a normally off state, the gate is used to help precisely control the surface potential and depletion region shape of the P-type body region, and affect the trigger point of the parasitic NPN BJT, while also assisting in discharging a small amount of current or improving trigger characteristics.

[0009] A method for manufacturing a TVS device using LDMOS technology includes the following steps: S1. Select a P-type silicon wafer with suitable resistivity as the starting substrate, and then perform standard RCA cleaning to remove surface contaminants and the natural oxide layer. S2. Apply photoresist, expose and develop through a mask to define the deep N-well region; S3. Coat the photoresist, expose and develop it through a mask to define the P-type body region; S4. Coat with photoresist, expose and develop through a mask to define the lightly doped N-type region from the drain to the P-type body, implant phosphorus (P) to form the N-drift region; S5. Grow / deposit oxide layer, and use photolithography to form isolation trenches (STI) or silicon oxide bumps (LOCOS) to prevent leakage between devices; S6. Fabricate the gate structure; S7, sidewall formation; S8. Coat the photoresist, expose and develop it through a mask, and define the N+ source region and N+ drain region; S9. Define the P+ contact region on the P-type body region, immediately adjacent to the source region; S10. Metal silicides are formed on the surfaces of the N+ source region, N+ drain region, gate region, and P+ contact region to significantly reduce contact resistance; S11. Coat photoresist, expose and develop through a mask, define the contact hole positions and etch the dielectric layer to open the contact holes to reach the N+ source, N+ drain, P+ contact area and gate; S12. Define the metal interconnect pattern, short-circuit the N+ source region, P+ contact region, and gate together, connect them to the cathode metal, connect the N+ drain region to the anode metal, and etch the metal layer. S13. As needed, continue to deposit dielectric layers, vias, and more metal layers, followed by the deposition of the final passivation layer, and photolithography to open the bonding pad.

[0010] In one possible implementation, in S2, after defining the deep N-well region, high-energy phosphorus (P) or arsenic (As) ions are implanted with an energy range of 600 keV to 1.5 MeV and a dose of 1e12 cm⁻² to 1e13 cm⁻² to form a low-doped deep junction isolation region, serving as the collector region of the parasitic NPN. This region is then subjected to long-term annealing at 1100°C to 1200°C for 3 to 5 hours to advance the junction depth to 3 μm to 8 μm, activating impurities and repairing lattice damage. In S3, after defining the P-type body region, boron (B) is implanted with medium to low energy (60 keV to 150 keV and a dose of 1e13 cm⁻² to 5e13 cm⁻²) to control lateral diffusion and undergo rapid thermal annealing or furnace tube annealing to form a 0.5 μm to 1.5 μm deep P-type body region, serving as the base region of the parasitic NPN BJT.

[0011] In one possible implementation, S6 specifically involves: growing a 10nm-50nm thick gate oxide layer using a dry or wet oxygen process to form an LPCVD-deposited polysilicon layer with a thickness of 200nm-400nm; implanting phosphorus or boron to adjust the resistivity; then coating with photoresist; defining the gate shape covering the edge of the P-type body region and the drift region through photomask exposure and development, typically a T-type or straight strip shape; and forming a precise gate electrode by dry etching of the polysilicon.

[0012] In one possible implementation, S7 specifically refers to: S701, Deposition: LPCVD deposition of silicon nitride (SiN) or silicon dioxide (SiO2); S702, Anisotropic Etching: Etching back forms 100-300nm wide sidewalls to isolate the gate from the subsequent heavily doped region.

[0013] In one possible implementation, S8 injects arsenic (As) after defining the N+ source and N+ drain regions, with a dose of >1e15 cm2 and an energy of 30 keV to 80 keV, forming a low-resistivity ohmic contact, and then rapidly anneals at 950°C to 1050°C to activate impurities and limit diffusion.

[0014] In one possible implementation, S11 specifically involves: defining the contact hole location, etching the dielectric layer, and opening contact holes to reach the N+ source, N+ drain, P+ contact region, and gate; S12 specifically involves: depositing a first metal layer, defining a metal interconnect pattern, then shorting the N+ source region, P+ contact region, and gate together to connect to the cathode metal, connecting the N+ drain region to the anode metal, and etching the metal layer.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: This invention features high integration: it can be easily integrated with CMOS logic, analog circuits, and power devices on the same chip (BCD process); high breakdown voltage: it can easily achieve breakdown voltages from tens to hundreds of volts; low clamping voltage: compared to a single-diode TVS, the clamping voltage is lower and the protection effect is better; low capacitance: through optimized design, very low parasitic capacitance can be achieved, suitable for high-speed interfaces (USB, HDMI, Ethernet); controllable triggering: the triggering characteristics can be precisely controlled through LDMOS structural parameters (gate connection, drift region); high current capability: by increasing the device area (multiple interdigitates), it can withstand very high surge currents. In summary, this invention utilizes the inherent high voltage capability and parasitic BJT structure of LDMOS to achieve fast triggering and low clamping. Its manufacturing process is highly compatible with standard CMOS / BCD processes. By precisely designing the drift region, P-body region, deep N-well, and layout, key parameters such as breakdown voltage, clamping voltage, capacitance, and surge capability can be optimized to meet various stringent circuit protection requirements, especially in applications requiring low capacitance, high integration, and high reliability. Attached Figure Description

[0016] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to implement and use the present disclosure.

[0017] Figure 1 This is a schematic diagram of a TVS device manufactured using LDMOS technology. Figure 2 This is a flowchart of a method for manufacturing a TVS device using LDMOS technology.

[0018] [Figure Labels] 1. P-type silicon substrate; 2. Deep N-well; 3. P-type body region; 4. N+ source region; 5. N+ drain region; 6. Drift region; 7. Gate; 8. Cathode; 9. Anode.

[0019] As shown in the figure, specific structures and devices are labeled in the figure to clearly illustrate the structure of the embodiments of the present invention. However, this is only for illustrative purposes and is not intended to limit the present invention to the specific structure, device and environment. Those skilled in the art can adjust or modify these devices and environments according to specific needs, and such adjustments or modifications are still included in the scope of the appended claims. Detailed Implementation

[0020] The following detailed description of an LDMOS process TVS device and its manufacturing method, in conjunction with the accompanying drawings and specific embodiments, illustrates the present invention. It should be noted that, to make the embodiments more comprehensive, the following embodiments are listed as best and preferred examples; other alternative methods may be used by those skilled in the art. Furthermore, the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the invention.

[0021] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0022] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather, alternatively, depending at least partly on the context, to allow for the presence of other factors that are not necessarily explicitly described.

[0023] It is understood that the meanings of “on”, “above”, and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on” something, but also includes something with an intermediary feature or layer, and that “above” or “above” means not only “on” something, but also includes something “above” or “above” without an intermediary feature or layer.

[0024] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for convenience to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially related terms are intended to cover different orientations in the use or operation of the device other than those depicted in the accompanying drawings. The device may be oriented in other ways, and the spatially related descriptive terms used herein can be interpreted similarly.

[0025] Example 1, as Figure 1As shown, an embodiment of the present invention provides an LDMOS process TVS device, including a P-type silicon substrate. A deep N-well is formed on the surface of the P-type silicon substrate. The deep N-well is used to provide isolation for the source / drain high voltage N+ region, preventing punch-through or premature breakdown between it and the P-type substrate, and serving as the collector region of the parasitic NPN BJT. A P-type body region is disposed in the deep N-well by implantation. A heavily doped N+ source region is disposed in the P-type body region. A heavily doped N+ drain region is disposed outside the P-type body region. A drift region is disposed in the lightly doped N-type region between the P-type body region and the N+ drain region. A gate is covered on the surface of the P-type body region and the drift region. The gate is located on the surface of the polysilicon layer. An anode is disposed on the side of the N+ drain region, and a cathode is disposed between the N+ source region and the gate. Both the anode and the cathode are made of metal. The N+ source region serves as the emitter region of the parasitic NPN BJT and is also an electrode of the TVS. The wire of the N+ source region is grounded. The N+ drain region serves as the other electrode of the TVS and is used to withstand surge voltage. The N+ drain region is also part of the collector region of the parasitic NPN BJT. There is a gate oxide layer under the gate. The gate is directly connected to the source. The channel under the gate is in a normally off state. The gate is used to help precisely control the surface potential of the P-type body region and the shape of the depletion region, and to affect the trigger point of the parasitic NPN BJT. It can also help discharge a small amount of current or improve the trigger characteristics.

[0026] Example 2, as Figure 2 As shown, an embodiment of the present invention provides a method for fabricating a TVS device using LDMOS technology, comprising the following steps: S1. Select a P-type silicon wafer with suitable resistivity as the starting substrate, and then perform standard RCA cleaning to remove surface contaminants and the natural oxide layer. S2. Coat with photoresist, expose and develop using a mask to define the deep N-well region; after defining the deep N-well region, implant high-energy phosphorus (P) or arsenic (As) ions, with an energy range of 600 keV to 1.5 MeV and a dose of 1e12 cm⁻² to 1e13 cm⁻², to form a low-doped deep junction isolation region as the collector region for the parasitic NPN, and perform long-term annealing at 1100℃ to 1200℃ for 3 to 5 hours to advance the junction depth to 3 μm to 8 μm, activate impurities and repair lattice damage; S3. Coat with photoresist, expose and develop using a mask to define the P-type body region; after defining the P-type body region, implant boron (B) with medium to low energy: energy: 60keV~150 keV; dose: 1e13cm~2~5e13cm~2, control lateral diffusion and perform rapid thermal annealing or furnace tube annealing to form a P-type body region with a depth of 0.5μm~1.5μm, which serves as the base region of the parasitic NPN BJT; S4. Coat with photoresist, expose and develop through a mask to define the lightly doped N-type region from the drain to the P-type body, implant phosphorus (P) to form the N-drift region; S5. Grow / deposit oxide layer, and use photolithography to form isolation trenches (STI) or silicon oxide bumps (LOCOS) to prevent leakage between devices; S6. Perform gate structure fabrication; use dry or wet oxygen processes to grow a 10nm-50nm thick gate oxide layer to form an LPCVD deposited polysilicon layer with a thickness of 200nm-400nm. Implant phosphorus or boron to adjust the resistivity, then coat with photoresist, and use a mask to expose and develop to define the gate shape covering the edge of the P-type body region and the drift region. It is usually T-shaped or straight strip. Then, dry etch the polysilicon to form a precise gate electrode. S7, sidewall formation; S701, Deposition: LPCVD deposition of silicon nitride (SiN) or silicon dioxide (SiO2); S702, Anisotropic Etching: Etching back forms 100-300nm wide sidewalls to isolate the gate from the subsequent heavily doped region; S8. Coat with photoresist, expose and develop using a mask to define the N+ source region and N+ drain region; after defining the N+ source region and N+ drain region, implant arsenic (As) in S8, dose: >1e15 cm~2; energy: 30 keV 80 keV, to form a low-resistivity ohmic contact, and rapidly anneal at 950℃~1050℃ to activate impurities and limit diffusion; S9. Define the P+ contact region on the P-type body region, immediately adjacent to the source region; S10. Metal silicides are formed on the surfaces of the N+ source region, N+ drain region, gate region, and P+ contact region to significantly reduce contact resistance; S11. Coat photoresist, expose and develop through a mask, define the contact hole positions and etch the dielectric layer to open the contact holes reaching the N+ source, N+ drain, P+ contact area and gate; S11 specifically involves: defining the contact hole positions, etching the dielectric layer, and opening the contact holes reaching the N+ source, N+ drain, P+ contact area and gate. S12. Define the metal interconnect pattern, short-circuit the N+ source region, P+ contact region, and gate together, connect them to the cathode metal, connect the N+ drain region to the anode metal, and etch the metal layer; S12 specifically involves: depositing the first metal layer, defining the metal interconnect pattern, then short-circuiting the N+ source region, P+ contact region, and gate together, connecting them to the cathode metal, connecting the N+ drain region to the anode metal, and etching the metal layer; S13. As needed, continue to deposit dielectric layers, vias, and more metal layers, followed by the deposition of the final passivation layer, and photolithography to open the bonding pad.

[0027] Working principle: Normal state: Anode voltage < Design breakdown voltage; Parasitic NPN BJT (emitter = N+ source, base = P body, collector = deep N-well / N+ drain) is in the off state. The main current path is N+ drain → drift region → deep N-well → reverse bias PN junction between P body / N+ source (the depletion region is very wide and the resistance is very high). The device presents very high impedance (leaking current is very small) and has no effect on the circuit. Triggered state: When a surge voltage is applied to the anode, the voltage rises rapidly beyond the design breakdown voltage. The reverse bias junction (base junction) between the N+ drain / drift region (N) and the P-type body region (P) first undergoes avalanche breakdown. The avalanche breakdown generates a large number of electron-hole pairs. Electrons are swept toward the N+ drain (anode), and holes are swept toward the P-body region (base region), causing the potential of the P-body region to rise (equivalent to injecting a forward current into the base region).

[0028] Clamping status: The increased potential in the P-body region (base region) causes the PN junction (emitter junction) between the N+ source (emitter) and the P-body region (base region) to become forward biased. Once the emitter junction is forward biased sufficiently (>-0.7V), the parasitic NPN BJT quickly turns on, and a large number of electrons are injected from the N+ source (emitter), pass through the P-body region (base region), and are collected by the deep N-well / N+ drain (collector). The device enters a low-resistance conduction state (snapback), forming a low-resistance path from the anode to the cathode. The surge current is effectively bypassed to ground by this low-resistance path, while clamping the anode voltage to a relatively low sustaining voltage level, protecting the subsequent circuitry.

[0029] Recovery status: After the surge pulse ends, the anode voltage drops. When the current drops below the sustaining current, the parasitic NPN BJT turns off, and the device returns to a high-impedance state, waiting for the next surge event.

[0030] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0031] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc.

[0032] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A TVS device using LDMOS technology, characterized in that, include: A P-type silicon substrate (1) has a deep N-well (2) formed on its surface. The deep N-well (2) is used to provide isolation for the source / drain high voltage N+ region, prevent punch-through or premature breakdown between it and the P-type substrate, and serve as the collector region of the parasitic NPN BJT. A P-type body region (3) is provided in the deep N-well (2). The P-type body region (3) is provided in the deep N-well (2) by implantation. A heavily doped N+ source region is provided in the P-type body region (3). A heavily doped N+ drain region is provided on the outside of the P-type body region (3). A drift region (6) is provided in the lightly doped N-type region between the P-type body region (3) and the N+ drain region. A gate (7) is covered on the surface of the P-type body region (3) and the drift region (6). The gate (7) is located on the surface of the polysilicon layer. An anode (9) is provided on the side of the N+ drain region, and a cathode (8) is provided between the N+ source region and the gate (7). Both the anode (9) and the cathode (8) are made of metal.

2. The LDMOS process TVS device according to claim 1, characterized in that, The N+ source region serves as the emitter region of the parasitic NPN BJT and is also an electrode of the TVS. The wire of the N+ source region is grounded.

3. A TVS device using LDMOS technology according to claim 1, characterized in that, The N+ drain region serves as another electrode of the TVS to withstand surge voltage, and it is also part of the collector region of the parasitic NPN BJT.

4. A TVS device using LDMOS technology according to claim 1, characterized in that, There is a gate oxide layer below the gate (7). The gate (7) is directly connected to the source. The channel below the gate (7) is in a normally off state. The gate (7) is used to help precisely control the surface potential and depletion region shape of the P-type body region (3) and affect the trigger point of the parasitic NPN BJT. At the same time, it can help discharge a small amount of current or improve the trigger characteristics.

5. A method for manufacturing an LDMOS process TVS device, applied to the LDMOS process TVS device according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. Select a P-type silicon wafer with suitable resistivity as the starting substrate, and then perform standard RCA cleaning to remove surface contaminants and the natural oxide layer. S2. Coat with photoresist, expose and develop through a mask to define the deep N-well (2) region; S3. Coat photoresist, expose and develop through a mask to define the P-type body region (3). S4. Coat photoresist, expose and develop through a mask to define the lightly doped N-type region between the drain and the P-type body region (3), implant phosphorus (P) to form the N-drift region (6). S5. Grow / deposit oxide layer, and use photolithography to form isolation trenches (STI) or silicon oxide bumps (LOCOS) to prevent leakage between devices; S6. Fabricate the gate (7) structure; S7, sidewall formation; S8. Coat the photoresist, expose and develop it through a mask, and define the N+ source region and N+ drain region; S9. Define the P+ contact region on the P-type body region (3) immediately adjacent to the source region; S10. Metal silicides are formed on the surfaces of the N+ source region, N+ drain region, gate (7), and P+ contact region to significantly reduce contact resistance; S11. Coat photoresist, expose and develop through a mask, define the contact hole position and etch the dielectric layer to open the contact hole to reach the N+ source, N+ drain, P+ contact area and gate (7); S12. Define the metal interconnect pattern, short-circuit the N+ source region, P+ contact region, and gate (7) together, connect them to the cathode (8) metal, connect the N+ drain region to the anode (9) metal, and etch the metal layer. S13. As needed, continue to deposit dielectric layers, vias, and more metal layers, followed by the deposition of the final passivation layer, and photolithography to open the bonding pad.

6. A method for manufacturing a TVS device using LDMOS process according to claim 5, characterized in that, In the S2, high-energy phosphorus (P) or arsenic (As) ions are injected after defining the deep N-well (2) region, with an energy range of 600 keV to 1.5 MeV; Dosage: 1e12cm~2 ~ 1e13 cm~2, used to form a deep junction isolation region with low doping concentration, as the collector region of parasitic NPN, and annealed for a long time at 1100℃~1200℃, with an annealing time of 3h~5h, to advance the junction depth to 3μm~8μm, activate impurities and repair lattice damage. In S3, after defining the P-type body region (3), boron (B) is injected with medium and low energy, with an energy of 60keV~150keV. Dosage: 1e13cm~2~5e13cm~2, control lateral diffusion and perform rapid thermal annealing or furnace tube annealing to form a P-type body region (3) with a depth of 0.5μm~1.5, which serves as the base region of parasitic NPN BJT.

7. A method for manufacturing a TVS device using LDMOS process according to claim 5, characterized in that, The S6 is specifically: a 10nm to 50nm thick gate oxide is grown using dry oxygen or wet oxygen process to form an LPCVD deposited polysilicon layer with a thickness of 200nm to 400nm. Phosphorus or boron is implanted to adjust the resistivity. Then, photoresist is coated and the gate (7) shape covering the edge of the P-type body region (3) and the drift region (6) is defined by exposure and development through a mask. It is usually T-shaped or straight. The polysilicon is then etched by dry etching to form a precise gate electrode.

8. A method for manufacturing a TVS device using LDMOS process according to claim 5, characterized in that, Specifically, S7 is: S701, Deposition: LPCVD deposition of silicon nitride (SiN) or silicon dioxide (SiO2); S702, Anisotropic etching: Etching back forms a 100-300nm wide sidewall to isolate the gate (7) from the subsequent heavily doped region.

9. A method for manufacturing a TVS device using LDMOS process according to claim 5, characterized in that, S8 injects arsenic (As) after defining the N+ source region and N+ drain region, with a dose of >1e15 cm~2; Energy: 30 keV to 80 keV, forming a low-resistance ohmic contact, and rapidly annealing at 950℃~1050℃ to activate impurities and limit diffusion.

10. A method for manufacturing a TVS device using LDMOS process according to claim 5, characterized in that, S11 specifically involves: defining the contact hole location, etching the dielectric layer, and opening the contact holes to reach the N+ source, N+ drain, P+ contact area, and gate (7); S12 specifically involves: depositing the first metal layer, defining the metal interconnect pattern, then shorting the N+ source area, P+ contact area, and gate (7) together, connecting them to the cathode (8) metal, connecting the N+ drain area to the anode (9) metal, and etching the metal layer.

Images