Automatic simplification and lightweight processing system for massive three-dimensional grid models

Abstract

The invention discloses an automatic simplification and lightweight processing system for massive three-dimensional grid models, which relates to the technical field of mineral product screening and comprises a time sequence dependence index construction module, a nonlinear aggregation detection module, a memory remapping correction module, a time sequence playback adaptive control module and a phase conjugate self-correction mistake proofing module. And the time sequence dependency index construction module is used for acquiring a time sequence baseline and memory access mapping of multi-thread cache release, constructing a dynamic dependency index table according to a thread scheduling sequence, identifying a release path triggered in advance under the constraint of the dynamic dependency index table, extracting corresponding cache node information and generating a memory fragment distribution initial mapping. According to the method, accurate alignment of multi-thread memory release is achieved through the time sequence base line and the dynamic dependency index, the consistency and stability of memory management are improved, memory self-adaptive correction and error-proofing control are achieved through a closed-loop mechanism of remapping, playback and regulation, and efficient and reliable operation of the batch three-dimensional grid simplification process is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mineral screening, in particular to a massive three-dimensional grid model automatic simplification and lightweight processing system. BACKGROUND

[0002] The massive three-dimensional grid model automatic simplification and lightweight processing system is an intelligent three-dimensional data optimization platform for multi-field three-dimensional technical application scenarios. The system takes three-dimensional wireframe rendering as the core, integrates the bidirectional algorithm mechanism of polygon simplification and refinement, and can dynamically adjust the precision and data volume of the model according to different application requirements. In the simplification mode, the system performs structural compression and geometric downsampling on the model through redundant face identification, topology reconstruction and error control algorithm, thereby significantly reducing the file size and improving the transmission and loading speed; in the refinement mode, the system uses boundary preservation, normal correction and texture reconstruction technology to strengthen the local detail performance of the model, and realizes high-fidelity rendering effect. The system can be widely applied to fields such as architectural design, urban digital twin, game development and special effects production, and can efficiently deal with the performance bottleneck of massive three-dimensional data in storage, transmission and real-time rendering, providing efficient and reliable technical support for the digital upgrading and intelligent visualization development of the three-dimensional industry.

[0003] The prior art has the following disadvantages: In the batch three-dimensional grid model simplification processing process, since the system needs to perform multi-thread cache release operations in parallel, when the thread scheduling sequence appears slight timing drift under high load conditions, the release instructions of part of the intermediate cache blocks will be triggered in advance without completing the dependent cleaning, causing the memory fragments to present nonlinear aggregation in spatial distribution. Such abnormal fragment distribution will destroy the original memory continuity and pointer mapping relationship, causing the stack pointer to jump out of place, resulting in address reverse reflux of the cache management unit in subsequent access. If the abnormality is not detected in time, the system will appear data out-of-bound writing and access conflict when performing memory recycling or reallocation operations, thereby causing process-level crash and irreversible damage and task interruption of batch model data.

[0004] The above information disclosed in the background section is only used to enhance the understanding of the background of the present disclosure, and therefore it can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present application is to provide a massive three-dimensional grid model automatic simplification and lightweight processing system to solve the problems in the background art.

[0006] In order to achieve the above object, the present application provides the following technical scheme: the mass three-dimensional grid model automatic simplification and lightweight processing system, including time sequence dependent index construction module, nonlinear aggregation detection module, memory remapping correction module, time sequence playback adaptive control module and phase conjugate self-correction fault prevention module; The time sequence dependent index construction module acquires the time sequence baseline and memory access mapping of the multi-thread cache release, constructs a dynamic dependent index table according to the thread scheduling sequence, identifies the release path triggered in advance under the constraint of the dynamic dependent index table, extracts the corresponding cache node information, and generates an initial mapping of memory fragment distribution, thereby providing a benchmark reference for subsequent nonlinear detection. The nonlinear aggregation detection module constructs a nonlinear aggregation detection matrix according to the initial mapping of memory fragment distribution, performs hierarchical analysis on the cache node information, extracts the drift gradient of the stack pointer, establishes a pointer correlation path tracking model, locates the stack misplacement trigger point under the constraint of the nonlinear aggregation detection matrix, and generates a spatial anchor point for remapping operation. The memory remapping correction module generates a memory remapping sequence according to the stack misplacement trigger point and the spatial anchor point, performs bidirectional adjustment on the pointer reference path and the allocation window boundary by using a time synchronization mechanism and a phase correction mechanism, restores the heap area continuity under the constraint of the remapping sequence, and ensures the consistency of the cache release sequence and the access sequence in time sequence. The time sequence playback adaptive control module constructs a time sequence playback chain under the condition of restoring the heap area continuity, dynamically replays the entire cache release process, generates a false release judgment threshold according to the time sequence residual obtained by the replay, and realizes adaptive control of the release behavior through the false release judgment threshold, thereby forming a memory stability control field with self-healing characteristics. The phase conjugate self-correction fault prevention module constructs a phase conjugate regulation instruction set according to the memory stability control field, performs address reverse flow suppression and access path amplitude limiting calibration, realizes inter-thread synchronization correction based on residual density feedback under the constraint of the phase conjugate regulation instruction set, and thereby constructs a stack pointer fault prevention mechanism with dynamic self-correction capability, so as to ensure the continuous and stable operation of the batch three-dimensional grid model simplification process.

[0007] Preferably, the process of acquiring the time sequence baseline and memory access mapping of the multi-thread cache release includes the following steps: The time characteristics of the multi-thread cache release are captured to establish the time sequence baseline, the time start point and duration interval of the cache allocation, reference and release of each thread are recorded, the thread behavior characteristics are extracted to determine the time boundary and dependent order of the cache release, and the time sequence baseline is established. After the time sequence baseline is established, a memory access mapping is constructed according to a thread scheduling sequence, read and write behaviors of each thread to a cache unit during execution are spatially associated and mapped, and the time sequence baseline is combined with the memory access mapping to form a multi-dimensional relationship network with time continuity and spatial dependence; A dynamic dependence index table is constructed according to the memory access mapping, and an early triggered release path is identified under the constraint of the index table, the release path is cross-compared to find a potential dependence breaking point; After the early triggered release path is identified, corresponding cache node information is extracted, and an initial memory fragmentation distribution mapping is generated according to the spatial position, release time and reference level of the cache node, thereby providing a benchmark reference for nonlinear aggregation detection.

[0008] Preferably, in the step of generating the initial memory fragmentation distribution mapping, the logical position of the cache node involved in the early triggered release path in the memory space, the release time point and the access state of the adjacent cache unit are spatially reorganized and logically mapped, so that the initial memory fragmentation distribution mapping is measured by spatial continuity, thereby characterizing the structural integrity and fragmentation aggregation trend of the memory space after the cache is released.

[0009] Preferably, the process of constructing a nonlinear aggregation detection matrix and generating a spatial anchor point according to the initial memory fragmentation distribution mapping includes the following steps: According to the initial memory fragmentation distribution mapping, the cache node is analyzed in a hierarchical structure, and a hierarchical structure is established according to spatial continuity, time release order and dependence relationship, thereby providing a hierarchical basis for the construction of the nonlinear aggregation detection matrix; After obtaining the hierarchical cache node structure, a nonlinear aggregation detection matrix is constructed according to the spatial contact strength between levels, the dependence overlap degree and the release order residual, thereby reflecting the nonlinear degree and local abnormal trend of the fragmentation aggregation; According to the spatial comparison relationship of the nonlinear aggregation detection matrix, the cache node information is analyzed in layers, the drift gradient of the stack pointer is extracted, and a pointer association path tracking model is established, thereby describing the drift trajectory of the pointer in the memory space; The drift gradient change characteristics of the pointer association path tracking model are compared and analyzed by using the constraint condition of the nonlinear aggregation detection matrix, the stack misalignment trigger point is located, and a spatial anchor point for memory remapping operation is generated at the location.

[0010] Preferably, in the process of generating the spatial anchor point, the drift node recorded in the pointer association path tracking model is compared with the abnormal distribution area in the nonlinear aggregation detection matrix, and when the drift gradient discontinuously jumps in the local space, the stack misalignment trigger point is determined, and the consistency of the cache nodes in the trigger point neighborhood is verified to ensure the accuracy of the spatial anchor point positioning and the reliability of the memory remapping.

[0011] Preferably, the process of generating the memory remapping sequence and restoring the heap area continuity according to the stack misalignment trigger point and the spatial anchor point includes the following steps: According to the determined stack misalignment trigger point and the spatial anchor point, a memory remapping sequence is generated, and the physical location, time release order and association degree of the dependent path of the adjacent cache units in the heap area are sequentially arranged to establish an order framework for the heap area space adjustment; According to the remapping sequence, the time synchronization adjustment is performed on the pointer reference path, so that the cache release process and the reference path execution order are time consistent, thereby eliminating the time misalignment caused by thread scheduling drift; After completing the time synchronization adjustment, a phase correction mechanism is used to perform bidirectional adjustment on the allocation window boundary, so that the space allocation change and the time synchronization process are mutually compensated, thereby maintaining the phase consistency of the heap area space; Under the joint action of the time synchronization mechanism and the phase correction mechanism, the heap area is continuously restored according to the constraint relationship of the remapping sequence, so that the cache release sequence and the access sequence are time consistent, thereby restoring the overall continuous structure of the heap area.

[0012] Preferably, in the bidirectional adjustment of the allocation window boundary, the spatial anchor point is taken as a reference, the boundary offset direction and amplitude are determined by comparing the space occupation relationship of the cache unit before and after remapping, and the heap area space layout is compensated and adjusted under the cooperation of the time synchronization mechanism, so as to prevent local structure misalignment and avoid the generation of secondary fragmentation.

[0013] Preferably, the process of realizing adaptive control of the release behavior through the misrelease judgment threshold includes the following steps: Under the condition of restoring the heap area continuity, a time sequence playback chain is constructed, the time identifier, access dependency relationship and space corresponding information of each cache unit are integrated into a playback structure with time sequence logic, which is used to trace the whole process from cache allocation to release; Based on the time sequence playback chain, the whole process of cache release is dynamically replayed, time sequence residual data is generated according to the change track of the release and access actions, which is used to reflect the time offset characteristics of the heap area stability; The error release judgment threshold is established according to the time sequence residual data, and the residual distribution and the amplitude change are used to distinguish the normal release behavior and the abnormal release behavior, so that the quantitative identification of the release behavior is realized; The release process is adaptively constrained and corrected according to the error release judgment threshold, so that the release rhythm automatically returns to the safe interval, thereby forming an internal memory stable control field with time residual as a feedback factor, and realizing self-detection and self-healing maintenance of the heap area state.

[0014] Preferably, the error release judgment threshold is updated in real time according to the time sequence residual recorded in the time sequence playback chain, and is dynamically corrected in combination with the heap area continuity recovery state and the pointer path mapping relationship, so that the release rhythm and the access rhythm are kept synchronized under the condition of multi-thread parallel execution, thereby improving the adaptive accuracy of the internal memory stable control field and the self-healing response speed of the heap area.

[0015] Preferably, the process of realizing the inter-thread synchronous correction based on the residual density feedback under the constraint of the phase conjugate control instruction set comprises the following steps: According to the formed internal memory stable control field, a phase conjugate control instruction set is constructed, and the thread execution residual, the release time sequence offset and the spatial layout change information are integrated to establish a unified control benchmark of the space-time coupling between threads; Under the action of the phase conjugate control instruction set, address reverse flow suppression is performed, the reverse access trend is suppressed and reoriented by comparing the access path direction and the time sequence relationship, so that the one-way continuity of the heap area access is maintained; After completing the address reverse flow suppression, the access path amplitude limiting calibration is performed according to the phase conjugate control instruction set, and the thread access amplitude and boundary position are constrained, so that the heap area space reaches a dynamic balance state; Under the continuous constraint of the phase conjugate control instruction set, the inter-thread execution offset is synchronously corrected based on the residual density feedback, so that the stack pointer maintains a stable mapping relationship, thereby constructing a stack pointer fault-tolerant mechanism with dynamic self-correction ability.

[0016] In the above technical solution, the technical effects and advantages provided by the present application are as follows: By introducing the cooperative constraint mechanism of the time sequence baseline and the dynamic dependency index in the multi-thread cache release process, the present application realizes accurate alignment of the cache release and the memory access in the time dimension, thereby effectively avoiding the premature release of the cache and the abnormal aggregation of the space fragments caused by the dependency drift. By constructing the initial mapping of the memory fragment distribution and the nonlinear aggregation detection matrix, the present application can realize the pre-judgment and positioning of the potential misplacement before the release behavior occurs, significantly improve the time sequence consistency and the space continuity of the memory management, and make the heap area still maintain a stable logical structure and recoverability under high-load parallel processing, thereby fundamentally reducing the occurrence of data misplacement and memory overflow.

[0017] This invention achieves adaptive correction and continuous calibration of memory state through the dynamic linkage of memory remapping sequences, timing replay chains, and phase conjugate control instruction sets, enabling cache release behavior to possess self-healing capabilities and real-time error prevention characteristics. By forming a closed-loop feedback mechanism in the three stages of remapping, replay, and control, the synchronization rhythm between threads can be automatically adjusted according to changes in residual density, maintaining a dynamic balance between heap space and access paths. This significantly improves the operational stability and task completion rate of the batch 3D mesh simplification process, effectively preventing process-level crashes and data corruption, and ensuring the long-term reliability of the overall processing flow. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0019] Figure 1 This is a schematic diagram of the modules of the automatic simplification and lightweighting system for massive 3D mesh models of the present invention. Detailed Implementation

[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0021] This invention provides, for example Figure 1 The massive 3D mesh model automatic simplification and lightweight processing system shown includes a time-dependent index construction module, a nonlinear aggregation detection module, a memory remapping correction module, a time-series playback adaptive control module, and a phase conjugate self-correction error prevention module; The timing dependency index building module obtains the timing baseline and memory access mapping of multi-threaded cache release, builds a dynamic dependency index table based on the thread scheduling sequence, identifies early-triggered release paths under the constraints of the dynamic dependency index table, extracts the corresponding cache node information, and generates an initial mapping of memory fragmentation distribution to provide a benchmark reference for subsequent nonlinear detection. The initial mapping for memory fragmentation distribution is generated through the following steps: A baseline is captured to establish a temporal baseline for the timing characteristics of multi-threaded cache release. In practice, for the simplified processing of batch 3D mesh models, the start and duration of cache allocation, referencing, and release for each thread are synchronously recorded during the multi-threaded task startup phase. By sampling and analyzing the time span of multi-threaded execution, temporal baseline data representing thread behavior characteristics is extracted. This temporal baseline reflects the relative execution rhythm and cache release sequence structure of different threads within the same processing cycle, describing the temporal relationship between threads in terms of resource occupation and release. By establishing a temporal baseline, the time boundaries and dependency order of each thread's cache release actions can be clearly defined, providing a time-alignable reference for subsequent dependency index construction. The temporal baseline is not only used to measure the stability of thread scheduling but also to identify potential premature release trends, ensuring the accuracy of subsequent dependency analysis.

[0022] After the timing baseline is established, a memory access map is constructed based on the thread scheduling sequence. At this stage, based on the captured timing baseline information, the read and write behaviors of each thread to cache units during execution are spatially associated and mapped. By logically sorting the access order of cache units, a complete memory access map structure is formed, in which each cache unit establishes a traceable correspondence with its corresponding accessing thread, access time, and dependency state. This mapping is used to reveal the sharing, overwriting, and cross-access of memory space between threads, accurately reflecting the lifecycle connection relationship of cached data across different threads. By combining the timing baseline and the memory access map, a multi-dimensional relationship network that reflects both temporal continuity and spatial dependency can be obtained, providing a data foundation for the construction of a dynamic dependency index table. It is worth noting that this memory access map is synchronized with the timing baseline during generation, thereby avoiding record misalignment caused by time drift between different threads under high load conditions.

[0023] After obtaining the memory access mapping, a dynamic dependency index table is constructed based on the thread scheduling sequence, and premature release paths are identified under the constraints of this index table. In this stage, the timing baseline and memory access mapping are used as input references to build the dynamic dependency index table through the thread scheduling sequence. This index table, with the thread execution order as the main axis, hierarchically associates the cache dependencies between threads according to the access timing, thus forming a multi-dimensional dependency index network. Under the constraints of the index network, cache release paths that are prematurely triggered in the time dimension can be identified, that is, cache nodes that have been marked as released before the dependency relationship is completely resolved. By cross-referencing the release paths in the dependency index table, potential dependency corruption points and premature release behaviors can be discovered. This process not only reveals the micro-timeline drift in resource release between threads but also provides a crucial dependency control basis for the subsequent generation of fragmentation distribution mapping. The construction of the dynamic dependency index table enables the entire cache release process to have dynamic constraints, thereby avoiding the accumulation of structural fragmentation caused by timing imbalances between threads.

[0024] After the premature release path is identified, the corresponding cache node information is extracted, and an initial memory fragmentation distribution map is generated to provide a benchmark for subsequent nonlinearity detection. Specifically, under the constraints of the dynamic dependency index table, information is extracted from the cache nodes involved in the identified premature release path. This information includes the logical location of the cache node in memory space, the release time point, the reference level, and the access status of adjacent cache units. By spatially reorganizing and logically mapping the above information, an initial memory fragmentation distribution map is generated. This map uses spatial continuity as the core metric to characterize the structural integrity and fragmentation trend of the memory space after cache release. By analyzing the spatial intervals and temporal residuals of each cache node in the initial map, the distribution characteristics and potential focusing areas of nonlinear aggregation can be intuitively revealed. This initial memory fragmentation distribution map not only provides a benchmark for subsequent nonlinear aggregation detection but also provides a structural reference for subsequent heap continuity restoration. Through this step, a unified mapping from the time dimension to the spatial dimension is achieved, making the dependencies, temporal order, and memory structure state of the entire cache release process form a complete correspondence system, thus laying the foundation for subsequent stack misalignment detection and memory stability control.

[0025] Through the above steps, the timing baseline, memory access mapping, dynamic dependency index table, and initial mapping of memory fragmentation distribution are organically integrated in the multi-threaded cache release process. This method can accurately characterize the spatial and temporal characteristics of cache release without interfering with thread scheduling efficiency, thus providing a high-precision, low-latency reference for subsequent nonlinear aggregation detection and heap continuity reconstruction.

[0026] The nonlinear clustering detection module constructs a nonlinear clustering detection matrix based on the initial mapping of memory fragmentation distribution, performs hierarchical analysis of cache node information, extracts the drift gradient of stack pointers, establishes a pointer association path tracing model, locates the stack misalignment trigger point under the constraint of the nonlinear clustering detection matrix, and generates spatial anchor points for remapping operations. The stack misalignment trigger point is located under the constraint of the nonlinear clustering detection matrix, and spatial anchor points for remapping operations are generated. The specific steps are as follows: Based on the initial memory fragmentation distribution mapping generated in the previous stage, a hierarchical structured analysis of cache nodes is performed to establish the basic structure of the nonlinear clustering detection matrix. In practice, the cache node information contained in the initial memory fragmentation distribution mapping is first classified and organized according to spatial continuity, temporal release order, and the degree of interrelationship of dependencies. This hierarchical approach allows cache nodes located in the same memory segment region or sharing similar release dependency characteristics to be grouped into the same level, forming comparable spatial units in the analysis. Each level not only includes the spatial coordinate range and temporal attributes of the cache nodes but also records the connection relationships between adjacent levels, used to characterize cross-level dependency migration characteristics. Through this hierarchical structured processing, the fragmentation state of the memory space is transformed from a discrete distribution into a hierarchical mapping system, providing structural support for the establishment of the nonlinear clustering detection matrix. The core of this step lies in the hierarchical abstraction of the complex fragmentation distribution, enabling subsequent spatial relationship analysis to be conducted within a unified reference framework.

[0027] After obtaining the hierarchical cache node structure, a nonlinear clustering detection matrix is ​​constructed to describe the spatial coupling degree and dependency offset relationship between each level. In specific execution, the hierarchical cache node set is used as input, and an interrelated detection matrix is ​​established according to the spatial contact strength, dependency overlap, and release order residual between levels. Logically, this detection matrix can be understood as a set of spatial correlations that quantify the relationships between levels, reflecting the nonlinearity of fragment clustering and the local anomalous focusing trend. Through the establishment of the detection matrix, the coupling phenomenon between different levels is clearly presented. When a cache node at a certain level experiences a spatial clustering offset, the corresponding relationship in the matrix will show obvious asymmetry or discontinuity. The introduction of the nonlinear clustering detection matrix allows fragment clustering characteristics that were originally difficult to intuitively identify to be characterized in the form of hierarchical relationships, thus forming a dynamically updated spatial dependency monitoring structure. Through the establishment of this matrix, not only can the overall distribution of fragments be observed macroscopically, but also local regions that may cause stack drift can be identified at the microscopic level.

[0028] Based on the spatial correlation of the nonlinear clustering detection matrix, a hierarchical analysis of cache node information is performed to extract the stack pointer drift gradient and establish a pointer association path tracing model. In this step, the hierarchical coupling features reflected in the detection matrix are combined with the spatial displacement data of cache nodes. By comparing the spatial offsets between cache nodes at different levels, the drift gradient of the stack pointer in the multi-level structure is obtained. This drift gradient reflects the offset trend of the pointer reference path between different levels, revealing the continuous offset relationship of the pointer in memory space caused by fragmentation. Based on the extracted drift gradient, the drift trend is further combined with the specific cache node dependency path through association path tracing to form a complete pointer association path tracing model. This model can be used to track the migration trajectory of the stack pointer in memory space, revealing the jump relationship and mapping dependency between different stages of the pointer. By combining the drift gradient with the path tracing model, the entire process of abnormal pointer drift can be described, providing a reliable basis for the accurate location of subsequent stack misalignment trigger points.

[0029] After obtaining the pointer-associated path tracing model, the characteristics of drift gradient changes are comprehensively compared using the constraints of the nonlinear clustering detection matrix to locate the trigger point of stack misalignment and generate spatial anchor points for remapping operations. In the specific implementation, the drift nodes recorded in the pointer-associated path tracing model are compared with the abnormal distribution regions in the nonlinear clustering detection matrix. When a discontinuous jump characteristic is detected in the drift gradient of a pointer path within a local space, this location is identified as a potential stack misalignment trigger point. To ensure the accuracy of the location, the initial mapping of memory fragmentation distribution from the previous stage is combined with a neighborhood consistency analysis of the cache nodes surrounding the trigger point to verify whether this location is the actual source of heap misalignment. Once confirmed, a spatial anchor point is generated at this location to mark the physical boundary of the stack misalignment region. This spatial anchor point not only records the spatial coordinates and temporal markers of the trigger point but also serves as a reference benchmark for the subsequent memory remapping process. By establishing anchor points, it is possible to accurately lock the abnormal offset positions in the heap area, so that subsequent remapping operations can restore memory continuity with the anchor points as the center, thereby effectively eliminating the structural misalignment caused by fragmentation.

[0030] Through the above steps, based on the initial mapping of memory fragmentation distribution, the construction of a nonlinear clustering detection matrix, the extraction of stack pointer drift gradients, the establishment of a pointer path tracing model, and the generation of spatial anchor points were successfully achieved. This method enables accurate identification and location of stack misalignment triggers based on a spatial hierarchy after multi-threaded cache release, providing data support for subsequent memory remapping and timing replay.

[0031] The memory remapping correction module generates a memory remapping sequence based on the stack misalignment trigger point and space anchor point. It uses time synchronization and phase correction mechanisms to adjust the pointer reference path and allocation window boundary in both directions. Under the constraint of the remapping sequence, it restores the continuity of the heap area to ensure the consistency of the cache release sequence and the access sequence in terms of timing. A memory remapping sequence is generated based on the stack misalignment trigger point and the space anchor point. Under the constraints of the remapping sequence, the continuity of the heap area is restored. The specific steps are as follows: First, a memory remapping sequence is generated based on the identified stack misalignment trigger points and spatial anchors to establish a sequential framework for heap space adjustment. In practice, the spatial location of the stack misalignment trigger points and their corresponding spatial anchor information have been determined in the previous stage. Based on these anchors, a set of spatially extensible remapping sequences is formed by systematically organizing the physical locations, release order, and dependency paths of adjacent cache units within the heap. This remapping sequence represents the spatial mapping path of the heap memory from its current distribution state to its target continuous state, reflecting the reorganization order and reference relationships that each cache unit should follow during the adjustment process. By establishing this sequence, the restoration of the memory structure has an executable timeline and spatial direction, providing a clear constraint basis for subsequent synchronization and correction. The generation of the remapping sequence not only considers the overall spatial layout of the heap but also uses the misalignment trigger points as core references to ensure that the adjustment process maintains coordination between local areas and the overall structure.

[0032] After generating the memory remapping sequence, the pointer reference paths are time-synchronized according to this sequence, ensuring that the reference chain and spatial distribution have a unified execution rhythm. During this process, cache units in the memory remapping sequence are rearranged according to their release order, ensuring that the start and end points of each reference path remain temporally continuous. By analyzing the time difference between release and remapping for each cache node, a time synchronization adjustment window is determined. This adjustment window dynamically coordinates the call order of the pointer reference paths, ensuring that pointers execute sequentially according to the spatial order of the remapping sequence during access, avoiding cross-anchor point or out-of-bounds references. Through this time synchronization mechanism, the cache release process and the execution order of the reference paths are realigned, eliminating time misalignment caused by thread scheduling drift. This synchronization process not only ensures the logical continuity of the reference paths but also provides a stable temporal basis for subsequent spatial phase correction.

[0033] After completing the time synchronization adjustment, a phase correction mechanism is used to bidirectionally adjust the allocation window boundary, enabling a coordinated response between space allocation and time execution. In practice, the spatial anchor points in the remapping sequence are used as boundary references, and the allocation window is considered an adjustable region of the heap space. By comparing the space occupancy of each cache unit before and after remapping, the offset direction and magnitude of the boundary region are determined. The phase correction mechanism is used to coordinate the interaction between space and time, ensuring that changes in the allocation window boundary are consistent with the time synchronization adjustment process. Through this bidirectional correction, when the release order on the timeline changes, the spatial layout can be compensated in the opposite or corresponding direction, thus maintaining the phase consistency of the overall structure. The introduction of this mechanism prevents the heap from exhibiting nonlinear misalignment caused by fragmentation in space, while ensuring that the arrangement order of cache units after reallocation conforms to the temporal sequence. The bidirectional effect of the phase correction mechanism effectively avoids the secondary fragmentation problem caused by local adjustments in traditional linear memory reclamation, improving the stability and predictability of the heap space.

[0034] Finally, under the combined action of the time synchronization and phase correction mechanisms, the heap area is restored to continuity based on the constraints of the remapping sequence, ensuring the temporal consistency between the cache release sequence and the access sequence. In practice, the corrected remapping sequence is used as the execution path to sequentially restore discontinuous or misaligned cache units in the heap area, re-forming a complete and continuous structure in space. This restoration process follows the principle of anchoring first, then connecting, and finally unifying; that is, starting with a spatial anchor point, the spatial positions of surrounding cache nodes are gradually connected, ultimately restoring the entire heap area to a continuously accessible memory structure. As the restoration process progresses, the cache release sequence and the access sequence are resynchronized in time, maintaining a one-to-one correspondence in their execution logic. Thus, when multiple threads access the cache or write data again, the system can access it based on the new memory mapping relationship, thereby avoiding conflicts between the access path and the release path. Ultimately, through this continuous recovery process, the integrity of the heap space is re-established, the logical order and temporal order of the memory structure are unified, and cache release and access behaviors remain completely consistent during dynamic execution, providing a stable memory foundation for subsequent timing replay and false release detection.

[0035] Through the above steps, a memory remapping and continuity restoration method based on stack misalignment trigger points and spatial anchors was constructed. This method realizes closed-loop control of the entire process from spatial anchoring to time synchronization, then to phase correction and finally continuity restoration, enabling the spatial and temporal structures of multi-threaded cache release to be rematched, significantly improving the stability and access consistency of heap memory layout.

[0036] The timing replay adaptive control module constructs a timing replay chain under the condition of continuous recovery of the heap area, dynamically replays the entire cache release process, generates a false release judgment threshold based on the timing residual obtained from the replay, and realizes adaptive control of release behavior through the false release judgment threshold, thereby forming a memory stable control field with self-healing characteristics. Adaptive control of the release behavior is achieved by using a false release determination threshold. The specific steps are as follows: Under the condition of heap continuity recovery, a time-series replay chain is constructed to reconstruct the temporal structure and dependency order of the cache release process. In specific implementation, based on the previously recovered heap continuity state, the time identifiers, access dependencies, and space correspondence information of each cache unit during the release phase are reintegrated into a replay chain with temporal logic. This time-series replay chain establishes a temporal mapping relationship for release behavior by comparing the memory states before and after recovery, enabling the system to fully trace the entire process from cache allocation to release. Through the construction of the time-series replay chain, not only can the release order and interdependencies of each thread be recorded, but the impact of heap continuity adjustments on the release rhythm during the recovery process can also be accurately reflected. The key to this step is transforming the static heap state into a dynamically replayable time-series structure, providing accurate temporal references for subsequent behavior replay and erroneous release analysis.

[0037] Based on the constructed timing replay chain, the entire cache release process is dynamically replayed to reproduce the trajectory of memory state changes during actual execution. In practice, according to the time sequence and dependency paths in the timing replay chain, the release and access actions of cache units in each time period are simulated sequentially. Through the replay process, the coordinated release behavior between threads under high load can be dynamically recovered, revealing timing drift and release anomalies that may occur in the real execution environment. This replay process not only reproduces the release order of cache units but also synchronously tracks the dynamic changes in the heap structure, thus reflecting the impact of release behavior on memory continuity and space balance. During the dynamic replay, the system can gradually accumulate the timing offset and access latency at each moment, forming a set of timing residual data for evaluating heap stability. This process allows the heap to be logically re-verified, ensuring that the spatial structure after continuity recovery remains coherent and correct in the time dimension. Through dynamic replay, minute release deviations caused by thread scheduling changes or dependency chain delays can be accurately identified, providing a reliable data foundation for subsequent erroneous release judgments.

[0038] A threshold for determining false releases is generated based on the timing residuals obtained from dynamic replay, enabling quantitative identification and dynamic evaluation of cache release behavior. In this stage, the timing residual data recorded during the replay process is comprehensively analyzed, and the threshold for determining false releases is established based on the temporal distribution and amplitude changes of the residuals. This threshold characterizes the boundary conditions between normal and abnormal release behaviors. When the timing residual corresponding to the release behavior of a thread or cache unit exceeds this threshold, it can be determined that the release action has a potential risk of premature triggering or dependency corruption. By setting this threshold, the system can have adaptive judgment capabilities in subsequent execution, automatically distinguishing between normal release delays and abnormal timing drifts. The generation process of this threshold simultaneously considers the continuous recovery state of the heap area, the stability of pointer association paths, and the access frequency of cache units, thereby ensuring the dynamic adaptability and universal applicability of the judgment standard. Through this step, a dynamic feedback mechanism of timing residuals is introduced on the basis of traditional static verification, giving the judgment of memory release behavior real-time and intelligent characteristics.

[0039] Adaptive control of cache release behavior is achieved by using a threshold for determining erroneous releases, thereby forming a stable memory control field with self-healing characteristics. In this implementation step, the aforementioned threshold is used as a dynamic adjustment basis to constrain and correct the behavior during cache release in real time. When the timing residual of a release action exceeds the threshold, the system automatically adjusts the release rhythm based on the current continuity state of the heap and the pointer path mapping relationship, bringing it back to a safe range within the threshold. Through this adaptive adjustment process, cache release behavior can achieve self-detection, self-correction, and self-recovery during execution, effectively avoiding instability or collapse of the heap structure due to continuous erroneous releases. As adaptive control continues, a stable control field is further formed, based on the heap space as the physical foundation and using the timing residual as the feedback factor. This control field can continuously monitor changes in the heap state under multi-threaded parallel execution conditions, automatically balancing the dynamic differences between the release rhythm and the access rhythm, enabling the system to maintain a stable memory structure and high resource utilization during long-term operation. With the establishment of this self-healing mechanism, the stability of the stack area no longer depends on external intervention, but achieves self-maintenance through internal feedback, thereby significantly improving the reliability and continuity of the batch simplification process of the three-dimensional mesh model.

[0040] Through the above steps, a time-series replay and adaptive control mechanism under the condition of continuous heap recovery was constructed. This mechanism realizes a closed loop of the entire process from time replay and residual extraction to dynamic judgment and self-healing control, enabling high-precision reproduction and real-time correction of the cache release process in both time and space dimensions. Using this method, the system can proactively identify potential release anomalies and repair them in real time under high-load parallel processing environments, thereby preventing data corruption and process crashes, and achieving highly reliable and stable memory operation.

[0041] The phase conjugate self-correction error prevention module constructs a phase conjugate control instruction set based on the memory stability control field, executes address reverse flow suppression and access path limiting calibration, and realizes inter-thread synchronization correction based on residual density feedback under the constraints of the phase conjugate control instruction set, thereby constructing a stack pointer error prevention mechanism with dynamic self-correction capability to ensure the continuous and stable operation of the batch 3D mesh model simplification process. Under the constraints of the phase conjugate modulation instruction set, inter-thread synchronization correction is achieved based on residual density feedback. The specific steps are as follows: A phase conjugate control instruction set is constructed based on the established memory stability control field to establish a unified control benchmark for inter-thread spatiotemporal coupling. In implementation, the memory stability control field established in the previous stage is used as the input foundation. This control field contains dynamic feedback information such as thread execution residuals, release timing offsets, and spatial layout changes. By integrating and summarizing this information, a phase conjugate control instruction set is constructed at the logical level. This instruction set, with the concept of conjugate as its core, emphasizes the mutual mapping and reciprocal correction relationship between time series and spatial structure, enabling threads to achieve synchronization compensation in opposite phases during execution. The establishment of the phase conjugate control instruction set ensures that the execution behavior of each thread is dynamically coupled with its adjacent threads in time and space, thereby ensuring the system's self-balancing capability during overall operation. Through the construction of this instruction set, the memory stability control field transforms from a passive state to an active control state, providing a unified behavioral constraint basis for subsequent access path calibration and synchronization correction.

[0042] Under the control of the phase conjugate control instruction set, address reversal suppression is implemented to prevent erroneous access to the stack pointer due to address mapping reversal. In practice, the phase conjugate control instruction set is applied to the monitoring and constraint of memory access paths. When a thread performs cache access or release operations, the system compares and analyzes the address mapping relationship in real time. If a reversal trend is detected in an access path, i.e., the access direction is inconsistent with the time sequence, the reversal constraint mechanism in the phase conjugate control instruction set is immediately triggered to suppress and redirect the access behavior. This suppression process is not a simple interruption, but rather, under the action of a memory stability control field, the access path is brought back to normal timing by synchronously correcting the space access direction and time rhythm. This effectively prevents the stack pointer from reversing or overlapping during multi-threaded parallel access, thus preventing abnormal phenomena such as out-of-bounds writes, pointer misalignment, and stack structure corruption. The implementation of address reversal suppression maintains unidirectional continuity in heap space access, creating a stable structural environment for fine calibration of subsequent access paths.

[0043] After address reversal suppression is completed, access path limiting calibration is performed based on the phase conjugate control instruction set to further stabilize the access boundaries between threads and the effective range of heap pointers. In this stage, the access path of each thread is compared and analyzed with the residual density recorded in the memory stability control field to determine the access amplitude and boundary position of each thread in the heap space. When a thread's access behavior is detected to exceed the normal amplitude range or to encroach on the access space of adjacent threads, the limiting calibration mechanism is immediately triggered to compress the amplitude and perform space reversal on the thread's access path. This calibration process uses the phase conjugate control instruction set as a constraint, making the calibration direction complementary to the previous reversal suppression behavior, thereby maintaining the symmetry and balance of space access overall. Through this limiting calibration method, the access boundaries of each thread in the heap can be precisely constrained without affecting thread execution efficiency, preventing stack spread and memory imbalance caused by excessive access. The execution of this step enables the heap space to achieve a dynamic equilibrium state in structure, and the access paths remain coordinated and consistent in both time and space dimensions.

[0044] Under the continuous constraints of the phase conjugate control instruction set, a stack pointer error prevention mechanism with dynamic self-correction capability is constructed by implementing inter-thread synchronization correction based on residual density feedback. In this implementation step, the residual density generated in real-time in the memory stability control field is used as a dynamic feedback signal to continuously monitor the offset of each thread during execution. When the residual density exhibits concentrated or abrupt characteristics in a certain region, the system performs synchronization correction on the corresponding thread according to the phase inversion principle of the phase conjugate control instruction set, causing its execution rhythm, access latency, and spatial positioning to return to a unified control benchmark. Through this residual feedback-based synchronization correction mechanism, execution differences between threads can be canceled out in real time, and the stack pointer maintains a relatively stable mapping relationship globally, thus forming an adaptive error prevention system. During continuous operation, this error prevention mechanism can automatically identify abnormal characteristics such as pointer offset, access drift, and release latency, and achieve immediate repair through phase conjugate control, enabling the system to maintain dual consistency of heap space and temporal logic without external intervention. Ultimately, with the continuous action of this error prevention mechanism, the entire batch simplification process of the 3D mesh model can run stably under high concurrency conditions, avoiding task interruptions and data corruption caused by memory drift or access misalignment, and significantly improving the reliability and operating efficiency of the system.

[0045] Through the above steps, a complete closed-loop control process is achieved, from memory stability control field to phase conjugate modulation, and then to access path limiting and thread synchronization correction. This method transforms heap space management from passive monitoring to active self-correction, ensuring logical consistency and spatial stability of memory access in complex multi-threaded environments. By constructing a phase conjugate modulation instruction set and introducing a residual density feedback mechanism, dynamic adaptive error prevention control of the stack pointer is effectively realized, providing technical support for the high-reliability operation of batch simplified processing of 3D mesh models.

[0046] This invention introduces a collaborative constraint mechanism of timing baseline and dynamic dependency index during multi-threaded cache release, enabling precise alignment between cache release and memory access in the time dimension. This effectively avoids premature cache release and abnormal aggregation of space fragmentation caused by dependency drift. By constructing an initial mapping of memory fragmentation distribution and a nonlinear aggregation detection matrix, potential misalignment points can be predicted and located before the release behavior occurs, significantly improving the timing consistency and spatial continuity of memory management. This allows the heap area to maintain a stable logical structure and recoverability even under high-load parallel processing, fundamentally reducing data misalignment and memory overflow.

[0047] This invention achieves adaptive correction and continuous calibration of memory state through the dynamic linkage of memory remapping sequences, timing replay chains, and phase conjugate control instruction sets, enabling cache release behavior to possess self-healing capabilities and real-time error prevention characteristics. By forming a closed-loop feedback mechanism in the three stages of remapping, replay, and control, the synchronization rhythm between threads can be automatically adjusted according to changes in residual density, maintaining a dynamic balance between heap space and access paths. This significantly improves the operational stability and task completion rate of the batch 3D mesh simplification process, effectively preventing process-level crashes and data corruption, and ensuring the long-term reliability of the overall processing flow.

[0048] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A system for automatically simplifying and lightweighting massive 3D mesh models, characterized in that: It includes a time-dependent index building module, a non-linear aggregation detection module, a memory remapping correction module, a time-series playback adaptive control module, and a phase conjugate self-correction error prevention module; The timing-dependent index building module obtains the timing baseline and memory access mapping of multi-threaded cache release, builds a dynamic dependency index table based on the thread scheduling sequence, identifies early-triggered release paths under the constraints of the dynamic dependency index table, extracts the corresponding cache node information, and generates an initial mapping of memory fragmentation distribution. The nonlinear clustering detection module constructs a nonlinear clustering detection matrix based on the initial mapping of memory fragmentation distribution, performs hierarchical analysis of cache node information, extracts the drift gradient of stack pointers, establishes a pointer association path tracing model, locates the stack misalignment trigger point under the constraint of the nonlinear clustering detection matrix, and generates spatial anchor points for remapping operations. The memory remapping correction module generates a memory remapping sequence based on the stack misalignment trigger point and the space anchor point. It uses time synchronization and phase correction mechanisms to adjust the pointer reference path and allocation window boundary in both directions, and restores the continuity of the heap area under the constraint of the remapping sequence. The timing replay adaptive control module constructs a timing replay chain under the condition of continuous recovery of the heap area, dynamically replays the entire cache release process, generates a false release judgment threshold based on the timing residual obtained from the replay, and realizes adaptive control of release behavior through the false release judgment threshold, forming a memory stable control field with self-healing characteristics. The phase conjugate self-correction error prevention module constructs a phase conjugate control instruction set based on the memory stability control field, performs address reverse flow suppression and access path limiting calibration, and realizes inter-thread synchronization correction based on residual density feedback under the constraints of the phase conjugate control instruction set, thus constructing a stack pointer error prevention mechanism with dynamic self-correction capabilities.

2. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 1, characterized in that, The process of obtaining the timing baseline of multi-threaded cache release and memory access mapping includes the following steps: Baseline capture of the time characteristics of multi-threaded cache release is performed to establish a time-series baseline. By recording the start point and duration of cache allocation, reference and release for each thread, thread behavior characteristics are extracted to clarify the time boundaries and dependency order of cache release. After the timing baseline is established, a memory access map is constructed based on the thread scheduling sequence. The read and write behavior of each thread to the cache unit during execution is spatially associated and mapped, so that the timing baseline and the memory access map are combined to form a multi-dimensional relationship network that is both temporally continuous and spatially dependent. A dynamic dependency index table is constructed based on the memory access mapping, and premature release paths are identified under the constraints of the index table. The release paths are cross-compared to find potential dependency violation points. After identifying the prematurely triggered release path, the corresponding cache node information is extracted, and an initial mapping of memory fragment distribution is generated based on the spatial location, release time, and reference level of the cache node.

3. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 2, characterized in that, In the step of generating the initial mapping of memory fragmentation distribution, the logical location, release time point and access status of the cache nodes involved in the early trigger release path in memory space are reorganized and logically mapped, so that the initial mapping of memory fragmentation distribution is based on spatial continuity.

4. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 1, characterized in that, The process of constructing a nonlinear clustering detection matrix and generating spatial anchor points based on the initial mapping of memory fragmentation distribution includes the following steps: Based on the initial mapping of memory fragmentation distribution, a hierarchical structure analysis of cache nodes is performed, and a hierarchical structure is established according to spatial continuity, time release order and the degree of dependency. After obtaining the hierarchical cache node structure, a nonlinear clustering detection matrix is ​​constructed based on the spatial contact strength between levels, dependency overlap, and release order residuals. Based on the spatial correlation of the nonlinear clustering detection matrix, the cache node information is analyzed hierarchically, the drift gradient of the stack pointer is extracted, and a pointer association path tracing model is established. By utilizing the constraints of the nonlinear clustering detection matrix, the drift gradient change characteristics of the pointer-associated path tracing model are comprehensively compared to locate the stack misalignment trigger point, and a spatial anchor point for memory remapping operation is generated at that location.

5. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 4, characterized in that, During the generation of spatial anchor points, the drift nodes recorded in the pointer-associated path tracing model are compared with the abnormal distribution areas in the nonlinear aggregation detection matrix. When the drift gradient exhibits discontinuous jumps in the local space, it is determined as a stack misalignment trigger point. The consistency of the cache nodes in the neighborhood of the trigger point is verified in conjunction with the initial mapping of memory fragmentation distribution.

6. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 1, characterized in that, The process of generating a memory remapping sequence and restoring heap continuity based on stack misalignment trigger points and spatial anchor points includes the following steps: Based on the determined stack misalignment trigger points and spatial anchors, a memory remapping sequence is generated. By orderly organizing the physical location, time release order, and dependency path correlation of adjacent cache units in the heap area, a sequential framework for heap area space adjustment is established. The pointer reference path is adjusted for time synchronization based on the remapping sequence to ensure that the cache release process is consistent with the execution order of the reference path, thus eliminating the time misalignment caused by thread scheduling drift. After completing the time synchronization adjustment, the phase correction mechanism is used to adjust the allocation window boundary in both directions, so that the spatial allocation change and the time synchronization process compensate each other and maintain the phase consistency of the reactor space. With the combined action of time synchronization and phase correction mechanisms, the heap area is restored to continuity based on the constraints of the remapping sequence, ensuring that the cache release sequence and access sequence are consistent in time, thus restoring the overall continuous structure of the heap area.

7. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 6, characterized in that, When the phase correction mechanism makes bidirectional adjustments to the allocation window boundary, it uses the spatial anchor point as a reference, determines the boundary offset direction and magnitude by comparing the spatial occupancy relationship of the cache unit before and after remapping, and makes compensation adjustments to the heap space layout in conjunction with the time synchronization mechanism.

8. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 1, characterized in that, The process of achieving adaptive control of release behavior by using a false release determination threshold includes the following steps: Under the condition of continuous recovery of the heap area, a time-series replay chain is constructed, which integrates the time identifier, access dependency relationship and space correspondence information of each cache unit into a replay structure with time-series logic, so as to trace the entire process from cache allocation to release. Based on the timing replay chain, the entire cache release process is dynamically replayed, and timing residual data is generated according to the change trajectory of release and access actions to reflect the time offset characteristics of heap stability. A threshold for determining false release is established based on time-series residual data. Normal release behavior and abnormal release behavior are distinguished based on the distribution and amplitude changes of residuals, thereby achieving quantitative identification of release behavior. Based on the threshold for determining erroneous releases, the release process is adaptively constrained and corrected, so that the release rhythm automatically returns to the safe range, forming a memory stability control field with time residuals as feedback factors, and realizing the self-detection and self-healing maintenance of the heap state.

9. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 8, characterized in that, The threshold for determining erroneous releases is updated in real time based on the timing residuals recorded in the timing replay chain, and dynamically corrected by combining the heap continuity recovery status and the pointer path mapping relationship, so as to keep the release rhythm and access rhythm synchronized under the condition of multi-threaded parallel execution.

10. The automatic simplification and lightweighting system for massive 3D mesh models according to claim 8, characterized in that, The process of achieving inter-thread synchronization correction based on residual density feedback under the constraint of phase conjugate modulation instruction set includes the following steps: Based on the established memory stability control field, a phase conjugate control instruction set is constructed to integrate information on thread execution residuals, release timing offsets, and spatial layout changes, so as to establish a unified control benchmark for inter-thread spatiotemporal coupling. Under the action of the phase conjugate control instruction set, reverse address backflow suppression is performed. By comparing the relationship between the access path direction and the time series, the reverse access trend is suppressed and redirected to maintain the unidirectional continuity of heap area access. After address reverse flow suppression is completed, access path limiting calibration is performed according to the phase conjugate control instruction set to constrain the thread access amplitude and boundary position, so that the heap space reaches a dynamic balance state. Under the continuous constraint of the phase conjugate control instruction set, the execution offset between threads is synchronously corrected based on residual density feedback, so that the stack pointer maintains a stable mapping relationship and a stack pointer error prevention mechanism with dynamic self-correction capability is constructed.

Images