Apparatus comprising bidirectional data transceiver and method of operation thereof

Abstract

A device for transmitting first data to an external device and receiving second data from the external device is provided. The apparatus includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; the current source circuit is connected to the second node and comprises a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit based on first data; a receiver connected to the second node and configured to obtain second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0068022, filed with the Korean Intellectual Property Office on May 24, 2024, and Korean Patent Application No. 10-2024-0099707, filed with the Korean Intellectual Property Office on July 26, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to devices including bidirectional data transceivers and methods of operating thereof. Background Technology

[0004] When a device is configured to transmit and receive signals bidirectionally with another device using Synchronous Two-Way Signaling (SBD), the outgoing signal (i.e., the signal being transmitted) is superimposed on the incoming signal (i.e., the signal being received) on the transmission line connecting the two devices. In this case, at the receiving end, it is necessary to remove the outgoing signal from the superimposed signal in order to correctly receive the signal provided by the other party.

[0005] There is a need to design a chip that can remove outgoing signals from superimposed signals, while improving the pin efficiency and data rate of the semiconductor chip and reducing the chip's power consumption. Summary of the Invention

[0006] One or more embodiments provide a method that can remove outgoing signals from superimposed signals, improve pin efficiency and data rate of semiconductor chips, and reduce power consumption of semiconductor chips.

[0007] This invention is not limited to solving the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of the embodiments, a device configured to send first data to an external device and receive second data from the external device includes: a voltage-mode driver electrically connected to a first node, the voltage-mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors and the pull-down resistor circuit including a plurality of pull-down resistors; a current source circuit electrically connected to a second node and including a first current source and a second current source; a pre-driver configured to control the voltage-mode driver and the current source circuit based on the first data; a receiver electrically connected to the second node and configured to obtain the second data based on the voltage level of the second node; and a hybrid resistor electrically connected between the first node and the second node.

[0009] According to another aspect of an embodiment, a method of a device for controlling transmission of first data to an external device and reception of second data from the external device includes calibrating a voltage-mode driver using a calibration circuit; calibrating a current source circuit using the calibration circuit; adjusting a resistance value of a pull-up resistor circuit of the voltage-mode driver based on the first data; adjusting a resistance value of a pull-down resistor circuit of the voltage-mode driver based on the first data; adjusting a current value of the current source circuit based on the first data; and obtaining the second data based on a voltage level applied to a receiver.

[0010] According to another aspect of an embodiment, a device configured to transmit first data to an external device and receive second data from the external device includes a voltage-mode driver electrically connected to a first node, the voltage-mode driver including a pull-up resistor circuit including a plurality of pull-up resistors and a pull-down resistor circuit including a plurality of pull-down resistors; a current source electrically connected between a power supply voltage and a second node; a pre-driver configured to control the voltage-mode driver and the current source based on the first data; a receiver electrically connected to the second node and configured to obtain the second data based on a voltage level of the second node; and a hybrid resistor electrically connected between the first node and the second node. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects and features will become more apparent from the following description of embodiments, when taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating an integrated circuit according to an embodiment;

[0013] Figure 2 is a block diagram illustrating an integrated circuit according to an embodiment;

[0014] Figure 3 is a circuit diagram illustrating a transceiver according to an embodiment;

[0015] Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D is a circuit diagram illustrating a transceiver according to an embodiment;

[0016] Figure 5 is a circuit diagram illustrating a calibration circuit according to an embodiment;

[0017] Figure 6 is a circuit diagram illustrating a calibration circuit according to an embodiment;

[0018] Figure 7 is a circuit diagram illustrating a calibration circuit according to an embodiment;

[0019] Figure 8A 、 Figure 8B ,Figure 8C and Figure 8D This shows a circuit diagram of a transceiver according to an embodiment;

[0020] Figure 9 This is a flowchart illustrating the operation method of the device according to an embodiment;

[0021] Figure 10 This is a flowchart illustrating the operation method of the device according to an embodiment;

[0022] Figure 11 This is a flowchart illustrating the operation method of the device according to an embodiment; and

[0023] Figure 12 This is a block diagram illustrating a system including a storage device, including the device according to an embodiment. Detailed Implementation

[0024] In the following description, embodiments are illustrated with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding components are labeled with the same reference numerals, and descriptions already given are omitted. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, directly connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of other examples or other embodiments also provided herein or not provided herein but consistent with this disclosure.

[0025] Figure 1 This is a block diagram illustrating an integrated circuit according to an embodiment.

[0026] Reference Figure 1 The integrated circuit 10 may include a first device 100, a second device 200, a first external resistor RE1, and a second external resistor RE2.

[0027] The first device 100 and the second device 200 can transmit signals through a transmission line TL. The first device 100 can send first data D1 to the second device 200 through the transmission line TL. The second device 200 can send second data D2 to the first device 100 through the transmission line TL. The transmission line TL can be referred to as a channel. The first device 100 and the second device 200 can transmit data simultaneously (i.e., data can be transmitted simultaneously in different directions), and in this case, the signal corresponding to the first data D1 on the transmission line TL can be superimposed on the signal corresponding to the second data D2.

[0028] In the embodiments, the first device 100 and the second device 200 can be various types of storage devices, such as dynamic random access memory (DRAM) or flash memory, or they can be controllers that control various types of storage devices.

[0029] The first device 100 may include a transceiver 110 and a calibration circuit 120. The transceiver 110 can be connected to the transmission line TL via the first DQ pin DQ_P. The calibration circuit 120 can be connected to a first external resistor RE1 via the first ZQ pin ZQ_P.

[0030] Transceiver 110 can send first data D1 from first device 100 to second device 200, and can also receive second data D2 from second device 200. See below for further details. Figure 2 Provide a detailed description of the configuration of transceiver 110.

[0031] The calibration circuit 120 can be a circuit that calibrates errors in the configuration of the transceiver 110 (e.g., resistance value errors of resistors caused by process, voltage, and temperature (PVT) variations, etc.). The calibration circuit 120 can perform a calibration operation on the transceiver 110 via a first driver calibration signal VD_CAL1 and a first current source calibration signal CS_CAL1. The calibration circuit 120 can be referred to as the ZQ calibration circuit. See below for reference. Figure 5 The configuration of calibration circuit 120 is described in detail.

[0032] To distinguish between the calibration signals of the first calibration circuit 120 and the second calibration circuit 220, the calibration signals of the first calibration circuit 120 can be referred to as the first driver calibration signal VD_CAL1 and the first current source calibration signal CS_CAL1, respectively. The calibration signals of the second calibration circuit 220 can be referred to as the second driver calibration signal VD_CAL2 and the second current source calibration signal CS_CAL2, respectively.

[0033] The second device 200 may have a configuration similar to that of the first device 100. The second device 200 may include a transceiver 210 and a calibration circuit 220. The transceiver 210 can be connected to the transmission line TL via the second DQ pin DQ_P'. The calibration circuit 220 can be connected to a second external resistor RE2 via the second ZQ pin ZQ_P'.

[0034] The calibration circuit 220 can perform a calibration operation on the transceiver 210 via the second driver calibration signal VD_CAL2 and the second current source calibration signal CS_CAL2. Furthermore, the description already given in the configuration of the first device 100 is omitted in the remaining description of the configuration of the second device.

[0035] The first external resistor RE1 and the second external resistor RE2 can be used as reference resistors, and the calibration circuits 120 and 220 can use the first external resistor RE1 and the second external resistor RE2 as references to perform calibration operations.

[0036] Figure 2 This is a block diagram illustrating an integrated circuit 10 according to an embodiment. Figure 2 It could be shown in more detail. Figure 1 A block diagram of integrated circuit 10. (Refer to...) Figure 1 To describe Figure 2 And the description already given can be omitted.

[0037] Reference Figure 2 The integrated circuit 10 may include a first device 100, a second device 200, a first external resistor RE1, and a second external resistor RE2. Figure 2 The first device 100 may have a similar configuration to the second device 200. The following description focuses on the first device 100, and descriptions already given may be omitted.

[0038] The first device 100 may include a transceiver 110 and a calibration circuit 120. The transceiver 110 may include a pre-driver (i.e., pre-drive circuitry) 111, a voltage-mode driver (i.e., voltage-mode drive circuitry) 112, a current source circuitry 113, a receiver (i.e., receiver circuitry) 114, and a first hybrid resistor RH1. The configuration including the first hybrid resistor RH1 and the current source circuitry 113 may be referred to as a subtractor SUB1. Furthermore, in some embodiments, the subtractor may also be referred to as a hybrid circuit.

[0039] The pre-driver 111 can control the voltage-mode driver 112 and the current source circuit 113 based on the value corresponding to the first data D1. Based on the first device 100, the first data D1 can correspond to an outgoing signal, which is the signal that the first device 100 wants to send to the second device 200. Similarly, based on the first device 100, the second data D2 can correspond to an incoming signal.

[0040] The voltage-mode driver 112 can be electrically connected to the first node N1. The voltage-mode driver 112 may include multiple resistors and multiple switches.

[0041] In an embodiment, based on the first data D1, the pre-driver 111 can control the voltage mode driver 112 by controlling each switch included in the voltage mode driver 112 to be in a closed or open state.

[0042] The current source circuit 113 can be electrically connected to the second node N2. The current source circuit 113 may include at least one current source.

[0043] In an embodiment, the pre-driver 111 may adjust the value of the current output by each current source included in the current source circuit 113 based on the first data D1, or disconnect the electrical connection with the second node N2 by turning on (i.e. turning off) each current source.

[0044] One end of the first hybrid resistor RH1 can be electrically connected to the first node N1, and the other end of the first hybrid resistor RH1 can be electrically connected to the second node N2.

[0045] In an embodiment, during the production of the first device 100, the resistance value indicated by the first hybrid resistor RH1 may be incorrect due to PVT variations. For example, the designed resistance value of the first hybrid resistor RH1 is 75Ω, but due to PVT variations, the resistance value of the first hybrid resistor RH1 may be 60Ω. In this case, the first device 100 can compensate for the effect of the resistance value error of the first hybrid resistor RH1 (the phenomenon that the voltage level of the second node N2 does not appear as expected during design) by performing a current calibration operation. This current calibration operation calibrates the amplitude of the current output by the current source circuit 113 through a calibration circuit. In this respect, the voltage level difference of the second node N2 caused by the resistance value error of the first hybrid resistor RH1 can be calibrated. The following will refer to... Figure 7 Describe the current calibration procedure in detail.

[0046] Receiver 114 can be electrically connected to the second node N2. Receiver 114 can obtain the second data D2 by decoding the voltage level of the second node N2 into second data D2. In an embodiment, the first device 100 and the second device 200 can transmit and receive signals based on a Pulse Amplitude Modulation Level 4 (PAM-4) method. In this case, receiver 114 can decode the received input voltage level (i.e., the voltage level of the second node N2) into one of a first value 2'b00, a second value 2'b01, a third value 2'b10, and a fourth value 2'b11.

[0047] In this embodiment, the first device 100 and the second device 200 may transmit data based on multi-level signal modulation techniques. For example, data transmission between the first device 100 and the second device 200 may be achieved by modulating the signal using the PAM-4 method. However, this is an example and is not intended to limit the inventive concept. For example, data transmission between the first device 100 and the second device 200 may be achieved using non-return-to-zero (NRZ), PAM-2, and PAM-8.

[0048] The calibration circuit 120 can generate a driver calibration signal VD_CAL and a current source calibration signal CS_CAL. The calibration circuit 120 can calibrate the resistance value of the resistors included in the voltage-mode driver 112 using the driver calibration signal VD_CAL. The calibration circuit 120 can adjust the reference current value of the current source circuit 113 using the current source calibration signal CS_CAL to calibrate the voltage level difference at the second node N2 caused by the resistance value error of the first hybrid resistor RH1.

[0049] The second device 200 may include a transceiver 210 and a calibration circuit 220. The transceiver 210 may include a pre-driver 211, a voltage-mode driver 212, a current source circuit 213, a receiver 214, and a second hybrid resistor RH2. The configuration including the second hybrid resistor RH2 and the current source circuit 213 may be referred to as a subtractor SUB2.

[0050] Based on the second device 200, the second data D2 can correspond to an outbound signal, which is the signal that the second device 200 wants to send to the first device 100. Similarly, based on the second device 200, the first data D1 can correspond to an inbound signal.

[0051] One end of the second hybrid resistor RH2 can be electrically connected to the first node N1', and the other end of the second hybrid resistor RH2 can be electrically connected to the second node N2'.

[0052] Since the description of the corresponding configuration of the first device 100 can be applied equally to the remaining configurations of the second device 200, the description already given is omitted.

[0053] According to an embodiment, signal transmission between the first device 100 and the second device 200 can be implemented in a single-ended manner instead of a differential manner. Furthermore, since the voltage-mode driver 112 operates in voltage mode (i.e., the voltage-mode driver 112 does not include a current source), power consumption can be reduced compared to a driver operating in current mode. Additionally, since the first device 100 and the second device 200 transmit and receive signals in a synchronous bidirectional (SBD) manner, the data rate can be increased.

[0054] Figure 3 This shows a circuit diagram of a transceiver according to an embodiment. (Refer to...) Figure 1 and Figure 2 To describe Figure 3 And the description already given can be omitted.

[0055] Reference Figure 3 Transceiver 110 and transceiver 210 can transmit data via transmission line TL. Transceiver 110 can send first data D1 to transceiver 210. Transceiver 210 can send second data D2 to transceiver 110.

[0056] Transceiver 110 may include a pre-driver 111, a voltage-mode driver 112, a current source circuit 113, a receiver 114, and a first hybrid resistor RH1.

[0057] The voltage-mode driver 112 may include a pull-up resistor circuit 112_1 and a pull-down resistor circuit 112_2. The pull-up resistor circuit 112_1 may include multiple pull-up resistors RU11, RU12, and RU13 and multiple pull-up switches SU11, SU12, and SU13. The pull-down resistor circuit 112_2 may include multiple pull-down resistors RD11, RD12, and RD13 and multiple pull-down switches SD11, SD12, and SD13. One end of the pull-up resistor circuit 112_1 may be supplied with a power supply voltage VDD. The other end of the pull-up resistor circuit 112_1 may be electrically connected to a first node N1. One end of the pull-down resistor circuit 112_2 may be electrically connected to the first node N1. The other end of the pull-down resistor circuit 112_2 may be electrically connected to ground.

[0058] The resistors included in the pull-up resistor circuit 112_1 can be called pull-up resistors, and the resistors included in the pull-down resistor circuit 112_2 can be called pull-down resistors.

[0059] In an embodiment, the pre-driver 111 can control the voltage mode driver 112 by controlling the states of the pull-up switches SU11, SU12 and SU13 and the pull-down switches SD11, SD12 and SD13 to be open or closed based on the data to be sent to the transceiver 210, namely the first data D1.

[0060] For ease of explanation, the pull-up switches SU11, SU12 and SU13 and the pull-down switches SD11, SD12 and SD13 may be omitted from the accompanying drawings in this specification.

[0061] The pre-driver 111 controlling the switch to the open state can be described as turning off the resistor corresponding to the switch controlled to the open state. Similarly, the pre-driver 111 controlling the switch to the closed state can be described as turning on the resistor corresponding to the switch controlled to the closed state.

[0062] In an embodiment, Figure 3 The pull-up resistor circuit 112_1 and pull-down resistor circuit 112_2 are shown as including three switches and three resistors respectively, but this is exemplary and can obviously include more switches and resistors.

[0063] The current source circuit 113 may include a first current source CS11 and a second current source CS12. A power supply voltage VDD may be applied to one end of the first current source CS11, and the other end of the first current source CS11 may be electrically connected to the second node N2. One end of the second current source CS12 may be electrically connected to the second node N2, and the other end of the second current source CS12 may be electrically connected to ground.

[0064] In an embodiment, the pre-driver 111 can control the first current source CS1 and the second current source CS2 of the current source circuit 113 based on the data to be sent to the transceiver 210, namely the first data D1. For example, the pre-driver 111 can control the current values ​​output from the first current source CS1 and the second current source CS2. Furthermore, for example, the pre-driver 111 can disconnect the first current source CS1 and the second current source CS2 from the second node N2.

[0065] Transceiver 210 may include a pre-driver 211, a voltage-mode driver 212, a current source circuit 213, a receiver 214, and a second hybrid resistor RH2.

[0066] The voltage-mode driver 212 may include a pull-up resistor circuit 212_1 and a pull-down resistor circuit 212_2. The pull-up resistor circuit 212_1 may include multiple pull-up resistors RU21, RU22, and RU23 and multiple pull-up switches SU21, SU22, and SU23. The pull-down resistor circuit 212_2 may include multiple pull-down resistors RD21, RD22, and RD23 and multiple pull-down switches SD21, SD22, and SD23. One end of the pull-up resistor circuit 212_1 may be supplied with a power supply voltage VDD. The other end of the pull-up resistor circuit 212_1 may be electrically connected to a first node N1'. One end of the pull-down resistor circuit 212_2 may be electrically connected to the first node N1'. The other end of the pull-down resistor circuit 212_2 may be electrically connected to ground.

[0067] In an embodiment, the pre-driver 211 can control the voltage-mode driver 212 by changing the state of the pull-up switches SU21, SU22 and SU23 and the pull-down switches S211, SD22 and SD23 to an open or closed state based on the data to be sent to the transceiver 110, namely the second data D2.

[0068] The current source circuit 213 may include a first current source CS21 and a second current source CS22. A power supply voltage VDD may be applied to one end of the first current source CS21, and the other end of the first current source CS21 may be electrically connected to the second node N2'. One end of the second current source CS22 may be electrically connected to the second node N2', and the other end of the second current source CS22 may be electrically connected to ground.

[0069] In an embodiment, the pre-driver 211 can control the first current source CS21 and the second current source CS22 of the current source circuit 213 based on the data to be sent to the transceiver 110, namely the second data D2. For example, the pre-driver 211 can control the current values ​​output from the first current source CS21 and the second current source CS22. Furthermore, for example, the pre-driver 211 can disconnect the first current source CS21 and the second current source CS22 from the second node N2'.

[0070] Figures 4A-4D This shows a circuit diagram of a transceiver according to an embodiment. (Refer to...) Figures 1-3 To describe Figures 4A-4D Furthermore, the descriptions already given can be omitted. The following mainly describes the operation of the transceiver 110 of the first device 100, and for ease of explanation, details are omitted from the illustrations. Figure 3 The pre-drivers 111 and 211, pull-up switches SU11, SU12, SU13, SU21, SU22 and SU23, and pull-down switches SD11, SD12, SD13, SD21, SD22 and SD23 are included.

[0071] In this specification, portions marked with relatively light solid lines in the circuit diagram may indicate that the portion is disconnected or inactive and does not affect other components on the circuit diagram.

[0072] Figure 4A This is a diagram used to illustrate the case where the first data D1 is the first value 2'b00 and the second data D2 is the fourth value 2'b11.

[0073] Reference Figure 4A When the first data D1 is the first value 2'b00, the pre-driver 111 ( Figure 3 (China) can control Figure 3 In this circuit, pull-up switches SU11, SU12, and SU13 are in the open state, electrically disconnecting the pull-up resistor circuit 112_1 from the first node N1. At this time, no current can flow between the two ends of the pull-up resistor circuit 112_1.

[0074] When the first data D1 is the first value 2'b00, the pre-driver 111 can cause the first current source CS11 to generate current and disconnect the second current source CS12 from the second node N2. The amplitude of the current generated by the first current source CS11 can be the first current value I1.

[0075] When the second data D2 is the fourth value 2'b11, the pre-driver 211 ( Figure 3 (China) can control Figure 3 When the pull-down switches SD21, SD22, and SD23 are in the open state, the pull-down resistor circuit 212_2 is electrically disconnected from the first node N1'. At this time, there is no current flowing between the two ends of the pull-down resistor circuit 212_2.

[0076] When the second data D2 is the fourth value 2'b11, the pre-driver 211 can cause the second current source CS22 to generate current and disconnect the first current source CS21 from the second node N2'. The amplitude of the current generated by the second current source CS22 can be the first current value I1.

[0077] Figure 4B This is a diagram used to illustrate the case where the first data D1 is the second value 2'b01 and the second data D2 is the fourth value 2'b11.

[0078] Reference Figure 4BWhen the first data D1 is the second value 2'b01, the pre-driver 111 can electrically disconnect all but one of the pull-up resistors RU11, RU12, and RU13 from the first node N1 by controlling the pull-up switches SU11, SU12, and SU13. For example, the first pull-up resistor RU11 can be electrically connected to the first node N1, and the second pull-up resistor RU12 and the third pull-up resistor RU13 can be electrically disconnected from the first node N1. At this time, there may be no current flowing between the two ends of the second pull-up resistor RU12 and the two ends of the third pull-up resistor RU13.

[0079] Additionally, the pre-driver 111 can electrically disconnect one of the pull-down resistors RD11, RD12, and RD13 from the first node N1 by controlling pull-down switches SD11, SD12, and SD13. For example, the first pull-down resistor RD11 can be electrically disconnected from the first node N1, and the second pull-down resistor RD12 and the third pull-down resistor RD13 can be electrically connected to the first node N1. In this case, no current can flow between the two ends of the first pull-down resistor RD11.

[0080] When the first data D1 is the second value 2'b01, the pre-driver 111 can cause the first current source CS11 to generate current and disconnect the second current source CS12 from the second node N2. The amplitude of the current generated by the first current source CS11 can be the second current value I2.

[0081] Figure 4C This is a diagram used to illustrate the case where the first data D1 is the third value 2'b10 and the second data D2 is the fourth value 2'b11.

[0082] Reference Figure 4C When the first data D1 is the third value 2'b10, the pre-driver 111 can electrically disconnect one of the pull-up resistors RU11, RU12, and RU13 from the first node N1 by controlling the pull-up switches SU11, SU12, and SU13. For example, the first pull-up resistor RU11 can be electrically disconnected from the first node N1, and the second pull-up resistor RU12 and the third pull-up resistor RU13 can be electrically connected to the first node N1. At this time, there may be no current flowing between the two ends of the first pull-up resistor RU11.

[0083] Furthermore, the pre-driver 111 can electrically disconnect all but one of the pull-down resistors RD11, RD12, and RD13 from the first node N1 by controlling pull-down switches SD11, SD12, and SD13. For example, the first pull-down resistor RD11 is electrically connected to the first node N1, and the second pull-down resistor RD12 and the third pull-down resistor RD13 can be electrically disconnected from the first node N1. In this case, no current can flow between the two ends of the second pull-down resistor RD12 and the third pull-down resistor RD13.

[0084] When the first data D1 is the third value 2'b10, the pre-driver 111 can cause the second current source CS12 to generate current and disconnect the first current source CS11 from the second node N2. The amplitude of the current generated by the second current source CS12 can be the second current value I2.

[0085] Figure 4D This is a diagram used to illustrate the case where the first data D1 is the fourth value 2'b11 and the second data D2 is the fourth value 2'b11.

[0086] Reference Figure 4D When the first data D1 is the fourth value 2'b11, the pre-driver 111 can electrically disconnect the pull-down resistor circuit 112_2 from the first node N1 by switching the pull-down switches SD11, SD12 and SD13 to the open state. At this time, the current can not flow from the pull-down resistor circuit 112_2 to the first node N1.

[0087] When the first data D1 is the fourth value 2'b11, the pre-driver 111 can cause the second current source CS12 to generate current and disconnect the first current source CS11 from the second node N2. The amplitude of the current generated by the second current source CS12 can be the first current value I1.

[0088] Reference Figures 4A-4D The first current value I1 can correspond to three times the second current value I2. For example, when the second current value I2 is 0.5mA, the first current value I1 can be 1.5mA. The second current value I2 can correspond to a reference current value. The first current value I1 can correspond to three times the reference current value. In this specification, the reference current value can indicate the amplitude of the reference current.

[0089] In this embodiment, the reference current value can be changed when the calibration circuit 120 calibrates the current output by the current source circuit 113. (See below for further details.) Figure 5 This needs to be explained. According to... Figures 4A-4DIn the disclosed embodiments, the voltage level corresponding to the second node N2 can be a voltage level from which the influence of the first data D1 is eliminated. The receiver 114 can obtain the second data D2 provided from the transceiver 210 by decoding the voltage level of the second node N2.

[0090] Figure 5 This is a circuit diagram showing the calibration circuit 120 according to an embodiment. (Refer to...) Figure 1 and Figure 2 To describe Figure 5 And the description already given can be omitted.

[0091] Reference Figure 5 The calibration circuit 120 may include a first comparator CP1, a second comparator CP2, a third comparator CP3, a first replica resistor circuit 121, a first replica current source circuit 122, a first replica hybrid resistor RRH1, a second replica resistor circuit 123, a second replica current source circuit 124, and a second replica hybrid resistor RRH2.

[0092] Furthermore, the calibration circuit 120 can be electrically connected to the first external resistor RE1 via the first ZQ pin ZQ_P. The first ZQ pin ZQ_P can also be electrically connected to the first node RN1.

[0093] The first replicated resistor circuit 121 and the second replicated resistor circuit 123 may have the same structure as the voltage-mode driver 112 of the transceiver 110. When the resistor constituting the first replicated resistor circuit 121 has an error due to problems in the semiconductor manufacturing process, the resistor constituting the voltage-mode driver 112 may also have an error. The calibration circuit 120 may calibrate the resistor constituting the voltage-mode driver 112 based on the driver calibration signal VD_CAL obtained by calibrating the first replicated resistor circuit 121. Similarly, the first replicated current source circuit 122 and the second replicated current source circuit 124 may have the same structure as the current source circuit 113 of the transceiver 110. Furthermore, the first replicated hybrid resistor RRH1 and the second replicated hybrid resistor RRH2 may have the same resistance value as the first replicated hybrid resistor RH1 of the transceiver 110.

[0094] The first replica resistor circuit 121 may include a first replica pull-up resistor circuit 121_1 and a first replica pull-down resistor circuit 121_2.

[0095] The first replica pull-up resistor circuit 121_1 may include pull-up resistors RRU11, RRU12, and RRU13. A power supply voltage VDD may be applied to one end of the first replica pull-up resistor circuit 121_1, and the other end of the first replica pull-up resistor circuit 121_1 may be electrically connected to the first node RN1.

[0096] The first replica pull-down resistor circuit 121_2 may include pull-down resistors RRD11, RRD12, and RRD13. One end of the first replica pull-down resistor circuit 121_2 may be electrically connected to the first node RN1, and the other end of the first replica pull-down resistor circuit 121_2 may be electrically connected to ground.

[0097] One end of the first replicated hybrid resistor RRH1 can be electrically connected to the first node RN1, and the other end of the first replicated hybrid resistor RRH1 can be electrically connected to the second node RN2.

[0098] The first replication current source circuit 122 may include a first replication current source CSR11 and a second replication current source CSR12.

[0099] One end of the first replica current source CSR11 can be supplied with the power supply voltage VDD, and the other end of the first replica current source CSR11 can be electrically connected to the second node RN2. One end of the second replica current source CSR12 can be electrically connected to the second node RN2, and the other end of the second replica current source CSR12 can be electrically connected to ground.

[0100] The second replica resistor circuit 123 may include a second replica pull-up resistor circuit 123_1 and a second replica pull-down resistor circuit 123_2.

[0101] The second replica pull-up resistor circuit 123_1 may include pull-up resistors RRU21, RRU22, and RRU23. A power supply voltage VDD may be applied to one end of the second replica pull-up resistor circuit 123_1, and the other end of the second replica pull-up resistor circuit 123_1 may be electrically connected to a third node RN3.

[0102] The second replica pull-down resistor circuit 123_2 may include pull-down resistors RRD21, RRD22, and RRD23. One end of the second replica pull-down resistor circuit 123_2 may be electrically connected to the third node RN3, and the other end of the second replica pull-down resistor circuit 123_2 may be electrically connected to ground.

[0103] One end of the second replica hybrid resistor RRH2 can be electrically connected to the third node RN3, and the other end of the second replica hybrid resistor RRH2 can be electrically connected to the fourth node RN4.

[0104] The second replication current source circuit 124 may include a first replication current source CSR21 and a second replication current source CSR22.

[0105] One end of the first replicating current source CSR21 can be supplied with the power supply voltage VDD, and the other end of the first replicating current source CSR21 can be electrically connected to the fourth node RN4. One end of the second replicating current source CSR22 can be electrically connected to the fourth node RN4, and the other end of the second replicating current source CSR22 can be electrically connected to ground.

[0106] The first input terminal of the first comparator CP1 can be electrically connected to the first node RN1, and the first reference voltage VREF1 can be applied to the second input terminal of the first comparator CP1.

[0107] Based on the comparison result between the first reference voltage VREF1 and the voltage of the first node RN1 (i.e., based on the difference between the first reference voltage VREF1 and the voltage of the first node RN1), the first comparator CP1 can generate a first calibration signal CAL1, and the first replica resistor circuit 121 and the second replica resistor circuit 123 can be calibrated by the first calibration signal CAL1.

[0108] In this embodiment, when the first reference voltage VREF1 is 0.3V, the first comparator CP1 can calibrate the first replica resistor circuit 121 and the second replica resistor circuit 123 by generating a first calibration signal CAL1, so that the voltage level of the first node RN1 can be 0.3V. The first reference voltage VREF1 being 0.3V is an example, and voltage values ​​less than or greater than 0.3V can be set.

[0109] The first input of the second comparator CP2 can be electrically connected to the third node RN3, and the first reference voltage VREF1 can be applied to the second input of the second comparator CP2.

[0110] Based on the comparison result between the first reference voltage VREF1 and the voltage of the third node RN3 (i.e., based on the difference between the first reference voltage VREF1 and the voltage of the third node RN3), the second comparator CP2 can generate a second calibration signal CAL2, and the second replica resistor circuit 123 can be calibrated by the second calibration signal CAL2.

[0111] In this embodiment, when the first reference voltage VREF1 is 0.3V, the second comparator CP2 can calibrate the second replica resistor circuit 123 by generating a second calibration signal CAL2, so that the voltage level of the third node RN3 can be 0.3V. The first reference voltage VREF1 being 0.3V is an example, and voltage values ​​less than or greater than 0.3V can be set.

[0112] The calibration circuit 120 can generate a driver calibration signal VD_CAL. The driver calibration signal VD_CAL can be a signal generated based on the first calibration signal CAL1 and the second calibration signal CAL2. The calibration circuit 120 can calibrate the voltage mode driver 112 through the driver calibration signal VD_CAL to calibrate the resistance value error generated in the resistors included in the pull-up resistor circuit 112_1 and the pull-down resistor circuit 112_2.

[0113] The first input of the third comparator CP3 can be electrically connected to the second node RN2. The second reference voltage VREF2 can be applied to the second input of the third comparator CP3. When the voltage level of the second node RN2 does not match the voltage level of the second reference voltage VREF2, the third comparator CP3 can adjust the current generated by the first replica current source circuit 122 through the third calibration signal CAL3 to adjust the voltage level of the second node RN2 to the voltage level of the second reference voltage VREF2.

[0114] The calibration circuit 120 can generate a current source calibration signal CS_CAL. The current source calibration signal CS_CAL can be a signal generated based on a third calibration signal CAL3. By calibrating the current source circuit 113 using the current source calibration signal CS_CAL, the resistance value error generated in the first hybrid resistor RH1 can be calibrated. In this embodiment, the calibration circuit 120 can calibrate the current output by the current source circuit 113 by adjusting the reference current value output by the current source circuit 113.

[0115] For example, suppose the reference current value before calibration is 0.5mA, and the reference current value after calibration is 0.58mA. In this case, the first current value I1 after calibration can be 1.74mA, and the second current value I2 after calibration can be 0.58mA. The calibration circuit 220 of the second device 200 can also have the same configuration as the calibration circuit 120 of the first device 100, and the description already given is omitted.

[0116] In this embodiment, the first reference voltage VREF1 can be half of the power supply voltage VDD. The second reference voltage VREF2 can be half of the first reference voltage VREF1.

[0117] Figure 6 This is a circuit diagram showing the calibration circuit 120 according to an embodiment. Specifically, Figure 6 It is used for explanation Figure 5 The calibration circuit 120 generates the driver calibration signal VD_CAL as shown in the diagram. (Refer to...) Figure 5 To describe Figure 6 And the description already given can be omitted.

[0118] Reference Figure 6For ease of illustration, the circuit configuration that is not related to the generation of the driver calibration signal VD_CAL is shown with relatively shallow solid lines.

[0119] In an embodiment, Figure 3 Pull-up resistors RU11, RU12, RU13, RU21, RU22 and RU23, and pull-down resistors RD11, RD12, RD13, RD21, RD22 and RD23. Figure 5 The replicated pull-up resistors RRU11, RRU12, RRU13, RRU21, RRU22, and RRU23, and the replicated pull-down resistors RRD11, RRD12, RRD13, RRD21, RRD22, and RRD23, can each be implemented using multiple transistors. In this specification, the resistance value can be calibrated via calibration circuit 120 by indicating that the resistance value is adjusted by turning on or off the multiple transistors constituting each resistor.

[0120] exist Figure 6 In this context, it is assumed that each resistor has an error. For example, when designing the first device 100 ( Figure 1 In the case of a resistor, the resistance value of each resistor can be designed to be 150Ω, but it is assumed that the value is not 150Ω due to the variation of PVT.

[0121] The calibration circuit 120 can calibrate the first replicated pull-up resistor circuit 121_1 and the second replicated pull-up resistor circuit 123_1 of the first replicated resistor circuit 121 through the first calibration signal CAL1, and can calibrate the second replicated pull-down resistor circuit 123_2 through the second calibration signal CAL2.

[0122] The calibration circuit 120 can disconnect the first replicated pull-down resistor circuit 121_2 from the first node RN1. Based on the comparison between the voltage of the first node RN1 and the first reference voltage VREF1 (i.e., based on the difference between the voltage of the first node RN1 and the first reference voltage VREF1), the calibration circuit 120 can generate a first calibration signal CAL1. The first calibration signal CAL1 can turn on or off multiple transistors constituting the resistors included in the first replicated pull-up resistor circuit 121_1, causing the voltage of the first node RN1 to become the first reference voltage VREF1. By turning on or off the multiple transistors constituting the resistors, the value indicated by each resistor in the first replicated pull-up resistor circuit 121_1 can be calibrated. For example, the value can be calibrated to 150Ω.

[0123] Based on the calibration of the first replicated pull-up resistor circuit 121_1, the calibration circuit 120 can calibrate the error of the second replicated pull-up resistor circuit 123_1.

[0124] Based on the comparison between the voltage of the third node RN3 and the first reference voltage VREF1 (i.e., based on the difference between the voltage of the third node RN3 and the first reference voltage VREF1), the calibration circuit 120 can generate a second calibration signal CAL2. The second calibration signal CAL2 can turn on or off multiple transistors constituting the resistors included in the second replicated pull-down resistor circuit 123_2, causing the voltage of the third node RN3 to become the first reference voltage VREF1. By turning on or off the multiple transistors constituting the resistors, the value indicated by each resistor in the second replicated pull-down resistor circuit 123_2 can be calibrated. For example, this value can be calibrated to 150Ω.

[0125] Based on the first calibration signal CAL1 and the second calibration signal CAL2, the calibration circuit 120 can generate a driver calibration signal VD_CAL. The driver calibration signal VD_CAL can be a signal that includes the first calibration signal CAL1 and the second calibration signal CAL2. Alternatively, the first calibration signal CAL1 and the second calibration signal CAL2 can each be a signal output from the calibration circuit 120 as the driver calibration signal VD_CAL.

[0126] In an embodiment, the first calibration signal CAL1 can be provided to the voltage-mode driver 112 as a driver calibration signal VD_CAL, thereby allowing calibration of the resistance value of the resistor in the pull-up resistor circuit 112_1 constituting the voltage-mode driver 112. For example, suppose the first calibration signal CAL1 is a signal that turns off at least one transistor of the plurality of transistors constituting the replica pull-up resistor RRU11 in the first replica pull-up resistor circuit 121_1 and turns on the remaining transistors, and turns off at least one transistor of the plurality of transistors constituting the replica pull-up resistor RRU21 in the second replica pull-up resistor circuit 123_1 and turns on the remaining transistors. The replica pull-up resistor RRU11 can correspond to the replica pull-up resistor RRU21, and both the replica pull-up resistor RRU11 and the replica pull-up resistor RRU21 can correspond to the pull-up resistor RRU11, respectively. The first calibration signal CAL1 can be provided to the voltage-mode driver 112 as the driver calibration signal VD_CAL, causing at least one transistor among the plurality of transistors constituting the pull-up resistor RU11 to turn off and the remaining transistors to turn on. In this case, the number of transistors turned on in the duplicate pull-up resistors RRU11 and RRU21 can be the same as the number of transistors turned on in pull-up resistor RU11. Similarly, the number of transistors turned off in the duplicate pull-up resistors RRU11 and RRU21 can be the same as the number of transistors turned off in pull-up resistor RU11.

[0127] In this embodiment, the second calibration signal CAL2 can be provided to the voltage-mode driver 112 as a driver calibration signal VD_CAL, thereby allowing calibration of the resistance value of the resistors in the pull-down resistor circuit 112_2 constituting the voltage-mode driver 112. For example, suppose the second calibration signal CAL2 is a signal that turns off at least one transistor of the plurality of transistors constituting the replicated pull-down resistor RRD21 in the second replicated pull-down resistor circuit 123_2 and turns on the remaining transistors. The replicated pull-down resistor RRD21 can correspond to the pull-down resistor RD11. The second calibration signal CAL2 can be provided to the voltage-mode driver 112 as a driver calibration signal VD_CAL, turning off at least one transistor of the plurality of transistors constituting the pull-down resistor RD11 and turning on the remaining transistors. In this case, the number of transistors turned on in the replicated pull-down resistor RRD21 can be the same as the number of transistors turned on in the pull-down resistor RD11. Similarly, the number of transistors turned off in the replicated pull-down resistor RRD21 can be the same as the number of transistors turned off in the pull-down resistor RD11.

[0128] Figure 7 This is a circuit diagram showing the calibration circuit 120 according to an embodiment. Specifically, Figure 7 It is used for explanation Figure 5 The calibration circuit 120 generates the current source calibration signal CS_CAL as shown in the diagram. Refer to... Figure 5 To explain Figure 7 And the description already given can be omitted.

[0129] Reference Figure 7 For ease of explanation, circuit configurations that are not related to the generation of the current source calibration signal CS_CAL are represented by relatively shallow solid lines.

[0130] exist Figure 7 In this context, it is assumed that each resistor included in the first replicated resistor circuit 121 is calibrated to its expected value (e.g., 150Ω) during the design phase. It is also assumed that an error occurs in the first replicated hybrid resistor RRH1. For example, it is assumed that the expected resistance value of the first replicated hybrid resistor RRH1 was 75Ω during the design phase, but due to a change in PVT, the resistance value is 60Ω.

[0131] The calibration circuit 120 can calibrate the error of the first hybrid resistor RRH1 by controlling the current of the first replica current source circuit 122. That is, the error in the voltage level of the second node RN2 caused by the error of the first hybrid resistor RRH1 is calibrated by controlling the current of the first replica current source circuit 122.

[0132] The calibration circuit 120 can disconnect any one of the resistors included in the first replicated pull-up resistor circuit 121_1 from the first node RN1. For example, it can disconnect the replicated pull-up resistor RRU13 from the first node RN1. The calibration circuit 120 can disconnect all but one of the resistors included in the first replicated pull-down resistor circuit 121_2 from the first node RN1. For example, it can disconnect the replicated pull-down resistors RRD11 and RRD12 from the first node RN1.

[0133] The second reference voltage VREF2 can be applied to the second input of the third comparator CP3. In an embodiment, the voltage of the second reference voltage VREF2 can be 1 / 4 VDD. In this case, the third comparator CP3 can control the first replica current source circuit 122 through the third calibration signal CAL3, so that the voltage of the second node RN2 becomes the second reference voltage VREF2. In an embodiment, the first replica current source CSR11 can be disconnected, and the current output of the second replica current source CSR12 can be adjusted based on the third comparator CP3. When the voltage of the second node RN2 becomes the second reference voltage VREF2, the current output of the second current source CSR12 can represent the calibration current ICAL.

[0134] The calibration circuit 120 can generate a current source calibration signal CS_CAL, which is used to calibrate the reference current of the current source circuit 113. In an embodiment, a third calibration signal CAL3 can be output from the calibration circuit 120 as the current source calibration signal CS_CAL. The amplitude of the calibration current ICAL can correspond to the reference current value of the current source circuit 113. The current source calibration signal CS_CAL can be a signal that adjusts the reference current value of the current source circuit 113 to the amplitude of the calibration current ICAL. For example, when the calibration current ICAL is 0.58mA, the current source calibration signal CS_CAL calibrates the current source circuit 113, such that the calibrated first current value I1 ( Figures 4A-4D The current value (three times the reference current value) becomes 1.74mA, and the calibrated second current value I2 ( Figures 4A-4D The current (same as the reference current) becomes 0.58mA.

[0135] Figures 8A-8D This shows a circuit diagram of a transceiver according to an embodiment. Specifically, Figures 8A-8D This is used to illustrate the configuration of current source circuits 113a and 213a. Figures 4A-4D The diagram shows different embodiments of the current source circuits 113 and 213. Refer to... Figure 1 and Figure 4A To describe Figures 8A-8D And the descriptions already given can be omitted. Figures 8A-8DThe description focuses on and Figures 4A-4D The differences.

[0136] Reference Figures 8A-8D , Figures 8A-8D The transceiver 110a can correspond to Figures 4A-4D The transceiver 110, and Figures 8A-8D The transceiver 210a can correspond to Figures 4A-4D The transceiver 210.

[0137] However, with Figures 4A-4D The current source circuits 113 and 213 are different. Figures 8A-8D Current source circuits 113a and 213a may not have a current source electrically connected between the second node N2 and ground. That is to say, Figures 8A-8D The current source circuits 113a and 213a may include current sources CS1 and CS2 respectively. One end of current sources CS1 and CS2 is supplied with a power supply voltage VDD, and the other end of current sources CS1 and CS2 is electrically connected to the second node N2.

[0138] Based on the value of the first data D1, the amplitude of the current supplied by the current source circuit 113a to the second node N2 can be changed. Similarly, based on the value of the second data D2, the amplitude of the current supplied by the current source circuit 213a to the second node N2' can be changed.

[0139] Figure 8A This is a diagram used to illustrate the case where the first data D1 is the first value 2'b00 and the second data D2 is the fourth value 2'b11.

[0140] Reference Figure 8A When the first data D1 is the first value 2'b00, the amplitude of the current generated by the first current source CS1 can correspond to three times the amplitude of the reference current. In an embodiment, the reference current amplitude can be 0.5mA, and when the first data D1 is the first value 2'b00, the amplitude of the current generated by the first current source CS1 can be 1.5mA.

[0141] When the second data D2 is the fourth value 2'b11, the second current source CS2 may not generate current. That is, the second current source CS2 can be disconnected from the second node N2'. In the embodiment, the reference current amplitude may be 0.5mA, and when the second data D2 is the fourth value 2'b11, the amplitude of the current generated by the second current source CS2 may be 0mA.

[0142] Figure 8B This is a diagram used to illustrate the case where the first data D1 is the second value 2'b01 and the second data D2 is the fourth value 2'b11.

[0143] Reference Figure 8BWhen the first data D1 is the second value 2'b01, the amplitude of the current generated by the first current source CS1 can correspond to twice the amplitude of the reference current. In an embodiment, the reference current amplitude can be 0.5mA, and when the first data D1 is the second value 2'b01, the amplitude of the current generated by the first current source CS1 can be 1.0mA.

[0144] Figure 8C This is a diagram used to illustrate the case where the first data D1 is the third value 2'b10 and the second data D2 is the fourth value 2'b11.

[0145] Reference Figure 8C When the first data D1 is the third value 2'b10, the amplitude of the current generated by the first current source CS1 can correspond to twice the amplitude of the reference current. In this embodiment, the reference current amplitude can be 0.5mA, and when the first data D1 is the third value 2'b10, the amplitude of the current generated by the first current source CS1 can be 0.5mA.

[0146] Figure 8D This is a diagram used to illustrate the case where the first data D1 is the fourth value 2'b11 and the second data D2 is the fourth value 2'b11.

[0147] Reference Figure 8D When the first data D1 is the fourth value 2'b11, the first current source CS1 may not generate current. That is, the first current source CS1 can be disconnected from the second node N2. In the embodiment, the amplitude of the reference current can be 0.5mA, and when the first data D1 is the fourth value 2'b11, the amplitude of the current generated by the first current source CS1 can be 0mA.

[0148] Figure 9 This is a flowchart illustrating a method of operating the device according to an embodiment. (Refer to...) Figures 1-7 To explain Figure 9 And the description already given can be omitted.

[0149] exist Figure 9 In, such as Figures 4A-4D As shown, it is assumed and described that the first device 100 sends first data D1 to the second device 200, and the first device 100 receives second data D2 from the second device 200.

[0150] Reference Figure 9In operation S110, the first device 100 can calibrate the voltage-mode driver 112 using the calibration circuit 120. Calibration of the voltage-mode driver 112 by the first device 100 can be performed to calibrate the error (i.e., error due to PVT variations, etc.) of the resistance value indicated by each of the plurality of resistors included in the voltage-mode driver 112 during the manufacturing process of the first device 100. See below for further details. Figure 10 The operation S110 is described in detail.

[0151] In operation S120, the first device 100 can calibrate the current source circuit 113 using the calibration circuit 120. The first device 100 can calibrate the current source circuit 113 by adjusting the amplitude of the reference current output by the current source circuit 113. (See below for further details.) Figure 11 The operation S120 is described in detail.

[0152] In operation S130, based on the first data D1, the first device 100 can adjust the resistance values ​​of the pull-up resistor circuit 112_1 and the pull-down resistor circuit 112_2 of the voltage mode driver 112, and adjust the current value of the current source circuit 113.

[0153] Based on the first data D1, the first device 100 adjusts the resistance values ​​of the pull-up resistor circuit 112_1 and the pull-down resistor circuit 112_2 of the voltage mode driver 112. This can indicate whether each resistor is disconnected from the first node N1 or connected to the first node N1 by controlling the switch corresponding to each resistor in the resistors constituting the pull-up resistor circuit 112_1 and the pull-down resistor circuit 112_2 to be in an open or closed state.

[0154] Similarly, based on the first data D1, the first device 100 can adjust the current value of the current source circuit 113, which can indicate whether the current source constituting the current source circuit 113 is disconnected from the second node N2 or the magnitude of the current is adjusted.

[0155] In the embodiment, when the first data D1 is the first value 2'b00, the first device 100 can electrically disconnect the pull-up resistor circuit 112_1 from the first node N1, and the first device 100 can electrically disconnect the second current source CS12 from the second node N2.

[0156] In this embodiment, when the first data D1 is the second value 2'b01, the first device 100 can electrically disconnect all but one of the pull-up resistors included in the pull-up resistor circuit 112_1 from the first node N1. The first device 100 can electrically disconnect one of the pull-down resistors included in the pull-down resistor circuit 111_2 from the first node N1. The first device 100 can electrically disconnect the second current source CS12 from the second node N2. In this case, the resistance value of the pull-up resistor circuit 112_1 can be greater than the resistance value of the pull-down resistor circuit 112_2.

[0157] In this embodiment, when the first data D1 is the third value 2'b10, the first device 100 can electrically disconnect one of the pull-up resistors included in the pull-up resistor circuit 112_1 from the first node N1. The first device 100 can electrically disconnect the remaining pull-down resistors in the pull-down resistor circuit 112_2 except for one pull-down resistor from the first node N1. The first device 100 can electrically disconnect the first current source CS11 from the second node N2. In this case, the resistance value of the pull-up resistor circuit 112_1 can be less than the resistance value of the pull-down resistor circuit 112_2.

[0158] In this embodiment, when the first data D1 is the fourth value 2'b11, the first device 100 can electrically disconnect the pull-down resistor circuit 112_2 from the first node N1. The first device 100 can electrically disconnect the first current source CS11 from the second node N2.

[0159] In operation S140, the first device 100 can obtain the second data D2 based on the voltage level of the input applied to the receiver 114 (i.e., the voltage level of the second node N2).

[0160] In an embodiment, when the voltage level of the second node N2 is the first voltage level, the receiver 114 can obtain the first value 2'b00.

[0161] In this embodiment, when the voltage level of the second node N2 is the second voltage level, the receiver 114 can obtain the second value 2'b01. The second voltage level can be greater than the first voltage level.

[0162] In this embodiment, when the voltage level of the second node N2 is the third voltage level, the receiver 114 can obtain the third value 2'b10. The third voltage level can be greater than the second voltage level.

[0163] In this embodiment, when the voltage level of the second node N2 is the fourth voltage level, the receiver 114 can obtain the fourth value 2'b11. The fourth voltage level can be greater than the third voltage level.

[0164] Figure 10This is a flowchart illustrating the operation method of the device according to an embodiment. Figure 10 It shows in detail Figure 9 The flowchart for operation S110 will be referenced. Figures 1-7 and Figure 9 To describe Figure 10 And the description already given can be omitted.

[0165] Reference Figure 10 In operation S111, the first device 100 can turn off the first replica resistor circuit 121 ( Figure 6 The pull-down resistors RRD11, RRD12 and RRD13 (in the middle) Figure 6 (in the middle). At this time, the first device 100 can be obtained from the first node RN1 ( Figure 6 (Middle) Disconnect pull-down resistors RRD11, RRD12 and RRD13.

[0166] In one embodiment, the first device 100 turning off the pull-down resistors can indicate that the switch corresponding to each pull-down resistor is turned off to the open state.

[0167] In an embodiment, the first node RN1 may be a node defined by an input terminal of the first comparator CP1, one end of the first replicated pull-up resistor circuit 121_1 of the first replicated resistor circuit 121, and one end of the first replicated pull-down resistor circuit 121_2 of the first replicated resistor circuit 121. The first node RN1 may be referred to as the first comparison reference node.

[0168] In operation S112, based on the result of comparing the first reference voltage VREF1 with the voltage of the first node RN1 via the first comparator CP1 (i.e., based on the difference between the first reference voltage VREF1 and the voltage of the first node RN1), the first device 100 can calibrate the pull-up resistors RRU11, RRU12 and RRU13 of the first replica resistor circuit 121.

[0169] In an embodiment, the signal indicating the calibration values ​​of the pull-up resistors RRU11, RRU12 and RRU13 of the first replica resistor circuit 121 may be the first calibration signal CAL1.

[0170] In operation S113, based on the results of calibrating the pull-up resistors RRU11, RRU12 and RRU13 of the first replica resistor circuit 121, the first device 100 can calibrate the pull-up resistors RRU21, RRU22 and RRU23 of the second replica resistor circuit 123.

[0171] In this embodiment, the signal representing the calibration values ​​of the pull-up resistors RRU21, RRU22, and RRU23 of the second replica resistor circuit 123 can be the first calibration signal CAL1. That is, the calibration values ​​corresponding to the pull-up resistors RRU11, RRU12, and RRU13 of the first replica resistor circuit 121 can be the same as the calibration values ​​corresponding to the pull-up resistors RRU21, RRU22, and RRU23 of the second replica resistor circuit 123.

[0172] In operation S114, based on the result of comparing the first reference voltage VREF1 with the third node RN3 via the second comparator CP2 (i.e., based on the difference between the voltages of the first reference voltage VREF1 and the third node RN3), the first device 100 can calibrate the pull-down resistors RRD21, RRD22 and RRD23 of the second replica resistor circuit 123.

[0173] In an embodiment, the signal representing the calibration value of the pull-down resistors RRD21, RRD22 and RRD23 of the second replica resistor circuit 123 may be the second calibration signal CAL2.

[0174] In an embodiment, the third node RN3 may be defined by an input terminal of the second comparator, one end of the pull-up resistor of the second replica resistor circuit, and one end of the pull-down resistor of the second replica resistor circuit. The third node RN3 may be referred to as the second comparison reference node.

[0175] In operation S115, based on the calibrated first replica resistor circuit 121 and the calibrated second replica resistor circuit 123, the first device 100 can calibrate the voltage mode driver 112.

[0176] Specifically, the first device 100 can generate a driver calibration signal VD_CAL indicating the calibration value indicated by the first calibration signal CAL1 and the calibration value indicated by the second calibration signal CAL2, and can calibrate the voltage mode driver 112 based on the driver calibration signal VD_CAL.

[0177] Figure 11 This is a flowchart illustrating the operation method of the device according to an embodiment. Figure 11 It shows in detail Figure 9 The flowchart for operation S120 will be referenced. Figures 1-7 and Figure 9 To describe Figure 11 And the description already given can be omitted.

[0178] Reference Figure 11In operation S121, based on the result of comparing the voltage of the second node RN2 with the second reference voltage VREF2 via the third comparator CP3 (i.e., based on the difference between the voltage of the second node RN2 and the second reference voltage VREF2), the first device 100 can determine the magnitude of the calibration current ICAL. The second node RN2 can be referred to as the third comparison reference node.

[0179] In one embodiment, the first device 100 can compare the voltage of the second node RN2 with the second reference voltage VREF2 using the third comparator CP3, and the result can be a third calibration signal CAL3. The third calibration signal CAL3 can represent the value of the amplitude of the current output by the first replicated current source circuit 122 for calibration.

[0180] In operation S122, based on the determined amplitude of the calibration current ICAL, the first device 100 can generate a current source calibration signal CS_CAL. Based on the current source calibration signal CS_CAL, the first device 100 can calibrate the current source circuit 113.

[0181] In an embodiment, the first device 100 can calibrate the current source circuit 113 by calibrating the basic current value of the current source constituting the current source circuit 113.

[0182] Figure 12 This is a block diagram illustrating a system 3000 including a storage device, including the device according to an embodiment.

[0183] Reference Figure 12 System 3000 may include a camera 3100, a display 3200, an audio processor 3300, a modem 3400, DRAM 3500a and 3500b, flash memory devices 3600a and 3600b, I / O devices 3700a and 3700b, and an application processor (AP) 3800. System 3000 can be implemented as a laptop computer, mobile phone, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, system 3000 can be implemented as a server or PC.

[0184] Camera 3100 can capture still images or videos under user control and store the captured image / video data or send the captured image / video data to display 3200. Audio processor 3300 can process audio data or network content included in flash memory devices 3600a and 3600b. Modem 3400 modulates and transmits signals for wired / wireless data transmission and reception, and can demodulate signals to restore the modulated signals to the original signals at the receiving end. I / O devices 3700a and 3700b may include devices that provide digital input and / or output functions, such as Universal Serial Bus (USB), storage devices, digital cameras, Secure Digital (SD) cards, Digital Multifunction Disk (DVD), network adapters, touch screens, etc.

[0185] AP 3800 can control the overall operation of system 3000. AP 3800 can control display 3200, causing a portion of the content stored in flash memory devices 3600a and 3600b to be displayed on display 3200. When user input is received through I / O devices 3700a and 3700b, AP 3800 can perform control operations corresponding to the user input. AP 3800 may include controller 3810 and interface 3830, and may include accelerator 3820, which is dedicated circuitry for artificial intelligence (AI) data manipulation, or may have an accelerator chip separate from AP 3800. Furthermore, DRAM 3500b may be mounted on accelerator 3820 or the accelerator chip. An accelerator is a functional block specifically performing the specific functions of AP 3800. An accelerator may include: a graphics processing unit (GPU), a functional block specifically performing graphics data processing; a neural processing unit (NPU), a block specifically performing AI computation and inference; and a data processing unit (DPU), a block specifically for data transmission.

[0186] System 3000 may include multiple DRAMs 3500a and 3500b. AP 3800 can control DRAMs 3500a and 3500b via Command and Mode Register (MRS) settings conforming to Joint Electronic Equipment Committee (JEDEC) standards, or communicate using company-specific features such as low-voltage / high-speed / reliability and Cyclic Redundancy Check (CRC) / Error Correction Code (ECC) functions by configuring the DRAM interface protocol. For example, AP 3800 can communicate with DRAM 3500a via an interface conforming to JEDEC standards such as LPDDR4 and LPDDR5, and accelerator blocks or accelerator chips can communicate by configuring new DRAM interface specifications to control accelerator DRAM 3500b, which has a higher bandwidth than DRAM 3500a.

[0187] existFigure 12 The diagram only shows DRAM 3500a and 3500b, but is not limited to them. Any memory, such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM, can be used, as long as it meets the bandwidth, response speed, and voltage requirements of the AP 3800 or accelerator chip. DRAM 3500a and 3500b have relatively lower latency and bandwidth than I / O devices 3700a and 3700b or flash memory devices 3600a and 3600b. DRAM 3500a and 3500b can be initialized when the system 3000 is powered on and can be used as temporary storage locations for operating system and application data by loading operating system and application data, or as execution space for various software code.

[0188] In DRAMs 3500a and 3500b, arithmetic operations such as addition / subtraction / multiplication / division, vector operations, address operations, or Fast Fourier Transform (FFT) operations can be performed. Furthermore, functions for performing inference can be executed within DRAMs 3500a and 3500b. Here, inference can be performed using deep learning algorithms employing artificial neural networks. Deep learning algorithms may include a training phase that learns a model from various data, and an inference phase that uses the learned model to recognize data. As an example, images captured by a user via camera 3100 can be signal-processed and stored in DRAM 3500b. An accelerator block or accelerator chip 3820 can use the data stored in DRAM 3500b and the inference functions to perform AI data operations to recognize the data.

[0189] System 3000 may include multiple storage devices or multiple flash memory devices 3600a and 3600b, with capacities greater than DRAM 3500a and 3500b. Accelerator blocks or accelerator chips may use flash memory devices 3600a and 3600b to perform training operations and AI data operations. In embodiments, flash memory devices 3600a and 3600b may use computing devices provided in memory controller 3610 to more efficiently perform training operations and inference AI data computations performed by AP 3800 and / or accelerator chips. Flash memory devices 3600a and 3600b may store images captured by camera 3100 or data transmitted via a data network. For example, it may store augmented reality / virtual reality, high-definition (HD), or ultra-high-definition (UHD) content.

[0190] System 3000 can send or receive signals between components to achieve high-speed operation. The camera 3100, display 3200, audio processor 3300, modem 3400, DRAM 3500a and 3500b, flash memory devices 3600a and 3600b, I / O devices 3700a and 3700b, and / or AP 3800 within system 3000 may include references. Figures 1-11 The first device 100 is described.

[0191] As described above, embodiments have been disclosed in the accompanying drawings and specification. Although specific terms have been used to describe the embodiments, these terms are for the purpose of illustrating the technical concept of the invention only and are not intended to limit the meaning or scope of the invention concept set forth in the claims.

[0192] Although various aspects of the embodiments have been specifically shown and described above, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A device configured to send first data to an external device and receive second data from the external device, the device comprising: A voltage-mode driver, connected to a first node, the voltage-mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors and the pull-down resistor circuit including a plurality of pull-down resistors; A current source circuit is connected to the second node and includes a first current source and a second current source; A pre-driver is configured to control the voltage-mode driver and the current source circuit based on the first data; A receiver is connected to the second node and is configured to obtain the second data based on the voltage level of the second node; as well as A hybrid resistor is connected between the first node and the second node.

2. The device according to claim 1 further includes a calibration circuit. in, The calibration circuit includes: The first replica current source circuit is configured to generate a first calibration current; A first comparator has a first input terminal and a second input terminal, wherein a first reference voltage is applied to the second input terminal; The first replica resistor circuit includes a plurality of first replica resistors; The first replica hybrid resistor has a first terminal and a second terminal, the first terminal being connected to the first input terminal of the first replica resistor circuit and the first input terminal of the first comparator, and the second terminal being connected to the output terminal of the first replica current source circuit. The second replication current source circuit is configured to generate a second calibration current; The second comparator has a first input terminal and a second input terminal, wherein the first reference voltage is applied to the second input terminal; The second replica resistor circuit includes a plurality of second replica resistors; and The second replica hybrid resistor has a first terminal and a second terminal, the first terminal being connected to the first input terminal of the second replica resistor circuit and the second comparator, and the second terminal being connected to the output terminal of the second replica current source circuit.

3. The device according to claim 2, wherein, The calibration circuit is configured as follows: Based on the first difference between the voltage at the first input terminal of the first comparator and the first reference voltage, the first replica resistor circuit and the second replica resistor circuit are calibrated. The second replica resistor circuit is calibrated based on the second difference between the voltage at the first input terminal of the second comparator and the first reference voltage. as well as The voltage-mode driver is calibrated based on the first difference and the second difference.

4. The device according to claim 2, wherein, The calibration circuit further includes a third comparator having a first input and a second input, wherein the first input is connected to the second terminal of the first replica hybrid resistor, and a second reference voltage is applied to the second input. The calibration circuit is configured to calibrate the first current source and the second current source based on a third difference between the voltage at the first input of the third comparator and the second reference voltage.

5. The device according to claim 1, wherein, One end of the first current source is supplied with a power supply voltage, and the other end of the first current source is connected to the second node. One end of the second current source is connected to the second node, and the other end of the second current source is grounded.

6. The device according to claim 5, wherein, The pre-driver is configured to disconnect the pull-up resistor circuit from the first node and disconnect the second current source from the second node based on the first data having a first value.

7. The device according to claim 5, wherein, The pre-driver is configured to, based on the first data having a second value, disconnect all but one of the plurality of pull-up resistors from the first node, disconnect one of the plurality of pull-down resistors from the first node, and disconnect the second current source from the second node. The resistance value of the pull-up resistor circuit is greater than the resistance value of the pull-down resistor circuit.

8. The device according to claim 5, wherein, The pre-driver is configured to have a third value based on the first data: Disconnect one of the plurality of pull-up resistors from the first node; Disconnect all but one of the multiple pull-down resistors from the first node; as well as Disconnect the first current source from the second node, and The resistance value of the pull-up resistor circuit is less than the resistance value of the pull-down resistor circuit.

9. The device according to claim 5, wherein, The pre-driver is configured to disconnect the pull-down resistor circuit from the first node and disconnect the first current source from the second node based on the first data having a fourth value.

10. A method for controlling an apparatus to send first data to an external device and receive second data from the external device, the method comprising: Use a calibration circuit to calibrate the voltage-mode driver; Use the calibration circuit to calibrate the current source circuit; Based on the first data, adjust the resistance value of the pull-up resistor circuit of the voltage mode driver; Based on the first data, adjust the resistance value of the pull-down resistor circuit of the voltage mode driver; Based on the first data, adjust the current value of the current source circuit; as well as The second data is obtained based on the voltage level applied to the receiver.

11. The method according to claim 10, wherein, The device also includes a hybrid resistor having one end connected to a first node and another end connected to a second node, the second node being connected to the input of the receiver. The current source circuit includes: a first current source having one end to which a power supply voltage is applied and another end connected to the second node; and a second current source having one end connected to the second node and another end grounded.

12. The method according to claim 11, wherein, Based on the first data having a first value, adjusting the resistance value of the pull-up resistor circuit, adjusting the resistance value of the pull-down resistor circuit, and adjusting the current value of the current source circuit includes: disconnecting the first current source from the first node by turning off the resistor of the pull-up resistor circuit; and disconnecting the second current source from the second node.

13. The method according to claim 11, wherein, Based on the first data having a second value, adjusting the resistance value of the pull-up resistor circuit, adjusting the resistance value of the pull-down resistor circuit, and adjusting the current value of the current source circuit include: Disconnect all but one of the multiple pull-up resistors included in the pull-up resistor circuit from the first node; Disconnect one of the multiple pull-down resistors included in the pull-down resistor circuit from the first node; and Disconnect the second current source from the second node, and The resistance value of the pull-up resistor circuit is greater than the resistance value of the pull-down resistor circuit.

14. The method according to claim 11, wherein, Based on the first data having a third value, adjusting the resistance value of the pull-up resistor circuit, adjusting the resistance value of the pull-down resistor circuit, and adjusting the current value of the current source circuit include: Disconnect one of the multiple pull-up resistors included in the pull-up resistor circuit from the first node; Disconnect all but one of the multiple pull-down resistors included in the pull-down resistor circuit from the first node; and Disconnect the first current source from the second node, and The resistance value of the pull-up resistor circuit is less than the resistance value of the pull-down resistor circuit.

15. The method according to claim 11, wherein, Based on the first data having a fourth value, adjusting the resistance value of the pull-up resistor circuit, adjusting the resistance value of the pull-down resistor circuit, and adjusting the current value of the current source circuit include: Disconnect the pull-down resistor circuit from the first node; and Disconnect the first current source from the second node.

16. A device configured to send first data to an external device and receive second data from the external device, the device comprising: A voltage-mode driver, connected to a first node, the voltage-mode driver including a pull-up resistor circuit containing multiple pull-up resistors and a pull-down resistor circuit containing multiple pull-down resistors; A current source is connected between the power supply voltage and the second node; A pre-driver is configured to control the voltage-mode driver and the current source based on the first data; A receiver is connected to the second node and is configured to obtain the second data based on the voltage level of the second node; as well as A hybrid resistor is connected between the first node and the second node.

17. The device according to claim 16, wherein, The pre-driver is also configured to disconnect the pull-up resistor circuit from the first node based on the first data having a first value, and adjust the amplitude of the current generated by the current source to three times the amplitude of the reference current.

18. The device according to claim 16, wherein, The pre-driver is also configured to, based on the first data having a second value, disconnect all but one of the plurality of pull-up resistors from the first node, disconnect one of the plurality of pull-down resistors from the first node, and adjust the amplitude of the current generated by the current source to twice the amplitude of the reference current. The resistance value of the pull-up resistor circuit is greater than the resistance value of the pull-down resistor circuit.

19. The device according to claim 16, wherein, The pre-driver is also configured to, based on the first data having a third value, disconnect one of the plurality of pull-up resistors from the first node, disconnect all but one of the plurality of pull-down resistors from the first node, and adjust the amplitude of the current generated by the current source to the amplitude of the reference current. The resistance value of the pull-up resistor circuit is less than the resistance value of the pull-down resistor circuit.

20. The device according to claim 16, wherein, The pre-driver is also configured to disconnect the pull-down resistor circuit from the first node and disconnect the current source from the second node based on the first data having a fourth value.

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