Ultra-low delay information transmission device and method based on FPGA (Field Programmable Gate Array) network
By directly transmitting real-time information in the FPGA network, the complexity and high cost caused by multi-network parallelism in existing technologies are solved, achieving ultra-low latency information transmission and high bandwidth utilization, thus reducing project complexity and cost.
Patent Information
- Application Number
- CN202511207296.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-27
- Publication Date
- 2025-11-25
AI Technical Summary
When existing FPGA networks are needed for ultra-low latency information transmission in scientific facilities such as the High Altitude Cosmic Ray Observatory and the Shanghai Hard X-ray Free Electron Laser, multiple networks need to be deployed in parallel, which increases complexity and cost. In addition, the standard Ethernet frame structure leads to low logic processing latency and low bandwidth utilization.
An ultra-low latency information transmission device based on FPGA network is adopted. Real-time information is divided into data characters and control characters through information segmentation layer, broadcast using switch, and transmitted directly at physical layer, reducing network frame buffering and logic processing latency and optimizing data transmission structure.
It achieves ultra-low latency information transmission, reduces reliance on dedicated networks, lowers project complexity and cost, while improving bandwidth utilization and approaching the theoretical limit of physical layer transmission.
Smart Images
Figure CN121012591A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of network communication technology, and in particular to an ultra-low latency information transmission device and method based on FPGA network. Background Technology
[0002] Currently, scientific facilities such as the High Altitude Cosmic Ray Observatory and the Shanghai Hard X-ray Free Electron Laser require the transmission of ultra-low latency information, such as interlocking and triggering messages. In these applications, dedicated networks are typically used to transmit these messages to ensure real-time performance and stability. Simultaneously, other networks exist in these applications, such as the White Rabbit time synchronization network or data networks. These networks are generally developed based on FPGAs (Field-Programmable Gate Arrays). For example, the White Rabbit time synchronization network uses Xilinx's FPGA GT module to implement the Ethernet physical layer (PHY). Currently, the parallel implementation of multiple networks increases both network complexity and project cost.
[0003] Meanwhile, in existing technologies, information transmission in FPGA networks is based on the standard Ethernet frame structure. Its latency mainly consists of fiber optic propagation time, PHY module decoding time, and network frame buffering time introduced by each module. Among these, fiber optic propagation time and PHY module decoding time are fixed physical delays that cannot be reduced. While network frame buffering time caused by logic processing can be reduced through code optimization, the network frame structure itself still contains certain inefficient overhead, failing to meet the requirements for ultra-low latency information transmission. Summary of the Invention
[0004] This invention provides an ultra-low latency information transmission device and method based on FPGA networks to solve the problems of existing technologies that require parallel deployment of FPGA networks (including time networks, data networks, etc.) and dedicated networks, resulting in high complexity and cost; information transmission based on Ethernet frame structures leads to logic processing delays, making it impossible to approach the theoretical minimum latency; and the standard frame structures used contain a large amount of protocol overhead (such as MAC addresses and check fields), occupying bandwidth resources and resulting in low bandwidth utilization.
[0005] A first aspect of the present invention provides an ultra-low latency information transmission device based on an FPGA network, comprising: a transmitting physical layer for constructing real-time information into real-time data packets; a switch connected to the transmitting physical layer for broadcasting the real-time data packets; and a receiving physical layer connected to the switch for receiving and releasing the real-time data packets, and sending the released real-time data packets to a target link layer.
[0006] Optionally, it also includes:
[0007] An information segmentation layer, which is connected to the physical layer of the sending end, is used to segment the real-time information into data characters and control characters.
[0008] Optionally, the transmitting end physical layer includes:
[0009] An Ethernet frame sending module is used to transmit the data characters; a real-time information sending module is used to transmit the control characters; a first buffer module, connected to the Ethernet frame sending module, is used to buffer the data characters to obtain buffered data characters; a multiplexer, connected to both the first buffer module and the real-time information sending module, is used to combine the control characters and the buffered data characters to obtain the real-time data packet; and an input interface, connected to the multiplexer, is used to transmit the real-time data packet to the switch.
[0010] Optionally, the control characters in the real-time data packet serve as identifiers, and the data characters in the real-time data packet represent actual data.
[0011] Optionally, the switch includes:
[0012] A first photoelectric conversion module, connected to the physical layer of the transmitting end, is used to receive the real-time data packet and perform electro-optical conversion on the real-time data packet to obtain an optical signal; a second photoelectric conversion module, connected to the first photoelectric conversion module, is used to perform photoelectric conversion on the optical signal to obtain a real-time data packet; multiple network ports, connected to the second photoelectric conversion module via an enable switch, are used to broadcast the real-time data packet to the physical layer of the receiving end.
[0013] Optionally, the receiver physical layer includes
[0014] The system includes: a receiving interface connected to the switch for receiving real-time data packets; a second buffer module connected to the receiving end for releasing the real-time data packets to obtain released data characters; an Ethernet frame processing module connected to the second buffer module for receiving the released data characters and sending them to the target link layer; and a real-time information receiving module connected to the receiving interface for sending control characters from the real-time data packets to the target link layer.
[0015] A second aspect of the present invention provides an ultra-low latency information transmission method based on an FPGA network, comprising the following steps:
[0016] The real-time information is constructed into real-time data packets by the sending end physical layer; the real-time data packets are broadcast using a switch; the real-time data packets are received and released by the receiving end physical layer, and the released real-time data packets are sent down to the target link layer.
[0017] A third aspect of the present invention provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the ultra-low latency information transmission method based on an FPGA network as described in the above embodiments.
[0018] A fourth aspect of the present invention provides a computer program product, which, when executed by a processor, implements the above-described ultra-low latency information transmission method based on an FPGA network.
[0019] A fifth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described ultra-low latency information transmission method based on an FPGA network.
[0020] The ultra-low latency information transmission device and method based on FPGA network proposed in this invention integrates ultra-low latency information transmission function in FPGA network, eliminating dependence on dedicated network; by optimizing data transmission structure, it reduces logic processing latency and approaches the theoretical limit of physical layer transmission; it improves bandwidth utilization and is compatible with existing standard Ethernet communication.
[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0022] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0023] Figure 1 This is a block diagram of an ultra-low latency information transmission device based on an FPGA network provided in an embodiment of the present invention.
[0024] Figure 2 This is a schematic diagram illustrating the specific execution of an ultra-low latency information transmission device based on an FPGA network, as provided in an embodiment of the present invention.
[0025] Figure 3 A flowchart illustrating a method for an ultra-low latency information transmission device based on an FPGA network, as provided in an embodiment of the present invention.
[0026] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0027] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.
[0028] The following description, with reference to the accompanying drawings, describes an embodiment of the ultra-low latency information transmission device and method based on an FPGA network.
[0029] Figure 1 This is a block diagram of an ultra-low latency information transmission device based on an FPGA network provided in an embodiment of the present invention.
[0030] like Figure 1 As shown, the ultra-low latency information transmission device 10 based on FPGA network includes: an information partitioning layer 101, a transmitting end physical layer 102, a switch 103, and a receiving end physical layer 104.
[0031] The information segmentation layer 101 is used to divide real-time information into data characters and control characters. The sending physical layer 102, connected to the information segmentation layer 101, is used to construct real-time data packets from the real-time information. The switch 103, connected to the sending physical layer 102, is used to broadcast the real-time data packets. The receiving physical layer 104, connected to the switch 103, is used to receive and release the real-time data packets, and then forward the released real-time data packets to the target link layer.
[0032] In some embodiments of the present invention, the traditional network frame structure is abandoned, and real-time information is received and sent directly at the Ethernet physical layer. The information partitioning layer 101 can use 8b / 10b encoding to divide the real-time information into D characters (i.e., data characters) and K characters (i.e., control characters). There are 12 K characters in total. The standard Ethernet physical layer uses 5 of them, and the remaining 7 unused K characters are used as identifiers for the real-time information.
[0033] In some embodiments, such as Figure 2 As shown, in this embodiment of the invention, the transmitting end physical layer 102 adds a real-time information transmission module and a multiplexer before the input interface, and adds a buffer (i.e., a first buffer module) to the standard Ethernet transmission interface to ensure that the data being transmitted by the standard Ethernet is not lost when real-time information is inserted.
[0034] Specifically, such as Figure 2As shown, the physical layer 102 of the transmitting end includes: an Ethernet frame transmitting module, a real-time information transmitting module, a first buffer module, a multiplexer, and an input interface. The Ethernet frame transmitting module is connected to the information partitioning layer 101 to transmit the D character; the real-time information transmitting module is connected to the information partitioning layer 101 to transmit the K character; the first buffer module is connected to the Ethernet frame transmitting module to buffer the D character, reading it step-by-step to avoid data loss or congestion due to rate mismatch, thus obtaining the buffered D character; the multiplexer is connected to both the first buffer module and the real-time information transmitting module, and is used to combine the K character and the buffered D character to construct a small real-time data packet where real-time information and standard data coexist. Each real-time data packet contains an identifier (K character) and a small amount of data (D character), typically a few bytes, to meet the needs of real-time information transmission; the input interface is connected to the multiplexer and is used to transmit the real-time data packet to the switch 103.
[0035] In some embodiments, such as Figure 2 As shown, this embodiment of the invention designs a switch 103. This switch 103 supports real-time information broadcast mode in a multi-node network and has multi-node scalability and compatibility. After receiving a small real-time data packet, the switch 103 immediately forwards it to all network ports for broadcasting. At the same time, each port of the switch 103 is equipped with an enable switch for real-time information transmission. In the off state, it can directly connect to standard Ethernet devices.
[0036] Specifically, such as Figure 2 As shown, the switch 103 includes a first optoelectronic conversion module, a second optoelectronic conversion module, and multiple network ports. The first optoelectronic conversion module is connected to the transmitting end physical layer 102 and is used to receive real-time data packets and perform electro-optical conversion on the real-time data packets to obtain optical signals. The second optoelectronic conversion module is connected to the first optoelectronic conversion module and is used to perform optoelectronic conversion on the optical signals to obtain real-time data packets. The multiple network ports are connected to the second optoelectronic conversion module via enable switches and are used to broadcast real-time data packets to the receiving end physical layer.
[0037] In some embodiments, such as Figure 2 As shown, in this embodiment of the invention, a buffer is also added after the receiving interface of the physical layer 104 at the receiving end. After receiving a standard network frame (i.e., receiving the inserted K-character real-time data packet), the buffered data is released and then sent down to the link layer to ensure that the data received by the link layer at the receiving end is continuous.
[0038] Specifically, such as Figure 2As shown, the physical layer 104 of the receiving end includes: a receiving interface, a second buffer module, an Ethernet frame processing module, and a real-time information receiving module. The receiving interface is connected to multiple network ports of the switch and is used to receive real-time data packets; the second buffer module is connected to the receiving interface and is used to release the D character from the real-time data packets to obtain the released D character; the Ethernet frame processing module is connected to the second buffer module and is used to receive the released D character and send it to the target link layer; the real-time information receiving module is connected to the receiving interface and is used to send the K character from the real-time data packets to the target link layer.
[0039] The specific workflow of the ultra-low latency information transmission device based on FPGA network proposed in this embodiment of the invention is described below.
[0040] In the information partitioning layer 101, 8b / 10b encoding is used to divide real-time information into D characters and K characters. The D characters are transmitted using the Ethernet frame transmission module in the transmitting end physical layer 102. During transmission, the first buffer module buffers the D characters to read them gradually, avoiding data loss or congestion due to rate mismatch. Simultaneously, the K characters are transmitted using the real-time information transmission module. A multiplexer combines the K characters and the buffered D characters to construct a small real-time data packet where real-time information and standard data coexist. The small real-time data packet is broadcast to the receiving end physical layer 104 using the switch 103. The receiving interface in the receiving end physical layer 104 first receives the real-time data packet. The second buffer module releases the D characters from the real-time data packet, and the Ethernet frame processing module sends the released D characters to the target link layer. Then, the real-time information receiving module sends the K characters from the real-time data packet to the target link layer. Therefore, this embodiment of the invention allows the FPGA network to transmit interlocking and other information, realizing the merging of the FPGA network and corresponding dedicated networks, reducing the number of networks in the project.
[0041] In summary, the ultra-low latency information transmission device based on FPGA network proposed in the embodiments of the present invention has the following characteristics:
[0042] Beneficial effects:
[0043] (1) Real-time information is transmitted directly at the physical layer by abandoning the network frame structure, which reduces the latency caused by network frame buffering and logical processing and approaches the theoretical minimum latency.
[0044] (2) Real-time data packets contain only a small amount of data, avoiding the invalid overhead of traditional network frames and improving bandwidth utilization;
[0045] (3) Integrating ultra-low latency information transmission function into FPGA network reduces the need for dedicated network and lowers project complexity and cost;
[0046] (4) Through the buffer design of the sending and receiving ends, the impact of real-time information transmission on standard Ethernet data is minimized, only increasing the constant buffer delay.
[0047] Next, referring to the accompanying drawings, the ultra-low latency information transmission method based on FPGA network proposed according to an embodiment of the present invention is described.
[0048] Figure 3 This is a flowchart illustrating an ultra-low latency information transmission method based on an FPGA network, as provided in an embodiment of the present invention.
[0049] like Figure 3 As shown, this ultra-low latency information transmission method based on FPGA networks includes the following steps:
[0050] In step S301, the real-time information is constructed into a real-time data packet through the physical layer of the sending end.
[0051] Specifically, real-time information is pre-divided into data characters and control characters through an information segmentation layer. Data characters are transmitted by the Ethernet frame sending module. During transmission, the data characters are buffered by the first buffer module to read them step by step. At the same time, control characters are transmitted by the real-time information sending module. The control characters and the buffered data characters are combined by a multiplexer to construct a small real-time data packet in which real-time information and standard data coexist.
[0052] In step S302, the switch is used to broadcast real-time data packets.
[0053] Specifically, the small real-time data is broadcast by using the electro-optical conversion in switch 103 for bidirectional conversion.
[0054] In step S303, the real-time data packet is received and released by the physical layer of the receiving end, and the released real-time data packet is sent down to the target link layer.
[0055] Specifically, the receiving interface in the physical layer of the receiving end receives small real-time data packets. After receiving the small real-time data packets, the D character in the data packets is released, and the released D character is sent to the target link layer. At the same time, the real-time information receiving module sends the K character in the real-time data packets to the target link layer.
[0056] It should be noted that the foregoing explanation of the embodiment of the ultra-low latency information transmission device based on FPGA network also applies to the ultra-low latency information transmission method based on FPGA network in this embodiment, and will not be repeated here.
[0057] The ultra-low latency information transmission method based on FPGA network proposed in this invention has the following advantages:
[0058] (1) Real-time information is transmitted directly at the physical layer by abandoning the network frame structure, which reduces the latency caused by network frame buffering and logical processing and approaches the theoretical minimum latency.
[0059] (2) Real-time data packets contain only a small amount of data, avoiding the invalid overhead of traditional network frames and improving bandwidth utilization;
[0060] (3) Integrating ultra-low latency information transmission function into FPGA network reduces the need for dedicated network and lowers project complexity and cost;
[0061] (4) Through the buffer design of the sending and receiving ends, the impact of real-time information transmission on standard Ethernet data is minimized, only increasing the constant buffer delay.
[0062] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.
[0063] The electronic device may include:
[0064] The memory 401, the processor 402, and the computer program stored on the memory 401 and capable of running on the processor 402.
[0065] When the processor 402 executes the program, it implements the ultra-low latency information transmission method based on the FPGA network provided in the above embodiments.
[0066] Furthermore, electronic devices also include:
[0067] Communication interface 403 is used for communication between memory 401 and processor 402.
[0068] The memory 401 is used to store computer programs that can run on the processor 402.
[0069] The memory 401 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.
[0070] If the memory 401, processor 402, and communication interface 403 are implemented independently, then the communication interface 403, memory 401, and processor 402 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0071] Optionally, in a specific implementation, if the memory 401, processor 402, and communication interface 403 are integrated on a single chip, then the memory 401, processor 402, and communication interface 403 can communicate with each other through an internal interface.
[0072] Processor 402 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
[0073] This invention also provides a computer program product, which, when executed by a processor, implements the above-described ultra-low latency information transmission method based on an FPGA network.
[0074] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described ultra-low latency information transmission method based on an FPGA network.
[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0076] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0077] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.
[0078] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.
[0079] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0080] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
[0081] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.
[0082] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.
Claims
1. An ultra-low latency information transmission device based on an FPGA network, characterized in that, include: The sending end physical layer is used to construct real-time data packets from real-time information; A switch, connected to the physical layer of the sending end, is used to broadcast the real-time data packets; The receiving end physical layer is connected to the switch and is used to receive and release the real-time data packets, and then send the released real-time data packets to the target link layer.
2. The ultra-low latency information transmission device based on FPGA network according to claim 1, characterized in that, Also includes: An information segmentation layer, which is connected to the physical layer of the sending end, is used to segment the real-time information into data characters and control characters.
3. The ultra-low latency information transmission device based on FPGA network according to claim 2, characterized in that, The transmitting end physical layer includes: An Ethernet frame sending module is used to transmit the data characters; A real-time information sending module is used to transmit the control characters; A first buffer module, connected to the Ethernet frame sending module, is used to buffer the data characters to obtain buffered data characters. A multiplexer, which is connected to the first buffer module and the real-time information sending module respectively, is used to combine the control characters and the buffered data characters to obtain the real-time data packet; An input interface, which is connected to the multiplexer, is used to transmit the real-time data packets to the switch.
4. The ultra-low latency information transmission device based on FPGA network according to claim 1, characterized in that, The control characters in the real-time data packet serve as identifiers, while the data characters in the real-time data packet represent the actual data.
5. The ultra-low latency information transmission device based on FPGA network according to claim 1, characterized in that, The switch includes: A first photoelectric conversion module, connected to the physical layer of the transmitting end, is used to receive the real-time data packet and perform electro-optical conversion on the real-time data packet to obtain an optical signal; The second photoelectric conversion module, connected to the first photoelectric conversion module, is used to perform photoelectric conversion on the optical signal to obtain a real-time data packet; Multiple network ports, which are connected to the second photoelectric conversion module via an enable switch, are used to broadcast the real-time data packets to the physical layer of the receiving end.
6. The ultra-low latency information transmission device based on FPGA network according to claim 1, characterized in that, The receiver physical layer includes A receiving interface, which is connected to the switch, is used to receive the real-time data packets; The second buffer module, connected to the receiving end, is used to release the real-time data packet to obtain the released data characters; An Ethernet frame processing module, which is connected to the second buffer module, is used to receive the released data characters and send them to the target link layer; A real-time information receiving module, which is connected to the receiving interface, is used to send the control characters of the real-time data packet to the target link layer.
7. A method for ultra-low latency information transmission based on FPGA networks, characterized in that, The ultra-low latency information transmission device based on an FPGA network according to any one of claims 1-6 is characterized by comprising the following steps: The real-time information is constructed into real-time data packets through the physical layer of the sending end; The real-time data packets are broadcast using a switch; The real-time data packets are received and released by the physical layer of the receiving end, and then the released real-time data packets are sent down to the target link layer.
8. An electronic device, characterized in that, include: The memory, the processor, and the computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the ultra-low latency information transmission method based on the FPGA network as described in claim 7.
9. A computer program product, characterized in that, When the computer program / instruction is executed by the processor, it implements the ultra-low latency information transmission method based on FPGA network as described in claim 7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the ultra-low latency information transmission method based on the FPGA network as described in claim 7.