Solar cell, preparation method thereof and solar cell production line

Abstract

The embodiment of the invention relates to the field of photovoltaic technology, and provides a solar cell and a preparation method thereof, and a solar cell production line. The preparation method of the solar cell comprises the following steps: forming a first lamination layer comprising a first tunneling layer, a boron-doped polycrystalline silicon layer and a first mask layer on a first surface of an N-type silicon substrate; corresponding parts of the first lamination layer and the N-type silicon substrate in the second region and at least part of the spacer region are removed, so that a groove is formed in the N-type silicon substrate, and the groove surface, formed in the N-type silicon substrate, of the groove is arc-shaped; forming a second lamination layer comprising a second tunneling layer, a phosphorus-doped polycrystalline silicon layer and a second mask layer which are laminated in sequence on the whole side of the first surface; the winding plating layer is removed, the winding plating layer is wound and plated on the second surface of the N-type silicon substrate when the first lamination layer and / or the second lamination layer are / is formed, and the second surface is opposite to the first surface; removing corresponding parts of the second lamination layer in the first region and the spacer region; and removing the first mask layer and the second mask layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of photovoltaic, in particular, to a solar cell, a preparation method thereof and a solar cell production line. BACKGROUND

[0002] TBC solar cells are a combination of tunnel oxide passivating contacts (TOPCon) and back contact (BC) technology. However, the existing preparation process of TBC solar cells has a low yield. SUMMARY

[0003] Therefore, it is necessary to provide a solar cell, a preparation method thereof and a solar cell production line to solve the technical problem of low yield of the existing preparation process of TBC solar cells.

[0004] The first aspect of the present application provides a preparation method of a solar cell. The preparation method of the solar cell comprises: forming a first stack on a first surface of an N-type silicon substrate, the first stack comprising a first tunnel layer, a boron-doped polysilicon layer and a first mask layer which are sequentially stacked; the first surface is defined with alternately arranged first regions, second regions and interval regions between adjacent first regions and second regions, removing the first stack and the corresponding part of the N-type silicon substrate in the second regions and at least part of the interval regions, thereby forming a groove in the N-type silicon substrate, the groove surface formed in the N-type silicon substrate being arc-shaped; forming a second stack on the side of the first surface, the second stack comprising a second tunnel layer, a phosphorus-doped polysilicon layer and a second mask layer which are sequentially stacked; removing a wrap-around plating layer formed on a second surface of the N-type silicon substrate during the formation of the first stack and / or the formation of the second stack, wherein the second surface is opposite to the first surface; removing the corresponding part of the second stack in the first regions and the interval regions; and removing the first mask layer and the second mask layer.

[0005] In the preparation method of the solar cell of the embodiments of the present application, the groove formed in the N-type silicon substrate has an arc-shaped groove surface, which is beneficial to reduce mechanical stress concentration and thus reduce the breakage rate of the solar cell, and also balances the insulation effect and the formation of leakage paths.

[0006] In some embodiments, the step of forming the groove includes: irradiating a region on a first mask layer corresponding to a second region and at least a partial spacer region with a first laser; and removing a first stack and a portion of the N-type silicon substrate below the region irradiated by the first laser by an alkaline etching process to form a groove, the groove being teardrop-shaped to have an arc-shaped groove surface.

[0007] In some embodiments, in the step of removing the first stack and part of the N-type silicon substrate below the area irradiated by the first laser to form a groove, the alkaline etching process uses the same alkaline washing solution to extend the alkaline etching time, so that the alkaline washing solution removes the boron-doped polysilicon layer below the area irradiated by the first laser, etches through the first tunneling layer below the area irradiated by the first laser, and forms a groove on the surface of the N-type silicon substrate, the groove being roughly in the shape of a smooth teardrop.

[0008] In some embodiments, the step of forming the first stack includes: forming a first tunneling layer and a first intrinsic silicon layer sequentially on a first surface by low-pressure chemical vapor deposition; and subjecting the first intrinsic silicon layer to boron diffusion treatment to convert the first intrinsic silicon layer into a boron-doped polycrystalline silicon layer, and forming a borosilicate glass layer on the surface of the boron-doped polycrystalline silicon layer, wherein the first mask layer includes the borosilicate glass layer.

[0009] In some embodiments, the step of forming the second stack includes: forming a second tunneling layer and a second intrinsic silicon layer sequentially on the side where the first surface is located by low-pressure chemical vapor deposition; and converting the second intrinsic silicon layer into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion treatment, and forming a phosphorus-silicon glass layer on the surface of the phosphorus-doped polycrystalline silicon layer, wherein the second mask layer includes the phosphorus-silicon glass layer.

[0010] In some embodiments, the step of removing the corresponding portions of the second stacked layer in the first region and the spacer region includes: irradiating the regions on the second mask layer corresponding to the first region and the spacer region with a second laser; and simultaneously removing the second stacked layer below the irradiated area by an alkaline etching process, and texturing the exposed portions of the second surface and the first surface in the spacer region.

[0011] In some embodiments, prior to forming the first stack, the second surface of the N-type silicon substrate is texturized to form a preliminary textured surface. In the step of removing corresponding portions of the second stack in the first region and the spacer region, the exposed portions of the second surface and the first surface in the spacer region are texturized to form a final textured surface on the second surface.

[0012] In some embodiments, the method for fabricating a solar cell further includes at least one of the following: Before forming the first stack, the N-type silicon substrate is polished on both sides; After removing the first mask layer and the second mask layer, a first passivation layer is formed on the side where the first surface is located, and a second passivation layer is formed on the side where the second surface is located; After removing the first mask layer and the second mask layer, a first anti-reflection layer is formed on the side where the first surface is located, and a second anti-reflection layer is formed on the side where the second surface is located; After removing the first and second mask layers, multiple gate lines are arranged on the side where the first surface is located, so that some gate lines are in electrical contact with the boron-doped polysilicon layer and the other part of the gate lines are in electrical contact with the phosphorus-doped polysilicon layer.

[0013] A second aspect of this application provides a solar cell. The solar cell includes: An N-type silicon substrate has a first surface and a second surface opposite to each other. The first surface defines an alternating first region, a second region, and a spacer region located between adjacent first and second regions. The second region and the spacer region have arc-shaped grooves. Both the first tunneling layer and the boron-doped polysilicon layer are located in the first region, wherein the first tunneling layer contacts the first surface, and the boron-doped polysilicon layer is located above the first tunneling layer; A second tunneling layer and a phosphorus-doped polysilicon layer are both located in the second region, wherein the second tunneling layer contacts the groove surface of the groove, and the phosphorus-doped polysilicon layer is located above the second tunneling layer; and Multiple gate lines, some of which are in electrical contact with the boron-doped polysilicon layer, and others of which are in electrical contact with the phosphorus-doped polysilicon layer.

[0014] The solar cell of the second aspect of this application has at least the same advantages as the solar cell of the first aspect of this application in terms of its preparation method, which will not be repeated here.

[0015] In some embodiments, the solar cell further includes a first passivation layer covering a boron-doped polycrystalline silicon layer, a phosphorus-doped polycrystalline silicon layer, and the exposed N-type silicon substrate surface within the spacer region.

[0016] A third aspect of this application provides a solar cell production line. The solar cell production line includes: A wet processing apparatus for double-sided polishing of an N-type silicon substrate, the N-type silicon substrate having opposing first and second surfaces, the first surface defining alternating first and second regions and a spacer region located between adjacent first and second regions; A first low-pressure chemical vapor deposition apparatus is used to sequentially form a first tunneling layer and a first intrinsic silicon layer on the first surface; A first diffusion apparatus is used to convert the first intrinsic silicon layer into a boron-doped polycrystalline silicon layer by boron diffusion treatment, and to form a borosilicate glass layer as a first mask layer, thereby obtaining a first stack. A first laser device is used to emit a first laser to irradiate the area on the first mask layer corresponding to the second region and the interval region; The first alkaline washing equipment is used to remove the first stack and part of the N-type silicon substrate below the area irradiated by the first laser by alkaline etching, so as to form a groove in the N-type silicon substrate, wherein the groove surface formed in the N-type silicon substrate is arc-shaped. A second low-pressure chemical vapor deposition apparatus is used to sequentially form a second tunneling layer and a second intrinsic silicon layer on the side where the first surface is located. The second diffusion device is used to convert the second intrinsic silicon layer into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion treatment, and to form a phosphorus-silicon glass layer as a second mask layer, thereby obtaining the second stack. A second laser device is used to emit a second laser to irradiate the area on the second mask layer corresponding to the first region and the interval region; A pickling device for removing the coating layer deposited around the second surface of the N-type silicon substrate during the formation of the first stack and / or the formation of the second stack; The second alkaline washing equipment is used to remove the second stack below the area irradiated by the second laser, at least texturing the exposed portion of the first surface in the interval area, and removing the first mask layer and the second mask layer. A passivation layer deposition apparatus for forming a first passivation layer on the side containing the first surface and a second passivation layer on the side containing the second surface; and An antireflection layer deposition apparatus is used to form a first antireflection layer on the side where the first surface is located, and to form a second antireflection layer on the side where the second surface is located.

[0017] The solar cell production line of the third aspect of this application has at least the same advantages as the solar cell preparation method of the first aspect of this application, and will not be described in detail here.

[0018] In some embodiments, a texturing machine is provided between the wet processing equipment and the first low-pressure chemical vapor deposition equipment, the texturing machine texturing at least the second side of the N-type silicon substrate.

[0019] In some embodiments, the second alkaline washing equipment is used to fabricate the exposed portion of the first surface within the interval area while simultaneously fabricating the second surface.

[0020] In some embodiments, the first antireflection layer includes a first silicon nitride layer; the second antireflection layer includes a second silicon nitride layer and a silicon oxide layer stacked sequentially. The antireflection layer deposition apparatus includes a first plasma-enhanced chemical vapor deposition apparatus and a second plasma-enhanced chemical vapor deposition apparatus. The first plasma-enhanced chemical vapor deposition apparatus is used to form the first silicon nitride layer and the second silicon nitride layer. The second plasma-enhanced chemical vapor deposition apparatus is used to form the silicon oxide layer. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a solar cell according to an embodiment of this application.

[0022] Figure 2 This is a cross-sectional structural diagram of double-sided polishing of an N-type silicon substrate in a method for fabricating a solar cell according to an embodiment of this application.

[0023] Figure 3 This is a cross-sectional schematic diagram of a method for fabricating a solar cell according to an embodiment of the present application, in which a first tunneling layer and a first intrinsic silicon layer are formed on a first surface of an N-type silicon substrate.

[0024] Figure 4 This is a cross-sectional view of a method for fabricating a solar cell according to an embodiment of the present application, after a first stack is formed on the first surface of an N-type silicon substrate.

[0025] Figure 5 This is a cross-sectional schematic diagram of a method for fabricating a solar cell according to an embodiment of this application, in which a first laser is used to irradiate the regions on a first mask layer corresponding to the second region and the spacer region.

[0026] Figure 6 This is a planar schematic diagram of a method for fabricating a solar cell according to an embodiment of this application, showing the formation of a groove in an N-type silicon substrate.

[0027] Figure 7 This is a cross-sectional view of a method for fabricating a solar cell according to an embodiment of this application, after a groove is formed in an N-type silicon substrate.

[0028] Figure 8 A schematic cross-sectional view of a method for fabricating a solar cell according to an embodiment of this application, wherein a second tunneling layer and a second intrinsic silicon layer are formed on the entire side of the first surface of an N-type silicon substrate.

[0029] Figure 9 This is a cross-sectional view of a method for fabricating a solar cell according to an embodiment of the present application, after a second stack is formed on the side of the first surface of an N-type silicon substrate.

[0030] Figure 10This is a cross-sectional schematic diagram of a method for fabricating a solar cell according to an embodiment of this application, in which a second laser is used to irradiate the regions on a second mask layer corresponding to the first region and the spacer region.

[0031] Figure 11 This is a cross-sectional view of a method for fabricating a solar cell according to an embodiment of this application, after removing the first mask layer and the second mask layer.

[0032] Figure 12 This is a cross-sectional view of a solar cell fabrication method according to an embodiment of this application, after the grid lines have been formed.

[0033] Figure 13 This is a schematic diagram of the structure of a solar cell production line according to an embodiment of this application.

[0034] Explanation of key component symbols: 100: Solar cell; 11: N-type silicon substrate; 11a: First surface; 11b: Second surface; 11c: Side surface; 11r: Groove; 12: First stack; 121: First tunneling layer; 122a: First intrinsic silicon layer; 122: Boron-doped polysilicon layer; 123: First mask layer; 13: Second stack; 131: Second tunneling layer; 132a: Second intrinsic silicon layer; 132: Phosphorus-doped polycrystalline silicon layer; 133: Second mask layer; 14a: First passivation layer; 14b: Second passivation layer; 15a: First antireflection layer; 151a: First silicon nitride layer; 15b: Second antireflection layer; 151b: Second silicon nitride layer; 152b: Silicon oxide layer; 16: Grid line; 200: Solar cell production line; 201: Wet processing equipment; 202: First low-pressure chemical vapor deposition equipment; 203: First diffusion equipment; 204: First laser equipment; 205: First alkaline washing equipment; 206: Second low-pressure chemical vapor deposition equipment; 207: Second diffusion equipment; 208: Second laser equipment; 209: Pickling equipment; 210: Second alkaline washing equipment; 211: Passivation layer deposition equipment; 212: Antireflection layer deposition equipment; A1: Zone 1; A2: Zone 2; G: Interval Zone; L1: First laser; L2: Second laser; X: First direction; Z: Thickness direction.

[0035] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0036] Figure 1 This is a method for fabricating a solar cell according to an embodiment of this application. For example... Figure 1 As shown, the method for fabricating this solar cell includes steps S10 to S40. Depending on different requirements, the order of some steps or sub-steps in the method for fabricating this solar cell can be changed, and some steps or sub-steps can be omitted or combined.

[0037] Step S10: A first stack is formed on the first surface of an N-type silicon substrate. The first stack includes a first tunneling layer, a boron-doped polysilicon layer, and a first mask layer stacked sequentially.

[0038] In some embodiments, step S10 includes steps S11 to S13.

[0039] Step S11: Polish the N-type silicon substrate on both sides using a wet processing device.

[0040] like Figure 2 As shown, the N-type silicon substrate 11 includes a first surface 11a and a second surface 11b opposite to each other, and a side surface 11c connecting the first surface 11a and the second surface 11b. After double-sided polishing, the first surface 11a and the second surface 11b of the N-type silicon substrate 11 are flat. It should be noted that the N-type silicon substrate 11 is also referred to as a silicon wafer in the following text, the first surface 11a of the N-type silicon substrate 11 is the back surface, and the second surface 11b of the N-type silicon substrate 11 is the front surface.

[0041] In some embodiments, the wet processing equipment includes a wet alkaline washing equipment. Step S11 includes carrying an N-type silicon substrate 11 in a first carrier basket, placing the first carrier basket carrying the N-type silicon substrate 11 into the wet alkaline washing equipment, and performing double-sided polishing on the N-type silicon substrate 11 through an alkaline washing step to deposit a polycrystalline silicon layer on the surface of the N-type silicon substrate 11.

[0042] In some embodiments, the wet processing apparatus further includes a wet texturing apparatus that can perform texturing on the second surface 11b of the N-type silicon substrate 11. The texturized surface after the texturing process can be a preliminary texturing surface, meaning it can be further texturized in a secondary process to form the final texturing surface. Alternatively, the texturized surface after the texturing process can directly form the final texturing surface.

[0043] Step S12: A first tunneling layer and a first intrinsic silicon layer are sequentially formed on the first surface by low-pressure chemical vapor deposition.

[0044] like Figure 3As shown, the first tunneling layer 121 is located on the first surface 11a, and the first intrinsic silicon layer 122a is located on the surface of the first tunneling layer 121 opposite to the first surface 11a.

[0045] In some embodiments, a first crystal boat carrying a silicon wafer is placed inside the furnace tube of a first low-pressure chemical vapor deposition (LPCVD) apparatus, the furnace door is sealed, a vacuum is drawn and the temperature is raised, and then process gas is introduced to deposit a first tunneling layer 121 (such as 1 nm to 2 nm thick SiO2) and a first intrinsic silicon layer 122a on the first surface 11a of the silicon wafer.

[0046] It should be noted that during the deposition of the first tunneling layer 121 and the second intrinsic silicon layer 122a on the first surface 11a, it is easy to cause circumferential deposition, that is, the tunneling layer and intrinsic silicon layer are also deposited on the second surface 11b and the side area between the first surface 11a and the second surface 11b. The circumferentially deposited tunneling layer and intrinsic silicon layer can be removed in subsequent processes.

[0047] In some embodiments, the deposition of the first tunneling layer 121 and the first intrinsic silicon layer 122a is performed in two steps. After the deposition of the first tunneling layer 121, the furnace tube of the first LPCVD apparatus is purged, and then a silicon source is introduced to deposit the first intrinsic silicon layer 122a.

[0048] In some embodiments, the deposition of the first intrinsic silicon layer 122a is performed twice, intermittently, within the first LPCVD apparatus to generate a thicker first intrinsic silicon layer 122a. Specifically, after depositing a portion of the first intrinsic silicon layer 122a within the first LPCVD apparatus, the furnace tubes of the first LPCVD apparatus are purged. The first LPCVD apparatus is then evacuated and heated again, and then process gases are introduced to deposit another portion of the first intrinsic silicon layer 122a.

[0049] After the deposition of the first intrinsic silicon layer 122a is completed in the first LPCVD process, the first wafer carrier is removed from the furnace of the first LPCVD equipment. The silicon wafer after the first LPCVD process is then removed and placed into the second wafer carrier basket. The time from when the untreated silicon wafer enters the first LPCVD equipment to when the silicon wafer after the first LPCVD process is removed and placed into the second wafer carrier basket can be, but is not limited to, 240 minutes.

[0050] In some embodiments, the processing temperature of the first LPCVD apparatus is increased, making the first intrinsic silicon layer 122a an intrinsic polycrystalline silicon layer. In some embodiments, the processing temperature of the first LPCVD apparatus is decreased, making the first intrinsic silicon layer 122a an intrinsic silicon layer composed of a mixture of intrinsic polycrystalline silicon and intrinsic amorphous silicon; or even, the first intrinsic silicon layer 122a may be an intrinsic amorphous silicon layer.

[0051] Step S13: Perform boron diffusion treatment on the first intrinsic silicon layer to transform the first intrinsic silicon layer into a boron-doped polycrystalline silicon layer, and form a borosilicate glass layer on the surface of the boron-doped polycrystalline silicon layer. The first mask layer includes the borosilicate glass layer.

[0052] like Figure 4 As shown, the first stack 12 includes a first tunneling layer 121, a boron-doped polysilicon layer 122, and a first mask layer 123.

[0053] In some embodiments, the first mask layer 123, in addition to the borosilicate glass layer, may also include an additionally formed silicon oxide layer 152b, etc.

[0054] In some embodiments, a second carrier basket is transported to the first diffusion equipment, and a silicon wafer is removed from the second carrier basket and placed into a second crystal boat. The second crystal boat carrying the silicon wafer is placed into the furnace tube of the first diffusion equipment, the furnace door is sealed, and the temperature is raised. Then, a boron source is introduced, and the temperature is adjusted so that a boron silicate glass (BSG) layer is formed on the surface of the first intrinsic silicon layer 122a of the first side 11a of the silicon wafer. Boron diffuses inward through the BSG layer, causing the intrinsic silicon layer to be doped with boron to form a P-poly layer (i.e., a boron-doped polycrystalline silicon layer). During this process, the grain growth is more robust, making the areas not irradiated by the laser less susceptible to damage from the laser grooving step in subsequent steps. The second crystal boat carrying the boron-diffused silicon wafer is removed from the furnace of the first diffusion equipment, and the boron-diffused silicon wafer is removed and carried into a third carrier basket. The P-poly layer formed in this step forms a PN junction with the silicon wafer. This operation can take, but is not limited to, 140 minutes.

[0055] When the first intrinsic silicon layer 122a contains amorphous silicon, the amorphous silicon can be crystallized and converted into polycrystalline silicon after being treated at high temperature in the first diffusion device.

[0056] Step S20: The first surface is defined by alternating first regions, second regions and spacer regions located between adjacent first and second regions. The corresponding portions of the first stack and the N-type silicon substrate in the second region and at least part of the spacer regions are removed, thereby forming a groove in the N-type silicon substrate. The groove formed on the N-type silicon substrate is arc-shaped.

[0057] In some embodiments, step S20 includes steps S21 to S22.

[0058] Step S21: Use the first laser to irradiate the area on the first mask layer corresponding to the second region and the spacer region.

[0059] like Figure 5 As shown, the first region A1 and the second region A2 are arranged alternately along a first direction X, which is perpendicular to the thickness direction Z of the N-type silicon substrate 11. Each adjacent first region A1 and second region A2 is separated by a gap region G. A first laser L1 irradiates the position on the first mask layer 123 corresponding to the second region A2 and at least a portion of the gap region G, while the position on the first mask layer 123 corresponding to the first region A1 is not irradiated by the first laser L1.

[0060] In some embodiments, the silicon wafer after the boron diffusion process is removed from the third carrier basket and placed onto the conveyor belt of the first laser device, with the first surface 11a of the silicon wafer facing the laser generator of the first laser device. The laser generator of the first laser device emits a dot matrix laser to scan the second region A2 and at least part of the spacing region G of the first surface 11a of the silicon wafer, but keeps the first region A1 unilluminated. The silicon wafer, with the second region A2 and the spacing region G irradiated by the laser, is removed from the first laser device and placed into the fourth carrier basket.

[0061] In some embodiments, the silicon wafer after the boron diffusion process is removed from the third support basket and placed into the positioning structure of the first laser device, with the first surface 11a of the silicon wafer facing the laser generator of the first laser device. The laser generator of the first laser device emits a dot matrix laser to scan the second region A2 and at least part of the spacing region G of the first surface 11a of the silicon wafer, but keeps the first region A1 unilluminated. The silicon wafer, with the second region A2 and the spacing region G irradiated by the laser, is removed from the positioning structure of the first laser device and placed into the fourth support basket.

[0062] Step S22: Remove the first stack and part of the N-type silicon substrate below the area irradiated by the first laser by alkaline etching process to form a groove.

[0063] Please refer to the following: Figure 6 and Figure 7 The first stack 12 of the second region A2 and the spacer region G is removed, and the N-type silicon substrate 11 of the second region A2 and the spacer region G is partially etched to form a groove 11r. The first stack 12 of the first region A1 is retained due to the action of the first mask layer 123. The groove 11r formed in the N-type silicon substrate has an arc-shaped groove surface. The arc protrudes towards the side facing the second surface 11b.

[0064] In some embodiments, a fourth carrier basket is transported to a first alkaline washing device, and the laser-irradiated silicon wafer carried by the fourth carrier basket is placed into the first alkaline washing device for alkaline etching.

[0065] Because the BSG layers of the second region A2 and the spacer region G form a loose structure due to laser irradiation, the BSG layers of the second region A2 and the spacer region G are washed away during the first alkaline washing process, and the P-poly layer located below the BSG layer in the second region A2 and the spacer region G is etched. The first tunneling layer 121 is silicon oxide, and it is generally believed that silicon oxide does not react with the alkaline washing solution in the alkaline etching process. However, on the one hand, the first tunneling layer 121 is only about 2nm, which is thin enough, and on the other hand, the alkaline etching time is extended in this application, so that the alkaline washing solution etches through the first tunneling layer 121, and makes the groove 11r roughly appear as a smooth teardrop shape, that is, the groove surface formed by the groove 11r on the N-type silicon substrate is arc-shaped rather than sharp or flat. The fourth carrier basket is removed from the first alkaline washing equipment. It should be noted that the first region A1 is not etched by alkaline polishing due to the protection of the dense BSG layer, and the BSG layer of the first region A1 also protects the P-poly layer and the first tunneling layer 121 below it. Understandably, the composition of the alkaline cleaning solution may vary slightly in different alkaline etching processes. However, those skilled in the art, based on the need to etch through the first tunneling layer 121 and etch the silicon substrate into a droplet shape, can determine the corresponding etching time by testing the alkaline cleaning solution used.

[0066] In some embodiments, the teardrop-shaped groove 11r has a gradually decreasing curvature from near the interface between the N-type silicon substrate and the first tunneling layer 121 into the depth of the N-type silicon substrate.

[0067] In some embodiments, the first alkaline washing equipment is a chain-type alkaline washing equipment. In some embodiments, the first alkaline washing equipment is a tank-type alkaline washing equipment.

[0068] By making the groove surface of the groove 11r formed on the N-type silicon substrate arc-shaped, the effective area of ​​the subsequently formed second tunneling layer 131 can be increased, thereby improving the majority carrier flux. Furthermore, the arc-shaped groove surface of the groove 11r also extends the thickness of the interfaces on both sides of the second tunneling layer 131, which can reduce carrier recombination caused by lateral carrier flow, improving carrier lifetime and utilization. Moreover, the arc-shaped groove surface of the groove 11r can reduce mechanical stress concentration, thereby reducing the fragmentation rate.

[0069] Step S30: A second stack is formed on the entire side of the first surface. The second stack includes a second tunneling layer, a phosphorus-doped polysilicon layer, and a second mask layer stacked sequentially.

[0070] In some embodiments, step S30 includes steps S31 to S32.

[0071] Step S31: A second tunneling layer and a second intrinsic silicon layer are sequentially formed on the side where the first surface is located by low-pressure chemical vapor deposition.

[0072] like Figure 8As shown, the second tunneling layer 131 and the second intrinsic silicon layer 132a are formed on the side where the first surface 11a of the N-type silicon substrate 11 is located.

[0073] In some embodiments, a fourth carrier basket is transported to a second LPCVD equipment. The silicon wafers in the fourth carrier basket, having undergone alkaline etching, are transferred to a third crystal boat. The third crystal boat carrying the silicon wafers is then placed inside the furnace tube of the second LPCVD equipment. The furnace door is sealed, a vacuum is created, and the temperature is raised. Process gases are then introduced to deposit the second tunneling layer 131 and the second intrinsic silicon layer 132a. The second tunneling layer 131 and the second intrinsic silicon layer 132a are deposited on the silicon wafer (in the first alkaline washing step described above, the first tunneling layer 121 is washed away, exposing the silicon wafer).

[0074] In some embodiments, the deposition of the second tunneling layer 131 and the second intrinsic silicon layer 132a is performed in two steps. After the deposition of the second tunneling layer 131, the furnace tube of the second LPCVD apparatus is purged, and then a silicon source is introduced to deposit the second intrinsic silicon layer 132a.

[0075] In some embodiments, the deposition of the second intrinsic silicon layer 132a is performed in two steps to generate a thicker second intrinsic silicon layer 132a. A third wafer boat carrying the silicon wafer processed by the second LPCVD process is removed from the furnace of the second LPCVD equipment, and the silicon wafer processed by the second LPCVD process is removed and placed into a fifth support basket. The entire operation time of step S31 can be, but is not limited to, 140 minutes.

[0076] In some embodiments, the processing temperature of the second LPCVD apparatus is increased, making the second intrinsic silicon layer 132a an intrinsic polycrystalline silicon layer. In some embodiments, the processing temperature of the second LPCVD apparatus is decreased, making the second intrinsic silicon layer 132a an intrinsic silicon layer composed of a mixture of intrinsic polycrystalline silicon and intrinsic amorphous silicon; or even, the second intrinsic silicon layer 132a can be an intrinsic amorphous silicon layer.

[0077] Step S32: The second intrinsic silicon layer is subjected to phosphorus diffusion treatment to transform the second intrinsic silicon layer into a phosphorus-doped polycrystalline silicon layer, and a phosphorus-silicon glass layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer, wherein the second mask layer includes the phosphorus-silicon glass layer.

[0078] like Figure 9 As shown, the second stack 13 includes a second tunneling layer 131, a phosphorus-doped polysilicon layer 132, and a second mask layer 133.

[0079] In some embodiments, a fifth carrier basket is transported to the second diffusion device, and a silicon wafer after the second LPCVD process is removed from the fifth carrier basket and placed into a fourth crystal boat. The fourth crystal boat carrying the silicon wafer after the second LPCVD process is placed into the furnace tube of the second diffusion device, the furnace door is sealed and the temperature is raised, and then a phosphorus source is introduced and the temperature is adjusted so that a phosphorus-silicon glass (PSG) layer is formed on the surface of the second intrinsic silicon layer 132a on the side where the first surface 11a of the silicon wafer is located. The phosphorus element diffuses inward through the PSG layer, so that the second intrinsic silicon layer 132a is doped with phosphorus element to form an N-poly layer (i.e., phosphorus-doped polycrystalline silicon layer 132). In this process, the grain growth is more robust, so that the areas not irradiated by laser in subsequent steps are less likely to be damaged by the laser grooving step.

[0080] Next, the fourth crystal boat carrying the phosphorus-diffused silicon wafer is removed from the furnace of the second diffusion equipment, and the phosphorus-diffused silicon wafer is then placed into the sixth carrier basket. The N-poly formed in this step constitutes the N+ layer (heavily doped phosphorus layer), forming field passivation, reducing carrier recombination, and the electric field generated can drive the directional flow of majority and minority carriers. This process can take up to, but is not limited to, 140 minutes.

[0081] When the second intrinsic silicon layer 132a contains amorphous silicon, the amorphous silicon can be crystallized and converted into polycrystalline silicon after high-temperature treatment in the second diffusion device.

[0082] Step S40: Remove the wrap-around coating deposited on the second surface of the N-type silicon substrate during the formation of the first stack and / or the formation of the second stack; remove the corresponding portions of the second stack in the first region and the spacer region.

[0083] In some embodiments, step S40 includes steps S41 to S43.

[0084] Step S41: Use the second laser to irradiate the area on the second mask layer corresponding to the first region and the spacer region.

[0085] like Figure 10 As shown, the region on the second mask layer 133 corresponding to the first region A1 and the spacer region G is irradiated by the second laser L2, while the portion of the second mask layer 133 corresponding to the second region A2 is not irradiated by the second laser L2.

[0086] In some embodiments, a silicon wafer is removed from the sixth carrier basket and placed onto the conveyor belt of the second laser device, with the first surface 11a of the wafer facing the laser generator of the second laser device. The laser generator of the second laser device emits a dot matrix laser to scan the first region A1 and at least part of the spacing region G of the first surface 11a of the silicon wafer, but leaves the second region A2 unilluminated. The silicon wafer, with the first region A1 and the spacing region G irradiated by the laser, is then removed from the second laser device and placed into the seventh carrier basket.

[0087] In some embodiments, the silicon wafer after the phosphorus diffusion process is removed from the sixth support basket and placed into the positioning structure of the second laser device, with the first surface 11a of the silicon wafer facing the laser generator of the second laser device. The laser generator of the second laser device emits a dot matrix laser to scan the first region A1 and at least part of the spacing region G of the first surface 11a of the silicon wafer, but leaves the second region A2 unilluminated. The silicon wafer, with the first region A1 and at least part of the spacing region G irradiated by the laser, is then removed from the positioning structure of the second laser device and placed into the seventh support basket.

[0088] Step S42: Remove the coating layers deposited around the second surface 11b of the N-type silicon substrate 11 during the formation of the first stack 12 and / or the formation of the second stack 13. The coating layers include the first stack 12 deposited around the second surface 11b of the N-type silicon substrate 11 during the formation of the first stack 12 and / or the second stack 13 deposited around the second surface 11b during the formation of the second stack 13.

[0089] In some embodiments, a seventh carrier basket is transported to an acid pickling device, and the silicon wafer is removed from the seventh carrier basket and placed into the acid pickling device with its second side 11b facing down to contact the acidic cleaning agent in the device. The plating on the second side 11b of the silicon wafer is removed by the acid pickling device. The silicon wafer is then removed from the acid pickling device and placed into an eighth carrier basket.

[0090] In some embodiments, the pickling equipment is a chain pickling equipment. In some embodiments, the pickling equipment is a tank pickling equipment.

[0091] Step S43: Using an alkaline etching process, the second layer below the area irradiated by the second laser is removed, and the exposed portions of the second and first surfaces in the interval area are texturized.

[0092] In some embodiments, during the alkaline etching process, the portion of the second mask layer 133 corresponding to the first region A1 and the spacer region G is removed, while the second stack 13 located in the first region A1 and the spacer region G is etched, and the second surface 11b and the first surface 11a form a textured surface in the exposed portion of the spacer region G.

[0093] Step S50: Remove the first mask layer and the second mask layer.

[0094] In some embodiments, after step S43, an acid washing process is performed to remove the first mask layer 123 remaining in the first region A1 and the second mask layer 133 remaining in the second region A2, thereby obtaining... Figure 11 The structure shown.

[0095] In some embodiments, the eighth carrier basket is transported to the second alkaline washing equipment and placed directly into the second alkaline washing equipment for processing. The front side of the silicon wafer is texturized using the first cleaning agent. The second region A2 on the back side of the silicon wafer, which is not irradiated by the second laser equipment, is not eroded by the first cleaning agent due to the mask protection of the PSG layer. However, the PSG layers of the first region A1 and the spacer region G are dispersed by the laser, causing the PSG layers of the first region A1 and the spacer region G to fall off. This etches the N-poly layer, P-poly layer, and the bottom first tunneling layer 121 and second tunneling layer 131 of the PSG layers of the first region A1 and the spacer region G, forming an insulating trench, so that the P-poly layer of the first region A1 is directly insulated from the N-poly layer of the second region A2. Then, the PSG layer and BSG layer on the back side of the silicon wafer are removed using the second cleaning agent.

[0096] In some embodiments, the second alkaline washing equipment is a chain-type alkaline washing equipment. In some embodiments, the second alkaline washing equipment is a tank-type alkaline washing equipment.

[0097] Understandably, the alkaline etching process may further include a preliminary texturing process for the second surface 11b after the wet processing equipment treatment in step S11. Then, between the first and second cleaning agents, a third cleaning agent can be used to perform a secondary texturing process on the second surface 11b and the bottom of the insulating tank to form a texturing surface on the bottom of the insulating tank and a final texturing surface on the second surface 11b. The composition of the first cleaning agent can also be adjusted so that it simultaneously serves to alkaline clean the N-poly layer, the P-poly layer, and the first tunneling layer 121 and the second tunneling layer 131 at the bottom, as well as to texturize the second surface 11b and the bottom of the insulating tank.

[0098] In some embodiments, after removing the first mask layer and the second mask layer, at least one of the following is further included: forming a first passivation layer on the side containing the first surface and forming a second passivation layer on the side containing the second surface; forming a first antireflection layer on the side containing the first surface and forming a second antireflection layer on the side containing the second surface; and providing multiple grid lines on the side containing the first surface, such that some of the grid lines are in electrical contact with the boron-doped polycrystalline silicon layer and other grid lines are in electrical contact with the phosphorus-doped polycrystalline silicon layer. Thus, a solar cell is obtained.

[0099] like Figure 12 As shown, the solar cell 100 includes an N-type silicon substrate 11, a first tunneling layer 121, a boron-doped polycrystalline silicon layer 122, a second tunneling layer 131, a phosphorus-doped polycrystalline silicon layer 132, and multiple grid lines 16.

[0100] The N-type silicon substrate 11 has a first surface 11a and a second surface 11b opposite to each other. The first surface 11a defines an alternating first region A1, a second region A2, and a spacer region G located between adjacent first regions A1 and second regions A2. And there are grooves 11r with arcuate groove surfaces at the positions of the second region A2 and the spacer region G.

[0101] Both the first tunneling layer 121 and the boron-doped polysilicon layer 122 are located in the first region A1. The first tunneling layer 121 contacts the first surface 11a, and the boron-doped polysilicon layer 122 is located on top of the first tunneling layer 121.

[0102] Both the second tunneling layer 131 and the phosphorus-doped polysilicon layer 132 are located in the second region A2. The second tunneling layer 131 contacts the groove surface of the groove 11r, and the phosphorus-doped polysilicon layer 132 is located on the second tunneling layer 131.

[0103] Part of the gate line 16 is in electrical contact with the boron-doped polysilicon layer 122, and another part of the gate line 16 is in electrical contact with the phosphorus-doped polysilicon layer 132.

[0104] The solar cell 100 also includes a first passivation layer 14a. The first passivation layer 14a covers the surface of the boron-doped polycrystalline silicon layer 122, the phosphorus-doped polycrystalline silicon layer 132, and the exposed N-type silicon substrate 11 within the spacer region G.

[0105] The solar cell 100 also includes a second passivation layer 14b. The second passivation layer 14b is formed on the second surface 11b of the N-type silicon substrate 11.

[0106] In some embodiments, the first passivation layer 14a may be, but is not limited to, aluminum oxide, and the second passivation layer 14b may be, but is not limited to, aluminum oxide.

[0107] In some embodiments, an eighth carrier basket is transported to a passivation layer deposition apparatus. This passivation layer deposition apparatus can be an atomic layer deposition (ALD) apparatus. The silicon wafer in the eighth carrier basket is transferred to a fifth boat, which is then placed inside the furnace tube of the ALD apparatus. The furnace door is sealed, a vacuum is created, and the temperature is increased. Process gases are then introduced to deposit an alumina passivation layer. The alumina passivation layer is deposited on both the front and back sides of the silicon wafer. The fifth boat carrying the silicon wafer with the deposited alumina passivation layer is removed from the ALD apparatus furnace, and the silicon wafer is removed and placed in a ninth carrier basket.

[0108] The solar cell 100 also includes a first antireflection layer 15a and a second antireflection layer 15b. The first antireflection layer 15a is formed on a first passivation layer 14a. The second antireflection layer 15b is formed on the first passivation layer 14a.

[0109] In some embodiments, the first antireflection layer 15a includes a first silicon nitride layer 151a. The second antireflection layer 15b includes a second silicon nitride layer 151b and a silicon oxide layer 152b stacked sequentially.

[0110] In some embodiments, forming the first antireflection layer 15a and the second antireflection layer 15b includes forming a first silicon nitride layer 151a and a second silicon nitride layer 151b using a first plasma-enhanced chemical vapor deposition (PECVD) apparatus; followed by forming a silicon oxide layer 152b using a second PECVD apparatus.

[0111] In other embodiments, forming the first antireflection layer 15a and the second antireflection layer 15b includes first forming a first silicon nitride layer 151a and a second silicon nitride layer 151b in a first PECVD apparatus; and then forming a silicon oxide layer 152b in the first PECVD apparatus.

[0112] In some embodiments, a ninth support basket is transported to a first PECVD apparatus. The silicon wafer in the ninth support basket is transferred to a sixth crystal boat. The sixth crystal boat carrying the silicon wafer is placed inside the furnace tube of the first PECVD apparatus, the furnace door is sealed, a vacuum is drawn, and the temperature is raised. Then, process gases are introduced and glow discharge is emitted to deposit a first silicon nitride layer 151a and a second silicon nitride layer 151b. The first silicon nitride layer 151a on the front side of the silicon wafer serves both as passivation and reduces reflection, improving light absorption. The second silicon nitride layer 151b on the back side of the silicon wafer forms a passivation layer. Afterward, the sixth crystal boat carrying the silicon wafer with the deposited silicon nitride layer is removed from the furnace of the first PECVD apparatus, and the silicon wafer is removed and placed in a tenth support basket.

[0113] In some embodiments, the tenth carrier basket is transported to the second PECVD equipment. The silicon wafer in the tenth carrier basket is transferred to the seventh crystal boat, which is then placed inside the furnace tube of the second PECVD equipment. The furnace door is sealed, a vacuum is drawn, and the temperature is raised. Process gases are then introduced, and glow discharge is emitted to deposit the silicon oxide layer 152b. The silicon oxide layer 152b on the front side of the silicon wafer increases light transmittance, improves light absorption, and protects the inner structure. The seventh crystal boat carrying the silicon wafer with the deposited silicon oxide layer 152b is removed from the furnace of the second PECVD equipment, and the silicon wafer is removed and placed in the eleventh carrier basket for subsequent patterning and emitter processes.

[0114] Understandably, the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth load-bearing baskets can be distinguished or not, depending on the actual scheduling. If no distinction is made, the load-bearing baskets that serve to support silicon wafers in different areas can be used interchangeably.

[0115] It should be noted that existing TBC solar cell production lines have long setup and investment periods, and the production processes are relatively complex, resulting in low yield rates. Especially in TBC cell production using the PECVD process, the in-situ grown polycrystalline silicon is highly susceptible to microcracks and polycrystalline silicon damage during laser grooving, thus affecting the open-circuit voltage and conversion efficiency of the finished TBC cells. Furthermore, the existing LPCVD process lacks seamless integration with other process steps, leading to discontinuous workflows and low production efficiency. Inappropriate LPCVD processes also face the problem of easily causing microcracks and polycrystalline silicon damage during laser grooving, thus affecting the open-circuit voltage and conversion efficiency of the finished TBC cells.

[0116] In the solar cell fabrication method of this application embodiment, a first tunneling layer under the P-poly layer and a second tunneling layer under the N-poly layer are formed respectively. Both sides of the first and second tunneling layers have better connection interfaces, effectively reducing defects, reducing carrier recombination, and improving conversion efficiency. Furthermore, intrinsic silicon is deposited through two LPCVD processes, and boron diffusion and phosphorus diffusion are performed through two diffusion devices to form the P-poly and N-poly layers respectively. This ensures uniform polycrystalline silicon deposition, reduces surface defects, reduces the occurrence of dangling bonds, and further improves conversion efficiency. In addition, the groove surface is arc-shaped and roughly teardrop-shaped. On the one hand, this helps reduce mechanical stress concentration, thereby reducing the breakage rate of the solar cell; on the other hand, it achieves a balance between insulation effect and leakage channel formation.

[0117] This application also provides a solar cell production line. This solar cell production line can be used to perform the above-described method for manufacturing solar cells.

[0118] like Figure 13 As shown, the solar cell production line 200 includes a wet processing equipment 201, a first low-pressure chemical vapor deposition equipment 202, a first diffusion equipment 203, a first laser equipment 204, a first alkaline washing equipment 205, a second low-pressure chemical vapor deposition equipment 206, a second diffusion equipment 207, a second laser equipment 208, an acid washing equipment 209, a second alkaline washing equipment 210, a passivation layer deposition equipment 211, and an antireflection layer deposition equipment 212, which are connected in sequence.

[0119] The wet processing equipment 201 is used to perform double-sided polishing on an N-type silicon substrate 11. The N-type silicon substrate 11 has a first surface 11a and a second surface 11b with opposite sides. The first surface 11a defines an alternating first region A1, a second region A2 and a spacer region G located between adjacent first regions A1 and second regions A2.

[0120] The first low-pressure chemical vapor deposition apparatus 202 is used to sequentially form a first tunneling layer 121 and a first intrinsic silicon layer 122a on the first surface 11a.

[0121] The first diffusion device 203 is used to convert the first intrinsic silicon layer 122a into a boron-doped polycrystalline silicon layer 122 through boron diffusion treatment, and to form a borosilicate glass layer as a first mask layer 123, thereby obtaining the first stack 12.

[0122] The first laser device 204 is used to emit a first laser L1 to irradiate the region on the first mask layer 123 corresponding to the second region A2 and the interval region G.

[0123] The first alkaline washing equipment 205 is used to remove the first stack 12 and part of the N-type silicon substrate 11 below the area irradiated by the first laser L1 by alkaline etching, so as to form a groove 11r with an arc-shaped groove surface.

[0124] The second low-pressure chemical vapor deposition apparatus 206 is used to sequentially form a second tunneling layer 131 and a second intrinsic silicon layer 132a on the side where the first surface 11a is located.

[0125] The second diffusion device 207 is used to convert the second intrinsic silicon layer 132a into a phosphorus-doped polycrystalline silicon layer 132 through phosphorus diffusion treatment, and to form a phosphorus-silicon glass layer as a second mask layer 133, thereby obtaining the second stack 13.

[0126] The second laser device 208 is used to emit a second laser L2 to irradiate the region on the second mask layer 133 corresponding to the first region A1 and the interval region G.

[0127] The pickling equipment 209 is used to remove the wrap-around coating deposited on the second surface 11b of the N-type silicon substrate 11 during the formation of the first stack 12 and / or the formation of the second stack 13. The wrap-around coating includes the first stack 12 and / or the second stack 13 deposited on the second surface 11b.

[0128] The second alkaline washing equipment 210 includes a polishing section and a texturing section. The polishing section is used to remove the second stack 13 below the area irradiated by the second laser L2. The texturing section textures the exposed portions of the second surface 11b and the first surface 11a within the interval G, and removes the first mask layer 123 and the second mask layer 133.

[0129] Understandably, a texturing machine may also be included between the wet processing equipment 201 and the first low-pressure chemical vapor deposition equipment 202. After the wet processing equipment 201 performs double-sided polishing on the N-type silicon substrate 11, a texturing machine is used to prepare a textured surface on at least the second surface 11b of the N-type silicon substrate 11. If the textured surface prepared on the second surface 11b of the N-type silicon substrate 11 by the texturing machine is a preliminary textured surface, then the N-type silicon substrate 11 can undergo secondary texturing in the second alkaline washing equipment 210 to form the final textured surface. If the textured surface prepared on the second surface 11b of the N-type silicon substrate 11 by the texturing machine is the final textured surface, texturing in the second alkaline washing equipment 210 may not be necessary.

[0130] The passivation layer deposition apparatus 211 is used to form a first passivation layer 14a on the side where the first surface 11a is located, and a second passivation layer 14b on the side where the second surface 11b is located. The passivation layer deposition apparatus 211 can be, but is not limited to, an ALD apparatus.

[0131] The antireflection layer deposition apparatus 212 is used to form a first antireflection layer 15a on the side where the first surface 11a is located, and to form a second antireflection layer 15b on the side where the second surface 11b is located.

[0132] In some embodiments, the first laser device 204 and the second laser device 208 can be the same device. An AGV robot is used to transport the silicon wafer from the second diffusion device 207 back to the first laser device 204 (in this embodiment, the second laser device 208) to realize the laser process.

[0133] In some embodiments, the first low-pressure chemical vapor deposition equipment 202 and the second low-pressure chemical vapor deposition equipment 206 can be the same equipment. An AGV robot is used to transport the silicon wafer from the first alkaline washing equipment 205 back to the first low-pressure chemical vapor deposition equipment 202 (in this embodiment, the second low-pressure chemical vapor deposition equipment 206) to achieve the deposition process.

[0134] In some embodiments, the first antireflection layer 15a includes a first silicon nitride layer 151a. The second antireflection layer 15b includes a second silicon nitride layer 151b and a silicon oxide layer 152b stacked sequentially. The antireflection layer deposition apparatus 212 includes a first PECVD apparatus and a second PECVD apparatus. Forming the first antireflection layer 15a and the second antireflection layer 15b includes forming the first silicon nitride layer 151a and the second silicon nitride layer 151b using the first PECVD apparatus; and then forming the silicon oxide layer 152b using the second PECVD apparatus.

[0135] In other embodiments, the antireflection layer deposition apparatus 212 includes a first PECVD apparatus, while the second PECVD apparatus may be omitted. Forming the first antireflection layer 15a and the second antireflection layer 15b includes first forming a first silicon nitride layer 151a and a second silicon nitride layer 151b in the first PECVD apparatus; and then forming a silicon oxide layer 152b in the first PECVD apparatus.

[0136] In some embodiments, the structure and process parameters of the various devices included in the solar cell production line 200 can be found in the description of the solar cell fabrication method above, and will not be repeated here.

[0137] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for preparing a solar cell, characterized in that, include: A first stack is formed on the first surface of an N-type silicon substrate, the first stack comprising a first tunneling layer, a boron-doped polysilicon layer and a first mask layer stacked sequentially. The first surface defines alternating first regions, second regions, and interval regions located between adjacent first regions and second regions. The first stack and the corresponding portions of the N-type silicon substrate in the second region and at least part of the interval regions are removed, thereby forming a groove in the N-type silicon substrate. The groove surface formed in the N-type silicon substrate is arc-shaped. A second stack is formed on the entire side where the first surface is located. The second stack includes a second tunneling layer, a phosphorus-doped polysilicon layer, and a second mask layer stacked sequentially. Remove the wrap-around coating, which is formed on a second surface of the N-type silicon substrate during the formation of the first stack and / or the formation of the second stack, wherein the second surface is opposite to the first surface; remove the corresponding portions of the second stack in the first region and the spacer region; as well as Remove the first mask layer and the second mask layer.

2. The method for preparing a solar cell according to claim 1, characterized in that, The steps for forming the groove include: The region on the first mask layer corresponding to the second region and at least a portion of the interval region is illuminated using a first laser; and The first stack and part of the N-type silicon substrate below the area irradiated by the first laser are removed by an alkaline etching process to form the groove, which is teardrop-shaped and has an arc-shaped groove surface.

3. The method for preparing a solar cell according to claim 1, characterized in that, The steps for forming the first stack include: The first tunneling layer and the first intrinsic silicon layer are sequentially formed on the first surface by low-pressure chemical vapor deposition; and The first intrinsic silicon layer is subjected to boron diffusion treatment to transform the first intrinsic silicon layer into the boron-doped polycrystalline silicon layer, and a borosilicate glass layer is formed on the surface of the boron-doped polycrystalline silicon layer, wherein the first mask layer includes the borosilicate glass layer.

4. The method for preparing a solar cell according to claim 1, characterized in that, The steps for forming the second stack include: The second tunneling layer and the second intrinsic silicon layer are sequentially formed on the side containing the first surface by low-pressure chemical vapor deposition; and The second intrinsic silicon layer is subjected to phosphorus diffusion treatment to transform the second intrinsic silicon layer into the phosphorus-doped polycrystalline silicon layer, and a phosphorus-silicon glass layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer, wherein the second mask layer includes the phosphorus-silicon glass layer.

5. The method for preparing a solar cell according to claim 1, characterized in that, The step of removing the corresponding portions of the second layer in the first region and the interval region includes: The second laser is used to irradiate the region on the second mask layer corresponding to the first region and the interval region; and The second layer below the area irradiated by the second laser is removed by an alkaline etching process, and the exposed portions of the second surface and the first surface within the interval are texturized.

6. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that, It also includes at least one of the following: Before forming the first stack, the N-type silicon substrate is polished on both sides; Before forming the first stack, the second side of the N-type silicon substrate is texturized; After removing the first mask layer and the second mask layer, a first passivation layer is formed on the side where the first surface is located, and a second passivation layer is formed on the side where the second surface is located; After removing the first mask layer and the second mask layer, a first anti-reflection layer is formed on the side where the first surface is located, and a second anti-reflection layer is formed on the side where the second surface is located; After removing the first mask layer and the second mask layer, multiple gate lines are provided on the side where the first surface is located, such that a portion of the gate lines are in electrical contact with the boron-doped polysilicon layer, and another portion of the gate lines are in electrical contact with the phosphorus-doped polysilicon layer.

7. A solar cell, characterized in that, include: An N-type silicon substrate has a first surface and a second surface opposite to each other. The first surface defines an alternating first region, a second region, and a spacer region located between adjacent first and second regions. The second region and the spacer region have arc-shaped grooves. Both the first tunneling layer and the boron-doped polysilicon layer are located in the first region, wherein the first tunneling layer contacts the first surface, and the boron-doped polysilicon layer is located above the first tunneling layer; A second tunneling layer and a phosphorus-doped polysilicon layer are both located in the second region, wherein the second tunneling layer contacts the groove surface of the groove, and the phosphorus-doped polysilicon layer is located above the second tunneling layer; and Multiple gate lines, some of which are in electrical contact with the boron-doped polysilicon layer, and others of which are in electrical contact with the phosphorus-doped polysilicon layer.

8. The solar cell according to claim 7, characterized in that, The solar cell further includes a first passivation layer, which covers the boron-doped polycrystalline silicon layer, the phosphorus-doped polycrystalline silicon layer, and the exposed N-type silicon substrate surface within the spacer region.

9. A solar cell production line, characterized in that, include: A wet processing apparatus for double-sided polishing of an N-type silicon substrate, the N-type silicon substrate having opposing first and second surfaces, the first surface defining alternating first and second regions and a spacer region located between adjacent first and second regions; A first low-pressure chemical vapor deposition apparatus is used to sequentially form a first tunneling layer and a first intrinsic silicon layer on the first surface; A first diffusion apparatus is used to convert the first intrinsic silicon layer into a boron-doped polycrystalline silicon layer by boron diffusion treatment, and to form a borosilicate glass layer as a first mask layer, thereby obtaining a first stack. A first laser device is used to emit a first laser to irradiate a region on the first mask layer corresponding to the second region and at least a portion of the interval region; The first alkaline washing equipment is used to remove the first stack and part of the N-type silicon substrate below the area irradiated by the first laser by alkaline etching, so as to form a groove in the N-type silicon substrate, wherein the groove surface formed in the N-type silicon substrate is arc-shaped. A second low-pressure chemical vapor deposition apparatus is used to sequentially form a second tunneling layer and a second intrinsic silicon layer on the side where the first surface is located. The second diffusion device is used to convert the second intrinsic silicon layer into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion treatment, and to form a phosphorus-silicon glass layer as a second mask layer, thereby obtaining the second stack. A second laser device is used to emit a second laser to irradiate the area on the second mask layer corresponding to the first region and the interval region; A pickling device for removing the first layer and the second layer coated on the second surface; The second alkaline washing equipment is used to remove the second stack below the area irradiated by the second laser, and to at least texturize the exposed portion of the first surface in the interval area, and to remove the first mask layer and the second mask layer. A passivation layer deposition apparatus for forming a first passivation layer on the side containing the first surface and a second passivation layer on the side containing the second surface; as well as An antireflection layer deposition apparatus is used to form a first antireflection layer on the side where the first surface is located, and to form a second antireflection layer on the side where the second surface is located.

10. The solar cell production line according to claim 9, characterized in that, A texturing machine is provided between the wet processing equipment and the first low-pressure chemical vapor deposition equipment, and the texturing machine is used to texture at least the second side of the N-type silicon substrate.

11. The solar cell production line according to claim 9, characterized in that, The second alkaline washing equipment is used to perform flocking on the exposed portion of the first side within the interval area, while simultaneously flocking the second side.

12. The solar cell production line according to claim 9, characterized in that, The first antireflection layer includes a first silicon nitride layer; The second antireflection layer comprises a second silicon nitride layer and a silicon oxide layer stacked sequentially; The antireflection layer deposition equipment includes: A first plasma-enhanced chemical vapor deposition apparatus is used to form the first silicon nitride layer and the second silicon nitride layer; and A second plasma-enhanced chemical vapor deposition apparatus is used to form the silicon oxide layer.

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