SON and silicon epitaxy process-based PMUT preparation method and PMUT
By using SON and silicon epitaxy processes to form precise cavities and single-crystal silicon epitaxial layers in PMUT fabrication, the problems of inaccurate edge control and high cost in traditional processes are solved, achieving efficient and stable PMUT production.
Patent Information
- Application Number
- CN202511141125.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2025-11-28
AI Technical Summary
Traditional PMUT fabrication processes suffer from inaccurate edge control and high production costs, especially the front sacrificial layer process and the back deep silicon cavity process, which are difficult to control precisely and produce efficiently.
By employing SON and silicon epitaxial processes, a PMUT structure is fabricated by forming a cavity on a silicon substrate, performing annealing and silicon epitaxial layer growth, and combining it with CMP planarization, which simplifies the process steps and improves edge control accuracy.
Precise control of the PMUT structure edge was achieved, improving the consistency and stability of device performance, reducing production costs, and facilitating large-scale industrial production. Furthermore, the sensitivity and reliability of the PMUT were improved by selecting appropriate piezoelectric layer materials.
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Figure CN121020503A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of micro-electro-mechanical system devices, and particularly relates to a PMUT preparation method based on a SON and a silicon epitaxy process and a PMUT. BACKGROUND
[0002] As an important micro-electro-mechanical system (MEMS) device, a piezoelectric micromachined ultrasonic transducer (PMUT) has been widely concerned and applied in many fields due to its small size, low power consumption and high integration.
[0003] Traditional PMUT preparation usually adopts a front-side sacrificial layer process and a back-side deep silicon cavity process. The front-side sacrificial layer process is to first deposit a sacrificial layer on a silicon substrate, then prepare relevant structures of the PMUT on the sacrificial layer, and finally remove the sacrificial layer to form a cavity by etching. However, in the process of removing the sacrificial layer, it is difficult to accurately control the edge of the structure, which may easily lead to poor edge consistency between different devices, and further affect the performance stability and consistency of the device. Meanwhile, the removal process of the sacrificial layer may also introduce impurities, which adversely affects the performance of the device.
[0004] The back-side deep silicon cavity process is to perform deep silicon etching from the back side of the silicon substrate to form a cavity. This process needs complex back-side photolithography alignment, which requires high equipment precision and increases the process difficulty. Moreover, in the process of deep silicon etching, the etching depth and profile are difficult to accurately control, which may easily lead to irregularities at the edge of the cavity, affecting the vibration characteristics of the PMUT. In addition, the back-side deep silicon cavity process involves many steps and consumes a large amount of materials, which makes the production cost high and is not conducive to large-scale production. SUMMARY
[0005] The technical problem to be solved by the present application is to overcome the deficiencies in the prior art, and to provide a PMUT preparation method based on a SON and a silicon epitaxy process and a PMUT, which replaces the traditional front-side sacrificial layer and back-side deep silicon cavity process route, and solves the problems of inaccurate edge control and high production cost in the traditional PMUT preparation process.
[0006] The technical scheme adopted by the present application to solve the technical problem is as follows:
[0007] In a first aspect, a PMUT preparation method based on a SON and a silicon epitaxy process comprises the following steps:
[0008] S1. Forming a cavity on a silicon substrate by using a SON process;
[0009] S2. Annealing treatment to optimize the roughness of the silicon surface above the cavity;
[0010] S3. Forming a single-crystal silicon epitaxial layer above the cavity by using a silicon epitaxy process;
[0011] S4. Planarization treatment is performed by CMP to optimize the surface roughness of the single crystal silicon epitaxial layer;
[0012] S5. A PMUT is prepared above the single crystal silicon epitaxial layer.
[0013] Further, the step S1 comprises the following steps:
[0014] S11. The silicon substrate is cleaned to remove impurities and natural oxide layer on the surface;
[0015] S12. An etching process is used to form a plurality of regularly arranged shallow trenches inside the silicon substrate;
[0016] S13. High-temperature annealing treatment is performed to make silicon atoms around each shallow trench migrate and fill the bottom of each shallow trench, thereby forming a cavity with a predetermined size inside the silicon substrate.
[0017] Further, the step S3 comprises:
[0018] The silicon substrate is placed in an epitaxial growth furnace, and in a high-temperature and low-pressure environment, silicon source gas is introduced to make silicon atoms deposit on the surface of the silicon substrate and above the cavity, thereby growing a single crystal silicon epitaxial layer.
[0019] Further, the step S5 comprises:
[0020] A lower electrode, a piezoelectric layer and an upper electrode are sequentially prepared above the single crystal silicon epitaxial layer; and a photolithography and etching process is used to pattern the lower electrode, the piezoelectric layer and the upper electrode, thereby forming a vibration unit of the PMUT.
[0021] Further, the upper electrode and the lower electrode are both made of metal material and are both prepared by sputtering or evaporation process.
[0022] Further, the piezoelectric layer is made of at least one material selected from PZT, PVDF, AIN and their doped materials, and is prepared by sol-gel method or sputtering method.
[0023] Further, in the step S13, the depth and width of the cavity satisfy a depth-width ratio of 3:1 to 9.5:1.
[0024] Further, in the step S3, the growth temperature of the silicon epitaxial layer is 1050-1150°C, and the growth pressure is 10-50 mbar.
[0025] Further, in the step S3, the thickness of the single crystal silicon epitaxial layer is 1-20 μm.
[0026] In a second aspect, a PMUT prepared by the PMUT preparation method based on the SON and silicon epitaxy process is provided, comprising a silicon substrate, a cavity, a single-crystal silicon epitaxial layer, a lower electrode, a piezoelectric layer, and an upper electrode; the cavity is formed in the interior of the silicon substrate; the single-crystal silicon epitaxial layer is arranged on the upper surface of the silicon substrate; the lower electrode is arranged on the upper surface of the single-crystal silicon epitaxial layer; the piezoelectric layer is arranged on the upper surface of the lower electrode; and the upper electrode is arranged on the upper surface of the piezoelectric layer.
[0027] The present application has the following advantages:
[0028] (1) The SON process of the present application can form a cavity with high precision in shape and size in the silicon substrate in advance through precise photolithography and etching steps, and the single-crystal silicon epitaxial layer with a thickness of 1-20 μm grown above the cavity can form a good match with the cavity, so that the edges of the subsequently prepared PMUT structure are precisely controlled, and the consistency and stability of the device performance are improved.
[0029] (2) The process route of the present application is relatively simple, and does not require complex backside photolithography alignment and deep silicon etching steps, thereby reducing the process steps and equipment investment, lowering the production cost, and being conducive to large-scale industrial production.
[0030] (3) The single-crystal silicon epitaxial layer of the present application has good crystalline quality and mechanical properties, and can provide stable support for the vibration of the PMUT, thereby reducing the influence of structural defects on the performance of the device.
[0031] (4) The piezoelectric layer of the present application uses PZT, PVDF, AIN, and their dopants, etc., and appropriate materials can be selected according to different application requirements, thereby further improving the sensitivity and reliability of the PMUT. BRIEF DESCRIPTION OF DRAWINGS
[0032] The present application will be further described below in conjunction with the drawings and examples.
[0033] Figure 1 is a flowchart of the PMUT preparation method based on the SON and silicon epitaxy process in the present application;
[0034] Figures 2 to 9 is a device cross-sectional structure schematic diagram presented by each step of the PMUT preparation method based on the SON and silicon epitaxy process in the present application;
[0035] Figure 10 is a PMUT cross-sectional structure schematic diagram provided with a passivation layer and an electrical connection electrode in the present application.
[0036] In the figure: 1, silicon substrate; 2, cavity; 3, single-crystal silicon epitaxial layer; 4, lower electrode; 5, piezoelectric layer; 6, upper electrode; 7, passivation layer; 8, electrical connection electrode. DETAILED DESCRIPTION
[0037] The present application will now be further described with reference to the drawings and preferred embodiments. These drawings show only the essential features of the application and are not to scale and they should not be considered as limiting the scope of the application, as described and defined by the claims.
[0038] Some of the technologies involved in the present application are briefly described as follows:
[0039] Silicon On Nothing (SON): A semiconductor fabrication technique to form a suspended structure by etching a cavity on a silicon substrate.
[0040] Silicon Epitaxy: A technique to grow a single-crystalline silicon film on a silicon substrate by chemical vapor deposition or other methods to form a silicon layer with the same crystal orientation as the substrate.
[0041] Annealing: A thermal treatment technique to heat and then cool down slowly in a controlled environment by precisely controlling the temperature and time in semiconductor fabrication.
[0042] Chemical Mechanical Polishing (CMP): A planarization technique in semiconductor fabrication to achieve surface planarization by the synergistic effect of chemical etching and mechanical grinding.
[0043] Magnetron Sputtering: A physical vapor deposition technique to enhance the sputtering efficiency by confining the plasma with a magnetic field.
[0044] Electron Beam Evaporation: A physical vapor deposition technique to locally melt and vaporize the target material by high-energy electron beam bombardment, and then condense the vapor-phase atoms on the substrate surface to form a thin film.
[0045] Photolithography: A patterning technique to accurately transfer the circuit pattern on a mask to the surface coated with photoresist by optical projection.
[0046] Wet Etching: A semiconductor patterning technique to selectively dissolve the material by chemical solution.
[0047] Dry Etching: A semiconductor patterning technique to selectively remove the material by plasma or reactive gas.
[0048] Ion Beam Etching: A dry etching technique to achieve anisotropic etching by physical sputtering with high-energy ion beam generated by inert gas ionization.
[0049] Example 1
[0050] Reference is made to Figure 1 A PMUT fabrication method based on SON and silicon epitaxy process, comprising the following steps:
[0051] S1. Forming a cavity 2 on a silicon substrate 1 by using a SON process;
[0052] S2. Annealing treatment, optimizing the roughness of the silicon surface above the cavity 2;
[0053] S3. Forming a monocrystalline silicon epitaxial layer 3 above the cavity 2 by using a silicon epitaxial process;
[0054] S4. Planarization treatment by using CMP, optimizing the surface roughness of the monocrystalline silicon epitaxial layer 3;
[0055] S5. Preparing a PMUT above the monocrystalline silicon epitaxial layer 3.
[0056] Referring to Figures 2 to 4 , the above step S1 includes the following steps:
[0057] S11. Cleaning the silicon substrate 1 as shown in Figure 2 , removing the impurities and natural oxide layer on the surface. Optionally, RCA cleaning method is adopted, first, the silicon substrate 1 is put into a mixed solution with a volume ratio of NH4OH:H2O2:H2O = 1:1:5, and cleaned at 75-85℃ for 10-15 minutes; then put into a mixed solution with a volume ratio of HCl:H2O2:H2O = 1:1:5, and cleaned at 75-85℃ for 10-15 minutes; finally, washed clean with deionized water, and dried by nitrogen blowing;
[0058] S12. Forming a plurality of regularly arranged shallow grooves inside the silicon substrate 1 as shown in Figure 3 , by using etching process. Optionally, photoresist is coated on the surface of the silicon substrate 1, and the cavity 2 pattern is transferred to the photoresist by photoetching exposure, and the photoresist image is obtained after development; then, the photoresist is used as a mask, and dry etching (such as reactive ion etching) process is adopted to etch the silicon substrate 1, forming a plurality of regularly arranged shallow grooves, the shape of each shallow groove is circular or polygon with curvature, and the curvature radius of the polygon is generally not more than 30% of its side length, the ratio of the width to the pitch of the shallow groove is between 1:1 and 4:3, the ratio of the width to the depth of the shallow groove is between 1:16 and 3:20, and the depth of the shallow groove is at most 10μm; the shallow groove adopts the above shape specifications and etching depth, which is convenient for limiting the aspect ratio of the subsequent formed vacuum cavity structure to be between 3:1 and 9.5:1;
[0059] S13. High-temperature annealing treatment, making the silicon atoms around the shallow groove migrate and fill the bottom of the shallow groove, as shown in Figure 4A cavity 2 of a predetermined size is formed inside the silicon substrate 1. Optionally, the silicon substrate 1 is placed in an annealing furnace, and annealed at a temperature of 1000-1200 °C for 10-60 minutes in a high vacuum environment or in a low-pressure hydrogen or argon environment (pressure of 1-10 Torr, hydrogen flow of 1-20 SLM), so that silicon atoms around the shallow trench migrate and fill the bottom of the shallow trench, forming the cavity 2 with a depth-to-width ratio of 3:1-9.5:1.
[0060] Referring to Figure 6 The above step S3 includes:
[0061] The silicon substrate 1 is placed in an epitaxial growth furnace, and silicon atoms are deposited on the surface of the silicon substrate 1 and above the cavity 2 to grow a monocrystalline silicon epitaxial layer 3 under a high-temperature, low-pressure environment with a silicon source gas being introduced. Figure 6 Optionally, the silicon substrate 1 on which the cavity 2 is formed is placed in a reduced-pressure epitaxial furnace, and a surface oxide layer is removed by pre-treating at a temperature of 1000-1100 °C for 10-20 minutes in a hydrogen atmosphere; then a silane (SiH4) gas is introduced at a flow rate of 50-100 sccm, a reaction temperature of 1050-1150 °C, and a pressure of 10-50 mbar to grow a monocrystalline silicon epitaxial layer 3 with a thickness of 1-20 μm. The monocrystalline silicon epitaxial layer 3 obtained through this step has good crystalline quality and mechanical properties, and can provide stable support for the vibration of the PMUT, reducing the influence of structural defects on the performance of the device.
[0062] It should be noted that Figure 4 The upper surface of the silicon substrate 1 on which the cavity 2 is formed in step S1 is not flat, and after the surface roughness is optimized through the above step S2, a flat upper surface as shown in Figure 5 is formed, which facilitates the deposition of silicon atoms on the surface of the silicon substrate 1 in the subsequent step S3. In addition, Figure 6 The upper surface of the monocrystalline silicon epitaxial layer 3 formed in step S3 is not flat, and after the surface roughness is optimized through the above step S4, a flat upper surface as shown in Figure 7 is formed, which facilitates the preparation of the PMUT in the subsequent step S5.
[0063] It can be understood that the above SON process forms a cavity 2 with a highly precise shape and size and a depth-to-width ratio of 3-9.5 in the silicon substrate 1 through precise photolithography and etching steps, and the monocrystalline silicon epitaxial layer 3 with a thickness of 1-20 μm grown above the cavity 2 by the silicon epitaxial process can form a good match with the cavity 2, so that the edges of the subsequently prepared PMUT structure are precisely controlled, improving the consistency and stability of the performance of the device. Such a process route is relatively simple, without the need for complex backside lithography alignment and deep silicon etching steps, reducing the number of process steps and equipment investment, and lowering production costs, which is conducive to large-scale industrial production.
[0064] Specifically, the silicon substrate 1 is a p-type silicon substrate with a <100> crystal orientation, a resistivity of 1-10 Ω·cm, and a thickness of 500-600 μm; the upper electrode 4 and the lower electrode 6 are both made of metal material and are both prepared by sputtering or evaporation process; the piezoelectric layer 5 is made of at least one of PZT, PVDF, AIN and their dopants and is prepared by sol-gel method or sputtering method.
[0065] Referring to Figures 8 to 9 , the above step S5 includes:
[0066] On the single-crystal silicon epitaxial layer 3 as shown in Figure 8 , the lower electrode 4, the piezoelectric layer 5 and the upper electrode 6 are prepared in sequence; the lower electrode 4, the piezoelectric layer 5 and the upper electrode 6 are subjected to patterning treatment as shown in Figure 9 , to form the vibration unit of the PMUT. Optionally, the specific preparation process is as follows:
[0067] Preparation of the lower electrode 4: a metal thin film with a thickness of 100-200 nm is deposited on the surface of the single-crystal silicon epitaxial layer 3 by magnetron sputtering process; then the metal thin film is patterned by photolithography and ion beam etching process to form the lower electrode 4;
[0068] Preparation of the piezoelectric layer 5: according to the required PZT, PVDF, AIN and their dopants, the piezoelectric layer 5 is subjected to patterning treatment by photolithography and ion beam etching process;
[0069] Preparation of the upper electrode 6: a metal thin film with a thickness of 100-200 nm is deposited on the surface of the piezoelectric layer 5 by electron beam evaporation process; the metal thin film is patterned by photolithography and wet etching process to form the upper electrode 6.
[0070] It can be understood that the piezoelectric layer 5 can be selected according to different application requirements to further improve the sensitivity and reliability of the PMUT.
[0071] Embodiment 2
[0072] Referring to Figure 9 , a PMUT prepared by the PMUT preparation method based on SON and silicon epitaxial process of the above embodiment 1, includes a substrate 1, a cavity 2, a single-crystal silicon epitaxial layer 3, a lower electrode 4, a piezoelectric layer 5 and an upper electrode 6; the cavity 2 is formed in the interior of the silicon substrate 1; the single-crystal silicon epitaxial layer 3 is arranged on the upper surface of the silicon substrate 1 and covers the cavity 2; the lower electrode 4 is arranged on the upper surface of the single-crystal silicon epitaxial layer 3; the piezoelectric layer 5 is arranged on the upper surface of the lower electrode 4; and the upper electrode 6 is arranged on the upper surface of the piezoelectric layer 5.
[0073] Embodiment 3
[0074] Referring to Figure 10The difference between the embodiment and the embodiment 2 is that a passivation layer 7 is deposited on the upper surface of the upper electrode 6; and an electrical connection electrode 8 is arranged on the passivation layer 7 and penetrates the passivation layer 7 to contact the upper surface of the upper electrode 6. Optionally, the material of the passivation layer 7 is silicon oxide or silicon nitride; and the material of the electrical connection electrode 8 is aluminum, gold or platinum. The PMUT in the embodiment is prepared by using the PMUT preparation method based on the SON and silicon epitaxial process in the embodiment 1, which will not be described herein.
[0075] The above embodiments are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and essence of the present application should be covered within the protection scope of the present application.
Claims
1. A method for fabricating PMUTs based on SON and silicon epitaxial processes, characterized in that, Includes the following steps: S1. A cavity (2) is formed on a silicon substrate (1) using the SON process; S2. Annealing treatment to optimize the roughness of the silicon surface above the cavity (2); S3. A single-crystal silicon epitaxial layer (3) is formed above the cavity (2) using silicon epitaxial technology; S4. Planarization is performed using CMP to optimize the surface roughness of the single-crystal silicon epitaxial layer (3); S5. PMUT is prepared on top of the single-crystal silicon epitaxial layer (3).
2. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 1, characterized in that, Step S1 includes the following steps: S11. Clean the silicon substrate (1) to remove surface impurities and the native oxide layer; S12. Multiple shallow trenches arranged in a regular pattern are formed inside the silicon substrate (1) using an etching process; S13. High-temperature annealing treatment causes silicon atoms around each shallow trench to migrate and fill the bottom of each shallow trench, forming a cavity (2) of a predetermined size inside the silicon substrate (1).
3. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 1, characterized in that, Step S3 includes: The silicon substrate (1) is placed in an epitaxial growth furnace. Under high temperature and low pressure, silicon source gas is introduced to deposit silicon atoms on the surface of the silicon substrate (1) and above the cavity (2) to grow a single crystal silicon epitaxial layer (3).
4. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 1, characterized in that, Step S5 includes: A lower electrode (4), a piezoelectric layer (5), and an upper electrode (6) are sequentially fabricated above a single-crystal silicon epitaxial layer (3); the lower electrode (4), the piezoelectric layer (5), and the upper electrode (6) are patterned by photolithography and etching processes to form the vibration unit of the PMUT.
5. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 1, characterized in that, Both the upper electrode (4) and the lower electrode (6) are made of metallic materials and are prepared by sputtering or evaporation processes.
6. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 1, characterized in that, The piezoelectric layer (5) is made of at least one of PZT, PVDF, AIN and their dopants, and is prepared by sol-gel method or sputtering method.
7. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 2, characterized in that, In step S13, the depth and width of the cavity (2) satisfy the depth-to-width ratio between 3:1 and 9.5:
1.
8. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 3, characterized in that, In step S3, the growth temperature of silicon epitaxy is 1050–1150°C, and the growth pressure is 10–50 mbar.
9. The PMUT fabrication method based on SON and silicon epitaxial processes according to claim 3, characterized in that, In step S3, the thickness of the single-crystal silicon epitaxial layer (3) is 1 to 20 μm.
10. A PMUT fabricated using the PMUT fabrication method based on SON and silicon epitaxial processes as described in any one of claims 1 to 9, characterized in that, The device includes a silicon substrate (1), a cavity (2), a single-crystal silicon epitaxial layer (3), a lower electrode (4), a piezoelectric layer (5), and an upper electrode (6); the cavity (2) is formed inside the silicon substrate (1); the single-crystal silicon epitaxial layer (3) is disposed on the upper surface of the silicon substrate (1) and covers the cavity (2); the lower electrode (4) is disposed on the upper surface of the single-crystal silicon epitaxial layer (3); the piezoelectric layer (5) is disposed on the upper surface of the lower electrode (4); and the upper electrode (6) is disposed on the upper surface of the piezoelectric layer (5).