Chip surface defect detection method, electronic equipment and readable medium

Abstract

The invention discloses a chip surface defect detection method, electronic equipment and a readable medium. The method comprises the following steps: aligning an ROI (Region of Interest) of a reference image with a test image through affine transformation; obtaining a gray average value of the ROI of the reference image and the ROI of the aligned test image, and carrying out gray stretching normalization processing on the test image based on the gray average value; respectively carrying out mean filtering on the reference image and the test image after normalization processing, and carrying out differential operation to obtain a differential image; performing threshold-based binary segmentation on the difference image, extracting surface detection candidate areas of bright defects and dark defects, performing morphological corrosion operation on the surface detection candidate areas to suppress noise, and generating a final defect mask; and mapping a defect area in the final defect mask back to the original test image coordinate system through inverse transformation of affine transformation. According to the method, high-precision smudginess defect extraction of the IPM chip area under the background of complex brightness can be realized, and the method is suitable for various complex packaging working conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of machine vision detection, image processing and electronic device automatic detection, and particularly relates to a chip surface defect detection method. BACKGROUND

[0002] Intelligent Power Module (IPM) as a key high-integration device in power electronic system, is widely used in industrial automation, electric vehicles, household appliances, new energy power generation and other fields. IPM usually integrates IGBT, FRD, drive IC, protection circuit and other chips in the same package module, and has both high current transmission capability and control logic function. With the expansion of application fields, the integration of IPM continues to improve, the structure becomes more complex, the packaging form is diversified, and the manufacturing and detection difficulty increases significantly.

[0003] In the production process, due to the chip exposed in the module or using transparent colloid packaging, it is easy to be affected by process impurity residues, bonding pollution, lead deviation, chip oxidation and blackening and other factors, forming a series of microscopic defects. These defects may not necessarily cause electrical abnormalities at the beginning, but long-term use may induce breakdown, thermal runaway or module failure, which seriously affects the safety and stability of the whole machine. Therefore, the surface defect detection of the chip inside the IPM module has become an important link to ensure its reliability.

[0004] At present, the industry mainly uses the following detection methods to evaluate the quality of IPM module: · Manual visual inspection or magnifying glass inspection: this method relies on the experience of skilled inspectors for surface observation, but it is subjective, has poor stability, low efficiency, and it is difficult to find small or low-contrast defects; · Automatic optical inspection (AOI): through industrial camera combined with image algorithm to identify defects of chip, suitable for detecting surface problems such as stains, broken lines, scratches, etc., but has weak recognition ability for non-structured defects such as uneven gray scale, local darkening (such as chip blackening); · X-ray non-destructive testing: can identify internal virtual welding, bubbles and other structural problems of chip, but has no response to surface dirt, brightness change and non-structural abnormalities; · Electrical performance test: including on-resistance, gate drive, breakdown voltage and other parameter test, which can judge whether the chip function is abnormal, but it is difficult to trace the specific physical location of abnormality.

[0005] The above methods can guarantee the reliability of IPM module to some extent, but there are still obvious deficiencies in dealing with the surface non-structural defect detection of complex chip structure: • It is difficult to stably identify brightness unevenness or overall blackening defects, especially when the reflectivity of the encapsulating glue is inconsistent, the illumination is uneven, and the background stray light interferes. The threshold setting of the traditional algorithm is prone to failure; • The traditional AOI method based on template matching or edge detection is highly sensitive to chip arrangement. When the multi-chip (IGBT, FRD, control IC) arrangement in the IPM is irregular or slightly offset, the false detection rate significantly increases; • There is a lack of unified standardized image enhancement strategy. In a multi-batch, multi-light source, and multi-lens environment, the poor image stability leads to poor detection consistency; • The overall algorithm system has poor robustness and weak generalization ability. For "light pollution" defects or blackening shadow area defects, the recognition is unstable, resulting in missed detection or false reporting; • The defect positioning is not accurate, and it cannot effectively provide a basis for subsequent rework or failure analysis.

[0006] In summary, the prior art cannot effectively solve the problem of automatic detection of brightness unevenness and local pollution defects under complex chip structures. In order to improve detection accuracy, reduce manual intervention, and improve IPM yield and traceability, a high-robustness surface defect detection method combining image enhancement and differential detection strategy is needed, which is suitable for IPM modules with complex multi-chip structures, especially for non-structural defects such as micro-pollution, blackening, and uneven brightness, which are currently common but easily missed. SUMMARY

[0007] According to a first aspect of an embodiment of the present application, a chip surface defect detection method is provided, comprising the following steps: Image registration: Obtain the ROI of the reference image and the test image, align the ROI of the reference image with the test image through affine transformation, and eliminate the displacement and angle deviation between the test image and the reference image; Image normalization: Obtain the gray mean value of the ROI of the reference image and the aligned test image, perform gray stretch normalization processing on the test image based on the gray mean value, and eliminate the illumination difference; Differential enhancement: Perform mean filtering on the normalized reference image and test image, respectively, and perform differential operation on the filtered test image and the filtered reference image to obtain a differential image; Defect extraction: Perform threshold-based binary segmentation on the differential image, extract the surface detection candidate region of bright defects and dark defects, and perform morphological erosion operation on the surface detection candidate region to suppress noise, generating a final defect mask; Defect mapping: Map the defect area in the final defect mask back to the original test image coordinate system through inverse affine transformation, and complete defect positioning.

[0008] Further, the ROI of the reference image is aligned with the test image by affine transformation, specifically: Given a reference point and a target point and a rotation angle , a two-dimensional affine matrix is constructed: ; The ROI of the reference image is mapped to the test image by: ; Where (x, y) is the pixel coordinate of the reference image, is the corresponding coordinate in the test image after transformation.

[0009] Further, the test image is normalized by gray scale stretching based on the mean gray value, specifically: The normalization factor is calculated: ; Where, is the mean gray value of the ROI of the reference image; is the mean gray value of the ROI of the test image; The test image is subjected to a gray scale stretching transformation to obtain a stretched image: ; Where, is the test image; is the stretched image.

[0010] Further, the difference enhancement step is specifically: The normalized reference image and test image are subjected to mean filtering respectively: ; Where, is the mean filtering function; is the mean filtered test image; is the mean filtered reference image; The difference image is calculated: ; Where, is the difference image.

[0011] Further, the defect extraction step is specifically: The surface detection candidate regions of bright defects and dark defects are extracted in the difference image, if (x, y) < 128 - Td, it is the surface detection candidate region of dark defects, Td is the contrast of dark defects; if (x, y) > 128 + Tb, Tb is the contrast of dark defects; A morphological erosion operation is applied to the extracted candidate region to suppress noise regions, and a noise-eliminated image is obtained, and the formula is as follows: ; Wherein, is the noise-eliminated image; is the erosion operation; is the kernel size of the erosion operation; Based on the noise-eliminated image, a final defect mask is generated: ; Wherein, is the final defect mask; is the union operator.

[0012] Further, it further comprises a scratch detection step, specifically: A first-order Gaussian derivative filter is used to perform a multi-directional convolution operation on the difference image to extract a linear feature response map : ; Wherein, * is a convolution operation; is a first-order Gaussian derivative filter; The response scale is controlled, and is set for different scratch widths; The response map is subjected to gray threshold processing to extract a strong response region as a scratch candidate region : ; Wherein, is the pixel gray value of the linear response map at coordinates (x, y); is a dark defect threshold; is a bright defect threshold; Based on the aspect ratio and direction consistency of the scratch candidate region, geometric filtering is performed to remove non-linear artifacts, and a final scratch candidate region is obtained; The final scratch candidate region is mapped back to the original test image coordinate system through inverse affine transformation.

[0013] Further, it further comprises a collapse detection step, specifically: Based on the ROI profile of the chip, the central part is removed by an erosion operation, only the edge region is retained, and a boundary erosion band region is constructed : ; Wherein, is an erosion operator; d is an erosion distance; is a ROI region of the chip; erodes the boundary to a band region erodes again to obtain an intermediate difference region wherein s is a safety distance; in the intermediate difference region extracts pixel points with a gray value lower than a threshold T to form a collapse edge candidate region wherein, is a pixel brightness value of the original gray image at coordinates (x, y); cross-analyzes the collapse edge candidate region and the original boundary of the chip to verify whether the collapse edge candidate region intersects with the original edge of the chip, and obtains a final collapse edge candidate region; maps the final collapse edge candidate region back to the original test image coordinate system through inverse transformation of the affine transformation.

[0014] Further, the method further comprises a shielding processing step, specifically: excluding a non-detection region through a predefined mask, the non-detection region including a pad, an electrode, and a probe contact region.

[0015] According to a second aspect of the embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program, the computer program being stored in the memory, and the processor running the computer program to execute the chip surface defect detection method of the first aspect.

[0016] According to a third aspect of the embodiment of the present application, a readable medium having non-volatile program code executable by a processor is provided, the program code causing the processor to run the chip surface defect detection method of the first aspect.

[0017] The chip surface defect detection method according to the embodiment of the present application has the following beneficial effects: Combination of brightness normalization and difference enhancement: uniform processing for black and bright chips, taking into account high response and anti-interference; Dynamic mapping alignment of ROI region: automatic angle correction and region cropping, adaptive to mounting deviation; Morphology and region mask linkage to remove interference: improve the accuracy of defect extraction, suitable for complex packaging structures; Dual-channel defect judgment mechanism: separate threshold enhancement for light and dark, effectively avoiding single threshold misjudgment; Low computational overhead design throughout the process: suitable for deployment in real-time detection systems, supporting batch rapid processing. ​​​​

[0018] Direction-independent scratch extraction algorithm: a Gaussian derivative filter is used to detect linear gray scale changes, which is suitable for multi-directional micro scratches and has strong anti-interference ability; Automatic corrosion analysis of boundary area: for the fixed characteristics of edge collapse position, the edge abnormality is accurately positioned by using area corrosion, difference set and contour intersection; Modular three-class defect linkage detection: this method uniformly processes three types of defects, i.e. surface contamination, scratch and edge collapse, and is suitable for multiple types of IPM chips and convenient for online deployment; High adaptability ROI transformation mechanism: all detections are based on affine alignment and region difference, and support complex production environments such as chip placement micro-variation and angle variation.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the subject technology claimed. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A flowchart of a chip surface defect detection method according to an embodiment of the present application.

[0021] Figure 2 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting blackened products Figure 1 .

[0022] Figure 3 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting blackened products Figure 2 .

[0023] Figure 4 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting blackened products Figure 3 .

[0024] Figure 4 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting blackened products Figure 5 .

[0025] Figure 1 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting surface dirt Figure 7 .

[0026] Figure 2 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting surface dirt Figure 8 .

[0027] Figure 3 A schematic diagram of a chip surface defect detection method according to an embodiment of the present application when detecting surface dirt Figure 9 .

[0028] Figure 4 Schematic diagram for detecting surface dirt when a chip surface defect detection method according to an embodiment of the application is used Figure 10 .

[0029] Figure 5 Schematic diagram for detecting surface dirt when a chip surface defect detection method according to an embodiment of the application is used Figure 11 .

[0030] Figure 6 Schematic diagram for detecting surface dirt when a chip surface defect detection method according to an embodiment of the application is used Figure 12 .

[0031] Figure 7 Schematic diagram for detecting surface dirt when a chip surface defect detection method according to an embodiment of the application is used Figure 13 .

[0032] Figure 1 Schematic diagram for detecting edge collapse when a chip surface defect detection method according to an embodiment of the application is used Figure 14 .

[0033] Figure 2 Schematic diagram for detecting edge collapse when a chip surface defect detection method according to an embodiment of the application is used Figure 15 .

[0034] Figure 3 Schematic diagram for detecting edge collapse when a chip surface defect detection method according to an embodiment of the application is used Figure 16 .

[0035] Figure 1 Schematic diagram for detecting scratches when a chip surface defect detection method according to an embodiment of the application is used Figure 17 .

[0036] Figure 2 Schematic diagram for detecting scratches when a chip surface defect detection method according to an embodiment of the application is used Figure 18 .

[0037] Figure 3 Schematic diagram for detecting scratches when a chip surface defect detection method according to an embodiment of the application is used Figure 19 .

[0038] Figures 1 to 19 Structure schematic diagram of an electronic device according to an embodiment of the application. DETAILED DESCRIPTION

[0039] The preferred embodiments of the present application will be described in detail with reference to the drawings. The following description is made with reference to the accompanying drawings.

[0040] Firstly, the present application will be described in detailFigure 1 A chip surface defect detection method according to an embodiment of the present application is described, which is used for surface defect identification of chip packaging area (including IGBT, FRD, IC and other components) in IPM (intelligent power module), and is widely applied to surface quality detection links in semiconductor packaging, power electronic module manufacturing, automobile electronics and other industries.

[0041] As shown in Figures 2 to 5 A chip surface defect detection method according to an embodiment of the present application has the following steps: In S1, image registration: the ROI of the reference image and the test image are obtained, the ROI of the reference image is aligned with the test image through affine transformation, and the displacement and angle deviation between the test image and the reference image are eliminated. The ROI of the reference image is aligned with the test image through affine transformation specifically as follows: Given the reference point and the target point and the rotation angle , a two-dimensional affine matrix is constructed: ; The ROI of the reference image is mapped to the test image by the following formula: ; Where (x, y) is the pixel coordinate of the reference image, is the corresponding coordinate in the test image after transformation. The target image block is extracted from the transformed region for subsequent enhancement.

[0042] In S2, image normalization: the gray mean value of the ROI of the reference image and the ROI of the aligned test image is obtained, the test image is processed by gray stretch normalization based on the gray mean value, and the light difference is eliminated. The test image is processed by gray stretch normalization based on the gray mean value specifically as follows: The normalization factor is calculated: ; Where, is the ROI gray mean value of the reference image; is the ROI gray mean value of the test image; The test image is processed by gray stretch transformation to obtain a stretch image: ; Where, is the test image; is the stretch image.

[0043] In S3, differential enhancement: mean filtering is performed on the normalized reference image and test image respectively, and the filtered test image is subtracted from the filtered reference image to obtain a difference image. The differential enhancement step is specifically: The normalized reference image and test image are respectively subjected to mean filtering: Wherein, is a mean filtering function; is mean filtering on the test image; is mean filtering on the reference image; The difference image is calculated: Wherein, is a difference image.

[0044] In S4, defect extraction: threshold-based binary segmentation is performed on the difference image to extract surface detection candidate regions of bright defects and dark defects, and morphological erosion operation is performed on the surface detection candidate regions to suppress noise, generating a final defect mask. The defect extraction step is specifically: The surface detection candidate regions of bright defects and dark defects are extracted in the difference image, and if (x,y) < 128-T d , it is a surface detection candidate region of dark defects, T d is the dark defect contrast; if (x,y) > 128+T b , it is a surface detection candidate region of bright defects, T b is the dark defect contrast; Morphological erosion operation (convolution window size ) is applied to the extracted surface detection candidate regions to suppress noise regions, and the image after eliminating noise points is obtained, and the formula is as follows: Wherein, is an image after eliminating noise points; is an erosion operation; is an erosion operation kernel size; Based on the image after eliminating noise points, a final defect mask is generated: Wherein, is a final defect mask; is a union operator.

[0045] ​​​​In S5, defect mapping: mapping the defect area in the final defect mask back to the original test image coordinate system through inverse transformation of the affine transformation, completing defect positioning, and ensuring that the final result can be used for accurate review by the AOI system.

[0046] Further, the chip surface defect detection method of the embodiment of the present application further comprises a scratch detection step, specifically: using a first-order Gaussian derivative filter to filter the difference image performing multi-direction convolution operation to extract linear feature response map : ; wherein * is a convolution operation; is a first-order Gaussian derivative filter; controlling the response scale, and setting for different scratch widths; this operation can extract the linear features existing in any direction; performing gray threshold processing on the response map extracting the strong response area as a scratch candidate area : ; wherein, is the pixel gray value of the linear response map at coordinates (x, y); is a dark defect threshold; is a bright defect threshold; performing geometric filtering based on the aspect ratio and direction consistency of the scratch candidate area to remove non-linear artifacts, and obtaining the final scratch candidate area; if further stability enhancement is required, local gray contrast can be introduced as an additional filtering condition; mapping the final scratch candidate area back to the original test image coordinate system through inverse transformation of the affine transformation.

[0047] Further, the chip surface defect detection method of the embodiment of the present application further comprises a chip edge collapse detection step, specifically: based on the ROI profile of the chip, removing the center part through erosion operation, and only retaining the edge region to construct a boundary erosion band region : ; wherein, is an erosion operator; d is an erosion distance; is the ROI region of the chip; eroding the boundary erosion band region again to obtain an intermediate difference region : ; wherein s is a safety distance; In the middle difference region In the middle difference region, the pixel points with the gray value lower than the threshold T are extracted to form a chipped edge candidate region Wherein, is the pixel brightness value of the original gray image at coordinates (x, y); The chipped edge candidate region is cross-analyzed with the original chip boundary to verify whether the chipped edge candidate region intersects with the original chip edge, and the final chipped edge candidate region is obtained. The final chipped edge candidate region is mapped back to the original test image coordinate system through inverse transformation of the affine transformation.

[0048] Further, the chip surface defect detection method of the embodiment of the application further comprises a shielding processing step, specifically: excluding non-detection regions including pads, electrodes, and probe contact regions through a predefined mask.

[0049] Actual application examples: In an actual semiconductor packaging AOI system, the method of the application is applied to factory detection of multiple IPM modules. Through automatic identification of surface scratches, chipped edges, and dirt of IGBT and FRD chips, manual misjudgment is effectively reduced, and yield and efficiency are improved. The method has been successfully deployed in the third detection process of multiple power module manufacturing enterprises, and has high universality and portability.

[0050] The blackened product diagram is as shown in Figures 6 to 12 , which can be normally detected and will not be misdetected or missed; As shown in Figures 13 to 15 , surface dirt can be normally detected and will not be misdetected or missed; As shown in Figures 16 to 18 , the chipped edge can be normally detected and will not be misdetected or missed; As shown in Figures 1 to 18 , scratches can be normally detected and will not be misdetected or missed.

[0051] The chip surface defect detection method according to the embodiment of the application is described above with reference to the accompanying drawings. Figure 19 Further, the application can also be applied to an electronic device.

[0052] As shown in ​ , according to the second aspect of the embodiment of the application, an electronic device is provided, which comprises a memory 1, a processor 2, and a computer program 3, the computer program 3 is stored in the memory 1, and the processor 2 runs the computer program 3 to execute the chip surface defect detection method of the first aspect.

[0053] ​​According to a third aspect of the embodiments of the present application, a readable medium having non-volatile program codes executable by a processor is provided, and the program codes enable the processor to execute the chip surface defect detection method of the first aspect.

[0054] The readable storage medium can be a computer storage medium or a communication medium. The communication medium includes any medium that facilitates the transfer of computer program from one place to another. The computer storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. For example, the readable storage medium is coupled to the processor, so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an application-specific integrated circuit. In addition, the application-specific integrated circuit can be located in a device. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. The present application also provides a program product including execution instructions stored in a readable storage medium. At least one processor of the device can read the execution instructions from the readable storage medium, and the at least one processor executes the execution instructions to enable the device to implement the chip surface defect detection method provided by the various embodiments described above. In the above-mentioned embodiments of the device, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in the present application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0055] It should be noted that in the present specification, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles, or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles, or devices. Without more limitations, the elements defined by the statement "including" do not exclude the presence of other identical elements in the processes, methods, articles, or devices including the elements.

[0056] While the application has been described in detail and with reference to specific preferred embodiments thereof, it will be apparent to one skilled in the art that various modifications and alternatives can be employed without departing from the spirit and scope of the application. Accordingly, the scope of the application should be determined by the appended claims and their equivalents.

Claims

1. A method for detecting defects on the surface of a chip, characterized in that, It includes the following steps: Image registration: Obtain the ROI of the reference image and the test image, and align the ROI of the reference image with the test image through affine transformation to eliminate the displacement and angular deviation between the test image and the reference image; Image normalization: Obtain the mean grayscale value of the ROI of the reference image and the ROI of the aligned test image, and perform grayscale stretching normalization processing on the test image based on the mean grayscale value to eliminate illumination differences. Differential enhancement: The normalized reference image and the test image are respectively subjected to mean filtering, and the filtered test image and the filtered reference image are subjected to difference operation to obtain the difference image; Defect extraction: The differential image is subjected to threshold-based binary segmentation to extract surface detection candidate regions for bright and dark defects, and morphological erosion is performed on the surface detection candidate regions to suppress noise, generating the final defect mask. Defect mapping: The defect region in the final defect mask is mapped back to the original test image coordinate system through the inverse affine transformation to complete the defect localization.

2. The chip surface defect detection method as described in claim 1, characterized in that, Aligning the ROI of the reference image with the test image through affine transformation specifically involves: Given a reference point and target point and rotation angle Construct a two-dimensional affine matrix: ； The ROI of the reference image is mapped to the test image using the following formula: ； Where (x, y) are the pixel coordinates of the reference image. These are the coordinates of the transformed image in the test image.

3. The chip surface defect detection method as described in claim 2, characterized in that, The grayscale stretching and normalization process performed on the test image based on the grayscale mean is as follows: Calculate the normalization factor : ； in, The mean grayscale value of the ROI in the reference image; The mean grayscale value of the ROI in the test image; The stretched image is obtained by performing a grayscale stretching transformation on the test image: ； in, For testing images; For stretching the image.

4. The chip surface defect detection method as described in claim 3, characterized in that, The differential enhancement specifically refers to: Mean filtering is applied to both the normalized reference and test images: ； in, It is a mean filtering function; To perform mean filtering on the test image; To perform mean filtering on the reference image; Calculate the difference image: ； in, This is a difference image.

5. The chip surface defect detection method as described in claim 4, characterized in that, The defect extraction specifically involves: Extract candidate surface detection regions for bright and dark defects from the difference image. (x,y)<128-T d , then it is a candidate region for surface detection of dark defects, T d For dark defect contrast; if (x,y)>128+T b , then it is a candidate region for surface detection of bright defects, T b For dark defect contrast; Morphological erosion is applied to the extracted surface detection candidate regions to suppress noise, resulting in a noise-reduced image, as shown in the following formula: ； in, The image after noise removal; This is a corrosion operation; For the core size of the corrosion operation; Based on the noise-reduced image, generate the final defect mask: ； in, For the final defect mask; This is the union operator.

6. The chip surface defect detection method as described in claim 4, characterized in that, It also includes a scratch detection step, specifically: Using a first-order Gaussian derivative filter for difference images Perform multi-directional convolution operations to extract linear feature response maps. : ； Where * represents the convolution operation; It is a first-order Gaussian derivative filter; Control the response scale and set it for different scratch widths; Response diagram Perform grayscale thresholding to extract strong response regions as candidate scratch regions. : ； in, This represents the pixel grayscale value at coordinates (x, y) of the linear response map; The threshold for dark defects; Brightness defect threshold; Geometric filtering is performed based on the aspect ratio and orientation consistency of the scratch candidate region to eliminate nonlinear artifacts and obtain the final scratch candidate region. The final scratch candidate regions are mapped back to the original test image coordinate system through the inverse affine transformation.

7. The chip surface defect detection method as described in claim 1, characterized in that, It also includes a chipping detection step, specifically: Based on the chip's ROI profile, the central portion is removed through etching, leaving only the edge areas, thus constructing the boundary etched zone region. : ； in, Here, d represents the erosion operator; d is the erosion distance. This refers to the ROI region of the chip. For the boundary corrosion zone region Further erosion yields intermediate difference regions. : ； Where s is the safety distance; In the intermediate difference region Within the region, pixels with grayscale values ​​below a threshold T are extracted to form candidate regions for edge collapse. : ； in, This represents the pixel brightness value at coordinates (x, y) of the original grayscale image. Cross-analysis is performed between the candidate chip edge breakage regions and the original chip boundary to verify whether the candidate chip edge breakage regions intersect with the original chip edge, and the final candidate chip edge breakage regions are obtained. The final candidate regions for edge collapse are mapped back to the original test image coordinate system through the inverse affine transformation.

8. The chip surface defect detection method as described in claim 1, characterized in that, It also includes a shielding process, specifically: excluding non-detection areas using a predefined mask, the non-detection areas including pads, electrodes, and probe contact areas.

9. An electronic device, characterized in that, include: The device includes a memory, a processor, and a computer program, wherein the computer program is stored in the memory and the processor executes the computer program to perform a chip surface defect detection method according to any one of claims 1 to 8.

10. A readable medium having processor-executable non-volatile program code, characterized in that, The program code causes the processor to run a chip surface defect detection method according to any one of claims 1-8.

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