Active gate drive drain-source overvoltage and overcurrent suppression device of silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention provides a device for inhibiting drain-source overvoltage and overcurrent through active gate drive of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), aiming at solving the problem of voltage or current overshoot caused by circuit parasitic parameters in a high-speed switching process of the SiC MOSFET and simultaneously considering the switching speed and energy loss balance. According to the device, drain-source voltage vdc and direct-current bus voltage of the SiC MOSFET are collected to serve as feedback signals, and gate driving voltage and equivalent gate resistance are dynamically adjusted; in a key stage (a Miller plateau switching-on period and a voltage rising period switching-off period) of a switch transient state, a gate resistance network is switched through a logic control circuit, and suppression of drain current overshoot and drain-source voltage overshoot is realized. Simulation verification shows that the device can reduce voltage overshoot by 20%-30% and current overshoot by 25%-60%, only a single voltage feedback channel is needed, the cost is obviously lower than that of a traditional multi-signal acquisition active gate driving scheme, and the device is suitable for a high-efficiency SiC MOSFET power converter.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronic device driving, and particularly relates to an active gate driving device and method for silicon carbide (SiC) MOSFET, which is suitable for new energy grid-connected converters, electric vehicle inverters, industrial frequency converters and other high-efficiency power conversion scenarios. BACKGROUND

[0002] As a third-generation wide-bandgap semiconductor device, silicon carbide (SiC) MOSFET has the advantages of high breakdown field strength, fast switching speed, good high-temperature performance, etc., which can significantly reduce the switching loss of power converters and improve system efficiency. However, the high-speed switching characteristics of SiC MOSFET can cause high d i / dt and d v / dt in the switching transient process, combined with the parasitic inductance (such as power loop parasitic inductance L σ1 = 30nH, L σ2 = 50nH) and parasitic capacitance (such as gate-drain capacitance C gd） , which is easy to cause drain-source voltage overshoot ( ) and drain current overshoot ( ).

[0003] The traditional fixed gate resistance driving scheme (CGD) has inherent contradictions: if a small gate resistance is used to ensure switching speed, it will exacerbate voltage or current overshoot, which may cause SiC MOSFET to exceed the safe operating area (SOA); if a large gate resistance is used to suppress overshoot, it will increase switching loss and lose the efficiency advantage of SiC devices. The existing active gate driving scheme (AGD) relies on multi-channel current, voltage sampling and digital signal processor (DSP), which can achieve dynamic control, but has problems such as high cost, high circuit complexity, large delay, etc., and is difficult to be applied on a large scale.

[0004] Therefore, there is an urgent need for a low-cost, high-response-speed active gate driving scheme to balance switching speed, overshoot suppression and energy loss through precise transient control, and to fully exert the performance advantage of SiC MOSFET. SUMMARY

[0005] The purpose of the present application is to overcome the overvoltage and overcurrent between the drain and source caused by the fast switching of the existing silicon carbide (SiC) MOSFET, and to provide an active gate driving device and method for silicon carbide (SiC) MOSFET, which aims to realize a low-cost control method to solve the SIC switching overshoot.

[0006] In order to achieve the above purpose, the present application provides an active gate driving device for silicon carbide MOSFET to suppress drain-source overvoltage and overcurrent, which comprises: Conventional gate drive module, voltage sampling module, logic control module, dynamic gate resistor network module, and SiCMOSFET power module; The conventional gate drive module is used to generate two-stage gate drive voltages for turn-on and turn-off. The output is sent to the dynamic gate resistor network module. The voltage sampling module includes a drain-source voltage sampling unit to acquire the voltage of the SiC MOSFET. Signal obtained The DC bus voltage sampling unit transmits the sampled signal to the logic control module. The logic control module includes four ultra-high-speed comparators (COMP1-COMP4), AND gates, and NOR gates. With preset reference voltage ( The comparison generates a switching control signal for the dynamic gate resistor network. The dynamic gate resistor network module includes an N-channel MOSFET (M1, for the turn-on phase), a P-channel MOSFET (M2, for the turn-off phase), and a fixed gate resistor (M1, for the turn-off phase). , , , , The equivalent gate resistance is changed by switching M1 / M2 on and off; The SiC MOSFET power module is the driven object, and its drain-source voltage and drain current serve as the feedback signal and the monitoring object, respectively.

[0007] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: This device uses only a single feedback signal, Vds, without the need for current sampling or a digital processor. Furthermore, it differentiates the gate resistance for different overshoot stages during turn-on and turn-off, balancing "switching speed" and "overshoot suppression." The entire device's dynamic resistor network requires only two MOSFETs and a small number of resistors, making it a direct replacement for traditional CGDs with strong compatibility. Attached Figure Description

[0008] Figure 1 A block diagram of the overall structure of a SiC MOSFET active gate driving device based on voltage sampling provided in an embodiment of the present invention; Figure 2 A circuit diagram of a dynamic gate resistor network module provided in an embodiment of the present invention; Figure 3 The circuit diagram of the logic control module provided in the embodiment of the present invention. Detailed Implementation

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0010] The present invention proposes a device for suppressing drain-source overvoltage and overcurrent in the active gate drive of a silicon carbide MOSFET, such as... Figure 1 As shown, it includes: a conventional gate drive module, a voltage sampling module, a logic control module, a dynamic gate resistor network module, and a SiC MOSFET power module; The conventional gate drive module is used to generate two-stage gate drive voltages for turn-on and turn-off. The output is sent to the dynamic gate resistor network module. The voltage sampling module includes a drain-source voltage sampling unit to acquire the voltage of the SiC MOSFET. Signal obtained The DC bus voltage sampling unit transmits the sampled signal to the logic control module. The logic control module includes four ultra-high-speed comparators (COMP1-COMP4), AND gates, and NOR gates. With preset reference voltage ( The comparison generates a switching control signal for the dynamic gate resistor network. The preset reference voltage ( Derived from the DC bus voltage: and Turn-off phase voltage threshold and < , and Voltage threshold for the turn-on phase > The ultra-high-speed comparator uses TLV3601 (2.5ns delay) and LMV7219 (7ns delay) to ensure rapid response of control signals during transient processes.

[0011] The dynamic gate resistor network module includes an N-channel MOSFET (M1, for the turn-on phase), a P-channel MOSFET (M2, for the turn-off phase), and a fixed gate resistor (M1, for the turn-off phase). , , , , The equivalent gate resistance is changed by switching M1 / M2 on and off; Turn-on phase: Initially, M1 is off, and the equivalent gate resistance is... ;when Down to and When the AND gate outputs a high level, it triggers M1 to conduct, and the equivalent gate resistance switches to... ; Turn-off phase: Initially, M2 is turned off, and the equivalent gate resistance is... ;when Rise to and When the OR gate outputs a low level, it triggers M2 to conduct, and the equivalent gate resistance switches to... .

[0012] The SiC MOSFET power module is the driven object, and its drain-source voltage and drain current serve as the feedback signal and the monitoring object, respectively.

[0013] A method for suppressing drain-source overvoltage and overcurrent in an active gate drive of a silicon carbide MOSFET, applied to the aforementioned device, includes the following steps; Step 1: System Initialization: Set the turn-on resistor of the conventional gate drive module , turn-off resistor Dynamic resistance , Preset reference voltage ; Step Two: Activation Phase Control Conventional gate drive module output turn-on voltage Initially, M1 is turned off, and the SiC MOSFET enters the current rise period. The drain current rises rapidly. Voltage sampling module acquires data in real time. get ,when Down to (e.g., 120V) COMP3 outputs a high level; when Continue to decline (e.g., at 80V) COMP4 outputs a high level; The AND gate receives high-level signals from COMP3 and COMP4, outputs a trigger signal to turn on M1, increases the equivalent gate resistance, and slows down the reaction. The charging and discharging current ( Reduce drain current by 30%-50% and suppress drain current overshoot; The principle for suppressing drain current overshoot is as follows: by increasing the equivalent gate resistance, the iCgd of the Miller plateau period is reduced. As shown in Equation 1, the larger Rgon2 is, The smaller the value, the lower the current overshoot amplitude; (1) when When the voltage drops to its minimum value (close to 0V), COMP4 outputs a low level, M1 is turned off, the equivalent gate resistance returns to its initial value, and the turn-on phase ends. Step 3: Shutdown Phase Control Conventional gate drive module outputs turn-off voltage (negative voltage V) EE Initially, M2 is turned off, and the SiC MOSFET enters the voltage rise period. The drain-source voltage rises rapidly. Voltage sampling module acquires data in real time. get ,when Rise to When (e.g., 90V), COMP1 outputs a high level; when Continue to rise to (e.g., at 120V) COMP2 outputs a high level; The NOR gate receives high-level signals from COMP1 and COMP2, outputs a trigger signal to turn on M2, reduces the equivalent gate resistance, and accelerates the capacitance... The discharge rate is reduced (time constant τ is reduced by 20%-40%), suppressing drain-source voltage overshoot; The principle for suppressing drain-source voltage overshoot is as follows: by reducing the equivalent gate resistance, the discharge rate of Cgs is accelerated. As can be seen from Formula 2, The smaller, The faster the drop, the longer the drain current decreases ( The extension of the voltage overshoot reduces the voltage overshoot amplitude. (2) when When the DC bus voltage is reached, COMP2 outputs a low level, M2 is turned off, the equivalent gate resistance returns to its initial value, and the turn-off phase ends. Repeat steps 2-3 repeatedly, and monitor in real time. With drain current ( ), dynamically adjust the on / off state of M1 / M2.

[0014] The method also includes a hardware protection mechanism: a BAT41 diode is connected in series in the dynamic gate resistor network module to prevent current backflow caused by the conduction of the body diodes of M1 / M2; a ZXM61P03F (P-channel MOSFET, turn-on delay 1.9ns) is used as M2 to ensure a fast response during the turn-off phase.

[0015] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0016] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some units can be selected to achieve the purpose of this embodiment according to actual needs.

[0017] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0018] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0019] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A device for suppressing drain-source overvoltage and overcurrent in an active gate drive of a silicon carbide MOSFET, characterized in that, include: Conventional gate drive module, voltage sampling module, logic control module, dynamic gate resistor network module, and SiCMOSFET power module; The conventional gate drive module is used to generate two-stage gate drive voltages for turn-on and turn-off. The output is sent to the dynamic gate resistor network module. The voltage sampling module includes a drain-source voltage sampling unit to acquire the voltage of the SiC MOSFET. Signal obtained The DC bus voltage sampling unit transmits the sampled signal to the logic control module. The logic control module includes four ultra-high-speed comparators (COMP1-COMP4), AND gates, and NOR gates. With preset reference voltage ( The comparison generates a switching control signal for the dynamic gate resistor network. The dynamic gate resistor network module includes an N-channel MOSFET (M1, for the turn-on phase), a P-channel MOSFET (M2, for the turn-off phase), and a fixed gate resistor (M1, for the turn-off phase). , , , , The equivalent gate resistance is changed by switching M1 / M2 on and off; The SiC MOSFET power module is the driven object, and its drain-source voltage and drain current serve as the feedback signal and the monitoring object, respectively.

2. The apparatus according to claim 1, characterized in that, The preset reference voltage ( Derived from the DC bus voltage: and Turn-off phase voltage threshold and < , and Voltage threshold for the turn-on phase > The ultra-high-speed comparator uses TLV3601 (2.5ns delay) and LMV7219 (7ns delay) to ensure rapid response of control signals during transient processes.

3. The apparatus according to claim 1, characterized in that, The equivalent resistance switching logic of the dynamic gate resistor network module is as follows: Turn-on phase: Initially, M1 is off, and the equivalent gate resistance is... ;when Down to and When the AND gate outputs a high level, it triggers M1 to conduct, and the equivalent gate resistance switches to... ; Turn-off phase: Initially, M2 is turned off, and the equivalent gate resistance is... ;when Rise to and When the OR gate outputs a low level, it triggers M2 to conduct, and the equivalent gate resistance switches to... .

4. A method for suppressing drain-source overvoltage and overcurrent in an active gate drive of a silicon carbide MOSFET, applied to the apparatus described in any one of claims 1-3, characterized in that... Includes the following steps: Step 1: System Initialization: Set the turn-on resistor of the conventional gate drive module , turn-off resistor Dynamic resistance , Preset reference voltage ; Step Two: Activation Phase Control Conventional gate drive module output turn-on voltage Initially, M1 is turned off, and the SiC MOSFET enters the current rise period. The drain current rises rapidly. Voltage sampling module acquires data in real time. get ,when Down to (e.g., 120V) COMP3 outputs a high level; when Continue to decline (e.g., at 80V) COMP4 outputs a high level; The AND gate receives high-level signals from COMP3 and COMP4, outputs a trigger signal to turn on M1, increases the equivalent gate resistance, and slows down the reaction. The charging and discharging current ( Reduce drain current by 30%-50% and suppress drain current overshoot; when When the voltage drops to its minimum value (close to 0V), COMP4 outputs a low level, M1 is turned off, the equivalent gate resistance returns to its initial value, and the turn-on phase ends. Step 3: Shutdown Phase Control Conventional gate drive module outputs turn-off voltage (negative voltage V) EE Initially, M2 is turned off, and the SiC MOSFET enters the voltage rise period. The drain-source voltage rises rapidly. Voltage sampling module acquires data in real time. get ,when Rise to When (e.g., 90V), COMP1 outputs a high level; when Continue to rise to (e.g., at 120V) COMP2 outputs a high level; The NOR gate receives high-level signals from COMP1 and COMP2, outputs a trigger signal to turn on M2, reduces the equivalent gate resistance, and accelerates the capacitance... The discharge rate is reduced (time constant τ is reduced by 20%-40%), suppressing drain-source voltage overshoot; when When the DC bus voltage is reached, COMP2 outputs a low level, M2 is turned off, the equivalent gate resistance returns to its initial value, and the turn-off phase ends. Repeat steps 2-3 repeatedly, and monitor in real time. With drain current ( ), dynamically adjust the on / off state of M1 / M2.

5. The method according to claim 4, characterized in that, In step 2, the principle for suppressing drain current overshoot is as follows: by increasing the equivalent gate resistance, the iCgd of the Miller plateau period is reduced. As shown in Equation 1, the larger Rgon2 is, the lower the drain current overshoot. The smaller the value, the lower the current overshoot amplitude; （1）。 6. The method according to claim 4, characterized in that, In step 3, the principle for suppressing drain-source voltage overshoot is as follows: by reducing the equivalent gate resistance, the discharge rate of Cgs is accelerated. As can be seen from formula 2, The smaller, The faster the drop, the longer the drain current decreases ( The extension of the voltage overshoot reduces the voltage overshoot amplitude. （2）。 7. The method according to claim 4, characterized in that, The method also includes a hardware protection mechanism: a BAT41 diode is connected in series in the dynamic gate resistor network module to prevent current backflow caused by the conduction of the body diodes of M1 / M2; a ZXM61P03F (P-channel MOSFET, turn-on delay 1.9ns) is used as M2 to ensure a fast response during the turn-off phase.

Images