Convolutional code parallel pipeline decoding acceleration system and method based on memory-computing integrated architecture

Abstract

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.

Description

Technical Field

[0001] This invention relates to the field of magnetic storage device technology, and in particular to a parallel pipelined decoding acceleration system and method for convolutional codes based on a storage-computing integrated architecture. Background Technology

[0002] Magnetic tape storage plays an irreplaceable role in data storage due to its advantages such as high storage density, low cost, and long data storage lifespan. With the rapid development of information technology and the integration of data with various industries, data volume is exploding, and data transmission rates are constantly rising, placing higher demands on the data read / write speed and reliability of magnetic tape storage systems. Convolutional codes, as a commonly used error correction coding method, are widely used in magnetic tape storage to improve data reliability. The decoding process of convolutional codes relies on the Viterbi algorithm and requires steps such as branch metric calculation, path expansion, and surviving path backtracking. In traditional architectures, the intermediate results of mesh graph state transitions need to be repeatedly transferred between storage and computation units. This method processes data bit by bit, resulting in slow decoding speed and high latency, which cannot meet the ever-increasing demands for data storage and processing. Therefore, it is necessary to build an efficient, low-latency, and resource-utilization-efficient convolutional code decoding acceleration system to meet the requirements of low cost, long lifespan, and high density in modern magnetic tape storage.

[0003] Existing solutions for accelerating convolutional code decoding primarily focus on two aspects: software algorithm optimization and hardware architecture improvement. Regarding software algorithms, some studies employ improved Viterbi decoding algorithms to increase decoding efficiency by reducing unnecessary computational steps. However, this approach is limited by the hardware architecture and cannot completely solve the latency problem caused by data transfer. In terms of hardware architecture, some designs use application-specific integrated circuits (ASICs) to implement convolutional code decoding, improving processing speed through customized hardware structures. However, these ASIC designs are often designed for specific convolutional code parameters, lacking versatility and being difficult to flexibly adjust to complex and varied real-world application scenarios.

[0004] Furthermore, some field-programmable gate array (FPGA)-based solutions implement convolutional code decoding by dynamically configuring logic resources. However, FPGAs have shortcomings in the coordination between data storage and computation. Data transmission between on-chip storage and computation modules still incurs some latency, and the resource utilization efficiency of FPGAs needs further improvement. For example, some FPGA-implemented convolutional code decoding systems, when processing large-scale data, suffer from unreasonable resource allocation, resulting in some logic units being idle while others are overloaded, and overall performance failing to reach its optimal level.

[0005] Therefore, the existing technology has the following drawbacks:

[0006] (1) Low decoding efficiency. The data transfer delay of the convolutional code decoding acceleration system under the traditional architecture is serious. Whether it is software optimization or hardware improvement, it is impossible to avoid the frequent transmission of data between the storage unit and the computing unit. This has become a key factor restricting the improvement of decoding speed.

[0007] (2) Low resource utilization. Existing parallel computing schemes lack intelligence in task allocation and resource scheduling, and cannot dynamically adjust according to the real-time load and data characteristics of computing units, resulting in waste and idle computing resources.

[0008] (3) Insufficient real-time guarantee: In applications with extremely high real-time requirements, the high latency of traditional decoding systems can lead to untimely data processing, affecting user experience and even endangering system security. Summary of the Invention

[0009] Based on the technical problems existing in the background technology, this invention proposes a parallel pipelined decoding acceleration system and method for convolutional codes based on a storage-computing integrated architecture. By reducing data handling, optimizing resource allocation, and improving the system's versatility and flexibility, it achieves efficient and low-latency convolutional code decoding, meeting the requirements of tape storage systems for data processing speed and real-time performance in different application scenarios.

[0010] The present invention proposes a parallel pipelined decoding acceleration system for convolutional codes based on an in-memory computing architecture, comprising:

[0011] The global data scheduling module is used to slice convolutional code data from tape storage devices according to set rules and schedule it through a multi-level caching mechanism;

[0012] The in-memory computing unit array is used to store data tiles and intermediate results output from the global data scheduling module, and performs convolution operations, path metric calculations and surviving path selection through reconfigurable computing units;

[0013] Parallel pipeline controller, used to dynamically allocate decoding tasks and control the pipeline cycle of the in-memory computing unit array;

[0014] The adaptive resource configuration module monitors the system load in real time and dynamically adjusts the data allocation strategy and computing resource scheduling, thereby transmitting signals with the global data scheduling module, the in-memory computing unit array, and the parallel pipeline controller.

[0015] The verification and error correction unit is used to verify and correct the decoding results output by the in-memory computing unit array before outputting them.

[0016] Furthermore, in the global data scheduling module, data tiles are scheduled through a multi-level caching mechanism, specifically as follows:

[0017] Multi-level caching mechanisms include off-chip caching, on-chip caching, and on-chip caching;

[0018] The off-chip buffer receives data tiles output by the global data scheduling module.

[0019] Prefetching techniques are used to prefetch data that is expected to be used in the near future from the off-chip cache to the on-chip cache.

[0020] By using instruction-associated prefetching and execution-driven prefetching, data is prefetched from the on-chip cache to the on-chip cache. The instruction-associated prefetching is based on memory access patterns with fixed steps generated by a set instruction address. The execution-driven prefetching takes the decoded but not yet executed load instructions as the prefetching target and prepares the required data in the on-chip cache before the instructions are actually executed.

[0021] Furthermore, the in-memory computing unit array performs data processing under the control signal of the parallel pipeline controller, and simultaneously receives adjustment signals from the adaptive resource configuration module to optimize its working state.

[0022] Furthermore, the optimization of the working state by receiving the adjustment signal from the adaptive resource configuration module is specifically as follows:

[0023] The in-memory computing unit array dynamically adjusts its operating voltage and clock frequency according to the adjustment signal. The adjustment logic is as follows: the adjustment signal contains voltage and clock frequency configuration levels corresponding to the current system load state. When the system load is high, high voltage and high clock frequency are used to ensure performance; when the system load is low, it switches to low voltage and low clock frequency to reduce power consumption.

[0024] Based on the size of the computing load, some reconfigurable computing units are selectively gated or activated. The selection algorithm is as follows: the adaptive resource configuration module dynamically calculates a target number of active units based on the real-time computing load, and matches the current number of actually active reconfigurable computing units with the target number of active units by activating or gated reconfigurable computing units one by one.

[0025] Based on the numerical accuracy requirements of different computing tasks, the internal computing accuracy mode is adjusted in real time. The adjustment rule is as follows: the adaptive resource configuration module selects one of a set of preset accuracy modes according to the type of the current computing task.

[0026] Furthermore, in the in-memory computing unit array, convolution operations, path metric calculations, and surviving path selection are performed through reconfigurable computing units, specifically:

[0027] The parallel pipeline controller divides the decoding process of convolutional code data by the in-memory computing unit array into a three-stage pipeline;

[0028] The first-level pipeline performs branch metric calculation and accumulation; the second-level pipeline performs path metric comparison and surviving path selection; and the third-level pipeline performs surviving path backtracking.

[0029] Furthermore, the three-stage production line specifically comprises:

[0030] The first-stage pipeline: the in-memory computing unit array receives the received symbols from the channel, and the branch metric calculation unit generates a branch metric for each state in the current time in the mesh graph, and performs parallel addition with the cumulative path metrics of all states in the previous time, thereby generating a set of candidate path metric values ​​containing historical costs and current transfer costs for each current state.

[0031] The second-stage pipeline: The in-memory computing unit array, based on the multi-candidate path metrics from the first stage, selects the path with the smallest value for each state as the surviving path, updates the candidate path metric corresponding to the surviving path as the new official path metric for that state in the memory, and simultaneously generates decision bits by writing the selection result into the surviving path memory.

[0032] The third-stage pipeline: After the decoding process of a complete data block is completed, the backtracking unit locates the overall winning state with the global minimum path degree at the last moment of the data block. Starting from the overall winning state, it performs reverse tracing based on the decision bits recorded in the surviving path memory until it reaches the starting state of the trellis graph, thereby reconstructing the complete but reversed original information sequence. After being rearranged by a first-in-first-out buffer, the output is the decoding result in the correct order.

[0033] Furthermore, the adaptive resource allocation module adjusts the scheduling strategy of the parallel pipeline controller, allocating simple tasks to high-performance computing units within the in-memory computing unit array, specifically as follows:

[0034] The controller monitors the load status and task queue attributes of all processing units in the in-memory computing unit array in real time, and dynamically classifies tasks into simple tasks and complex tasks. Simple tasks are those with short execution cycles and no complex dependencies, while complex tasks are those with long execution cycles and complex dependencies.

[0035] The controller executes the core scheduling strategy: the high computing power unit priority principle; the high computing power unit is determined by comparing performance parameters with preset thresholds. When any or all performance parameters of the processing unit in the in-memory computing unit array are greater than or equal to the corresponding preset threshold, the processing unit is judged as a high computing power unit, thereby gaining priority in task scheduling. The performance parameters include the number of internal pipeline stages and the computing throughput per unit time.

[0036] Furthermore, the adaptive resource configuration module dynamically adjusts the computation mode of the in-memory computing unit array based on the constraint length and code rate of the convolutional code. Specifically, the dynamic adjustment involves: adjusting the parallelism and storage resource allocation of the in-memory computing unit array used to process the mesh graph state based on the constraint length; and changing the internal logic and parameters in the reconfigurable computing unit used to perform branch metric calculations based on the code rate.

[0037] Furthermore, the verification and error correction unit performs bit-by-bit or block-by-block verification calculations on the decoding results output by the in-memory computing unit array, and detects whether there are errors in the data by comparing them with pre-set verification rules or reference data.

[0038] If an error is found, the verification and error correction unit uses the error correction characteristics of the convolutional code itself, combined with the error correction code table and algorithm stored internally, to locate and correct the error.

[0039] After completing the verification and error correction of all data, the decoding result will be output.

[0040] A method for accelerating parallel pipelined decoding of convolutional codes based on an in-memory computing architecture includes:

[0041] The convolutional code data from the magnetic tape storage device is sliced ​​according to the set rules and scheduled through a multi-level caching mechanism. The cached sliced ​​data is then input into the in-memory computing unit array.

[0042] The in-memory computing unit array stores the convolutional code data to be decoded and intermediate results. It performs convolution operations, path metric calculations, and survival path selection through reconfigurable computing units. At the same time, it dynamically allocates decoding tasks and controls the pipeline cycle of the in-memory computing unit array through a parallel pipeline controller.

[0043] Real-time monitoring of system load, and dynamic adjustment of data allocation strategies and computing resource scheduling based on monitoring results;

[0044] The decoding results of the in-memory computing unit array are verified and corrected before being output.

[0045] The advantages of the parallel pipelined decoding acceleration system and method for convolutional codes based on an in-memory computing architecture provided by this invention are as follows: The system aims to design a decoding acceleration system that, through the collaborative design of hardware and algorithms, achieves a high degree of integration between data storage and computation, reducing data handling overhead and improving resource utilization and decoding real-time performance. By reducing data handling, optimizing resource allocation, and improving system versatility and flexibility, it achieves efficient and low-latency convolutional code decoding, meeting the requirements of tape storage systems for data processing speed and real-time performance in different application scenarios.

[0046] Specifically, the in-memory computing architecture significantly reduces the latency of data transfer between storage and computing units, and the parallel pipeline controller enables parallel processing of decoding tasks. When processing large-scale magnetic tape storage data, compared to traditional serial decoding methods and improved solutions with limited decoding efficiency, this embodiment can complete the decoding of large amounts of convolutional code data in a short time, greatly improving the decoding speed;

[0047] The adaptive resource configuration module monitors the load and data cache status of each unit in real time and dynamically adjusts task allocation and resource scheduling. When computational delays are encountered, unprocessed data slices can be reallocated, and the parallel pipeline controller scheduling strategy can be optimized to avoid wasting and idling computing resources and improve resource utilization efficiency.

[0048] By reducing data transfer latency, improving decoding efficiency, and optimizing resource allocation, this embodiment offers significant advantages in applications with high real-time requirements. It also enables timely data processing, reduces data processing latency, and prevents system operation from being affected by untimely decoding, thus ensuring user experience and system security. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the structure of the present invention;

[0050] Figure 2 A flowchart illustrating the data input and preprocessing workflow;

[0051] Figure 3 This is a flowchart of a parallel pipelined processing flow. Detailed Implementation

[0052] The technical solution of the present invention will now be described in detail through specific embodiments. Many specific details are set forth in the following description to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0053] like Figures 1 to 3 As shown, the parallel pipelined decoding acceleration system for convolutional codes based on an in-memory computing architecture proposed in this invention includes:

[0054] The global data scheduling module is used to slice input data from tape storage devices according to set rules and schedule it through a multi-level caching mechanism;

[0055] The in-memory computing unit array is used to store the convolutional code data to be decoded and intermediate results output from the global data scheduling module, and performs convolution operations, path metric calculations and surviving path selection through reconfigurable computing units;

[0056] Parallel pipeline controller, used to dynamically allocate decoding tasks and control the pipeline cycle of the in-memory computing unit array;

[0057] The adaptive resource configuration module monitors the system load in real time and dynamically adjusts the data allocation strategy and computing resource scheduling, thereby sending adjustment signals to the in-memory computing unit array.

[0058] The verification and error correction unit is used to verify and correct the decoding results output by the in-memory computing unit array before outputting them.

[0059] This embodiment aims to design a decoding acceleration system. Through the collaborative design of hardware and algorithms, it achieves a high degree of integration of data storage and computation, reduces data transfer overhead, and improves resource utilization and decoding real-time performance. By reducing data transfer, optimizing resource allocation, and improving system versatility and flexibility, it achieves efficient and low-latency convolutional code decoding, meeting the data processing speed and real-time requirements of tape storage systems in different application scenarios.

[0060] like Figure 1 As shown, the global data scheduling module receives input data from the tape storage device, provides data to the in-memory computing unit array, and simultaneously receives adjustment signals from the adaptive resource configuration module to optimize the data scheduling strategy. The global data scheduling module consists of a multi-level data caching module and a data slicing unit. The data slicing unit slices large data blocks read from the tape storage device according to specific rules and caches the processed data in the multi-level data caching module, thereby achieving efficient data scheduling and transmission between different levels of cache and reducing the data waiting time for the computing unit.

[0061] This data slicing unit integrates a slicing strategy engine, a slicing execution engine, and a metadata generation unit. Its workflow is as follows: First, the slicing strategy engine receives adjustment signals from the adaptive resource configuration module. These signals detail the available computing resources, topology, and task types of the downstream in-memory computing unit array. Based on these signals, the strategy engine dynamically determines the optimal slicing mode (e.g., fixed-size, variable-size, or dependency-aware slicing) and slicing granularity. Subsequently, the slicing execution engine physically partitions the data blocks according to the strategy to generate data tiles that maximize the parallel efficiency of the computing array.

[0062] The in-memory computing unit array receives input data from the global data scheduling module, processes the data under the control signal of the parallel pipeline controller, and outputs the processed data to the verification and error correction unit. At the same time, it receives adjustment signals from the adaptive resource configuration module to optimize its own working state.

[0063] The in-memory computing unit array receives adjustment signals from the adaptive resource configuration module to optimize its own working state. The specific optimization methods include: the in-memory computing unit array dynamically adjusts the working voltage and clock frequency according to the adjustment signal. The adjustment logic is as follows: the adjustment signal contains voltage and clock frequency configuration levels corresponding to the current system load state. When the system load is high, a high voltage (3.3-5V) and a high clock frequency (100-250MHz) are used to ensure performance; when the system load is low, it switches to a low voltage (1.8-3.3V) and a low clock frequency (25-100Hz) to reduce power consumption.

[0064] Based on the size of the computing load, some reconfigurable computing units are selectively gated or activated. The selection algorithm is as follows: the adaptive resource configuration module dynamically calculates a target number of active units based on the real-time computing load, and matches the current number of actually active reconfigurable computing units with the target number of active units by activating or gated reconfigurable computing units one by one.

[0065] Based on the numerical precision requirements of different computing tasks, the internal computing precision mode is adjusted in real time. The adjustment rule is as follows: the adaptive resource configuration module selects one of a set of preset precision modes according to the type of the current computing task. For example, for branch metric computing tasks with high fault tolerance and low precision requirements, a low bit width (such as 8-bit integer) mode is selected to reduce power consumption and improve speed; while for final path metric accumulation tasks that need to avoid overflow and have high precision requirements, a high bit width (such as 16-bit or 32-bit) mode is switched to ensure decoding accuracy.

[0066] The adaptive resource configuration module dynamically adjusts its operating voltage and clock frequency to minimize power consumption while meeting performance requirements; it selectively gates or activates some computing units based on the size of the computing load; and it adjusts its internal computing accuracy mode in real time according to the numerical accuracy requirements of different computing tasks, thereby achieving the best balance between power consumption, speed, and accuracy.

[0067] The in-memory computing unit array uses static random access memory (SRAM) to store the trellis graph state information, branch metric table, and surviving path history of the convolutional code. Simultaneously, it performs key decoding operations such as convolution operations, path metric calculation, and surviving path selection through computing units based on a reconfigurable architecture. For example, in the path metric calculation stage, the computing unit directly reads the branch metric value of the current state from the SRAM and accumulates it in conjunction with the received codewords. In the surviving path selection stage, it compares the accumulated metric values ​​of multiple paths in parallel, selects the optimal path, and updates it to the SRAM, achieving deep integration of computation and storage.

[0068] The parallel pipeline controller sends control signals to the in-memory computing unit array, directing its workflow and task allocation. The adaptive resource configuration module is bidirectionally connected to the in-memory computing unit array, the global data scheduling module, and the parallel pipeline controller, sending adjustment signals and receiving status feedback information. The verification and error correction unit receives the data processing results from the in-memory computing unit array and outputs decoded data.

[0069] The system workflow is divided into four stages: data input and preprocessing, parallel decoding and computation, system monitoring and dynamic adjustment, and data verification and output. The working principles of each stage will be described below:

[0070] 1. Data input and preprocessing stage;

[0071] like Figure 2 As shown, the magnetic tape storage device transmits the stored convolutional code data to the global data scheduling module at a certain rate and format. In the global data scheduling module, the data slicing unit first determines suitable slicing rules for large blocks of data based on the characteristics of the convolutional code, the processing capability of the in-memory computing unit array, and the requirements of parallel computing. For example, based on the constrained length and code rate of the convolutional code, the large data block is divided into several smaller data blocks with relatively balanced lengths and features, each suitable for independent processing by the in-memory computing unit.

[0072] Subsequently, the multi-level data caching module initiates a complex cache management mechanism. The off-chip cache (L3 cache), acting as a large-capacity data buffer, first receives and stores data blocks segmented by the data slicing unit. Next, the cache management algorithm monitors data access patterns and task execution order in real time. Through analysis of historical data access records and prediction of current tasks, prefetching technology is activated, prefetching data expected to be used soon from the off-chip cache (L3 cache) to the on-chip cache (L2 cache).

[0073] The prefetching technology is driven by both hardware and software, enabling multi-level intelligent data scheduling. At the hardware level, a built-in step-size prefetcher continuously monitors the memory access flow, automatically identifying and preloading consecutive or equally spaced data blocks. At a higher software level, the global data scheduling module makes more accurate task predictions based on the data tiles to be executed. Specifically, this parsing process does not perform real-time analysis of the data content, but rather is based on a pre-defined task model of the Viterbi decoding algorithm's internal logic. This idea draws on mature technologies in the field of computer architecture, but this embodiment innovatively applies it to an in-memory computing decoding system. That is, at the software level, the global data scheduling module, based on the pre-defined task model of the Viterbi decoding algorithm, parses the data dependencies of the data tiles (i.e., the temporal dependency on the "predecessor tile result" and the spatial dependency on the "neighborhood data") and the corresponding computation types (such as computationally intensive, comparatively intensive, etc.), and actively issues prefetch instructions to prefetch the predecessor tile results (reflected in the temporal dependency) or the neighborhood data (reflected in the spatial dependency) required for the convolution operation from the off-chip cache (L3 Cache) to the on-chip cache (L2 Cache) in large quantities.

[0074] The on-chip cache (L2 cache) further prefetches the data most likely to be used immediately into the on-chip cache (L1 cache) based on more accurate access predictions. The data prefetching from the on-chip cache (L2 cache) to the on-chip cache (L1 cache) relies on a precise prediction mechanism tightly coupled with the processor core's execution state. Its implementation logic includes instruction-associated prefetching and execution-driven prefetching.

[0075] Instruction-associative prefetching: This mechanism monitors and records the relationship between data accesses and their source instructions through hardware. It can identify memory access patterns with fixed steps generated by a set instruction address (such as a program counter value). Once this pattern is identified, when that specific instruction is about to be executed again, the system automatically prefetches the next data into the on-chip cache based on the recorded step size.

[0076] Execution-driven prefetching: This mechanism monitors the processor core's instruction pipeline to pre-parse decoded but not yet executed load instructions. Since the target memory addresses of these instructions are calculated before execution, the system can directly obtain this deterministic address information and use it as a prefetch target, thus preparing the necessary data in the on-chip cache before the instructions are actually executed. The on-chip cache, with its extremely low access latency, is always ready to provide data support for in-memory compute unit arrays.

[0077] This embodiment optimizes the system's data management and transmission through the collaborative work of the data slicing unit and the multi-level data caching module.

[0078] 2. Parallel decoding computation stage;

[0079] The distributed architecture of the storage and computing unit array and the dynamic scheduling of the parallel pipeline controller in this stage enable efficient parallel decoding of convolutional codes. The parallel pipeline controller divides the convolutional code decoding into three pipeline stages: the first pipeline performs branch metric calculation and accumulation, the second pipeline performs path metric comparison and surviving path selection, and the third pipeline performs surviving path backtracking.

[0080] In the first-stage pipeline, the hardware unit first receives the received symbols from the channel. Then, the branch metric calculation unit generates a quantified "cost," or branch metric, for each state transition (branch) in the mesh graph at the current time step by calculating the Hamming distance between the received symbols and all ideal output symbols. Simultaneously, the processing unit reads the cumulative path metrics of all states from the previous time step from memory and performs parallel addition operations with the corresponding branch metrics, thereby generating a set of candidate path metric values ​​for each current state, containing both historical costs and the current transition cost.

[0081] In the second-stage pipeline, the core of this stage is performing the "compare-select" operation within the "add-compare-select" process for each state. The comparator array of the in-memory compute unit array performs parallel comparisons of the multiple candidate path metrics from the first stage, selecting the path with the smallest value for each state as the "surviving path." The path metric corresponding to this surviving path is then updated in memory as the new official path metric for that state, for use in the next round of computation. More importantly, the selection result of this comparison (e.g., the path from above or below wins) generates a decision bit, which is precisely written into the surviving path memory, thus recording the surviving path information for all state nodes at the current moment.

[0082] In the third-stage pipeline, this stage is activated after the decoding process of a complete data block is completed. The backtracking unit first locates the overall winning state with the lowest global path degree at the last moment of the data block. Starting from this overall winning state, the hardware performs reverse tracing based on the decision bits recorded in the surviving path memory. Each backtracking step "jumps" from the current state to its unique surviving predecessor state at the previous moment. This predecessor state is uniquely designated by the decision bit and is the path source state that won in the second-stage pipeline. Each jump itself uniquely corresponds to the decoded value of one bit of the original information. This reverse tracing process continues until the initial state of the trellis graph is reached, thereby reconstructing the complete, but reversed, sequence of original information. Finally, this sequence is rearranged through a first-in-first-out buffer, outputting the decoded data in the correct order.

[0083] The in-memory compute unit array processes multiple data tiles in parallel through a three-stage pipeline. Leveraging the low latency of in-memory computing, it ensures that intermediate results from each pipeline stage are directly stored in SRAM, eliminating the need for cross-module transfers. First, each compute-in-memory unit in the array loads preprocessed data from the on-chip cache (L1 cache) on demand and stores it in SRAM, awaiting control signals to execute computation tasks. Second, when the parallel pipeline controller broadcasts control signals to all in-memory compute arrays, the decoding task is divided into multiple subtasks (such as branch metric calculation, path expansion, and surviving path backtracking). Each in-memory compute array then executes these subtasks according to the pipeline rhythm based on the control signals, forming a multi-stage parallel pipeline to accelerate data processing. For example, as... Figure 3 As shown, after the in-memory computing array-1 completes the path metric calculation for the current data slice, it immediately passes the intermediate results to the in-memory computing array-2 for surviving path selection; at the same time, the in-memory computing array-1 loads the next data slice and starts a new round of calculation, realizing the superposition of task-level parallelism and data-level parallelism.

[0084] Meanwhile, the adaptive resource allocation module monitors the computational load and data cache status of each in-memory computing unit in the array in real time. If a certain in-memory computing unit experiences computational delays due to the complexity of its data, the module will trigger dynamic task migration: reassigning some unprocessed data tiles from that unit to idle or low-load in-memory computing units; and adjusting the scheduling strategy of the parallel pipeline controller to prioritize the allocation of simple tasks to high-performance units. This strategy adjustment process is a continuous closed-loop feedback: the controller monitors the load status of all processing units and the attributes of the task queues in real time, and dynamically classifies tasks into "simple tasks" (short execution cycle, no complex dependencies) and "complex tasks" (long execution cycle, complex dependencies). Based on this, the controller executes its core scheduling strategy: "high-performance unit priority principle." Here, "high-performance unit" specifically refers to processing units with deeper internal pipelines and stronger computing capabilities. This strategy does not simply match complex tasks to powerful units, but rather prevents powerful units from experiencing pipeline stagnation and performance idleness while waiting for suitable complex tasks. Specifically, when a powerful processing unit completes its task and becomes idle, the controller proactively and preemptively schedules a simple task from the queue to fill its computational gap. Finally, after all in-memory computing units have completed their survival path selection, the backtracking decoding operation begins.

[0085] Based on the recorded surviving path information, the in-memory computing unit traces back from the last state to recover the original information sequence. This process is also performed in parallel across multiple in-memory computing units in the array, leveraging the efficient data processing capabilities of the in-memory computing architecture to quickly complete the decoding task.

[0086] This embodiment effectively reduces the data transfer latency of traditional convolutional code parallel pipeline decoding acceleration systems by using an in-memory computing unit array; it achieves efficient task allocation and scheduling by utilizing a parallel pipeline controller, thereby improving decoding speed; in addition, it dynamically adjusts resource allocation and task scheduling strategies by monitoring the system status in real time through an adaptive resource configuration module.

[0087] 3. System testing and dynamic adjustment phase;

[0088] Throughout the entire decoding computation process of the in-memory computing unit array, the adaptive resource configuration module performs comprehensive and real-time monitoring of the operating status of each module in the system.

[0089] The adaptive resource configuration module dynamically adjusts the computation mode of the in-memory computing unit array based on parameters such as the constraint length and code rate of the convolutional code. Specifically, the dynamic adjustment involves: adjusting the parallelism and storage resource allocation of the in-memory computing unit array used to process the mesh graph state according to the constraint length; and changing the internal logic and parameters of the reconfigurable computing unit used to perform branch metric calculations according to the code rate.

[0090] For example, when new convolutional code parameters are received, the adaptive resource allocation module adjusts resources according to the change in constraint length K, based on the following determined logical relationship: The module first adjusts resources according to a deterministic formula. The adaptive resource allocation module calculates the total number of states N required for the Viterbi decoding mesh graph corresponding to the new constraint length. Based on the calculated total number of states N, the adaptive resource allocation module precisely allocates or activates N independent storage areas in static random access memory (SRAM) to store the path metric value for each state. At the same time, the adaptive resource allocation module activates or logically combines N reconfigurable computing units in parallel, so that each reconfigurable computing unit corresponds to a static random access memory (SRAM) storage area, so as to perform the path metric calculation and surviving path selection for all N states in parallel.

[0091] In addition, the adaptive resource configuration module monitors the load of each in-memory computing unit in the array, including the number of tasks currently being processed, the task queue length, and the consumption of computing resources. If an in-memory computing unit is found to be overloaded, resulting in task backlog or computing resource shortage, the adaptive resource configuration module sends an adjustment signal to the global data scheduling module, requesting it to adjust the data allocation strategy and transfer some tasks to less loaded in-memory computing units. Simultaneously, it also sends adjustment signals to in-memory computing units with excessive loads to balance the load of each unit through a defined optimization logic. The specific logic is as follows: the adaptive resource configuration module uses "task queue length" or "average task waiting time" as the load index for each unit; when the load index of a unit exceeds a preset high load threshold, the unit is identified as an overloaded unit; then, an adjustment signal is sent to the overloaded unit, which contains an instruction to rearrange the execution order of its internal tasks. The rearrangement rule is: prioritize the execution of tasks with short computation cycles or simple data dependencies, and place tasks with long computation cycles or complex dependencies at the end of the queue, thereby accelerating task processing speed and quickly reducing the load level of the unit.

[0092] For the global data scheduling module, the adaptive resource configuration module focuses on key indicators such as cache hit rate and data transfer rate. When the cache hit rate falls below a preset threshold, the memory access pattern recognition unit within the adaptive resource configuration module begins analyzing the data access flow. Based on the identified memory access pattern (e.g., sequential or random access), this module selects the optimal matching strategy from a preset "cache strategy set." The adjustment signal contains a unique identifier for the selected strategy. Upon receiving this identifier, the multi-level data caching module loads and executes the corresponding cache management algorithm. For example, it loads a large prefetch window strategy for sequential access patterns, or a strategy that disables prefetching and optimizes the replacement algorithm for random access patterns, thereby improving the cache hit rate.

[0093] 4. Data verification and output stage;

[0094] After the in-memory computing unit array completes the decoding of the data tiles, the processing result is transmitted to the verification and error correction unit. The verification and error correction unit first performs bit-by-bit or block-by-block verification calculations on the input data, comparing it with pre-set verification rules or reference data to detect any errors. Once an error is detected, the verification and error correction unit utilizes the error-correcting characteristics of the convolutional code itself, combined with an internally stored error correction code table and algorithm, to accurately locate and correct the error. For example, for common bit errors, it calculates the correct bit value based on the encoding rules and redundancy information of the convolutional code. After completing the verification and error correction processing of all data, the decoded data, ensuring accuracy, is output from the system and delivered to subsequent application systems or users. This completes the entire parallel pipelined decoding acceleration process for convolutional codes.

[0095] The in-memory computing architecture of this embodiment significantly reduces the latency of data transfer between storage and computing units, and the parallel pipeline controller enables parallel processing of decoding tasks. When processing large-scale magnetic tape storage data, compared with traditional serial decoding methods and improved solutions with limited decoding efficiency, this embodiment can complete the decoding of a large amount of convolutional code data in a short time, greatly improving the decoding speed.

[0096] The adaptive resource configuration module monitors the load and data cache status of each unit in real time, and dynamically adjusts task allocation and resource scheduling. When computational delays are encountered, unprocessed data slices can be reallocated, and the parallel pipeline controller scheduling strategy can be optimized to avoid wasting and idling computing resources and improve resource utilization efficiency.

[0097] By reducing data transfer latency, improving decoding efficiency, and optimizing resource allocation, this embodiment offers significant advantages in applications with high real-time requirements. It also enables timely data processing, reduces data processing latency, and prevents system operation from being affected by untimely decoding, thus ensuring user experience and system security.

[0098] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A parallel pipelined decoding acceleration system for convolutional codes based on an in-memory computing architecture, characterized in that, include: The global data scheduling module is used to slice convolutional code data from tape storage devices according to set rules and schedule it through a multi-level caching mechanism; The in-memory computing unit array is used to store data tiles and intermediate results output from the global data scheduling module, and performs convolution operations, path metric calculations and surviving path selection through reconfigurable computing units; Parallel pipeline controller, used to dynamically allocate decoding tasks and control the pipeline cycle of the in-memory computing unit array; An adaptive resource configuration module monitors system load in real time and dynamically adjusts data allocation strategies and computing resource scheduling, thereby enabling signal transmission between the global data scheduling module, the in-memory computing unit array, and the parallel pipeline controller. The adaptive resource configuration module dynamically adjusts the computing mode of the in-memory computing unit array based on the constraint length and code rate of the convolutional code. Specifically, this dynamic adjustment involves: adjusting the parallelism and storage resource allocation of the in-memory computing unit array used for processing mesh graph states based on the constraint length; and changing the internal logic and parameters in the reconfigurable computing unit used for performing branch metric calculations based on the code rate. The verification and error correction unit is used to verify and correct the decoding results output by the in-memory computing unit array before outputting them.

2. The decoding acceleration system according to claim 1, characterized in that, In the global data scheduling module, data tiles are scheduled through a multi-level caching mechanism, specifically: Multi-level caching mechanisms include off-chip caching, on-chip caching, and on-chip caching; The off-chip buffer receives data tiles output by the global data scheduling module. Prefetching techniques are used to prefetch data that is expected to be used in the near future from the off-chip cache to the on-chip cache. By using instruction-associated prefetching and execution-driven prefetching, data is prefetched from the on-chip cache to the on-chip cache. The instruction-associated prefetching is based on memory access patterns with fixed steps generated by a set instruction address. The execution-driven prefetching takes the decoded but not yet executed load instructions as the prefetching target and prepares the required data in the on-chip cache before the instructions are actually executed.

3. The decoding acceleration system according to claim 1, characterized in that, The in-memory computing unit array processes data under the control signals of the parallel pipeline controller, and simultaneously receives adjustment signals from the adaptive resource configuration module to optimize its working state.

4. The decoding acceleration system according to claim 3, characterized in that, The optimized operating state of the receiving adaptive resource configuration module is specifically as follows: The in-memory computing unit array dynamically adjusts its operating voltage and clock frequency according to the adjustment signal; Based on the size of the computing load, some reconfigurable computing units are selectively gated or activated. The selection algorithm is as follows: the adaptive resource configuration module dynamically calculates a target number of active units based on the real-time computing load, and matches the current number of actually active reconfigurable computing units with the target number of active units by activating or gated reconfigurable computing units one by one. Based on the numerical accuracy requirements of different computing tasks, the internal computing accuracy mode is adjusted in real time. The adjustment rule is as follows: the adaptive resource configuration module selects one of a set of preset accuracy modes according to the type of the current computing task.

5. The decoding acceleration system according to claim 1, characterized in that, In the in-memory computing unit array, convolution operations, path metric calculations, and surviving path selection are performed through reconfigurable computing units, specifically: The parallel pipeline controller divides the decoding process of convolutional code data by the in-memory computing unit array into a three-stage pipeline; The first-level pipeline performs branch metric calculation and accumulation; the second-level pipeline performs path metric comparison and surviving path selection; and the third-level pipeline performs surviving path backtracking.

6. The decoding acceleration system according to claim 5, characterized in that, The three-stage production line is specifically as follows: First-stage pipeline: The in-memory computing unit array receives the received symbols from the channel. The branch metric calculation unit generates a branch metric for each state in the current time in the grid graph and performs parallel addition with the cumulative path metric of all states in the previous time, thereby generating a set of candidate path metric values ​​for each current state. The second-stage pipeline: The in-memory computing unit array, based on the multi-candidate path metrics from the first stage, selects the path with the smallest value for each state as the surviving path, updates the candidate path metric corresponding to the surviving path as the new official path metric for that state in the memory, and simultaneously generates decision bits by writing the selection result into the surviving path memory. The third-stage pipeline: After the decoding process of a complete data block is completed, the backtracking unit locates the overall winning state with the global minimum path degree at the last moment of the data block. Starting from the overall winning state, it performs reverse tracing based on the decision bits recorded in the surviving path memory until it reaches the starting state of the trellis graph, thereby reconstructing the complete but reversed original information sequence. After being rearranged by a first-in-first-out buffer, the output is the decoding result in the correct order.

7. The decoding acceleration system according to claim 6, characterized in that, The adaptive resource allocation module adjusts the scheduling strategy of the parallel pipeline controller, allocating simple tasks to high-performance computing units within the in-memory computing unit array, specifically as follows: The controller monitors the load status and task queue attributes of all processing units in the in-memory computing unit array in real time, and dynamically classifies tasks into simple tasks and complex tasks. Simple tasks are those with short execution cycles and no complex dependencies, while complex tasks are those with long execution cycles and complex dependencies. The controller executes the core scheduling strategy: the high computing power unit priority principle; the high computing power unit is determined by comparing performance parameters with preset thresholds. When any or all performance parameters of the processing unit in the in-memory computing unit array are greater than or equal to the corresponding preset threshold, the processing unit is judged as a high computing power unit, thereby gaining priority in task scheduling. The performance parameters include the number of internal pipeline stages and the computing throughput per unit time.

8. The decoding acceleration system according to claim 1, characterized in that, The verification and error correction unit performs bit-by-bit or block-by-block verification calculations on the decoding results output by the in-memory computing unit array, and detects whether there are errors in the data by comparing them with pre-set verification rules or reference data. If an error is found, the verification and error correction unit uses the error correction characteristics of the convolutional code itself, combined with the error correction code table and algorithm stored internally, to locate and correct the error. After completing the verification and error correction of all data, the decoding result will be output.

9. A method for accelerating parallel pipelined decoding of convolutional codes based on a memory-computing architecture, characterized in that, include: The convolutional code data from the magnetic tape storage device is sliced ​​according to the set rules and scheduled through a multi-level caching mechanism. The cached sliced ​​data is then input into the in-memory computing unit array. The in-memory computing unit array stores the convolutional code data to be decoded and intermediate results. It performs convolution operations, path metric calculations, and survival path selection through reconfigurable computing units. At the same time, it dynamically allocates decoding tasks and controls the pipeline cycle of the in-memory computing unit array through a parallel pipeline controller. The system load is monitored in real time, and the data allocation strategy and computing resource scheduling are dynamically adjusted based on the monitoring results. Specifically, the computing mode of the in-memory computing unit array is dynamically adjusted according to the constraint length and code rate of the convolutional code. The dynamic adjustment specifically includes: adjusting the parallelism and storage resource allocation of the in-memory computing unit array used to process the mesh graph state according to the constraint length; and changing the internal logic and parameters of the reconfigurable computing unit used to perform branch metric calculations according to the code rate. The decoding results of the in-memory computing unit array are verified and corrected before being output.

Images