Class-d audio power amplifier bias voltage processing method and circuit, and class-d audio power amplifier

Abstract

The application relates to a D-class audio power amplifier bias voltage processing method, a circuit and a D-class audio power amplifier. The method comprises the following steps: setting multiple fine adjustment options for a feedback resistor at the differential ends of a D-class power amplifier; determining the feedback resistor setting with the minimum bias voltage in the chip factory test and burning the OTP to complete coarse adjustment of the bias voltage; after the coarse adjustment of the bias voltage is completed, dividing a PWM signal generated by a PWM modulator into two signals, processing one of the two signals through a delay unit, and then performing logical AND operation on the other signal to output a fine-adjusted PWM signal; and the fine-adjusted PWM signal is used to drive a loudspeaker after passing through a switching amplifier and a low-pass filter. The method can overcome the bias voltage caused by the deviation of the device process.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and relates to a method, circuit and Class D audio power amplifier bias voltage processing method. Background Technology

[0002] In Class D closed-loop audio power amplifier circuits, AD and BD are the most basic and commonly used modulation modes. In these modulation modes, the larger the output bias voltage, the more pronounced the noise during power stage switching, manifesting as pop-click noise from the speaker when the power is on and off. Furthermore, for the fully differential modulation mode with zero common-mode voltage output, when the power amplifier output signal is 0, if there is a bias voltage (offset) across the differential terminals, one end will continue switching continuously, preventing the system from achieving the power-saving design effect at low power levels. In chip design and manufacturing, deviations in device process technology, such as a certain mismatch in the feedback resistors across the differential terminals, can lead to the presence of bias voltage. Summary of the Invention

[0003] To address the problems existing in the aforementioned traditional methods, this invention proposes a bias voltage processing method, circuit, and Class D audio power amplifier for Class D audio power amplifiers. This method can be used in various modulation modes to achieve zero bias voltage output. In particular, it is used to assist in fully differential modulation mode, ensuring that when there is zero input, the two differential terminals of the PWM modulator no longer output PWM signals, thereby reducing losses.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a method for processing the bias voltage of a Class D audio power amplifier is provided, the method including the following steps:

[0006] Multiple fine-tuning options are set for the feedback resistors at the differential terminals of the Class D power amplifier. By determining the feedback resistor setting with the minimum bias voltage during chip factory testing and programming the OTP, the coarse adjustment of the bias voltage is completed.

[0007] After coarse adjustment of the bias voltage, the PWM signal generated by the PWM modulator is divided into two signals. One signal is processed by a delay unit and then ANDed with the other signal to output a finely adjusted PWM signal. The finely adjusted PWM signal is used to drive the speaker after passing through a switching amplifier and a low-pass filter.

[0008] In one embodiment, the delay unit is implemented using several levels of gate circuits; the process of determining the number of gate circuit levels includes:

[0009] Based on the typical values ​​of system voltage, switching frequency, and individual gate delay, determine the impact of each gate circuit on the bias voltage.

[0010] The number of cascaded gate circuits is determined based on the remaining bias voltage after coarse adjustment and the influence of each gate circuit on the bias voltage.

[0011] In one embodiment, a fine-tuning switch is connected in parallel for each gate circuit. During the factory testing of the Class D power amplifier chip, based on the test results, the bypass switch configuration of the gate delay circuit that can achieve the minimum bias voltage is programmed into the OTP to connect the required number of gate delay circuits and achieve extremely low bias voltage.

[0012] In one embodiment, the method further includes: processing the coarsely tuned PWM signal through a delay unit and performing a logical AND operation with the coarsely tuned PWM signal to obtain a finely tuned PWM signal.

[0013] On the other hand, a Class D audio power amplifier bias voltage processing circuit is also provided, the circuit including: a bias coarse adjustment unit and a PWM duty cycle fine adjustment unit;

[0014] The bias coarse adjustment unit is used to set multiple fine-tuning options for the feedback resistors at the differential terminals of the Class D power amplifier. By determining the feedback resistor setting with the minimum bias voltage during chip factory testing and programming the OTP, the bias voltage coarse adjustment is completed.

[0015] The PWM duty cycle fine-tuning unit is used to split the PWM signal generated by the PWM modulator into two signals after the bias voltage coarse adjustment is completed. One signal is processed by the delay unit and then ANDed with the other signal to output the finely tuned PWM signal. The finely tuned PWM signal is used to drive the speaker after passing through the switching amplifier and low-pass filter.

[0016] In one embodiment, the PWM duty cycle fine-tuning unit includes: a delay unit and an AND gate; the input of the delay unit receives the coarsely tuned PWM signal (including the remaining bias voltage), the output of the delay unit is connected to one input of the AND gate, the other input of the AND gate receives the coarsely tuned PWM signal (including the remaining bias voltage), and the output of the AND gate is used to output the finely tuned PWM signal.

[0017] The delay unit is implemented using several levels of gate circuits; the process of determining the number of gate circuit levels includes:

[0018] Based on the typical values ​​of system voltage, switching frequency, and individual gate delay, determine the impact of each gate circuit on the bias voltage.

[0019] The number of cascaded gate circuits is determined based on the remaining bias voltage after coarse adjustment and the influence of each gate circuit on the bias voltage.

[0020] In one embodiment, a fine-tuning switch is connected in parallel for each gate circuit. During the factory testing of the Class D power amplifier chip, based on the test results, the gate delay circuit bypass switch configuration that can achieve the minimum bias voltage is programmed into the OTP to connect the required number of gate delay circuits and achieve extremely low bias voltage.

[0021] In one embodiment, the circuit further includes a noise gate; the noise gate is used to perform a logical AND operation between the finely tuned PWM signal after it has been processed by the delay unit and the finely tuned PWM signal, and to filter out the output signal with an amplitude below a preset value as noise to obtain the final PWM signal.

[0022] In one embodiment, the noise gate includes a second delay unit and a second AND gate; the input of the second delay unit is used to receive the finely tuned PWM signal, the output of the second delay unit is connected to one input of the second AND gate, the other input of the second AND gate receives the finely tuned PWM signal, and the output of the second AND gate is used to output the final PWM signal.

[0023] Furthermore, a Class D audio power amplifier is also provided, which includes a PWM modulator, any of the aforementioned Class D audio power amplifier bias voltage processing circuits, a full-bridge power stage, and a low-pass filter unit.

[0024] The input of the PWM modulator receives an analog audio signal. The output of the PWM modulator is connected to the input of the Class D audio power amplifier bias voltage processing circuit. The output of the Class D audio power amplifier bias voltage processing circuit is connected to the input of the full-bridge power stage. The output of the full-bridge power stage is connected to the speaker after passing through a low-pass filter unit.

[0025] One of the above technical solutions has the following advantages and beneficial effects:

[0026] The aforementioned Class D audio power amplifier bias voltage processing method, circuit, and Class D audio power amplifier include the following: The method involves setting multiple fine-tuning options for the feedback resistor across the differential terminals of the Class D power amplifier. During chip factory testing, the feedback resistor setting with the minimum bias voltage is determined and programmed into the OTP (Optical Pointer Protocol), thus completing the coarse bias voltage adjustment. After coarse bias voltage adjustment, the PWM signal generated by the PWM modulator is split into two signals. One signal is processed through a delay unit and then logically ANDed with the other signal to output a finely tuned PWM signal. The finely tuned PWM signal is used to drive the speaker after passing through a switching amplifier and a low-pass filter. This method can overcome bias voltage issues caused by variations in device manufacturing processes. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating a method for processing the bias voltage of a Class D audio power amplifier in one embodiment.

[0029] Figure 2 This is a schematic diagram of a PWM duty cycle fine-tuning unit in one embodiment;

[0030] Figure 3 Here is a schematic diagram of a noise gate in one embodiment;

[0031] Figure 4 A Class D audio amplifier component block in one embodiment Figure 1 ;

[0032] Figure 5 A Class D audio amplifier component block in one embodiment Figure 2 . Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0035] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0036] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0037] In one embodiment, such as Figure 1 As shown, a method for processing the bias voltage of a Class D audio power amplifier is provided, which may include the following processing steps 100 to 101:

[0038] Step 100: Set multiple fine-tuning options for the feedback resistors across the differential terminals of the Class D power amplifier. By determining the feedback resistor setting with the minimum bias voltage during chip factory testing and programming the OTP, the coarse adjustment of the bias voltage is completed.

[0039] Specifically, the purpose of step 100 is to control the bias voltage at the output of the Class D power amplifier to within 1mV. This is achieved by providing multiple fine-tuning options for the feedback resistors across the differential terminals of the Class D power amplifier, which can be selected via OTP (One-time Programming) programming. During chip factory testing, the minimum bias setting is determined and the OTP is programmed. Subsequently, each time the chip powers on, it automatically reads the OTP content and selects the configuration with the minimum bias voltage. Using this method for initial coarse adjustment ensures that the bias voltage is controlled within 1mV.

[0040] Step 101: After completing the coarse adjustment of the bias voltage, the PWM signal generated by the PWM modulator is divided into two signals. One signal is processed by the delay unit and then ANDed with the other signal to output the finely adjusted PWM signal. The finely adjusted PWM signal is used to drive the speaker after passing through the switching amplifier and low-pass filter.

[0041] Specifically, Class D audio amplifiers rely on their output power stage to output a PWM signal with strong current-driven capability. This signal then passes through an LC low-pass filter to remove the carrier frequency signal, restoring the original audio signal. The static common-mode output voltage (static refers to 0 input) of a Class D audio amplifier is equal to its static output duty cycle multiplied by the supply voltage. Therefore, adjusting this duty cycle allows for individual adjustment of the static voltage across the differential terminals, thereby adjusting the differential-mode voltage, commonly known as the bias voltage. This duty cycle is determined by the smallest delay unit achievable by a single gate circuit and the operating frequency of the Class D audio amplifier. The shorter the delay, the more precise the adjustment.

[0042] In the field of mixed-signal chip design, the most commonly used process is BCD.

[0043] On the most commonly used 0.18µm BCD process platform, the typical delay of a single gate circuit is 60ps. Taking the 500kHz switching frequency, most commonly used in Class D audio power amplifiers, as an example, its period is 2µs. Therefore, the impact of a single gate circuit on the duty cycle is: 60ps / 2µs = 0.003%. Taking a 24V power amplifier operating voltage (24V and below can cover more than 80% of everyday audio power amplifier applications) as an example, its impact on the output common-mode voltage, and also on the bias voltage, is as follows: .

[0044] On the 90nm BCD process platform, the typical latency of a single gate is 30ps. Similarly, the minimum achievable adjustment capability is: .

[0045] On the 55nm BCD process platform, the typical latency of a single gate is 15ps. Similarly, the minimum achievable adjustment capability is:

[0046] .

[0047] Furthermore, the minimum adjustable capability achievable by the 12V power supply voltage most commonly used in televisions can be doubled.

[0048] The aforementioned method for handling the bias voltage of a Class D audio power amplifier includes setting multiple fine-tuning options for the feedback resistor across the differential terminals of the Class D power amplifier. During chip factory testing, the feedback resistor setting that minimizes the bias voltage is determined and programmed into the OTP (Optical Transfer Protocol), thus completing a coarse bias voltage adjustment. After coarse adjustment, the PWM signal generated by the PWM modulator is split into two signals. One signal is processed by a delay unit and then ANDed with the other signal to output a finely tuned PWM signal. This finely tuned PWM signal is then used to drive the speaker after passing through a switching amplifier and a low-pass filter. This method can overcome bias voltage issues caused by variations in device manufacturing processes.

[0049] In one embodiment, the delay unit in step 101 is implemented using several levels of gate circuits; the process of determining the number of gate circuit levels includes: determining the influence value of each level of gate circuit on the bias voltage based on the system voltage, switching frequency and typical value of the delay of a single gate circuit; and determining the number of cascaded gate circuits based on the remaining bias voltage after coarse adjustment and the influence value of each level of gate circuit on the bias voltage.

[0050] In one embodiment, a fine-tuning switch is connected in parallel for each gate circuit. During the factory testing of the Class D power amplifier chip, based on the test results, the bypass switch configuration of the gate delay circuit that can achieve the minimum bias voltage is programmed into the OTP to connect the required number of gate delay circuits and achieve extremely low bias voltage.

[0051] Specifically, by programming the number of delay gates in the OTP control access signal link, bias voltage adjustments in steps as small as 0.18mV can be achieved. More specifically, for the fully differential modulation mode with zero common-mode voltage output, similar to step 100, during factory testing, the chip is first coarsely adjusted using method one, then finely adjusted using step 101, and further assisted by noise gates to ensure that when there is zero input, the two differential terminals of the PWM modulator no longer output PWM signals.

[0052] In one embodiment, the method further includes: processing the coarsely tuned PWM signal through a delay unit and performing a logical AND operation with the coarsely tuned PWM signal to obtain a finely tuned PWM signal.

[0053] Specifically, after coarse adjustment in step 100 and fine adjustment in step 101, the bias voltage can be controlled within 0.5mV in the current 90nm product.

[0054] It should be understood that, although the above process Figure 1 The steps in the diagram are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, the above process... Figure 1 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0055] In one embodiment, a Class D audio power amplifier bias voltage processing circuit is also provided. The bias circuit includes: a coarse adjustment unit and a PWM duty cycle fine adjustment unit. The coarse adjustment unit is used to set multiple fine adjustment options for the feedback resistors at the differential terminals of the Class D power amplifier. By determining the feedback resistor setting with the minimum bias voltage during chip factory testing and programming the OTP, the coarse adjustment of the bias voltage is completed.

[0056] The PWM duty cycle fine-tuning unit is used to split the PWM signal generated by the PWM modulator into two signals after the bias voltage coarse adjustment is completed. One signal is processed by the delay unit and then ANDed with the other signal to output the finely tuned PWM signal. The finely tuned PWM signal is used to drive the speaker after passing through the switching amplifier and low-pass filter.

[0057] The schematic diagram of the PWM duty cycle fine-tuning unit is as follows: Figure 2As shown. The principle of the PWM duty cycle fine-tuning unit: The PWM signal generated by the modulator is sent to the PWM duty cycle fine-tuning unit, where it is divided into two paths. One path passes through multiple buffer stages, and then is ANDed with the original signal through an AND gate to output the PWM signal with a finely adjusted duty cycle. The delay introduced by each buffer stage is fixed. The number of buffers connected can be determined during chip factory testing based on the remaining bias voltage after coarse adjustment, and is programmed into the OTP.

[0058] Figure 2 illustrate: Figure 2 The duty cycle change of the PWM input and output signals is actually very small, only <0.1%; the figure is only shown for illustration purposes.

[0059] In one embodiment, the PWM duty cycle fine-tuning unit includes a delay unit and an AND gate. The input of the delay unit receives the coarsely adjusted residual bias voltage, the output of the delay unit is connected to one input of the AND gate, the other input of the AND gate receives the coarsely adjusted residual bias voltage, and the output of the AND gate is used to output the finely tuned PWM signal. The delay unit is implemented using several levels of gate circuits. The process of determining the number of gate circuit levels includes: determining the influence value of each gate circuit level on the bias voltage based on the system voltage, switching frequency, and typical delay values ​​of a single gate circuit; and determining the number of cascaded gate circuits based on the coarsely adjusted residual bias voltage and the influence value of each gate circuit level on the bias voltage.

[0060] In one embodiment, a fine-tuning switch is connected in parallel for each gate circuit. During the factory testing of the Class D power amplifier chip, based on the test results, the bypass switch configuration of the gate delay circuit that can achieve the minimum bias voltage is programmed into the OTP to connect the required number of gate delay circuits and achieve extremely low bias voltage.

[0061] In one embodiment, the circuit further includes a noise gate; the noise gate is used to perform a logical AND operation between the finely tuned PWM signal (after processing by the delay unit) and the finely tuned PWM signal, filtering out output signals with amplitudes below a preset value as noise, thus obtaining the final PWM signal. The schematic diagram of the noise gate is shown below. Figure 3 As shown.

[0062] In one embodiment, the noise gate includes a second delay unit and a second AND gate; the input of the second delay unit is used to receive the finely tuned PWM signal, the output of the second delay unit is connected to one input of the second AND gate, the other input of the second AND gate receives the finely tuned PWM signal, and the output of the second AND gate is used to output the final PWM signal.

[0063] In one embodiment, such as Figure 4As shown, a Class D audio power amplifier is provided, which includes a PWM modulator, any of the above-mentioned Class D audio power amplifier bias voltage processing circuits, a full-bridge power stage, and a low-pass filter unit.

[0064] The input of the PWM modulator receives an analog audio signal. The output of the PWM modulator is connected to the input of the Class D audio power amplifier bias voltage processing circuit. The output of the Class D audio power amplifier bias voltage processing circuit is connected to the input of the full-bridge power stage. The output of the full-bridge power stage is connected to the speaker after passing through a low-pass filter unit.

[0065] Specifically, the overall connection relationship between the PWM modulator, bias voltage processing module, and power output stage is as follows: Figure 4 As shown, the PWM modulator first modulates the analog signal into a pair of PWM signals according to the BD modulation mode. This pair of PWM signals is then processed by the bias voltage adjustment circuit described above, adjusting PWM_P and PMN into a pair of 0-bias voltage signals. In the mute state with a 0-input analog signal, the duty cycles of PWM_P and PWM_N are almost identical at 50%, thus eliminating the bias voltage. For extremely narrow PWM signals (on-time less than 200ps), they are filtered out. The bias-voltage-eliminated PWM_P_0offset and PWM_N_0offset are then sent to the full-bridge power stage to drive the speaker.

[0066] In a specific embodiment, such as Figure 5 As shown, a Class D audio power amplifier modulation circuit employing a fully differential modulation mode is provided, comprising: a differential input module, a PWM modulation module, a PWM logic processing module, a common-mode feedback link, a differential-mode feedback link, a Class D audio power amplifier bias voltage processing circuit, and a power output module.

[0067] The differential input module is used to amplify, filter, and adjust the gain of the differential audio signal input to the input terminal of the differential input module to obtain intermediate information in differential form; and transmit the intermediate information to the PWM modulation module.

[0068] The PWM modulation module is used to perform PWM modulation on the received intermediate information to obtain PWM_P and PWM_N signals. The PWM modulation module includes a ramp generator and two comparators. The ramp generator generates a high-frequency triangular carrier wave and transmits it to the inverting input of the two comparators. The differential intermediate signal output by the differential input module is input to the positive input of the two comparators.

[0069] The PWM logic processing module uses combinational logic circuits to separate the PWM_P and PWM_N signals into common-mode and differential-mode components, outputting the common-mode and differential-mode components. Specifically, the PWM logic processing module includes three AND gates and one XOR gate; the common-mode components include the PWM_P_CM and PWM_N_CM signals; and the differential-mode components include the PWM_P_DIFF and PWM_N_DIFF signals.

[0070] The two inputs of the XOR gate receive the PWM_P and PWM_N signals, respectively. The output of the XOR gate is input to one input of the second AND gate and the third AND gate, respectively. The other input of the second AND gate and the third AND gate receive the PWM_P and PWM_N signals, respectively. The outputs of the second AND gate and the third AND gate output the PWM_P_DIFF and PWM_N_DIFF signals, respectively. The two inputs of the first AND gate receive the PWM_P and PWM_N signals, respectively. The output of the first AND gate outputs the PWM_P_CM and PWM_N_CM signals, respectively.

[0071] The PWM logic processing module separates the common-mode and differential-mode components of the BD-modulated signals PWM_P and PWM_N output from the PWM modulator, outputting the common-mode components PWM_P_CM and PWM_N_CM, and the differential-mode components PWM_P_DIFF and PWM_N_DIFF. This module is implemented entirely with combinational logic. The input signals PWM_P and PWM_N are XORed by a gate XOR1 to obtain the differential-mode components, which are then ANDed with the original signals to retain only the differential-mode components in the original signals for output. Simultaneously, the input signals PWM_P and PWM_N are ANDed by a gate AND1 to obtain the common-mode components, which are then output. Here, PWM_P_CM and PWM_N_CM are identical signals.

[0072] The common-mode feedback link is used to amplify the common-mode component and feed it back to the input terminal of the differential input module; the common-mode component and the common-mode feedback link are entirely integrated within the chip. The common-mode feedback link includes two common-mode negative feedback loops; each common-mode negative feedback loop includes a common-mode driver module and a first resistor; the common-mode driver module includes a complementary push-pull circuit composed of MOSFETs; in the first common-mode negative feedback loop: the PWM_P_CM signal is amplified by the common-mode driver module, passes through the first resistor, and then fed back to the non-inverting input terminal of the differential input module; in the second common-mode negative feedback loop: the PWM_N_CM signal is amplified by the common-mode driver module, passes through the first resistor, and then fed back to the inverting input terminal of the differential input module.

[0073] The differential-mode feedback link amplifies the differential-mode component and feeds it back to the input terminal of the differential input module. The differential-mode component and differential-mode feedback link are implemented using power MOSFETs integrated within the chip or external power MOSFETs. The differential-mode feedback link includes two differential-mode negative feedback loops; each loop includes a power amplifier module and a second resistor. The differential-mode drive module includes a complementary push-pull circuit composed of MOSFETs. In the first differential-mode negative feedback loop, the PWM_P_DIFF signal is amplified by the power amplifier module, passed through the second resistor, and then fed back to the non-inverting input terminal of the differential input module. In the second differential-mode negative feedback loop, the PWM_N_DIFF signal is amplified by the power amplifier module, passed through the second resistor, and then fed back to the inverting input terminal of the differential input module.

[0074] The input of the Class D audio power amplifier bias voltage processing circuit receives differential mode components PWM_P_DIFF and PWM_N_DIFF. The output of the Class D audio power amplifier bias voltage processing circuit is connected to the input of the power output module to process the differential mode components PWM_P_DIFF and PWM_N_DIFF and output the finely tuned PWM signal to the power output module.

[0075] The power output module is used to amplify and filter the finely tuned PWM signal and transmit the processed audio signal to the object to be driven.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A method for processing the bias voltage of a Class D audio power amplifier, characterized in that, The method includes the following steps: Multiple fine-tuning options are set for the feedback resistors at the differential terminals of the Class D power amplifier. By determining the feedback resistor setting with the minimum bias voltage during chip factory testing and programming the OTP, the coarse adjustment of the bias voltage is completed. After coarse adjustment of the bias voltage, the PWM signal generated by the PWM modulator is divided into two signals. One signal is processed by a delay unit and then ANDed with the other signal to output a finely adjusted PWM signal. The finely adjusted PWM signal is used to drive the speaker after passing through a switching amplifier and a low-pass filter.

2. The method for processing the bias voltage of a Class D audio power amplifier according to claim 1, characterized in that, The delay unit is implemented using several levels of gate circuits; the process of determining the number of gate circuit levels includes: Based on the typical values ​​of system voltage, switching frequency, and individual gate delay, determine the impact of each gate circuit on the bias voltage. The number of cascaded gate circuits is determined based on the remaining bias voltage after coarse adjustment and the influence of each gate circuit on the bias voltage.

3. The method for processing the bias voltage of a Class D audio power amplifier according to claim 2, characterized in that, A fine-tuning switch is connected in parallel for each gate circuit. During the factory testing of the Class D power amplifier chip, based on the test results, the bypass switch configuration of the gate delay circuit that can achieve the minimum bias voltage is programmed into the OTP to connect the required number of gate delay circuits and achieve extremely low bias voltage.

4. The method for processing the bias voltage of a Class D audio power amplifier according to claim 2, characterized in that, The method further includes: After the coarsely tuned PWM signal is processed by the delay unit, it is then ANDed with the coarsely tuned PWM signal to obtain the finely tuned PWM signal.

5. A bias voltage processing circuit for a Class D audio power amplifier, characterized in that, The circuit includes: a bias coarse adjustment unit and a PWM duty cycle fine adjustment unit; The bias coarse adjustment unit is used to set multiple fine adjustment options for the feedback resistors at the differential terminals of the Class D power amplifier. By determining the feedback resistor setting with the minimum bias voltage during chip factory testing and programming the OTP, the bias voltage coarse adjustment is completed. The PWM duty cycle fine-tuning unit is used to divide the PWM signal generated by the PWM modulator into two signals after the bias voltage coarse adjustment is completed. One signal is processed by the delay unit and then ANDed with the other signal to output the finely tuned PWM signal. The finely tuned PWM signal is used to drive the speaker after passing through the switching amplifier and low-pass filter.

6. The Class D audio power amplifier bias voltage processing circuit according to claim 5, characterized in that, The PWM duty cycle fine-tuning unit includes a delay unit and an AND gate. The input of the delay unit receives the coarsely tuned PWM signal, which contains the coarsely tuned residual bias voltage. The output of the delay unit is connected to one input of the AND gate, the other input of the AND gate receives the coarsely tuned PWM signal, and the output of the AND gate is used to output the finely tuned PWM signal. The delay unit is implemented using several levels of gate circuits; the process of determining the number of gate circuit levels includes: Based on the typical values ​​of system voltage, switching frequency, and individual gate delay, determine the impact of each gate circuit on the bias voltage. The number of cascaded gate circuits is determined based on the remaining bias voltage after coarse adjustment and the influence of each gate circuit on the bias voltage.

7. The Class D audio power amplifier bias voltage processing circuit according to claim 6, characterized in that, A fine-tuning switch is connected in parallel for each gate circuit. During the factory testing of the Class D power amplifier chip, based on the test results, the bypass switch configuration of the gate delay circuit that can achieve the minimum bias voltage is programmed into the OTP to connect the required number of gate delay circuits and achieve extremely low bias voltage.

8. The Class D audio power amplifier bias voltage processing circuit according to claim 5, characterized in that, The circuit also includes a noise gate; The noise gate is used to perform a logical AND operation between the finely tuned PWM signal and the delayed PWM signal after processing by the delay unit, and to filter out the output signal with an amplitude below the preset value as noise to obtain the final PWM signal.

9. The Class D audio power amplifier bias voltage processing circuit according to claim 8, characterized in that, The noise gate includes a second delay unit and a second AND gate; The input of the second delay unit is used to receive the finely tuned PWM signal. The output of the second delay unit is connected to one input of the second AND gate. The other input of the second AND gate receives the finely tuned PWM signal. The output of the second AND gate is used to output the final PWM signal.

10. A Class D audio power amplifier, characterized in that, The Class D audio power amplifier includes a PWM modulator, a Class D audio power amplifier bias voltage processing circuit as described in any one of claims 5 to 9, a full-bridge power stage, and a low-pass filter unit. The input terminal of the PWM modulator receives an analog audio signal, the output terminal of the PWM modulator is connected to the input terminal of the Class D audio power amplifier bias voltage processing circuit, the output terminal of the Class D audio power amplifier bias voltage processing circuit is connected to the input terminal of the full-bridge power stage, and the output terminal of the full-bridge power stage is connected to the speaker after passing through the low-pass filter unit.

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