Pwm control analog output method and device, computer device, and storage medium

Abstract

The application relates to a PWM control analog quantity output method and device, computer equipment and a storage medium. The method comprises the following steps: obtaining a target analog quantity output value V and converting the target analog quantity output value V into a target fixed-point quantization value D; selecting a time point at which an output analog quantity change rate is lower than a preset threshold value as a stable time point t1, collecting a steady-state duty cycle P1, a steady-state quantization value D1 and a steady-state analog quantity output value V1 at the stable time point t1, and calculating an RC time constant of a capacitor at the stable time point t1 according to the steady-state duty cycle P1, the steady-state quantization value D1 and the steady-state analog quantity output value V1; selecting a corresponding segmented processing strategy according to the target fixed-point quantization value D and the steady-state quantization value D1 at the stable time point to generate a PWM output duty cycle P; performing integral correction on the PWM output duty cycle P to obtain a corrected duty cycle P'; updating the corrected duty cycle P' after correction to a PWM register to obtain an actual output analog quantity, and the value of the actual output analog quantity is an actual analog quantity output value V'. The application has the effect of improving the real-time performance of PWM control analog quantity output.

Description

Technical Field

[0001] This application relates to the technical field of analog output control, and in particular to a PWM control method, apparatus, computer device, and storage medium for analog output. Background Technology

[0002] Currently, PWM (Pulse Width Modulation) technology is widely used in the control of analog outputs, especially in motor speed regulation, temperature control, audio signal generation, and power regulation. PWM technology controls the average value of the output signal by adjusting the duty cycle of the pulses, thereby achieving precise load control. However, in practical applications, PWM technology has certain limitations, particularly in terms of output waveform accuracy and stability.

[0003] Traditional PWM control of analog output primarily alters the average voltage of the output signal by adjusting the duty cycle. However, due to the characteristics of components such as capacitors, the actual output waveform does not instantly transform into a square wave, but rather exhibits a gradual change. This waveform transition caused by component characteristics affects the accuracy and response speed of the output signal, especially at higher frequencies where the waveform smoothing process is more pronounced, leading to increased measurement errors.

[0004] Existing PWM control methods for analog output typically employ digital filters or increase PWM resolution to improve the quality of the output waveform. However, these methods often rely on more complex hardware or computational resources, resulting in poor real-time performance and an inability to promptly raise the analog output to the target value.

[0005] The existing technical solutions mentioned above have the drawback of poor real-time performance of PWM control for analog output. Summary of the Invention

[0006] To improve the real-time performance of analog output in PWM control, this application provides a method, apparatus, computer device, and storage medium for analog output in PWM control.

[0007] The above-mentioned objective of this application is achieved through the following technical solution:

[0008] Obtain the target analog output value V, and convert the target analog output value into a target fixed-point quantization value D;

[0009] The moment when the rate of change of the output analog quantity is lower than a preset threshold is selected as the stable moment t1. The steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1 of the stable moment t1 are collected. The RC time constant of the capacitor at the stable moment t1 is calculated based on the steady-state duty cycle P1, the steady-state quantization value D1 and the steady-state analog quantity output value V1.

[0010] Based on the target fixed-point quantization value D and the steady-state quantization value D1 at the stable moment, a corresponding segmented processing strategy is selected to generate the PWM output duty cycle P;

[0011] The PWM output duty cycle P is integrally corrected to obtain the corrected duty cycle P';

[0012] The corrected duty cycle P' is updated to the PWM register to obtain the actual output analog quantity, the value of which is the actual analog output value V'.

[0013] By adopting the above technical solutions, the target analog output value is converted into a target fixed-point quantized value, unifying the control target into the digital domain and reducing the time delay caused by analog-to-digital conversion and jitter. This provides a low-overhead input basis for subsequent rapid calculation of the duty cycle, thereby improving the real-time performance of PWM control analog output. By acquiring the duty cycle, quantized value, and output voltage at a stable moment, the RC time constant of the capacitor is calculated, facilitating the elimination of the influence of capacitor charging characteristics on the analog output, thus improving the accuracy of PWM control analog output. By selecting a segmented processing strategy to generate the duty cycle based on the target quantized value and the steady-state quantized value, the control quantity can be quickly obtained by directly solving in the low region and using the superposition compensation of the preceding duty cycle in the high region, thereby saving computational resources. By performing integral correction through the corresponding PWM output duty cycle and writing it to the PWM register in real time, the influence of capacitor charging characteristics on the analog output is eliminated, thereby improving the real-time performance of PWM control analog output.

[0014] In a preferred embodiment, this application can be further configured such that: the RC time constant of the capacitor at the steady-state time t1 is calculated based on the steady-state duty cycle P1, the steady-state quantization value D1, and the steady-state analog output value V1, specifically including:

[0015] According to the capacitor charging formula V t =V u *(1−e −t / RC The value of the RC time constant is obtained by solving the problem.

[0016] At steady time t1, t=t1, the initial voltage V0 of the capacitor when it starts charging is 0.

[0017] By adopting the above technical solution, the RC time constant can be solved at the steady moment based on the capacitor charging formula, which facilitates the elimination of the influence of capacitor charging characteristics on analog output, thereby improving the accuracy of PWM control of analog output.

[0018] In a preferred embodiment, this application can be further configured such that the segmented processing strategy specifically includes:

[0019] Obtain the PWM period time T;

[0020] When the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D.

[0021] When the target fixed-point quantization value D is greater than the steady-state quantization value D1, the sum of the preceding duty cycle before the steady-state time t1 and the compensated duty cycle after the steady-state time t1 is calculated to obtain the PWM output duty cycle P.

[0022] By adopting the above technical solution, and by obtaining the PWM cycle time and using a segmented processing strategy (the duty cycle is directly calculated for D≤D1, and the previous duty cycle is superimposed to compensate for D>D1), a simpler solution path can be selected in different target intervals, thereby reducing the amount of real-time calculation and waiting time, and improving the real-time performance of PWM control analog output.

[0023] In a preferred embodiment, this application can be further configured such that: when the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D, specifically including:

[0024] When the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, the PWM high-level output time t is calculated by inversely solving the capacitor charging formula.

[0025] The PWM output duty cycle P is obtained by calculating the ratio of the PWM high-level output time t to the PWM period time T.

[0026] By adopting the above technical solution, the high-level duration is obtained by inversely solving the capacitor charging formula, and the duty cycle is obtained by comparing it with the PWM period. The control quantity can be directly given with a closed-form solution, avoiding the multi-cycle delay caused by iterative solution, thereby reducing the calculation delay, increasing the control frequency, and shortening the time for the analog output to reach the target output, thus improving the real-time performance of PWM control analog output.

[0027] In a preferred embodiment, this application can be further configured as follows: when the target fixed-point quantization value D is greater than the steady-state quantization value D1, the sum of the preceding duty cycle before the stable time t1 and the compensated duty cycle after the stable time t1 is calculated to obtain the PWM output duty cycle P, specifically including:

[0028] Since the capacitor is in the charging process driven by the same duty cycle before the stable time t1, the preceding duty cycle P0 = P1 before the stable time t1;

[0029] Calculate the analog output value ΔV = V - V1 that needs to be compensated after steady time t1 based on the target analog output value V and the steady-state analog output value V1;

[0030] Substituting the analog output value ΔV into the capacitor charging formula, the high-level compensation time t2 required for compensation is calculated by inverse solution.

[0031] The high-level compensation time t2 is calculated as the ratio of the PWM period time T to obtain the compensation duty cycle P2;

[0032] The preceding duty cycle P1 is added to the compensated duty cycle P2 to obtain the final PWM output duty cycle P.

[0033] By adopting the above technical solution, the compensation amount is calculated by the difference between the target analog output value and the steady-state analog output value, and the compensation time is obtained by inverse solution. Then, the compensation duty cycle is obtained and summed with the previous duty cycle, thus eliminating the influence of capacitor charging characteristics on analog output and improving the accuracy of PWM control analog output.

[0034] In a preferred embodiment, this application may be further configured to include, before calculating the PWM output duty cycle P based on the target fixed-point quantization value D:

[0035] Multiple fixed-point quantization values ​​and corresponding data points with duty cycles are pre-sampled, and a lookup table is established to search for the target fixed-point quantization value D in the lookup table.

[0036] If the corresponding fixed-point quantization value can be found, the corresponding PWM output duty cycle P can be obtained directly;

[0037] If the corresponding fixed-point quantization value cannot be found, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D.

[0038] By adopting the above technical solution, a quantization value-duty cycle lookup table is established by pre-sampling and the table is looked up first during operation. The control quantity can be given with constant time complexity, thereby significantly reducing computational overhead and saving computing resources. By recalculating the duty cycle when the value is not hit, the entire domain can be controlled, thus ensuring real-time performance while taking into account the accuracy of analog output control.

[0039] In a preferred embodiment, this application can be further configured such that: the integral correction of the PWM output duty cycle P to obtain the corrected duty cycle P' specifically includes:

[0040] The deviation δV between the actual analog output value V` and the target analog output value V is calculated using the formula δV=V`-V;

[0041] Based on the deviation value δV, the cumulative deviation ΣδV is obtained by integrating and accumulating.

[0042] The corrected duty cycle P` is calculated using the formula P`=P+Ki*ΣδV based on the output duty cycle P and the cumulative deviation ΣδV, where Ki refers to a preset integral coefficient.

[0043] By adopting the above technical solution, the deviation between the actual output and the target output is calculated and integrated, and a duty cycle correction is generated with a preset integral coefficient, thereby eliminating the influence of capacitor charging characteristics on analog output and further improving the real-time performance of PWM control analog output.

[0044] The second objective of this invention is achieved through the following technical solution:

[0045] A PWM-controlled analog output device, the PWM-controlled analog output device comprising:

[0046] The target acquisition module is used to acquire the target analog output value V and convert the target analog output value into a target fixed-point quantization value D;

[0047] The steady-state modeling module is used to select the moment when the rate of change of the output analog quantity is lower than a preset threshold as the steady-state moment t1, collect the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1 at the steady-state moment t1, and calculate the RC time constant of the capacitor at the steady-state moment t1 based on the steady-state duty cycle P1, the steady-state quantization value D1 and the steady-state analog quantity output value V1.

[0048] The segmented processing module is used to select the corresponding segmented processing strategy to generate the PWM output duty cycle P based on the target fixed-point quantization value D and the steady-state quantization value D1 at the stable moment.

[0049] An integral correction module is used to perform integral correction on the PWM output duty cycle P to obtain a corrected duty cycle P;

[0050] The output update module is used to update the corrected duty cycle P to the PWM register to obtain the actual output analog quantity, the value of which is the actual analog output value V`.

[0051] By adopting the above technical solutions, the target analog output value is converted into a target fixed-point quantized value, which unifies the control target to the digital domain, reduces the time delay caused by analog-to-digital conversion and jitter, and provides a low-overhead input basis for subsequent rapid calculation of the duty cycle, thereby improving the real-time performance of PWM control analog output. By acquiring the duty cycle, quantized value, and output voltage at the steady-state moment, the RC time constant of the capacitor is calculated, which facilitates the elimination of the influence of capacitor charging characteristics on the analog output, thereby improving the accuracy of PWM control analog output. By selecting a segmented processing strategy to generate the duty cycle based on the target quantized value and the steady-state quantized value, the control quantity can be quickly obtained by directly solving in the low region and by superimposing compensation with the previous duty cycle in the high region, thereby saving certain computing resources. By performing integral correction through the corresponding PWM output duty cycle and writing it into the PWM register in real time, the influence of capacitor charging characteristics on the analog output is eliminated, thereby improving the real-time performance of PWM control analog output.

[0052] The above-mentioned objective three of this application is achieved through the following technical solution:

[0053] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described PWM control analog output method.

[0054] The fourth objective of this application is achieved through the following technical solution:

[0055] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described PWM control analog output method.

[0056] In summary, this application includes at least one of the following beneficial technical effects:

[0057] 1. Solving for the RC time constant at steady time based on the capacitor charging formula facilitates the subsequent elimination of the influence of capacitor charging characteristics on analog output. The compensation amount is calculated by the difference between the target analog output value and the steady-state analog output value, and the compensation time is obtained by inverse solution. Then, the compensation duty cycle is obtained and summed with the previous duty cycle, thus eliminating the influence of capacitor charging characteristics on analog output. By pre-sampling to establish a quantization value-duty cycle lookup table and prioritizing table lookup during operation, the control quantity can be given with constant time complexity, thereby significantly reducing computational overhead and saving computational resources. By recalculating the duty cycle when a match is missed, full controllability can be ensured, thus ensuring both real-time performance and accuracy of analog output control.

[0058] 2. By acquiring the PWM cycle time and adopting a segmented processing strategy (directly calculating the duty cycle for D≤D1, and using the preceding duty cycle to compensate for the duty cycle when D>D1), a simpler solution path can be selected in different target intervals, thereby reducing real-time calculation and waiting time. The high-level duration is obtained by inversely solving the capacitor charging formula, and the duty cycle is obtained by comparing it with the PWM cycle. The control quantity can be directly given with a closed-form solution, avoiding the multi-cycle delay caused by iterative solutions, thereby reducing calculation delay, increasing control frequency, and shortening the time for analog output to reach the target output. By calculating the deviation between the actual output and the target output and performing integration and accumulation, a duty cycle correction quantity is generated with a preset integration coefficient, thereby eliminating the influence of capacitor charging characteristics on analog output and improving the real-time performance of PWM control analog output. Attached Figure Description

[0059] Figure 1 This is a flowchart of a PWM control analog output method in one embodiment of this application.

[0060] Figure 2 This is a flowchart illustrating the implementation of step S20 in a PWM control analog output method according to an embodiment of this application.

[0061] Figure 3 This is a flowchart illustrating the implementation of step S30 in a PWM control analog output method according to an embodiment of this application.

[0062] Figure 4 This is a flowchart illustrating the implementation of step S32 in the PWM control analog output method of one embodiment of this application.

[0063] Figure 5 This is a flowchart illustrating the implementation of step S33 in a PWM control analog output method according to an embodiment of this application.

[0064] Figure 6 This is another implementation flowchart of step S32 in the PWM control analog output method in one embodiment of this application.

[0065] Figure 7 This is a flowchart illustrating the implementation of step S40 in a PWM control analog output method according to an embodiment of this application.

[0066] Figure 8 This is a schematic block diagram of a PWM-controlled analog output device in one embodiment of this application.

[0067] Figure 9 This is a schematic diagram of a device according to one embodiment of this application. Detailed Implementation

[0068] The present application will be further described in detail below with reference to the accompanying drawings.

[0069] In one embodiment, such as Figure 1 As shown, this application discloses a PWM control analog output method, which specifically includes the following steps:

[0070] S10: Obtain the target analog output value V and convert the target analog output value into the target fixed-point quantization value D.

[0071] Specifically, the target voltage range (e.g., 0~10V) is linearly mapped to a fixed-point numerical range (e.g., 0~32000), and the target voltage V is mapped to the corresponding fixed-point quantization value D. Let the duty cycle be PWM and the output voltage be D. AC Then D AC When the data is fixed-point quantized, the correspondence is as follows: 0~32000 corresponds to 0~10V, where V CC If the voltage is 16.9V, then the duty cycle and the fixed-point data Data of the analog output have the following relationship: VCC*PWM=Data*10 / 32000. From this, we can derive PWM=Data / 54080. Therefore, the output voltage D... AC The control is actually the control of fixed-point quantized data Data, which can be converted into the control of the PWM output duty cycle P. That is, the output voltage D can be controlled by controlling the analog output duty cycle P. AC .

[0072] S20: Select the moment when the rate of change of the output analog quantity is lower than the preset threshold as the stable time t1, collect the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1 at the stable time t1, and calculate the RC time constant of the capacitor at the stable time t1 based on the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1.

[0073] Specifically, based on the capacitor charging formula V t =V u *(1−e −t / RC Establish the relationship, and use the collected P1, D1 and V1 to solve for the value of the RC time constant of capacitor charging.

[0074] S30: Select the corresponding segmented processing strategy to generate the PWM output duty cycle P based on the target fixed-point quantization value D and the steady-state quantization value D1 at the steady moment.

[0075] Specifically, the pre-set target fixed-point quantization value D is compared with the fixed-point quantization value D1 at the stable time t1 of the PWM output. Segmentation is performed using D1 as the critical point to obtain the analog output duty cycle P, thereby saving computing resources.

[0076] S40: Perform integral correction on the PWM output duty cycle P to obtain the corrected duty cycle P'.

[0077] Specifically, the deviation is obtained by the difference between the target analog output value and the actual analog output value. The deviation is then integrated and accumulated cycle by cycle, and the accumulated value is weighted according to the preset integration parameters to obtain the corrected duty cycle P'.

[0078] S50: Update the corrected duty cycle P' to the PWM register to obtain the actual output analog quantity. The value of the actual output analog quantity is the actual analog output value V.

[0079] Specifically, the corrected duty cycle P' is written into the PWM register, and the output waveform is controlled by the PWM register. After being filtered by a capacitor, an analog output signal corresponding to the target voltage is obtained.

[0080] In one embodiment, such as Figure 2 As shown, in step S20, the RC time constant of the capacitor at steady time t1 is calculated based on the steady-state duty cycle P1, the steady-state quantization value D1, and the steady-state analog output value V1. Specifically, this includes:

[0081] S21: According to the capacitor charging formula V t =V u *(1−e −t / RC The value of the RC time constant is obtained by solving the problem.

[0082] Specifically, the calculated PWM output stability (V t =V u At time t1, the duty cycle P1, the fixed-point quantization value D1, and the actual analog output V1 are given. Theoretically, it takes 5 RC cycles to fully charge the device capacitor. Substituting these values ​​into the capacitor charging formula yields the following result. V u To represent the analog quantity of a fully charged capacitor, set V. u =16.9, V0=0, then given t1, the RC value of the device can be solved.

[0083] In one embodiment, such as Figure 3 As shown, in step S30, the segmented processing strategy specifically includes:

[0084] S31: Get the PWM cycle time T.

[0085] Specifically, the fixed period T of the PWM set by the system is obtained.

[0086] S32: When the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D.

[0087] Specifically, the corresponding PWM output duty cycle P is obtained by inversely solving the capacitor formula.

[0088] S33: When the target fixed-point quantization value D is greater than the steady-state quantization value D1, calculate the sum of the preceding duty cycle before the steady-state time t1 and the compensation duty cycle after the steady-state time t1 to obtain the PWM output duty cycle P.

[0089] Specifically, the duty cycle P1 recorded at the stable moment is taken as the preceding duty cycle. The additional high-level duration t required to reach the target is calculated based on the difference between the target analog output value V and the stable analog output value V1. Then, it is converted into a compensation duty cycle according to the period and added to the preceding duty cycle to obtain the final duty cycle.

[0090] In one embodiment, such as Figure 4 As shown, in step S32, when the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D, specifically including:

[0091] S321: When the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, the PWM high-level output time t is calculated by inversely solving the capacitor charging formula.

[0092] Specifically, based on the capacitor charging formula, the formula t=−RC*ln(1−V / V1) is derived.

[0093] S322: The PWM output duty cycle P is obtained by calculating the ratio of the PWM high-level output time t to the PWM period time T.

[0094] Specifically, the PWM output duty cycle P = t / T.

[0095] In one embodiment, such as Figure 5 As shown, in step S33, when the target fixed-point quantization value D is greater than the steady-state quantization value D1, the sum of the preceding duty cycle before the steady-state time t1 and the compensated duty cycle after the steady-state time t1 is calculated to obtain the PWM output duty cycle P, specifically including:

[0096] S331: Since the capacitor is in the charging process driven by the same duty cycle before the steady-state time t1, the preceding duty cycle P0 = P1 before the steady-state time t1.

[0097] Specifically, the PWM register remains unchanged before and after t1, so the duty cycle is the same. Therefore, the preceding duty cycle P0 is equal to the steady-state duty cycle P1 at the steady moment.

[0098] S332: Calculate the analog output value ΔV = V − V1 that needs to be compensated after steady time t1 based on the target analog output value V and the steady-state analog output value V1.

[0099] Specifically, the analog output value ΔV that needs to be compensated is obtained by subtracting the target analog output value V from the analog output value V1 at the steady time.

[0100] S333: Substitute the analog output value ΔV into the capacitor charging formula and inversely calculate the high-level compensation time t2 required for compensation.

[0101] Specifically, setting an absolute tolerance ε, the error between the final analog output value and the target output value does not exceed ε, then V−V(t2)=ε, since the final analog output value V(t2)=V−(V−V1)e −t2 / RC From this, we can deduce that t2 = -RC*ln(ε / (V-V1)).

[0102] S334: Calculate the ratio of the high-level compensation time t2 to the PWM period time T to obtain the compensation duty cycle P2.

[0103] Specifically, P2 = t2 / T.

[0104] S335: Add the preceding duty cycle P1 to the compensation duty cycle P2 to obtain the final PWM output duty cycle P.

[0105] Specifically, the PWM output duty cycle P = P1 + P2.

[0106] In one embodiment, such as Figure 6 As shown, in step S32, before calculating the PWM output duty cycle P based on the target fixed-point quantization value D, the following steps are also included:

[0107] S3201: Presample multiple fixed-point quantization values ​​and corresponding data points of duty cycle, and establish a lookup table.

[0108] Specifically, during the debugging or calibration phase, several representative quantization values ​​are output and the actual voltage after stabilization is collected. Based on this, the available duty cycle is deduced, and the paired data is stored in non-volatile memory or program constants in the form of key values.

[0109] S3202: Find the target fixed-point quantization value D in the lookup table.

[0110] Specifically, in the lookup table, key-value pairs whose key value is equal to the target fixed-point quantization value D are matched.

[0111] S3203: If the corresponding fixed-point quantization value can be found, the corresponding PWM output duty cycle P can be obtained directly.

[0112] Specifically, if an exact correspondence exists, the corresponding duty cycle is taken as the PWM output duty cycle.

[0113] S3204: If the corresponding fixed-point quantization value cannot be found, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D.

[0114] Specifically, if a precise correspondence cannot be found, a formula is used for calculation.

[0115] In one embodiment, such as Figure 7 As shown, in step S40, the PWM output duty cycle P is integrally corrected to obtain the corrected duty cycle P, which specifically includes:

[0116] S41: Calculate the deviation δV between the actual analog output value V1 and the target analog output value V according to the formula δV=V−V1.

[0117] Specifically, the actual voltage V1 is read according to the sampling period, and δV=V−V1 is calculated from the target analog output value V.

[0118] S42: Integrate and accumulate based on the deviation value δV to obtain the cumulative deviation ΣδV.

[0119] Specifically, the current deviation is added to the cumulative amount ΣδV in each cycle.

[0120] S43: Based on the output duty cycle P and the cumulative deviation ΣδV, use the formula P=P+K i The corrected duty cycle P is calculated using *ΣδV, where K i This refers to the preset integral coefficient.

[0121] Specifically, a preset integral coefficient K is used. i After weighting the cumulative amount, it is added to the duty cycle P to obtain the correction result, thus avoiding overcompensation or oscillation of the system.

[0122] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0123] In one embodiment, a PWM-controlled analog output device is provided, which corresponds one-to-one with the PWM-controlled analog output method described in the above embodiments. For example... Figure 8 As shown, this PWM-controlled analog output device includes a target acquisition module, a steady-state modeling module, a segmented processing module, an integral correction module, and an output update module. Detailed descriptions of each functional module are as follows:

[0124] The target acquisition module is used to acquire the target analog output value V and convert the target analog output value into the target fixed-point quantization value D;

[0125] The steady-state modeling module is used to select the moment when the rate of change of the output analog quantity is lower than a preset threshold as the steady-state moment t1, collect the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1 at the steady-state moment t1, and calculate the RC time constant of the capacitor at the steady-state moment t1 based on the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1.

[0126] The segmented processing module is used to select the corresponding segmented processing strategy to generate the PWM output duty cycle P based on the target fixed-point quantization value D and the steady-state quantization value D1 at the stable moment.

[0127] The integral correction module is used to perform integral correction on the PWM output duty cycle P to obtain the corrected duty cycle P;

[0128] The output update module is used to update the corrected duty cycle P to the PWM register to obtain the actual output analog quantity. The value of the actual output analog quantity is the actual analog output value V`.

[0129] Optional, the steady-state modeling module includes:

[0130] The formula derivation submodule is used to derive the capacitor charging formula V. t =V u *(1−e −t / RC The value of the RC time constant is obtained by solving for the value of the capacitor. At the steady time t1, t=t1, the initial voltage V0=0 when the capacitor starts charging.

[0131] Optionally, the segmentation processing module includes:

[0132] The period acquisition submodule is used to acquire the PWM period time T;

[0133] The low-zone duty cycle calculation submodule is used to calculate the PWM output duty cycle P based on the target fixed-point quantization value D when the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1.

[0134] The high-zone duty cycle calculation submodule is used to calculate the sum of the preceding duty cycle before the stable time t1 and the compensated duty cycle after the stable time t1 when the target fixed-point quantization value D is greater than the steady-state quantization value D1, so as to obtain the PWM output duty cycle P.

[0135] Optional, the low-zone duty cycle calculation submodule includes:

[0136] The inverse calculation unit is used to calculate the PWM high-level output time t by inversely solving the capacitor charging formula;

[0137] The ratio calculation unit is used to calculate the ratio of the PWM high-level output time t to the PWM period time T to obtain the PWM output duty cycle P.

[0138] Optional, the high-zone duty cycle calculation submodule includes:

[0139] The preceding duty cycle confirmation unit is used to ensure that the capacitor is in the charging process driven by the same duty cycle before the stable time t1, so the preceding duty cycle P0=P1 before the stable time t1.

[0140] The voltage difference calculation unit is used to calculate the analog output value ΔV=V−V1 that needs to be compensated after the steady-state time t1 based on the target analog output value V and the steady-state analog output value V1.

[0141] The compensation time calculation unit is used to substitute the analog output value ΔV into the capacitor charging formula and inversely calculate the high-level compensation time t2 required for compensation.

[0142] The compensation duty cycle calculation unit is used to calculate the ratio of the high-level compensation time t2 to the PWM period time T, and obtain the compensation duty cycle P2.

[0143] The output duty cycle synthesis unit is used to add the preceding duty cycle P1 and the compensation duty cycle P2 to obtain the final PWM output duty cycle P.

[0144] Optionally, the low-zone duty cycle calculation submodule also includes:

[0145] A lookup table is used to pre-sample multiple fixed-point quantization values ​​and corresponding data points of duty cycle to establish a lookup table;

[0146] The target quantization value lookup submodule is used to look up the target fixed-point quantization value D in the lookup table.

[0147] The duty cycle acquisition submodule is used to directly obtain the corresponding PWM output duty cycle P if a corresponding fixed-point quantization value can be found; otherwise, the PWM output duty cycle P is calculated based on the target fixed-point quantization value D.

[0148] Optionally, the integral correction module includes:

[0149] The deviation calculation module is used to calculate the deviation value δV between the actual analog output value V1 and the target analog output value V according to the formula δV=V−V1;

[0150] The integral accumulation module is used to perform integral accumulation based on the deviation value δV to obtain the cumulative deviation ΣδV;

[0151] The duty cycle correction module is used to adjust the output duty cycle P and the cumulative deviation ΣδV using the formula P=P+K. i The corrected duty cycle P` is calculated using *ΣδV, where K i This refers to the preset integral coefficient.

[0152] Specific limitations regarding the PWM-controlled analog output device can be found in the above description of the PWM-controlled analog output method, and will not be repeated here. Each module in the aforementioned PWM-controlled analog output device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the computer device's memory, so that the processor can call and execute the corresponding operations of each module.

[0153] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a PWM control analog output method.

[0154] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0155] Obtain the target analog output value V, and convert the target analog output value into the target fixed-point quantization value D;

[0156] The moment when the rate of change of the output analog quantity is lower than a preset threshold is selected as the stable time t1. The steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1 at the stable time t1 are collected. The RC time constant of the capacitor at the stable time t1 is calculated based on the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1.

[0157] Based on the target fixed-point quantization value D and the steady-state quantization value D1 at the steady moment, the corresponding segmented processing strategy is selected to generate the PWM output duty cycle P;

[0158] The PWM output duty cycle P is integrally corrected to obtain the corrected duty cycle P';

[0159] The corrected duty cycle P' is updated to the PWM register to obtain the actual output analog quantity, which is the actual analog output value V'.

[0160] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0161] Obtain the target analog output value V, and convert the target analog output value into the target fixed-point quantization value D;

[0162] The moment when the rate of change of the output analog quantity is lower than a preset threshold is selected as the stable time t1. The steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1 at the stable time t1 are collected. The RC time constant of the capacitor at the stable time t1 is calculated based on the steady-state duty cycle P1, steady-state quantization value D1 and steady-state analog quantity output value V1.

[0163] Based on the target fixed-point quantization value D and the steady-state quantization value D1 at the steady moment, the corresponding segmented processing strategy is selected to generate the PWM output duty cycle P;

[0164] The PWM output duty cycle P is integrally corrected to obtain the corrected duty cycle P';

[0165] The corrected duty cycle P' is updated to the PWM register to obtain the actual output analog quantity, which is the actual analog output value V'.

[0166] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0167] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0168] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A PWM control analog output method, characterized by, The PWM control analog quantity output method comprises: acquiring a target analog quantity output value V and converting the target analog quantity output value into a target fixed-point quantization value D; selecting a time point at which an output analog quantity change rate is lower than a preset threshold value as a stable time point t1, collecting a steady-state duty cycle P1, a steady-state quantization value D1 and a steady-state analog quantity output value V1 at the stable time point t1, and calculating an RC time constant of a capacitor at the stable time point t1 according to the steady-state duty cycle P1, the steady-state quantization value D1 and the steady-state analog quantity output value V1; generating a PWM output duty cycle P according to a corresponding segmented processing strategy selected according to the target fixed-point quantization value D and the steady-state quantization value D1 at the stable time point; integrally correcting the PWM output duty cycle P to obtain a corrected duty cycle P'; updating the corrected duty cycle P' after correction to a PWM register to obtain an actual output analog quantity, and the value of the actual output analog quantity is an actual analog quantity output value V'; The RC time constant of the capacitor at the stable time point t1 calculated according to the steady-state duty cycle P1, the steady-state quantization value D1 and the steady-state analog quantity output value V1 specifically comprises: According to the capacitor charging equation V t = V u *(1 - e −t / RC) to solve for the value of the RC time constant, i.e., At the stable time instant t1, i.e. at t = t1, V t = V1, and the initial voltage of the capacitor at the beginning of the charging V0= 0, Since V u = VCC*P1, VCC*P1 = D1*V max / D max , So P1=D1*V max / (Vcc*D max ), derived V u =VCC*P1=D1*V max / D max , into the capacitor charging formula V1=D1*V max / D max *(1-e −t1 / RC), further derived RC=t1 / -ln(1-(V1*D max ) / (D1*V max )), wherein V t is the analog quantity of the capacitor at t, V u is the analog quantity when the capacitor is fully charged, Vcc is the analog quantity of the power supply, V max is the maximum value of PWM analog output, D max is the maximum value of the vertex quantization value; The segmented processing strategy specifically comprises: acquiring a PWM cycle time T; when the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, calculating a PWM output duty cycle P according to the target fixed-point quantization value D; when the target fixed-point quantization value D is greater than the steady-state quantization value D1, calculating a sum of a preceding duty cycle before the stable time point t1 and a compensation duty cycle after the stable time point t1 to obtain the PWM output duty cycle P.

2. The PWM control analog output method according to claim 1, characterized by, When the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, calculating a PWM output duty cycle P according to the target fixed-point quantization value D specifically comprises: when the target fixed-point quantization value D is less than or equal to the steady-state quantization value D1, calculating a PWM high-level output time t by inversely solving a capacitor charging formula; calculating a ratio of the PWM high-level output time t to the PWM cycle time T to obtain the PWM output duty cycle P.

3. The PWM control analog output method according to claim 1, characterized by, When the target fixed-point quantization value D is greater than the steady-state quantization value D1, calculating a sum of a preceding duty cycle before the stable time point t1 and a compensation duty cycle after the stable time point t1 to obtain the PWM output duty cycle P specifically comprises: Since the capacitor is in a charging process driven by the same duty cycle before the stable time point t1, the preceding duty cycle P0 before the stable time point t1 is equal to the steady-state duty cycle P1; calculating an analog quantity output value ΔV=V-V1 that needs to be compensated after the stable time point t1 according to the target analog quantity output value V and the steady-state analog quantity output value V1; substituting the analog quantity output value ΔV into a capacitor charging formula to inversely calculate a high-level compensation time t2 required for compensation; calculating a ratio of the high-level compensation time t2 to the PWM cycle time T to obtain a compensation duty cycle P2; The pre-sequence duty ratio P0 is added to the compensation duty ratio P2 to obtain a final PWM output duty ratio P.

4. The PWM control analog output method according to claim 1, characterized by, Before the PWM output duty ratio P is calculated according to the target fixed-point quantization value D, the method further comprises: A plurality of corresponding data points of fixed-point quantization values and duty ratios are pre-sampled to establish a lookup table, and the target fixed-point quantization value D is looked up in the lookup table. If the corresponding fixed-point quantization value can be found, the corresponding PWM output duty ratio P can be directly obtained. If the corresponding fixed-point quantization value cannot be found, the PWM output duty ratio P is calculated according to the target fixed-point quantization value D.

5. The PWM control analog output method according to claim 1, characterized by, The integral correction of the PWM output duty ratio P is performed to obtain a corrected duty ratio P`. The deviation value δV of the actual analog output value V` and the target analog output value V is calculated according to the formula δV = V`-V. The integral accumulation based on the deviation value δV is performed to obtain a cumulative deviation ΣδV. According to the output duty ratio P and the accumulated deviation ΣδV, a revised duty ratio P` is calculated by the formula P`=P+K i *ΣδV, wherein the K i is a preset integral coefficient.

6. A PWM control analog output device, characterized by, The PWM control analog output device comprises: A target acquisition module is configured to acquire a target analog output value V and convert the target analog output value into a target fixed-point quantization value D. A steady-state modeling module is configured to select a time point at which an output analog change rate is lower than a preset threshold as a steady time t1, collect a steady-state duty ratio P1, a steady-state quantization value D1 and a steady-state analog output value V1 at the steady time t1, and calculate an RC time constant of a capacitor at the steady time t1 according to the steady-state duty ratio P1, the steady-state quantization value D1 and the steady-state analog output value V1. A segmented processing module is configured to select a corresponding segmented processing strategy according to the target fixed-point quantization value D and the steady-state quantization value D1 at the steady time to generate a PWM output duty ratio P. An integral correction module is configured to perform integral correction on the PWM output duty ratio P to obtain a corrected duty ratio P`. An output updating module is configured to update the corrected duty ratio P to a PWM register to obtain an actual output analog, and a value of the actual output analog is an actual analog output value V`. The steady-state modeling module comprises: The formula derivation submodule is used to derive the capacitor charging formula V. t =V u *(1−e −t The value of the RC time constant is obtained by solving for / RC, that is, at the steady time t1, i.e., t=t1, V t =V1, and the initial voltage V0 of the capacitor when it starts charging is 0, since V u =VCC*P1, VCC*P1=D1*V max / D max Therefore, P1 = D1 * V max / (Vcc*D max ), and derived V u =VCC*P1=D1*V max / D max Substituting into the capacitor charging formula, we get V1 = D1 * V max / D max *(1−e −t1 / RC), further derivation yields RC=t1 / -ln(1-(V1*D) max ) / (D1*V max )), where V t Let V be the analog quantity of the capacitor at time t. u Vcc is the analog quantity at the moment the capacitor is fully charged, and V is the analog quantity of the power supply. max D represents the maximum value of the PWM analog output. max The maximum value of the vertex quantization; The segmented processing module comprises: A cycle acquisition submodule is configured to acquire a PWM cycle time T. A low-zone duty ratio calculation submodule is configured to calculate a PWM output duty ratio P according to a target fixed-point quantization value D when the target fixed-point quantization value D is less than or equal to a steady-state quantization value D1. A high-zone duty ratio calculation submodule is configured to calculate a sum of a pre-sequence duty ratio before a steady time t1 and a compensation duty ratio after the steady time t1 to obtain a PWM output duty ratio P when the target fixed-point quantization value D is greater than the steady-state quantization value D1.

7. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the PWM control analog output method according to any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, the computer-readable storage medium comprising: The computer program is executed by the processor to implement the steps of the PWM control analog output method according to any one of claims 1 to 5.

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