Verification excitation automatic generation method and system based on backtracking thinking tree

Abstract

The invention discloses an automatic verification excitation generation method based on a backtracking thinking tree, and the method comprises the steps: constructing a backtracking thinking tree frame based on a self-feedback mechanism based on a thinking tree for a to-be-verified processor function; under the backtracking thinking tree framework, decoupling a to-be-verified function from top to bottom through a large language model, and recursively decomposing the whole to-be-verified function into function points capable of being independently verified layer by layer through a tree structure; according to each function point, determining a normal function and a boundary of each function point, and for each function point, generating verification excitation layer by layer in a tree structure; after the verification excitation is generated, self-verification and self-backtracking are carried out layer by layer through a tree structure, and finally, the generated verification excitation is executed on the processor design to verify the correctness of the processor function. According to the method and the system, the function verification efficiency and the verification coverage rate of the processor are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor function verification, and in particular to a processor function verification stimulus automatic generation method and system based on a backtracking thought tree. BACKGROUND

[0002] In the field of processor verification, the cost of manually writing verification stimuli is high, and there is currently a lack of tools that can automatically extract function points from design specification documents and generate verification stimuli for the extracted function points. The development of large models has made it possible to design such automated tools.

[0003] Currently, in the LLM code generation based on the prompt method, the ToT (Tree of Thought) method has made significant progress in the field of natural language processing and artificial intelligence, especially in logical reasoning and complex problem solving. The ToT method effectively improves the ability of the model to handle complex tasks by guiding the artificial intelligence model to gradually unfold the thinking process, which is particularly evident in the field of automated code generation, significantly advancing the development of related technologies.

[0004] However, although ToT has been successful in the above fields, its direct application in the field of function verification stimulus generation has relatively limited effectiveness. The reason is that the ToT method is not good at effectively decoupling the design to be verified, that is, decomposing the entire system into independently verifiable modules. In the process of function verification, it is usually necessary to verify each component of the system in a modular manner to ensure that each module can correctly perform its intended function. The continuous thinking mode of the ToT method is more suitable for handling problems that require a coherent and continuous thought process, rather than for scenarios that require step-by-step and modular detailed verification.

[0005] In function verification, the design usually needs to be decomposed into multiple sub-modules, each of which needs to be tested and verified individually. This approach helps to identify and isolate problems, making the verification process more systematic and efficient. In contrast, the continuous thinking mode of the ToT method may cause some modules or steps to be overlooked in the verification process, thereby failing to comprehensively cover all possible test cases. In addition, the ToT method may not be able to effectively capture the functional dependencies between complex modules, which is crucial for ensuring the correctness and reliability of the entire system.

[0006] In summary, although LLM reasoning paradigms such as ToT have achieved remarkable results in general reasoning tasks, their direct migration to the field of function verification stimulus generation exposes obvious shortcomings:

[0007] 1. Weak decoupling ability. ToT's linear thinking makes it difficult to break down complex SoCs into independently verifiable submodules, which does not conform to the "top-down, layer-by-layer verification" engineering practice, resulting in high coupling of generated stimuli, making it impossible to accurately and comprehensively test individual functional points.

[0008] 2. Large coverage blind area. Once the continuous reasoning path is missing in the middle, the subsequent steps will be missing, which will easily miss the boundary scenarios, and the capture of inter-module dependencies is insufficient, making it difficult to ensure the overall functional correctness.

[0009] Therefore, although the ToT method has shown great potential in some fields, in the field of functional verification stimulus generation, further adjustment and optimization may be needed to meet the needs of modular verification. This requires further development and exploration of new technologies or methods to better combine the advantages of ToT with the characteristics of functional verification, thereby improving the efficiency and effectiveness of verification.

[0010] In summary, a new verification stimulus automatic generation method based on self-feedback backtracking thinking tree (BToT) is needed to solve the technical problems of insufficient decoupling, difficulty in capturing dependencies, and difficulty in generating stimuli directly for modular verification in the field of functional verification. SUMMARY

[0011] To solve the technical problems of long cycle in the functional verification stage of "manual extraction of functional points + handwritten verification stimuli" and the high coupling and difficulty in ensuring coverage of the current BToT-based prompt-guided LLM reasoning method, the present application proposes a verification stimulus automatic generation method based on a self-feedback backtracking thinking tree (BToT).

[0012] In a first aspect, the present application provides a verification stimulus automatic generation method based on a backtracking thinking tree, applied to processor functional verification, the method comprising:

[0013] Backtracking thinking tree construction step: for the processor function to be verified, a backtracking thinking tree framework based on a self-feedback mechanism is constructed based on the thinking tree;

[0014] Functional point dynamic decoupling step: under the backtracking thinking tree framework, the large language model is used to recursively decompose the entire function to be verified into independently verifiable functional points in a tree structure from top to bottom;

[0015] Stimulus hierarchical generation step: determine the normal function and boundary of each functional point respectively, and generate verification stimuli for each functional point in a tree structure layer by layer;

[0016] Self-verification backtracking step: after generating the verification incentive, self-verification and self-backtracking are performed layer by layer in a tree structure, and finally the generated verification incentive is executed on the processor design to verify the correctness of the processor function under the backtracking thinking tree framework.

[0017] In specific embodiments of the present application, the above-mentioned verification incentive automatic generation method based on the backtracking thinking tree further comprises:

[0018] Backtracking re-partitioning step: in the self-verification backtracking step, the verification function point decomposition error is executed.

[0019] In specific embodiments of the present application, the above-mentioned function point dynamic decoupling step comprises:

[0020] The to-be-verified task is input into the root node of the backtracking thinking tree, and a large language model extracts a plurality of to-be-verified function points, each root node of the thinking tree representing an extracted independent to-be-verified function point, wherein the number of extracted function points is determined by the large language model according to the complexity of the task, and the function points are independent of each other.

[0021] In specific embodiments of the present application, the above-mentioned incentive hierarchical generation step comprises:

[0022] Each function point is subjected to separate verification incentive generation, and a large language model simulates data changes of a processor component during incentive runtime.

[0023] In specific embodiments of the present application, the above-mentioned self-verification backtracking step comprises:

[0024] Self-verification step: based on the generated verification incentive and data change process, a large language model performs verification of each function point, and if the verification fails, the incentive hierarchical generation step is repeatedly executed, and if the number of consecutive verification failures reaches a preset threshold, the backtracking re-partitioning step is executed.

[0025] Self-backtracking step: if the verification is successful, backtracking is performed, the code of the generated verification incentive is submitted to the parent node of the upper level, and jumping is continued to execute the integration step;

[0026] Integration step: when the parent node obtains the code of the verification incentive submitted by all child nodes of the lower level, integration is performed, if the parent node is a non-root node, the integrated verification incentive is submitted to the parent node of the upper level, and the integration step is repeatedly executed until the root node, then the task is completed, and a list of extracted verification function points and complete verification incentive code are output.

[0027] In specific embodiments of the present application, the above-mentioned backtracking re-partitioning step comprises:

[0028] The large language model determines whether to continue to subdivide the function points according to the complexity index value of the current to-be-verified task. If the complexity index value is greater than a preset threshold, the function points are continued to be divided, and the excitation hierarchical generation step is re-executed.

[0029] If the complexity index value is less than the preset threshold, the function point division is wrong, backtracking is performed, the current node and all sibling nodes of the current node are deleted, the function points are re-extracted for the parent node, and the excitation hierarchical generation step is re-executed for the extracted new function points.

[0030] In a second aspect, an embodiment of the present application provides a verification excitation automatic generation system based on a backtracking thinking tree, applied to processor function verification, adopting the verification excitation automatic generation method based on the backtracking thinking tree as described above, and the system comprises:

[0031] A backtracking thinking tree construction module: based on the thinking tree, a backtracking thinking tree framework based on a self-feedback mechanism is constructed for the to-be-verified processor function.

[0032] A function point dynamic decoupling module: under the backtracking thinking tree framework, the to-be-verified function is decoupled from top to bottom by the large language model, and the entire to-be-verified function is recursively decomposed into function points that can be independently verified layer by layer in a tree structure.

[0033] An excitation hierarchical generation module: the normal function and the boundary of each function point are determined respectively, and the verification excitation is generated layer by layer in a tree structure for each function point.

[0034] A self-verification backtracking module: after the verification excitation is generated, self-verification and self-backtracking are performed layer by layer in a tree structure, and finally the generated verification excitation is executed on the processor design under the backtracking thinking tree framework to verify the correctness of the processor function.

[0035] In a specific embodiment of the present application, the verification excitation automatic generation system based on the backtracking thinking tree as described above further comprises:

[0036] A backtracking redivision module: in the self-verification backtracking step, if the function point decomposition is wrong, a backtracking redivision operation is performed.

[0037] In a third aspect, an embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, and the program, when executed by a processor, implements the steps of the verification excitation automatic generation method based on the backtracking thinking tree.

[0038] In a fourth aspect, an embodiment of the present application provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor, when executing the program, implements the steps of the verification excitation automatic generation method based on the backtracking thinking tree.

[0039] Compared with the related prior art, the following outstanding benefits are achieved:

[0040] 1) The method of the present application proposes a three-section BToT framework of "dynamic decoupling of function points - generation of excitation hierarchy - self-verification backtracking", which recursively decomposes the verification task into independent function points, and then generates, verifies and merges the excitation code layer by layer in a tree structure, achieving high decoupling of complex designs.

[0041] 2) The method of the present application proposes to embed the Top-Down modular design idea and Design-for-Verification (DFV) process into the BToT prompting engineering, so that the large model follows the engineering paradigm of "verification of sub-modules first, then system-level integration" when generating excitation, reducing the semantic gap between excitation and design implementation.

[0042] 3) The method of the present application proposes a self-verification and self-backtracking mechanism of "failure - re-generation - re-subdivision": when a certain function point fails in self-verification for three consecutive times, secondary subdivision or backtracking re-partition is automatically triggered, ensuring that the excitation is neither excessively redundant nor misses boundary scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0043] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The illustrative embodiments of the present application and their descriptions serve to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0044] Figure 1 This is a personnel division diagram for the embodiment project of the present application;

[0045] Figure 2 This is a diagram of the automatic verification excitation method of the present application based on the backtracking thinking tree;

[0046] Figure 3 This is a diagram of the self-feedback backtracking thinking tree method of the embodiment of the present application;

[0047] Figure 4 This is a diagram of the method of guiding the LLM to generate verification excitation of the embodiment of the present application;

[0048] Figure 5 This is a diagram of the automatic verification excitation system of the present application based on the backtracking thinking tree;

[0049] Figure 6 This is a diagram of the computer hardware of the present application. DETAILED DESCRIPTION

[0050] In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or the like means any combination of the items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0051] It should also be understood that the term "and / or" herein merely describes an associated relationship between associated objects, and means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after it, but can also represent an "and / or" relationship. The specific meaning can be understood according to the context before and after it.

[0052] It should also be understood that the order of the above processes in various embodiments of the present application does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0053] In several embodiments provided by the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are only schematic. The division of units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another device, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed objects can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0054] The units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e. they can be located in one place or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0055] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0056] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0057] In order to make the above-mentioned features and effects of the present application more clear and easy to understand, the following embodiments are specifically described below, and the detailed description is made in conjunction with the accompanying drawings. The present application discloses one or more embodiments comprising the features of the present application. The disclosed embodiments are only used for illustration. The protection scope of the present application is not limited to the disclosed embodiments, and the present application is defined by the appended claims.

[0058] The following is a system embodiment corresponding to the above-mentioned method embodiment, and the present embodiment can be implemented in cooperation with the above-mentioned embodiments. The related technical details mentioned in the above-mentioned embodiments are still valid in the present embodiment. In order to reduce repetition, they will not be described here again. Correspondingly, the related technical details mentioned in the present embodiment can also be applied in the above-mentioned embodiments.

[0059] The present application aims to propose a method of guiding Large Language Model (LLM) reasoning by using self-feedback thought tree with function decoupling driving, automatically generating verification stimuli, so as to improve the efficiency and verification coverage of processor function verification.

[0060] In the process of exploring the automatic generation of verification stimuli based on large models, the following key technical difficulties have been gradually discovered and overcome:

[0061] 1. The existing LLM prompt framework ToT mainly uses linear or shallow tree reasoning, lacks a systematic mechanism of "decoupling first, then generating, and then backtracking", which makes it difficult to split complex processors into independent verification points, resulting in coarse verification granularity and high coupling degree.

[0062] 2. Deep combination of the function decoupling idea and LLM requires the design of a new prompt structure: to make the model divide modules from top to bottom like a verification engineer, realize the closed loop of "decoupling-generation-self verification-re-generation-self backtracking".

[0063] 3. When running on the processor, the stimulus code must simultaneously satisfy both syntactic correctness and functional correctness. In the functional verification of the processor, any tiny error will bring high reproduction costs; therefore, the LLM needs to have self-verification and self-backtracking capabilities to complete error correction and convergence within three iterations.

[0064] The Backtrack Tree-of-Thought (BToT) framework proposed in this invention addresses the aforementioned problems by: firstly, using LLM (Layered Modeling) for top-down functional decoupling, breaking down complex tasks into independent functional points; then, discussing the normal function and boundary conditions of each functional point; next, generating verification stimuli for each functional point, and performing self-verification and backtracking after generation; finally, executing the generated verification stimuli on the processor design to verify the functional correctness of the design and shorten the verification cycle. This method overcomes the inherent shortcomings of the ToT method in processor functional decoupling, verification, and high coverage requirements.

[0065] The backtracking tree technique employed in this invention is a problem-solving method that systematically explores all possible solutions by breaking down the problem into smaller subproblems. Starting from the root node, branches represent potential paths, with deeper levels corresponding to further decisions. When a dead end is encountered or constraints are violated, the algorithm backtracks to previous decision points, avoiding unnecessary exploration. This combination of branching and backtracking ensures an efficient and thorough depth search for solutions.

[0066] In actual project development, designers, verification engineers, and product managers each have different responsibilities, working together to ensure the smooth progress of the project. Designers are responsible for reviewing the product manager's project plan, completing module designs, and debugging based on feedback from verification engineers. They need to possess strong technical knowledge and innovative capabilities to ensure the design meets project requirements and achieves the expected performance standards. A diagram illustrating the division of labor in the specific project development process is shown below. Figure 1 As shown.

[0067] The system of this application embodiment will be described in detail below with reference to specific embodiments:

[0068] Example 1

[0069] like Figure 2 As shown in the figure, this application proposes an automatic generation method for verification incentives based on backtracking mind trees, applied to processor functional verification. The method includes:

[0070] Step 101 of building the backtracking mind tree: For the processor function to be verified, build a backtracking mind tree framework based on the self-feedback mechanism.

[0071] Inspired by the division of labor among designers, verification engineers, and product managers during project development, it can be recognized that a systematic and modular approach is also needed in verification work. This approach first involves decoupling complex verification tasks, i.e., breaking them down into multiple independent, more manageable functional points. In this way, the requirements and potential problems of each functional point can be more accurately located, thereby improving the efficiency and accuracy of verification.

[0072] After extracting the functional points, the verification engineer can develop a special verification plan and test cases for each functional point. This approach not only helps to ensure that each functional point is fully tested and verified, but also facilitates quick localization and repair when problems are found. In addition, through the modular approach, verification work can be more flexible to adapt to changes in project requirements, as each functional point can be independently adjusted and optimized without the need for large-scale modifications to the entire system.

[0073] Based on the above thinking and the inspiration of IC design methodology (e.g., Top-down and DFV), the present application proposes a novel self-feedback backtrack thought tree (BToT) framework that simulates the real project developer's workflow to achieve fine control of the thinking process, thereby generating accurate and complete verification stimulus codes. The entire process can be modeled as a self-feedback backtrack thought tree, as shown in Figure 3

[0074] Functional point dynamic decoupling step 102: Under the backtrack thought tree framework, the large language model is used to decouple the function to be verified from top to bottom, and the entire function to be verified is recursively decomposed into independently verifiable functional points in a tree structure;

[0075] Stimulus hierarchical generation step 103: Determine the normal function and boundary of each functional point respectively, and generate verification stimuli for each functional point in a tree structure;

[0076] Self-verification backtracking step 104: After generating the verification stimuli, perform self-verification and self-backtracking in a tree structure, and finally execute the generated verification stimuli on the processor design under the backtrack thought tree framework to verify the correctness of the processor function.

[0077] In specific embodiments of the present application, the above-mentioned verification stimulus automatic generation method based on the backtrack thought tree further comprises:

[0078] Backtracking re-partitioning step 105: In the self-verification backtracking step, if the verification functional point decomposition is incorrect, perform a backtracking re-partitioning operation.

[0079] ​In the embodiment of the present application, the function point dynamic decoupling step 102 comprises:

[0080] The to-be-verified task is input into the root node of the backtracking thinking tree, and the large language model extracts a plurality of to-be-verified function points, each root node of the thinking tree representing an independent to-be-verified function point extracted, wherein the number of extracted function points is determined by the large language model according to the complexity of the task, and the function points are independent of each other.

[0081] When the root node inputs the verification task description, the LLM first extracts a plurality of to-be-verified function points therefrom, wherein the number of extracted function points is determined by the LLM according to the complexity of the task, and the function points are as independent as possible, so as to decouple the to-be-verified task as much as possible, each node representing an independent to-be-verified function point, and the excitation hierarchical generation step 103 is continued to be executed.

[0082] As shown in FIG. 1, Figure 3 The two white rectangular boxes at the top of the figure represent the initial function points extracted from the input. These are root nodes, each representing an independent to-be-verified function point.

[0083] In the embodiment of the present application, the excitation hierarchical generation step 103 comprises:

[0084] The verification excitation is generated separately for each extracted function point, and the large language model simulates the data changes of the processor components during excitation.

[0085] The verification excitation is generated separately for each extracted function point, and the LLM simulates the data changes of the processor key components during excitation, and the self-verification backtracking step 104 is continued to be executed. As shown in FIG. 2, Figure 3 Each node represents a function point to be verified.

[0086] In the embodiment of the present application, the self-verification backtracking step 104 comprises:

[0087] Self-verification step: based on the generated verification excitation and data change process, the large language model verifies each function point, if the verification fails, the excitation hierarchical generation step is repeated, if the number of consecutive verification failures reaches a preset threshold, the backtracking redivision step is executed;

[0088] Self-backtracking step: if the verification is successful, the generated verification excitation code is submitted to the parent node of the upper level, and the integration step is continued to be executed;

[0089] The integration step: when the parent node gets the verification incentive code submitted by all the child nodes in the lower layer, the integrated verification incentive is submitted to the upper parent node if the parent node is not the root node, and the integration step is repeated until the root node, then the task is completed, and the extracted verification function point list and the complete verification incentive code are output.

[0090] For the generated verification incentive and data change process, the LLM verifies whether it can correctly cover the verification function point, such as the repeated incentive grading generation step 103, if it fails three times in a row, it jumps to the backtracking step 105; if the verification is successful, the generated verification incentive code is submitted to the parent node, and the integration step is executed.

[0091] As shown in Figure 3 The third layer on the right side of the pink node represents the last self-verification failure, and the process of re-generating and verifying is being verified. The green node in the fourth layer represents the generated verification incentive, and the green arrow points to its parent node, representing the submission of the verification incentive code to the parent node for merging.

[0092] The non-leaf node gets the verification incentive code submitted by all the child nodes in the lower layer, and integrates the integrated code, if the node is not the root node, the integrated code is submitted to the parent node, and the integration step is repeated. If the node is the root node, the task is completed, and the extracted verification function point list and the complete verification incentive code are output.

[0093] In the embodiment of the application, the backtracking step 105 includes:

[0094] The large language model determines whether to continue to subdivide the function points according to the complexity index value of the current task to be verified, if the complexity index value is greater than the preset threshold, the function points are further divided, and the incentive grading generation step is re-executed;

[0095] If the complexity index value is less than the preset threshold, the function point division is wrong, the current node and all the brother nodes of the current node are deleted, the function points of the parent node are re-extracted, and the incentive grading generation step is re-executed for the extracted new function points.

[0096] The LLM determines whether the specific complexity of the current task to be verified needs to be further subdivided into function points, if it is too complex, the function point is further subdivided into multiple function points, which is helpful for the correct generation of verification stimuli, and the verification stimulus hierarchical generation step 103 is re-executed; if the function point is simple enough, it is considered that the function point division is incorrect and is not a correct task division, then backtracking is performed, the current node and all its sibling nodes are deleted, and the function point is re-extracted for the parent node, and the new function point extracted is re-executed The verification stimulus hierarchical generation step 103.

[0097] As shown in Figure 3 , the left two green leaf nodes of the fourth layer represent that the verification task of the parent node is too complex, and the two child function points are further subdivided. Although the generated verification stimuli are correct, there are still errors after merging into the parent node, and the LLM judges that the further division of the function point of the parent node is incorrect, and the two leaf nodes are deleted and the child function points are re-divided from the parent node.

[0098] Finally, as shown in Figure 4 , the above steps are put into the processor module function verification shown in Figure 4 . By inputting the function description file SPEC of the processor to be verified and combining the prompt based on the BToT framework to the LLM, the LLM is accurately guided to generate verification stimuli.

[0099] As described above, the system of the present application can be better implemented.

[0100] Compared with the prior art, the present application has the following outstanding advantages and beneficial effects:

[0101] The present application performs a function verification experiment on the ARMv7 instruction set, Cache and MMU three typical modules of a processor chip design on the ChatGPT-4o platform, and compares with the verification points extracted manually. The results show that:

[0102] 1. In the function verification of the ARMv7 instruction set, the compilation pass rate, running pass rate and function point coverage rate of the verification stimuli generated by the LLM can all reach more than 90%, only in the coprocessor instruction type the performance is poor.

[0103] 2. In the function verification of Cache and MMU, the Cache and MMU verification related function points extracted by the BToT framework have smaller granularity and better decoupling effect than the function points extracted manually in the third chapter, and the compilation pass rate and running pass rate of the verification stimuli generated for each function point are 100%, indicating that the test stimuli generated have correct syntax and execution logic, and most of the function points can be correctly covered.

[0104] The application provides a systematic and automated new approach for processor function verification, which can significantly shorten the verification period and improve the coverage rate, and has important reference value for future processor function verification.

[0105] Embodiment Two

[0106] As shown in Figure 5 The embodiment of the application provides a verification incentive automatic generation system based on a rollback thinking tree, which is applied to processor function verification, adopts the verification incentive automatic generation method based on the rollback thinking tree, and comprises the following steps:

[0107] The rollback thinking tree construction module 201: for the processor function to be verified, a rollback thinking tree framework based on a self-feedback mechanism is constructed based on a thinking tree;

[0108] The function point dynamic decoupling module 202: under the rollback thinking tree framework, the function to be verified is decoupled from top to bottom by a large language model, and the entire function to be verified is recursively decomposed into function points that can be independently verified in a tree structure layer by layer;

[0109] The incentive hierarchical generation module 203: the normal function and the boundary of each function point are determined respectively, and the verification incentive is generated layer by layer in a tree structure for each function point;

[0110] The self-verification rollback module 204: after the generation of the verification incentive, self-verification and self-rollback are performed layer by layer in a tree structure, and finally the generated verification incentive is executed on the processor design under the rollback thinking tree framework to verify the correctness of the processor function.

[0111] The rollback re-partitioning module 205: in the self-verification rollback step, if the function point decomposition is incorrect, the rollback re-partitioning operation is performed.

[0112] Embodiment Three

[0113] The embodiment of the application provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to realize the steps of the verification incentive automatic generation method based on the rollback thinking tree.

[0114] Embodiment Four

[0115] The embodiment of the application provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor realizes the steps of the verification incentive automatic generation method based on the rollback thinking tree when executing the program.

[0116] In addition, in combination with Figure 1The method for automatically generating verification incentives based on the backtracking thought tree described in the embodiments of the present application can be implemented by an electronic device, such as a computer device. Figure 6 A schematic diagram of a hardware structure of a computer device according to an embodiment of the present application.

[0117] In some embodiments, the computer device can further include a communication interface 83 and a bus 80. As shown, the processor 81, the memory 82, and the communication interface 83 are connected by the bus 80 and complete communication with each other. Figure 6

[0118] Specifically, the processor 81 described above can include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or can be configured as one or more integrated circuits that implement the embodiments of the present application.

[0119] The memory 82 can be used to store or cache various data files required for processing and / or communication, and possible computer program instructions executed by the processor 81.

[0120] The processor 81 reads and executes the computer program instructions stored in the memory 82 to implement any of the above-described embodiments of the method for automatically generating verification incentives based on the backtracking thought tree.

[0121] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but it should be understood that any combination of the technical features that does not cause contradiction shall be considered within the scope of the present disclosure.

[0122] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.​

Claims

1. A method for automatically generating verification incentives based on backtracking mind trees, characterized in that, The method is applied to processor function verification, and the method comprises the following steps: A backtracking thought tree construction step: constructing a backtracking thought tree framework based on a self-feedback mechanism for a processor function to be verified based on a thought tree; A function point dynamic decoupling step: under the backtracking thought tree framework, a large language model is used to perform function decoupling to be verified from top to bottom, and the entire function to be verified is recursively decomposed into function points capable of being independently verified in a tree structure layer by layer; An incentive hierarchical generation step: determining normal functions and boundaries of each function point respectively, and generating verification incentives for each function point in a tree structure layer by layer; A self-verification backtracking step: after the verification incentives are generated, self-verification and self-backtracking are performed layer by layer in a tree structure, and finally the generated verification incentives are executed on a processor design to verify the correctness of the processor function under the backtracking thought tree framework.

2. The method of claim 1, wherein, The method further comprises: A backtracking re-partitioning step: in the self-verification backtracking step, if the function point decomposition is incorrect, a backtracking re-partitioning operation is performed.

3. The method of claim 1 or 2, wherein, The function point dynamic decoupling step comprises: The task to be verified is input into the root node of the backtracking thought tree, the large language model extracts multiple function points to be verified, each root node of the thought tree represents an independent function point to be verified, the number of the extracted function points is determined by the large language model according to the complexity of the task, and the function points are independent of each other.

4. The method of claim 1, wherein, The incentive hierarchical generation step comprises: Separate verification incentive generation is performed for each extracted function point, and the large language model simulates data changes of a processor component during the incentive runtime.

5. The method of claim 1, wherein, The self-verification backtracking step comprises: A self-verification step: based on the generated verification incentives and data change processes, the large language model verifies each function point, if the verification fails, the incentive hierarchical generation step is repeatedly performed, if the number of consecutive verification failures reaches a preset threshold, the backtracking re-partitioning step is performed; A self-backtracking step: if the verification is successful, the generated verification incentive code is submitted to the parent node of the upper level, and the integration step is continued to be executed; An integration step: when the parent node obtains the verification incentive code submitted by all child nodes of the lower level, the verification incentive after integration is submitted to the parent node of the upper level, the integration step is repeatedly executed until the root node, the task is completed, and the extracted verification function point list and complete verification incentive code are output.

6. The method of claim 1, wherein, The backtracking re-partitioning step comprises: The large language model determines whether to continue to subdivide the function points according to the complexity index value of the current task to be verified, if the complexity index value is greater than a preset threshold, the function points are further divided, and the incentive hierarchical generation step is re-executed; If the complexity index value is less than the preset threshold, the function point subdivision is incorrect, the current node and all sibling nodes of the current node are deleted, the function points of the parent node are re-extracted, and the incentive hierarchical generation step is re-executed for the extracted new function points.

7. A verification incentive automatic generation system based on backtracking mind tree, characterized in that, The application is applied to processor function verification, adopts the verification incentive automatic generation method based on the backtracking thinking tree in any one of claims 1-6, and the system comprises: a backtracking thinking tree construction module: based on a thinking tree, a backtracking thinking tree framework based on a self-feedback mechanism is constructed for a processor function to be verified; a function point dynamic decoupling module: under the backtracking thinking tree framework, a large language model is used to decouple the function to be verified from top to bottom, and the entire function to be verified is recursively decomposed into function points that can be independently verified in a tree structure; an incentive hierarchical generation module: according to each function point, the normal function and the boundary of each function point are determined respectively, and verification incentives are generated layer by layer in a tree structure for each function point; a self-verification backtracking module: after the generation of the verification incentives, self-verification and self-backtracking are performed layer by layer in a tree structure, and finally the generated verification incentives are executed on the processor design under the backtracking thinking tree framework to verify the correctness of the processor function.

8. The system of claim 7, wherein, The system further comprises: a backtracking re-partitioning module: in the self-verification backtracking step, the function point decomposition error is verified, and a backtracking re-partitioning operation is performed.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to realize the steps of the backtracking thinking tree-based verification incentive automatic generation method in any one of claims 1-6.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to realize the steps of the backtracking thinking tree-based verification incentive automatic generation method in any one of claims 1-6.

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