Self-networking control protection method and device for grid-connected energy storage converter, and medium

Abstract

The invention provides a self-networking control protection method and device for a grid-connected energy storage converter, and a medium. The method comprises the following steps: acquiring electrical quantities of a grid-connected point and a direct current side, establishing a short-circuit capacity estimation value and a positive and negative zero sequence model, and generating a voltage phasor reference; generating a given frequency and a given voltage according to the power and frequency droop and the reactive power and voltage droop; generalized impedance shaping is executed in a control loop, and virtual impedance and selective filtering are configured according to frequency bands; completing grid connection or re-connection according to a sequence of frequency slope, phase angle slow alignment and voltage amplitude gradual combination based on a grid connection point reference phasor; setting positive-sequence, negative-sequence and zero-sequence fault current upper limits and a time sequence template in the symmetric component domain; and outputting the given frequency, the given voltage, the sequence component limit value and the protection state instruction to a converter power bridge driving and grid-connected switch control interface. According to the invention, phase-lock-free grid-connected synchronization, unified control protection switching, sequence component controlled fault current and weak grid stable operation can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new energy, and in particular to a grid-friendly energy storage converter self-networking control protection method and device and a medium. BACKGROUND

[0002] New energy high proportion access makes the short-circuit capacity of the distribution network fluctuate and the branch impedance rise. The energy storage converter needs to form controllable and limited power behavior in voltage, frequency and fault current, etc. to undertake tasks such as black start, isolated network power supply, grid support and re-grid.

[0003] The existing scheme mainly adopts grid-following control, relies on a phase-locked loop to obtain a phase, and adopts fixed droop parameters for power and reactive power. Although some self-networking schemes can independently build voltage and frequency, the control and protection are mostly designed separately, the impedance shaping is concentrated in a single frequency band, the grid synchronization mostly adopts hard phase locking, and the fault current limiting is realized by saturation of the current inner loop or simple derating.

[0004] However, the existing technology still has the following problems: under the conditions of weak grid and disturbance, negative damping and oscillation easily occur; the switching between grid connection, isolated network and current limiting protection lacks unified state machine and invariant constraint, resulting in transient impact; the re-griding process is insufficient in negative sequence and harmonic suppression; the fault current is difficult to be controlled and synthesized in the positive, negative and zero sequence dimensions; the external instruction lacks feasible region and rate constraint; the droop and inertia setting is not adaptive to short-circuit capacity and state of charge, and it is difficult to balance the self-networking capability and grid-friendly characteristics. SUMMARY

[0005] Therefore, the embodiments of the present application provide a grid-friendly energy storage converter self-networking control protection method and device and a medium to solve the problems that the existing technology depends on a phase-locked loop for grid synchronization and is unstable in a weak grid, the control and protection lack unified state switching constraint, and the fault current cannot be controlled and synthesized in the sequence component domain.

[0006] In a first aspect, the application provides a self-networking control and protection method for a grid-friendly energy storage converter, including: collecting electrical quantities of a grid-connected point and a DC side, establishing a short-circuit capacity estimation value and a positive and negative sequence model, and generating a voltage phasor reference; under the condition of not relying on a phase-locked loop, enabling parallel control of a voltage inner loop and a current inner loop, generating a frequency given value and a voltage given value according to power and frequency droop and reactive power and voltage droop, and adaptively setting droop coefficients and inertia parameters according to an energy storage state of charge and the short-circuit capacity estimation value; performing generalized impedance shaping in a control loop, configuring virtual impedance and selective filtering according to a frequency band, and updating an impedance template through online identification; performing amplitude and rate constraints and compatibility checking on external power, reactive power, voltage or frequency instructions, injecting the instructions that pass the checking into a droop loop under power change rate and frequency change rate constraints; completing grid connection or re-connection according to the order of frequency ramp, phase angle buffer alignment and voltage amplitude gradual convergence based on a grid-connected point reference phasor; setting positive sequence, negative sequence and zero sequence fault current upper limits and a time sequence template in a symmetrical component domain, and establishing a unified priority with current limiting and DC side protection to synthesize a limited fault current; switching between self-networking, grid-connected operation and protection current limiting states in an event-triggered manner, and maintaining voltage phasor continuity, phase angle and power change rate limitation and smooth migration of impedance templates during the switching process; outputting the frequency given value, the voltage given value, sequence component limit values and protection state instruction to a converter power bridge drive and a grid-connected switch control interface for control and protection execution of self-networking and grid-connected operation of the energy storage converter.

[0007] In a second aspect, the application provides a self-networking control and protection device for a grid-friendly energy storage converter, comprising: an acquisition module configured to acquire electrical quantities of a grid point and a DC side, establish a short-circuit capacity estimation value and a positive and negative sequence model, and generate a voltage phasor reference; a control module configured to enable parallel control of a voltage inner loop and a current inner loop without relying on a phase-locked loop, generate a frequency given value and a voltage given value according to power and frequency droop and reactive power and voltage droop, and adaptively set droop coefficients and inertia parameters according to an energy storage state of charge and the short-circuit capacity estimation value; a configuration module configured to perform generalized impedance shaping in a control loop, configure virtual impedance and selective filtering according to frequency bands, and update an impedance template through online identification; a verification module configured to perform amplitude and rate constraint and compatibility verification on external power, reactive power, voltage or frequency instructions, inject the verified instructions into a droop loop under power rate and frequency rate constraints, and perform grid connection or re-connection based on a grid point reference phasor according to the order of frequency ramp, phase angle alignment and voltage amplitude convergence; a synthesis module configured to set positive sequence, negative sequence and zero sequence fault current upper limits and a timing template in a symmetrical component domain, and establish a unified priority with current limiting and DC side protection to synthesize limited fault current; a switching module configured to switch between self-networking, grid-connected operation and protection current limiting in an event-triggered manner, and maintain voltage phasor continuity, phase angle and power rate constraints and smooth impedance template migration during the switching process; and an output module configured to output the frequency given value, the voltage given value, sequence component limits and protection state instructions to a converter power bridge drive and a grid connection switch control interface, and perform self-networking and grid-connected operation control and protection for the energy storage converter.

[0008] In a third aspect, the application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above method.

[0009] The above at least one technical solution adopted by the embodiments of the application can achieve the following beneficial effects:

[0010] The short-circuit capacity estimation value and positive and negative sequence models are established by collecting electrical quantities of the grid-connected point and the DC side to generate a voltage phasor reference; under the condition of not relying on a phase-locked loop, a voltage inner loop and a current inner loop are enabled for parallel control, frequency and voltage given values are generated according to power and frequency droop and reactive power and voltage droop, and the droop coefficients and inertia parameters are adaptively adjusted according to the energy storage state of charge and the short-circuit capacity estimation value; generalized impedance shaping is performed in the control loop, virtual impedance and selective filtering are configured according to the frequency band, and the impedance template is updated online; the amplitude and rate constraints and compatibility check are performed on the external power, reactive power, voltage or frequency instructions, and the instructions passing the check are injected into the droop loop under the constraints of power change rate and frequency change rate; the grid connection or reconnection is completed in the order of frequency ramp, phase angle alignment and voltage amplitude convergence based on the grid-connected point reference phasor; the positive sequence, negative sequence and zero sequence fault current upper limits and time sequence templates are set in the symmetrical component domain, and the limited fault current is synthesized by establishing a unified priority with the current limiting and DC side protection; the self-networking, grid-connected operation and protection limiting state are switched in an event-triggered manner, and the voltage phasor is continuous, the phase angle and power change rate are limited, and the impedance template is smoothly migrated during the switching process; the frequency given value, voltage given value, sequence component limit value and protection state instruction are output to the converter power bridge drive and grid-connected switch control interface for controlling and protecting the self-networking and grid-connected operation of the energy storage converter. The application can realize phase-locked grid connection synchronization, unified control and protection switching, sequence component controlled fault current and weak grid stable operation. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0012] Figure 1 is a flowchart of a grid-friendly energy storage converter self-networking control and protection method provided by an embodiment of the present application;

[0013] Figure 2 is a structural schematic diagram of a grid-friendly energy storage converter self-networking control and protection device provided by an embodiment of the present application;

[0014] Figure 3 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0015] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, technologies, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0016] The existing energy storage converter is mostly grid-following type, which relies on phase-locked loop to obtain phase, and power and reactive power mostly use fixed droop parameters; although some self-networking schemes can build voltage and frequency, the control and protection are independent of each other, impedance shaping is concentrated in a single frequency band, grid synchronization mostly uses hard phase-locked loop, and fault current limiting often relies on saturation of current inner loop or simple derating, and external dispatching instructions lack feasible region and rate constraints.

[0017] The existing technical solutions still have the following problems: negative damping and oscillation easily occur under weak grid conditions; there is a lack of unified state switching and invariant constraints between self-networking, grid connection and fault current limiting protection, resulting in transient impact and instability; fault current is difficult to be controlled and synthesized in positive, negative and zero sequence dimensions; droop and inertia parameters cannot be self-adaptive to short-circuit capacity and state of charge.

[0018] In view of the problems existing in the prior art, the present application proposes a grid-friendly energy storage converter self-networking control and protection method: collecting grid points and DC side electrical quantities, establishing short-circuit capacity estimation value and positive, negative and zero sequence model and generating voltage phasor reference; under the condition of not relying on phase-locked loop, voltage inner loop and current inner loop run in parallel, frequency given and voltage given are generated according to power and frequency droop, reactive power and voltage droop, and are self-adaptive to state of charge and short-circuit capacity; generalized impedance shaping is performed in the control loop, virtual impedance and selective filtering are configured according to frequency band and are updated smoothly through online identification template; after the feasible region convex projection, rate gating and compatibility discrimination of external active, reactive, voltage and frequency instructions are implemented by the instruction sandbox, the instructions are injected into the droop loop; grid connection or reconnection is completed according to frequency slope, phase angle alignment and voltage amplitude gradual convergence based on grid point reference phasor; the upper limit of fault current and time sequence template are set in the symmetric component domain, and unified priority is established with the fault current limiting and DC side protection to synthesize the limited fault current; the state machine triggered by events performs switching between self-networking, grid connection and fault current limiting protection, maintains continuous voltage phasor, limited phase angle and power change rate, and smooth migration of impedance template.

[0019] Through the above technical solutions of the present application, the present application can realize lockless grid synchronization, form a unified control and protection switching mechanism, and control and synthesize fault current in sequence components domain, and maintain stability and limited operation during weak grid and reconnection.

[0020] The content of the technical solutions of the present application will be described in detail below in combination with the drawings and specific embodiments.

[0021] Figure 1 FIG. 1 is a flowchart of a method for self-networking control and protection of a grid-friendly energy storage converter according to an embodiment of the present application. As shown in the figure, the method for self-networking control and protection of the grid-friendly energy storage converter can specifically include the following steps. Figure 1

[0022] S101, collecting electrical quantities of a grid point and a DC side, establishing a short-circuit capacity estimation value and a positive and negative zero sequence model, and generating a voltage phasor reference;

[0023] S102, enabling parallel control of a voltage inner loop and a current inner loop without relying on a phase-locked loop, generating a frequency given value and a voltage given value according to power and frequency droop and reactive power and voltage droop, and adaptively adjusting droop coefficients and inertia parameters according to an energy storage state of charge and the short-circuit capacity estimation value;

[0024] S103, performing generalized impedance shaping in a control loop, configuring virtual impedance and selective filtering according to a frequency band, and updating an impedance template through online identification;

[0025] S104, performing amplitude and rate constraint and compatibility checking on external power, reactive power, voltage or frequency instructions, and injecting the instructions that pass the checking into a droop loop under power change rate and frequency change rate constraints;

[0026] S105, completing grid connection or reconnection according to the order of frequency ramp, phase angle slow alignment and voltage amplitude gradual convergence based on a grid point reference phasor;

[0027] S106, setting positive sequence, negative sequence and zero sequence fault current upper limits and a time sequence template in a symmetrical component domain, and establishing a unified priority with current limiting and DC side protection to synthesize a limited fault current;

[0028] S107, switching between self-networking, grid-connected operation and protection current limiting state in an event-triggered manner, and maintaining voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process;

[0029] S108, outputting the frequency given value, the voltage given value, the sequence component limit value and the protection state instruction to a converter power bridge drive and a grid connection switch control interface for control and protection execution of self-networking and grid-connected operation of the energy storage converter.

[0030] In some embodiments, the step of establishing a short-circuit capacity estimation value and a positive and negative zero sequence model, and generating a voltage phasor reference includes:

[0031] a sliding phasor estimator outputting positive sequence voltage and current phasors using frequency change rate gating;

[0032] ​The positive and zero sequence equivalent impedances are obtained by frequency band switchable perturbation injection and recursive online identification with forgetting factor, and the short circuit capacity estimation value is calculated according to the equivalent impedances;

[0033] The voltage phasor reference is formed by the phasor generator weighted by positive, negative and zero sequence under the double boundary of phase angle integration and amplitude limiting;

[0034] The phasor freezing and parameter self-updating are performed when the frequency variation rate or identification deviation exceeds the threshold.

[0035] Specifically, first, the system collects three-phase voltage and current signals at the grid connection point, and obtains positive, negative and zero sequence channels through symmetrical component transformation; when the frequency variation rate meets the gating condition, the sliding phasor estimator outputs the positive sequence voltage and current phasors; then, under the perturbation injection with controlled amplitude, the positive and zero sequence equivalent impedances are obtained by recursive online identification with forgetting factor, and the short circuit capacity estimation value is calculated; finally, the voltage phasor reference is formed by the phasor generator weighted by positive, negative and zero sequence under the double boundary of phase angle integration and amplitude limiting; when the frequency variation rate or identification deviation exceeds the threshold, the phasor freezing and parameter self-updating are triggered.

[0036] Further, the frequency variation rate gating is used to limit the effective window of phasor estimation, and the phasor is updated only when the frequency variation rate is below the threshold, which improves the estimation stability; the frequency band switchable perturbation injection refers to switching the injection frequency point and duration time among the preset low frequency, subsynchronous and harmonic frequency bands as needed, to ensure that identifiable impedance information can be obtained under different power grid conditions; the recursive online identification with forgetting factor adjusts the forgetting factor adaptively according to the operating state, to realize the consideration of parameter slow change and sudden change; the phasor freezing refers to keeping the phasor unchanged and suspending the phase angle integration during the abnormal period, and then resuming the continuous evolution after the parameter self-updating is completed; the double boundary phasor generation refers to integrating the phase angle by the estimated frequency and constraining the phase angle variation rate, and the amplitude is constrained within the allowed range by the amplitude limiter, while the negative and zero sequence components are suppressed by the weight.

[0037] In some specific scene examples, the embodiment can be implemented as follows. The sampling module obtains three-phase voltage and current with a fixed sampling period, and first removes the direct current bias and filters out the frequency outside the band pass; after symmetrical component transformation, the frequency variation rate threshold is set, and the positive and negative sequence voltage and current phasors are estimated with a sliding window, the window length is adaptively selected as one to two fundamental periods, and when the frequency variation rate approaches the threshold, the window is automatically shortened to reduce the hysteresis.

[0038] To obtain the equivalent impedance, the controller injects a small-amplitude perturbation current in the positive sequence channel, and the perturbation frequency is planned to switch between low frequency and subsynchronous frequency. In the zero sequence channel, intermittent injection is used to avoid persistent imbalance. The identification module uses recursive online identification, and the forgetting factor is adjusted according to the operating state in the range of 0.95 to 0.995. When the frequency change rate increases or the harmonic content increases, the forgetting factor is reduced to speed up the convergence. The identification output includes the amplitude and phase of the positive and zero sequence equivalent impedance and the resonance characteristic index. The short-circuit capacity estimation value is converted from the amplitude of the positive sequence impedance and the rated voltage at the point of common coupling.

[0039] The phasor generator takes the estimated frequency as the integral input of the phase angle, and sets the upper limit of the phase angle change rate to limit the phase angle advancing speed. The amplitude limiter sets the amplitude boundary according to the upper and lower limits of the voltage at the point of common coupling. The signal suppression weight is set for the negative and zero sequence components, so that the output voltage phasor reference is mainly positive sequence and suppresses the imbalance component. The controller continuously monitors the frequency change rate and identification deviation. When either of them exceeds the limit, the phasor freezing is immediately executed, the last valid phasor is retained, and the phase angle integration is suspended. At the same time, the priority of perturbation injection is increased, the identification frequency band is switched, and the forgetting factor is reset to a smaller value to speed up the re-identification. After the identification error falls within the threshold, the phase angle integration is restored according to the preset slope and the freezing is released.

[0040] In a typical operating example, the rated frequency at the point of common coupling is 50 Hz, and the voltage level is 10 kV. The system sets the frequency change rate threshold to 0.5 Hz / s, the upper limit of the phase angle change rate to 20 degrees per second, and the voltage amplitude limiting interval to ±10% of the rated value. The amplitude of the perturbation injection does not exceed 5% of the rated current, the low-frequency injection lasts for 200 ms, and the subsynchronous injection lasts for 100 ms, which are executed alternately. The initial value of the forgetting factor is 0.99, which is reduced to 0.97 when the frequency change rate exceeds 0.3 Hz / s or the harmonic distortion rate increases to speed up parameter updating. According to the positive sequence equivalent impedance amplitude obtained by identification and the short-circuit capacity estimation value converted from the rated voltage, the positive and negative zero sequence models are updated in real time. The phasor generator outputs the voltage phasor reference under the above double boundary and weighted suppression conditions, providing a unified phasor reference for subsequent droop control and grid synchronization.

[0041] In some embodiments, voltage inner loop and current inner loop parallel control are enabled, and frequency given and voltage given are generated according to power and frequency droop and reactive power and voltage droop, including:

[0042] A droop and inertia coordinator is constructed, taking active power, reactive power, energy storage state of charge, short-circuit capacity estimation value, and frequency change rate as input, and outputting frequency given and voltage given;

[0043] The active droop coefficient, reactive droop coefficient, and inertia parameter are segmented and set by the energy and short-circuit capacity joint mapper, and a hysteresis dead zone is set;

[0044] a dual-domain rate constraint of power change rate and phase angle change rate and a frequency change rate based gate-controlled integrator;

[0045] a sequence component weighted and negative sequence gated introduction to the reactive power and voltage droop to limit the composition of voltage given;

[0046] The current reference is generated by the voltage inner loop without relying on the phase-locked loop, and the current inner loop is followed by execution.

[0047] Specifically, first, the controller takes active, reactive, energy storage state of charge, short circuit capacity estimate and frequency change rate as input, builds droop and inertia coordinator output frequency given and voltage given; Active droop coefficient, reactive droop coefficient and inertia parameter are segmented and set hysteresis dead zone by energy and short circuit capacity joint mapper; The dual-domain rate constraint composed of power change rate and phase angle change rate limits the amplitude before given injection, and the frequency change rate gate-controlled integrator suppresses transient mutations; The sequence component weighted and negative sequence gated introduction to the reactive power and voltage droop limits the composition of voltage given; The current reference is generated by the voltage inner loop without relying on the phase-locked loop, and the current inner loop is followed by execution.

[0048] Further, the droop and inertia coordinator simultaneously generates frequency given and voltage given in a single interface, and binds inertia parameter and droop coefficient to the two-dimensional mapping surface of state of charge and short circuit capacity estimate; Joint mapping adjustment uses segmented intervals and hysteresis dead zone to avoid parameter back and forth jitter; Dual-domain rate constraint limits active change rate and phase angle change rate, and uses frequency change rate as gate signal to control integral on-off; Sequence component weighting and negative sequence gating adjust the weight of positive sequence, negative sequence and zero sequence to make the voltage given mainly in positive sequence and automatically suppressed when the negative sequence is over limit.

[0049] In some specific scene examples, the embodiment can be implemented as follows. The controller periodically reads the active and reactive measurement values, energy storage state of charge and short circuit capacity estimate, while calculating the frequency change rate. The droop and inertia coordinator takes active deviation and reactive deviation as input, generates frequency initial value and voltage initial value through active-frequency droop and reactive-voltage droop, and superimposes the inertia term output by joint mapping.

[0050] The combined mapping divides the state of charge into three sections, and the short-circuit capacity estimation value into three sections, forming a nine-square grid parameter table; each square corresponds to a set of active droop coefficients, reactive droop coefficients and inertia parameters, and a hysteresis band is set between adjacent squares. Only when the state of charge or the short-circuit capacity estimation value crosses the hysteresis band will the parameter set be switched. The frequency initial value enters the frequency rate of change gate integrator, and when the frequency rate of change is lower than the threshold, the integrator works and outputs the frequency given value, and when it is higher than the threshold, the last output is maintained; after the voltage initial value is subjected to the dual-domain rate constraint constituted by the power rate of change and the phase angle rate of change, the voltage given value is formed according to the amplitude limit value.

[0051] In order to avoid the influence of imbalance, the controller calculates the negative sequence and zero sequence amplitudes in real time, and when the negative sequence amplitude is lower than the threshold, the normal weighting is adopted, and when it exceeds the threshold, the negative sequence weight is reduced and the zero sequence is weighted to zero. Finally, the voltage inner loop generates the current reference with the voltage given value and the voltage phasor reference as input, and the current inner loop performs error adjustment and modulation output at the same time base, and the whole process does not enable the phase-locked loop.

[0052] In a typical example, the rated frequency of the grid-connected point is 50 Hz, the state of charge of the energy storage changes between 30% and 90%, and the short-circuit capacity estimation value is divided into low, medium and high three sections. The combined mapping selects a smaller active droop coefficient and a larger inertia parameter in the low state of charge and low short-circuit capacity estimation value interval, and selects a larger active droop coefficient and a moderate inertia parameter in the high state of charge and high short-circuit capacity estimation value interval; the hysteresis band is set to 5% of the boundary of the adjacent interval. The frequency rate of change threshold is set to 0.5 Hz per second, the phase angle rate of change upper limit is set to 20 degrees per second, and the active power rate of change upper limit is limited to 10% of the rated power per second. The negative sequence amplitude threshold is set to 5% of the positive sequence amplitude, and when it exceeds the threshold, the negative sequence weight is reduced to 50% of the original value, and the zero sequence weight is set to zero. Under the above parameters, the controller completes the parallel execution of the voltage inner loop and the current inner loop in the same sampling and modulation time base, and the frequency given value and the voltage given value are continuously injected after being subjected to the dual-domain rate constraint, and the current reference is generated by the voltage inner loop and is stably followed by the current inner loop.

[0053] The present embodiment cooperates the droop and inertia, the joint mapping of energy and short-circuit capacity setting, the dual-domain rate constraint and the sequence component weighting gate, so that the frequency given value and the voltage given value can be continuously output under different state of charge and short-circuit capacity conditions, and the voltage inner loop and the current inner loop work cooperatively under the premise of no phase-locked loop, completing the limited regulation and inner loop stable following of active power, reactive power and phase angle dynamics.

[0054] In some embodiments, generalized impedance shaping is performed in the control loop, virtual impedance is configured and selective filtering is selected according to frequency band, and impedance templates are updated online, including:

[0055] An impedance template library is established by segmenting low frequency, subsynchronous, harmonic and high frequency bands. Virtual resistance, virtual inductance and admittance clipping parameters are configured for positive, negative and zero sequences respectively, and switchable selective filter indexes are bound for each segment;

[0056] A double-channel perturbation injection and recursive online identification with forgetting factor are adopted to identify equivalent impedances and resonance characteristics of each sequence component within the frequency variation rate threshold, and to output template update quantities;

[0057] The selective filter index switching is driven by short-circuit capacity estimation value and resonance characteristics, and the impedance template smooth update is realized by template versioning and continuous interpolation;

[0058] The medium and high frequency band parameters are frozen in grid-connected handshake, weak network escort and current limiting protection states, only the low frequency damping parameter update is allowed, and the updated impedance template is connected to the voltage inner loop and current inner loop.

[0059] Specifically, first, an impedance template library is established by segmenting low frequency, subsynchronous, harmonic and high frequency bands. The low frequency band is used to set the virtual damping and phase lead element, the subsynchronous band sets the switchable notch and lead-lag combination, the harmonic band configures the targeted notch and admittance upper limit, and the high frequency band configures the equivalent rising inductance and admittance clipper. Virtual resistance parameters, virtual inductance parameters and admittance clipping parameters are set for positive, negative and zero sequences respectively, and switchable selective filter indexes are bound for each segment; each index corresponds to a set of center frequency, bandwidth and gain parameters, and the template version number is recorded.

[0060] Secondly, a double-channel perturbation injection and recursive online identification with forgetting factor are adopted to generate template update quantities. The positive sequence channel injects small amplitude current perturbation in low frequency and subsynchronous frequency band alternately, and the zero sequence channel injects in intermittent mode within the permitted window to avoid long-term imbalance; only when the frequency variation rate is below the threshold, the identification and parameter update are enabled. The identification output includes the amplitude and phase of the equivalent impedance of each sequence component, the suspected resonance center frequency and its quality factor, and the template update quantity is calculated accordingly. The forgetting factor is adaptively adjusted according to the operating state, and is reduced when the frequency variation rate increases or the harmonic index rises to speed up the convergence. To avoid sudden changes, the template parameters are smoothly transitioned by continuous interpolation with weights, and the update sequence is recorded with version number and time stamp.

[0061] Thirdly, the selective filter index switching is driven by short-circuit capacity estimation value and resonance characteristics, and the segmented freezing strategy is executed. When the short-circuit capacity estimation value is below the threshold or the resonance index exceeds the threshold, the index combination with stronger suppression is automatically switched; in the grid-connected handshake, weak network escort and current limiting protection states, the medium and high frequency band parameters are frozen, and only the low frequency damping parameter update is allowed. The updated impedance template is connected to the voltage inner loop feedforward and current inner loop clipping channel, so that the two inner loops call consistent template parameters under the same time base.

[0062] For example, in a typical example, the grid connection point has a rated voltage of 10 kV and a rated frequency of 50 Hz. The frequency band division and initial configuration are as follows: for the low frequency band (0.1 to 5 Hz), a virtual damping coefficient with a value range of 0.05 to 0.2 per unit is set, with a slight phase lead superimposed; for the subsynchronous band (5 to 40 Hz), a switchable notch filter is configured, with initial center frequencies of 25 Hz and 35 Hz, each with a bandwidth of 2 Hz; for the harmonic band (40 to 600 Hz), narrowband notches are set for 150 Hz and 250 Hz, with an admittance upper limit of 0.6 per unit of the rated admittance; for the high frequency band (greater than 600 Hz), an equivalent rising inductance parameter and an admittance limiter are set to suppress high-frequency circulating current.

[0063] The perturbation injection amplitude does not exceed 2% of the rated current. Low-frequency injection lasts for 200 milliseconds, and subsynchronous injection lasts for 120 milliseconds, alternating between the two. The frequency change rate threshold is set to 0.5 Hz per second. The recursive online identification forgetting factor is initially set to 0.99, decreasing to 0.97 as the identification residual increases to improve tracking speed. If the subsynchronous resonance center frequency is identified to have shifted to 28 Hz and the quality factor exceeds the threshold, the subsynchronous segment index is switched to a stronger suppression setting, and parameter transition is completed within 100 milliseconds using continuous interpolation. When the system enters grid handshake or current limiting protection state, harmonic and high-frequency parameters are frozen, allowing only the low-frequency virtual damping coefficient to be updated in small steps. The updated template parameters are simultaneously connected to the voltage setpoint correction branch of the voltage inner loop and the current reference limiting branch of the current inner loop to ensure consistent invocation of the same impedance shaping strategy by both inner loops.

[0064] This embodiment utilizes a segmented impedance template library with switchable filter indexes, online identification with dual-channel perturbation and forgetting factor, adaptive index switching based on short-circuit capacity estimates and resonance characteristics, and a segmented freezing and smooth update mechanism to ensure that impedance shaping remains configurable and online correctable across the entire frequency band. It also ensures consistent template usage and stable transition between the voltage inner loop and the current inner loop, thereby maintaining the expected impedance boundary and control stability under different grid connection intensities and operating conditions.

[0065] In some embodiments, amplitude and rate constraints and compatibility checks are performed on external power, reactive power, voltage, or frequency commands, and commands that pass the checks are injected into the droop loop under power change rate and frequency change rate constraints, including:

[0066] The verification and injection of external active, reactive, voltage, or frequency commands are implemented by a command sandbox. The command sandbox includes: a safety domain projector that performs convex set projection on the feasible domains of active, reactive, and frequency based on the energy storage state of charge and short-circuit capacity estimates; a rate gate that applies rate constraints to active, reactive, and frequency commands and is linked to the phase angle change rate and voltage transition limit; and a scheduling unit that performs compatibility discrimination based on priority mutual exclusion rules and synchronously injects consistent command increments into the droop loop within the effective window.

[0067] Specifically, first, the controller receives human-machine instructions from the dispatch side or locally, sequentially entering the safety domain projector, the rate gatekeeper, the compatibility discrimination and scheduling unit. The safety domain projector constructs the feasible region according to the energy storage state of charge, short-circuit capacity estimate value and active and reactive power capability boundary, and performs convex set projection on external active, reactive and frequency instructions to obtain an instruction vector located in the feasible region; the rate gatekeeper implements dual-domain constraints on active power change rate and frequency change rate, and links with phase angle change rate and voltage transition limit; the compatibility discrimination solves consistent solutions for active, reactive, voltage and frequency instructions according to priority exclusion rules; the scheduling unit issues consistent instruction increments in the effective window and injects them into the droop loop, and the instructions that do not pass are put into the pending queue.

[0068] Further, the feasible region is described by a convex set, and the dynamic boundary is obtained by associating the active and reactive power capability curve, the frequency offset permission boundary and the short-circuit capacity estimate value, and the safety domain projector uses weighted distance measurement to press the out-of-bound instructions back into the boundary; the dual-domain rate constraint simultaneously constrains the active power change rate and the frequency change rate, and uses the phase angle change rate to gate the integral on-off of the frequency channel, thereby limiting the "quantity fast change" and "phase advance" dual speed; the priority exclusion rule is used to handle the conflict of multiple types of instructions arriving at the same time, for example, when the frequency and voltage are given to change at the same time, the frequency consistency is given priority, and the voltage change is jointly constrained by the phase angle change rate and the voltage transition limit; the effective window is aligned with the control period to ensure that the instruction increments injected into the droop loop are time consistent among the loops.

[0069] For example, in a typical example, the energy storage converter rated power is 50 megawatts, and the grid point rated frequency is 50 hertz. The capability boundary defines the active upper and lower limits according to ±100% of the rated power, and the reactive upper limit is given according to the parameters of the inverter and transformer; the frequency permission offset is set to ±0.2 hertz. The short-circuit capacity estimate value is divided into low, medium and high segments: the low segment limits the active output to 60% of the rated value, the medium segment limits to 80%, and the high segment allows to 100%.

[0070] When the external instruction requires the active power to be raised from 30 megawatts to 45 megawatts within 1 second, the safety domain projector first determines the feasible upper limit according to the current short-circuit capacity estimate value, and if it is in the medium segment, the target active power is projected to 40 megawatts; the rate gatekeeper sets the upper limit of the active power change rate to 10% of the rated power per second, i.e. at most 5 megawatts per second, and simultaneously sets the upper limit of the frequency change rate to 0.5 hertz per second and links the upper limit of the phase angle change rate per second to 20 degrees; therefore, only an increase from 30 megawatts to 35 megawatts is allowed in the first effective window, and the corresponding frequency given increment and voltage given constraint are given.

[0071] If the frequency is set to 50.05 Hz and the voltage is increased by 2% at the same time, the priority exclusion rule is to meet the frequency first, and the voltage change is limited to no more than 0.5% per cycle by the voltage transition limit under the condition of keeping the phase angle change rate within the upper limit. The scheduling unit takes the controller unified time base 5 milliseconds as the effective window, synchronously injects the active, reactive and frequency command increments after projection and speed limit into the droop loop, and the voltage increment that is not adopted enters the pending queue and is gradually released according to the remaining margin in the subsequent window.

[0072] When the frequency change rate exceeds 0.5 Hz per second or the phase angle change rate approaches the upper limit, the rate limiter automatically reduces the integral step of the frequency channel and temporarily tightens the active change rate upper limit to 5% of the rated power per second; if the short-circuit capacity estimate value decreases from the middle section to the low section, the security domain projector immediately reconstructs the feasible region and performs secondary projection on the in-transit command increments, and the scheduling unit recovers the excess part to the queue and marks it for reduced execution. Under the above mechanism, external continuous commands are decomposed into a series of limited increments and gradually absorbed by the droop loop, and the voltage inner loop and the current inner loop seamlessly follow under the same time base.

[0073] The embodiment realizes the transformation of external multi-source commands into executable consistent command increments under different short-circuit capacities and operating states through the security domain constraint of convex set projection, the dual-domain rate limiter linked with phase angle change rate and voltage transition limit, and the synchronous injection based on priority exclusion rule and effective window, avoiding the loop impact caused by boundary crossing and mutation, and ensuring the timing consistency and controllability of command injection and droop loop.

[0074] In some embodiments, the grid connection or reconnection is completed in the order of frequency ramp, phase angle slow alignment and voltage amplitude gradual convergence based on the grid point reference phasor, including:

[0075] A phase angle sequence-preserving synchronization unit is constructed, taking the grid point reference phasor and voltage phasor reference as input, and sequentially executing a frequency ramp generator, a phase angle slow aligner and an amplitude gradual converger in series;

[0076] The frequency ramp generator outputs a monotonic ramp under the constraints of short-circuit capacity estimate and energy storage state of charge, the phase angle slow aligner implements monotonic phase angle increment and prohibits phase angle reversal under the phase angle change rate and alignment window gating, and the amplitude gradual converger implements segmented gradual synthesis on the positive sequence channel and applies gating attenuation on the negative sequence and zero sequence channels; the synchronization process does not enable the phase-locked loop, and the grid connection permission command is issued when the alignment window, frequency deviation and negative sequence amplitude threshold are met simultaneously.

[0077] Specifically, first, the controller receives the grid-connected point reference phasor and the voltage phasor reference, and then starts the phase angle sequence preservation synchronization unit, and sequentially executes the frequency ramp generator, the phase angle slow alignment device, and the amplitude gradual synthesizer. The frequency ramp generator outputs a monotonic frequency ramp under the constraints of short-circuit capacity estimation and energy storage state of charge, and limits the phase angle change rate; when the frequency deviation enters the alignment window, the phase angle slow alignment device approaches the reference phase with a monotonic phase angle increment and prohibits reverse phase angle; then, the amplitude gradual synthesizer implements segmented gradual synthesis on the positive sequence channel, while applying gate attenuation to negative sequence and zero sequence components. The synchronization process does not enable the phase-locked loop, and the grid connection permission instruction is issued when the alignment window, frequency deviation, and negative sequence amplitude threshold value are simultaneously satisfied and a preset dwell time is maintained.

[0078] Further, the phase angle sequence preservation means that the phase angle increment remains monotonic and in the same direction, avoiding back-and-forth swings that can cause oscillation; the alignment window uses a frequency and phase angle double window, and the phase angle alignment stage is only allowed to take effect after the frequency enters the narrow window; the segmented gradual synthesis of amplitude gradual synthesis uses different slopes in different amplitude intervals to reduce the parallel error at high amplitudes; the negative sequence gate is sensitive to imbalance, and when the negative sequence amplitude exceeds the threshold value, the amplitude gradual synthesis is inhibited and returns to the phase angle alignment stage; the dwell time is used to prevent false judgments caused by temporary satisfaction of conditions.

[0079] For example, in a typical example, the rated frequency of the grid-connected point is 50 Hz, and the voltage level is 10 kV. The short-circuit capacity estimation value is divided into low, medium, and high segments: the low segment uses a frequency ramp of 0.1 Hz per second and a phase angle change rate limit of 10 degrees per second; the medium segment uses a frequency ramp of 0.2 Hz per second and a phase angle change rate limit of 15 degrees per second; the high segment uses a frequency ramp of 0.3 Hz per second and a phase angle change rate limit of 20 degrees per second. When the energy storage state of charge is below 30%, each ramp is reduced by 20%. The frequency alignment window is set to ±0.05 Hz, the phase angle alignment window is set to ±3 degrees, the negative sequence amplitude threshold is set to 5% of the positive sequence amplitude, and the dwell time is set to 200 milliseconds.

[0080] Frequency ramp stage: when the deviation between the isolated grid output frequency and the reference frequency of the grid-connected point is 0.4 Hz and the short-circuit capacity estimation value is in the medium segment, the frequency ramp generator increases the frequency at a rate of 0.2 Hz per second while hard-constraining the phase angle change rate to no more than 15 degrees per second; if the energy storage state of charge is 25%, the ramp is reduced to 0.16 Hz per second. When the frequency error enters ±0.05 Hz, it automatically switches to the phase angle slow alignment stage.

[0081] Phase angle buffer alignment phase: Calculate the current phase angle difference. If the phase angle difference is -12 degrees, the phase angle buffer aligner approximates the reference phase in a monotonic positive direction with a step size constrained by the upper limit of phase angle change rate and the phase angle alignment window. If the frequency transient fluctuation of the grid connection point is detected during the process and the phase angle difference swings back from -4 degrees to -6 degrees, the buffer aligner only reduces the step size and does not allow the phase angle to reverse, maintaining the phase angle order. If the negative sequence amplitude is greater than the 5% threshold, the phase angle stepping is suspended and the negative sequence gating timing is triggered. After the timing ends and the negative sequence falls back, the stepping is resumed.

[0082] Amplitude gradual convergence phase: When the phase angle difference enters ±3 degrees and stays for 200 milliseconds, the amplitude gradual convergence unit starts. The positive sequence channel amplitude gradually converges in two stages: when the difference with the grid point positive sequence amplitude is within 5%, a slope of 0.5% per cycle is used, and when the difference is less than 2%, a slope of 0.2% per cycle is used until they are equal. The negative sequence and zero sequence channels are simultaneously attenuated in a preset exponential manner to below the target threshold. If a frequency deviation exceeding ±0.05 Hz or a negative sequence amplitude exceeding the threshold is detected during the gradual convergence process, the amplitude gradual convergence is immediately frozen and the phase angle buffer alignment phase is reverted to until the conditions are restored.

[0083] Grid connection permission and execution: When the frequency deviation, phase angle difference, and negative sequence amplitude continuously stay within their respective thresholds for no less than 200 milliseconds, the controller issues a grid connection permission instruction, and inserts an effective window between permission and execution to ensure time alignment with the voltage inner loop, current inner loop, and grid connection switch control interface. After completing grid connection, the phase angle order preservation synchronization unit exits and enters the grid-connected running state.

[0084] This embodiment achieves the sequential alignment of the frequency, phase angle, and amplitude of the grid point reference phasor without enabling the phase-locked loop by segmenting the frequency slope, preserving the order of the phase angle buffer alignment, and gradually converging the amplitude, and using negative sequence gating and residence criteria as consistency conditions. This reduces the parallel error and transient impact, and improves the synchronization reliability under weak grid conditions.

[0085] In some embodiments, the upper limits of positive sequence, negative sequence, and zero sequence fault currents and the timing templates are set in the symmetrical component domain, and a unified priority is established with the current limiting and DC side protection to synthesize the limited fault current, including:

[0086] A sequence component fault current synthesis unit is set, which determines the upper limits of positive sequence, negative sequence, and zero sequence currents and applies gating weights to negative sequence and zero sequence according to short-circuit capacity estimates and DC side voltage states by a limit mapper;

[0087] Each sequence component reference is generated by a timing generator according to the templates of rise, maintenance, and retreat, and the frequency change rate and phase angle change rate are used as thresholds;

[0088] The synthesized current reference is outputted by the priority resolver in the order of DC side protection first, bridge arm current limiting second, and sequence component upper limit last, and is injected into the current inner loop. When the fault exits, the recovery is sequenced by back-off and is consistent with the boundary of the voltage inner loop.

[0089] Specifically, the controller sets a sequence component fault current synthesis unit, which includes a limit value mapper, a timing generator, and a priority resolver. The limit value mapper takes the short-circuit capacity estimation value and the DC side voltage state as input, and outputs the positive sequence, negative sequence, and zero sequence current upper limit, and adds a gating weight to the negative sequence and zero sequence; the timing generator generates a reference trajectory for each sequence component according to a three-section template of rising, maintaining, and back-off, and takes the frequency change rate and the phase angle change rate as the effective threshold; the priority resolver resolves the synthesized current reference in the order of DC side protection first, bridge arm current limiting second, and sequence component upper limit last, and injects it into the current inner loop. When the fault exits, the recovery is sequenced by back-off and is consistent with the boundary of the voltage inner loop.

[0090] Further, the limit value mapper binds the positive sequence upper limit with the short-circuit capacity estimation value, binds the negative sequence and zero sequence upper limits with the DC side voltage deviation and thermal margin, and adjusts the negative sequence and zero sequence reference proportion downward when the imbalance is severe through the gating weight; the timing generator describes the reference evolution of the fault process with a three-section template, the rising section limits the climbing speed, the maintaining section limits the holding time, and the back-off section limits the decay slope; the priority resolver processes the energy side, device side, and sequence component side constraints in a unified order to avoid conflicts between multiple source current limiting, and performs consistency constraints with the same boundary quantity as the voltage inner loop.

[0091] For example, in a typical example, the energy storage converter rated power is 50 megawatts, and the grid point rated voltage is 10 kilovolts. The short-circuit capacity estimation value is divided into low, medium, and high three sections: the positive sequence current upper limit is set to 1.0 per unit of rated current in the low section, 1.2 per unit in the medium section, and 1.5 per unit in the high section with a maintaining time limit of no more than 200 milliseconds; the negative sequence current upper limit is set to 0.2, 0.3, and 0.4 per unit, respectively, and the zero sequence current upper limit is set to 0.05, 0.1, and 0.1 per unit, respectively. The upper and lower threshold values of the DC side voltage are set to 1.1 and 0.9 of the bus rated value, respectively. When the bus voltage exceeds the boundary or the ripple exceeds the threshold, the limit value mapper immediately falls back to 0.8 per unit of the positive sequence upper limit and reduces the negative sequence and zero sequence gating weight to zero.

[0092] The time sequence generator sets the rise time of the positive sequence reference to 20 ms, the maintenance time to 150 ms, and the retreat time to 300 ms, and sets the negative sequence and zero sequence to slower rise and shorter maintenance time to limit the thermal burden; the frequency change rate and the phase angle change rate are set as thresholds, which are 0.7 Hz / s and 20 degrees / s respectively, and if the thresholds are exceeded, the rise section is frozen and the retreat section is extended. The priority decision maker first checks the DC side protection trigger in any cycle, then checks whether the bridge arm current reaches the hard limit, and then decides the remaining channel reference according to the sequence component upper limit, and finally injects the synthesized current reference into the current inner loop, and performs consistency constraint together with the voltage given boundary of the voltage inner loop.

[0093] In the single-phase ground fault example, the negative sequence amplitude rises and the short-circuit capacity estimation value is in the middle section. The system first increases the positive sequence current reference to 1.2 per unit within 20 ms in the rise section, while limiting the negative sequence reference to below 0.3 per unit and the zero sequence reference to below 0.1 per unit according to the gating weight; if the DC bus voltage rises to the upper limit during the process, the priority decision maker immediately lowers the positive sequence reference to 0.8 per unit according to the DC side protection priority and freezes the negative sequence and zero sequence outputs, and enters the maintenance section to maintain the decision value after the bus is restored; when the fault is cleared, the retreat section is entered, and the synthesized reference is decayed to the rated operating point within 300 ms according to the preset slope, and the temporary constraints are released synchronously with the phase angle and amplitude boundaries of the voltage inner loop.

[0094] The embodiment completes the limited synthesis of the positive sequence, negative sequence and zero sequence fault currents by modeling the sequence component limit value, the DC side protection and the bridge arm current limit into a unified priority sequence, and coordinating the constraints of the three-section template and the threshold quantity; during the fault entering, maintaining and exiting, the current reference and the voltage inner loop boundary remain consistent and smoothly recover according to the retreat sequence, which is beneficial to realizing controllable fault response and orderly recovery in unbalanced and weak grid scenarios.

[0095] In some embodiments, the switching between self-forming network, grid-connected operation and protection current limiting state is realized in an event-triggered manner, and the voltage phasor continuity, the limited phase angle and power change rate, and the smooth migration of impedance template are maintained during the switching process, including:

[0096] setting a state machine controller, a switching invariant constrainter and a template migrator;

[0097] determining the switching condition by the state machine controller according to the frequency change rate, the short-circuit capacity estimation value, the DC bus voltage and the negative sequence amplitude, and issuing the switching instruction within the synchronization effective window;

[0098] applying the upper limit to the voltage phasor, the phase angle change rate and the active power change rate by the switching invariant constrainter, and maintaining the continuity of the grid-connected handshake step and the current limiting protection step;

[0099] The generalized impedance shaping impedance template is executed by the template migrator, and the medium and high frequency band parameters are frozen in the grid-connected handshake and current limiting protection state, and only the low frequency band parameter is allowed to be updated.

[0100] Specifically, first, a state machine controller is established. The state set includes three basic states of self-forming network, grid-connected operation and current limiting protection, and transition sub-states of splitting and grid-connected handshake are reserved. The state machine periodically reads the trigger quantity, including frequency change rate, short-circuit capacity estimation value, DC bus voltage, negative sequence amplitude and device temperature, etc., and determines the switching condition in the synchronization effective window. The effective window is aligned with the controller main loop, with a fixed step, for example, 5 milliseconds per cycle, to ensure that the switching command and the voltage inner loop, current inner loop and grid-connected switch control interface are executed at the same time base. Typical threshold settings are: the upper limit of frequency change rate is 0.5 Hz per second, the DC bus voltage permission interval is 0.9 to 1.1 of the rated value, the negative sequence amplitude threshold is 5% of the positive sequence amplitude, and the device temperature threshold is set according to the rated thermal design.

[0101] Secondly, the switching invariant constrainter is set. The switching invariant refers to the constraint quantity that must be satisfied simultaneously during switching, including voltage phasor continuity, phase angle change rate and active change rate limiting, and continuity of grid-connected handshake and current limiting protection steps. The upper limit of phase angle change rate is 20 degrees per second, and the upper limit of active change rate is 10% of rated power per second; when entering current limiting protection or negative sequence over-limit, the above upper limit is temporarily tightened to 10 degrees per second and 5% of rated power per second. The constrainter adopts a phase angle integral continuity maintenance strategy for voltage phasor, that is, the phase angle integral initial value is locked at the switching edge and is pushed forward with a limited slope to avoid phase angle reversal and sudden jump; for grid-connected handshake and current limiting protection, the constrainter requires to be executed in a predetermined order, and step skipping is not allowed, for example, only when the frequency and phase angle enter the window and the residence time meets the requirements, can the amplitude be gradually merged.

[0102] Thirdly, the template migrator is set. The generalized impedance shaping impedance template is maintained in a versioned manner, segmented by low frequency, subsynchronous, harmonic and high frequency. Template migration uses continuous interpolation to cross old and new versions, with an interpolation time constant of one hundred to two hundred milliseconds. In the grid-connected handshake and current limiting protection state, the template migrator freezes the medium and high frequency band parameters, and only allows small step updates of the low frequency band virtual damping; in the grid-connected operation state, it allows full frequency band to be updated smoothly according to priority. Template switching is triggered by the short-circuit capacity estimation value and resonance characteristics, when the short-circuit capacity estimation value decreases or the resonance index rises, the index combination with stronger suppression is preferred.

[0103] For example, example one: switching from self-networking to grid-connected operation. When it is detected that the grid-connected permission condition is met, i.e. the frequency deviation enters the ±0.05 Hz window, the phase angle difference enters the ±3 degree window, and the negative sequence amplitude is lower than 5% and stays for 200 ms, the state machine issues a switching instruction from self-networking to grid-connected handshake in the next effective window. The switching invariant restrictor limits the phase angle change rate to 15 degrees per second, the active change rate to 8% of the rated power per second, and the voltage phasor to align with the reference phasor of the grid-connected point at a limited slope. The template migrator freezes the harmonic and high frequency band parameters, and only allows the low frequency band damping coefficient to be fine-tuned at a set step, and after the handshake is completed and stability is confirmed, the state machine enters grid-connected operation.

[0104] Example two: entering current limiting protection from grid-connected operation and returning again. When it is monitored in operation that the DC bus voltage exceeds the upper limit of the permission or the bridge arm current approaches the limit value, the state machine triggers to enter the current limiting protection. The switching invariant restrictor immediately tightens the upper limit of the phase angle and active change rate, and issues a current limiting reference and derating instruction to the current inner loop; the voltage phasor is continuously pushed forward to avoid phasor jumping. The template migrator keeps the low frequency band small step update and freezes the medium and high frequency band parameters to prevent introducing additional high frequency adjustment during current limiting. After the fault or overload is removed, the state machine withdraws the current limiting in a back-off sequence, gradually releases the active change rate to 10% of the rated power per second, and restores the impedance template to the grid-connected operation version within 200 ms according to an interpolation strategy.

[0105] Example three: disconnection from grid-connected operation back to self-networking. If the short-circuit capacity estimate value suddenly drops and the grid-connected point appears persistent imbalance, the state machine determines that the disconnection condition is met, issues a disconnection instruction and enters the disconnection holding sub-state. The switching invariant restrictor keeps the voltage phasor continuous at the disconnection edge and limits the phase angle change rate to 10 degrees per second to smooth the transition; the template migrator switches to the self-networking template and completes the low frequency band damping enhancement with continuous interpolation. After the grid-connected point is restored and the re-connection condition is met, it enters the grid-connected handshake again according to the sequence of example one.

[0106] The embodiment ensures that in the three states of self-networking, grid-connected operation and current limiting protection and their transition processes, the voltage phasor is continuous, the phase angle and active change rate are limited, and the generalized impedance template is smoothly migrated at a controlled pace through the cooperation of event-triggered state machine determination, switching invariant restriction and template migration; in typical disturbance and fault scenarios, the above mechanism reduces the transient impact and parameter mutation caused by switching, and realizes the consistency and recoverability of control and protection.

[0107] The following is an apparatus embodiment of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the apparatus embodiments of the present application, please refer to the method embodiments of the present application.

[0108] Figure 2 is a structural schematic diagram of a self-networking control and protection device of a grid-friendly energy storage converter provided by the embodiment of the present application. As shown inFigure 2 The grid-friendly energy storage converter self-networking control protection device is shown in the figure, comprising:

[0109] The acquisition module 201 is configured to acquire electrical quantities of the grid-connected point and the DC side, establish a short-circuit capacity estimation value and a positive and negative zero sequence model, and generate a voltage phasor reference;

[0110] The control module 202 is configured to enable parallel control of the voltage inner loop and the current inner loop without relying on a phase-locked loop, generate a frequency given value and a voltage given value according to power and frequency droop and reactive power and voltage droop, and adaptively set the droop coefficient and the inertia parameter according to the energy storage state of charge and the short-circuit capacity estimation value;

[0111] The configuration module 203 is configured to perform generalized impedance shaping in the control loop, configure virtual impedance and selective filtering according to frequency bands, and update the impedance template through online identification;

[0112] The verification module 204 is configured to perform amplitude and rate constraints and compatibility verification on external power, reactive power, voltage or frequency instructions, and inject the verified instructions into the droop loop under the constraints of power change rate and frequency change rate;

[0113] The grid connection module 205 is configured to complete grid connection or reconnection in the order of frequency ramp, phase angle buffer alignment and voltage amplitude gradual convergence based on the grid-connected point reference phasor;

[0114] The synthesis module 206 is configured to set the positive sequence, negative sequence and zero sequence fault current upper limit and the time sequence template in the symmetrical component domain, and establish a unified priority with the current limiting and DC side protection to synthesize the limited fault current;

[0115] The switching module 207 is configured to switch between self-networking, grid-connected operation and protection current limiting state in an event-triggered manner, and maintain voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process;

[0116] The output module 208 is configured to output the frequency given value, the voltage given value, the sequence component limit value and the protection state instruction to the converter power bridge drive and the grid connection switch control interface, for controlling and protecting the self-networking and grid-connected operation of the energy storage converter.

[0117] In some embodiments, Figure 2 The acquisition module 201 of the grid-friendly energy storage converter outputs positive sequence voltage and current phasors using a frequency change rate gated sliding phasor estimator; obtains positive sequence and zero sequence equivalent impedances through frequency band switchable disturbance injection and recursive online identification with a forgetting factor, and converts the short-circuit capacity estimation value accordingly; forms the voltage phasor reference under the double boundaries of phase angle integration and amplitude limiting by the positive and negative zero sequence weighted phasor generator; and performs phasor freezing and parameter self-updating when the frequency change rate or identification deviation is out of limit.

[0118] In some embodiments, Figure 2 The control module 202 of the power plant 200 constructs a droop and inertia coordinator, taking active power, reactive power, energy storage state of charge, short circuit capacity estimate, and frequency rate of change as inputs, and outputting frequency setpoint and voltage setpoint; the active droop coefficient, reactive droop coefficient, and inertia parameter are segmented and set by an energy and short circuit capacity joint mapper, with a hysteresis dead zone; the dual-domain rate constraints of power rate of change and phase angle rate of change, and the frequency rate of change-based gated integration are configured; the sequence component weighting and negative sequence gating are introduced for the reactive and voltage droop to limit the voltage setpoint components; the current reference is generated by the voltage inner loop without relying on the phase-locked loop, and is followed by the current inner loop.

[0119] In some embodiments, Figure 2 The configuration module 203 of the power plant 200 establishes an impedance template library segmented by low frequency, subsynchronous, harmonic, and high frequency bands, configures virtual resistance, virtual inductance, and admittance clipping parameters for positive sequence, negative sequence, and zero sequence respectively, and binds the switchable selective filter index; the double-channel perturbation injection and recursive online identification with forgetting factor are used to identify the equivalent impedance and resonance characteristics of each sequence component within the frequency rate threshold, and output the template update amount; the selective filter index is switched by the short circuit capacity estimate and resonance characteristics, and the impedance template is smoothly updated by template versioning and continuous interpolation; the medium and high frequency band parameters are frozen in the grid-connected handshake, weak grid escort, and current limiting protection states, only allowing the low frequency band damping parameter to be updated, and the updated impedance template is connected to the voltage inner loop and the current inner loop.

[0120] In some embodiments, Figure 2 The verification module 204 of the power plant 200 verifies and injects external active, reactive, voltage, or frequency instructions by an instruction sandbox, which includes: a safety domain projector that performs convex set projection on the feasible region of active, reactive, and frequency according to the energy storage state of charge and the short circuit capacity estimate; a rate limiter that applies rate constraints to active, reactive, and frequency, and is linked with phase angle rate of change and voltage jump limiter; and a scheduling unit that discriminates compatibility based on priority exclusion rules and synchronously injects consistent instruction increments into the droop loop within the effective window.

[0121] In some embodiments, Figure 2The grid-connected module 205 constructs a phase angle sequence-preserving synchronization unit, taking the grid point reference phasor and the voltage phasor reference as inputs, and sequentially performing by a frequency slope generator, a phase angle buffer aligner, and an amplitude gradual converger in series; wherein the frequency slope generator outputs a monotonic slope under the short-circuit capacity estimation value and the energy storage state of charge constraint, the phase angle buffer aligner implements a monotonic phase angle increment and prohibits a phase angle reversal under the phase angle change rate and the alignment window gating, and the amplitude gradual converger implements a segmented gradual synthesis on the positive sequence channel and applies a gating attenuation on the negative sequence and zero sequence channels; the synchronization process does not enable a phase-locked loop, and issues a grid-connected permission instruction when the alignment window, the frequency deviation, and the negative sequence amplitude threshold value are simultaneously satisfied.

[0122] In some embodiments, Figure 2 The synthesis module 206 sets a sequence component fault current synthesis unit, which determines the upper limit of positive sequence, negative sequence, and zero sequence currents according to the short-circuit capacity estimation value and the DC side voltage state by a limit mapper, and applies a gating weight to the negative sequence and zero sequence; generates sequence component references according to the templates of rise, maintenance, and retreat by a timing generator, and takes the frequency change rate and the phase angle change rate as thresholds; outputs a synthesized current reference by a priority decider in the order of DC side protection first, bridge arm current limiting second, and sequence component upper limit last, and injects the current into the current inner loop, and restores according to the retreat sequence when the fault exits and keeps consistent with the voltage inner loop boundary.

[0123] In some embodiments, Figure 2 The switching module 207 sets a state machine controller, a switching invariant constrainter, and a template migrator; determines the switching condition according to the frequency change rate, the short-circuit capacity estimation value, the DC bus voltage, and the negative sequence amplitude, and issues a switching instruction within the synchronization effective window by the state machine controller; applies an upper limit to the voltage phasor, the phase angle change rate, and the active change rate by the switching invariant constrainter, and maintains the continuity of the grid-connected handshake step and the current limiting protection step; performs continuous interpolation migration on the impedance template shaped by the generalized impedance by the template migrator, and freezes the medium and high frequency band parameters in the grid-connected handshake and current limiting protection states, and only allows the low frequency band parameters to be updated.

[0124] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0125] Figure 3 FIG. 3 is a structural schematic diagram of an electronic device 3 provided by an embodiment of the present application. As shown in FIG. 3, the electronic device 3 comprises a power supply 301, a DC / AC converter 302, a grid-connected module 205, a synthesis module 206, and a switching module 207. Figure 3As shown, the electronic device 3 of this embodiment includes a processor 301, a memory 302, and a computer program 303 stored in the memory 302 and executable on the processor 301. The processor 301 implements the steps in each of the above method embodiments when executing the computer program 303. Alternatively, the processor 301 implements the functions of each module / unit in each of the above apparatus embodiments when executing the computer program 303.

[0126] By way of example, the computer program 303 can be divided into one or more modules / units, which are stored in the memory 302 and executed by the processor 301 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program 303 in the electronic device 3.

[0127] The electronic device 3 can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The electronic device 3 can include but is not limited to the processor 301 and the memory 302. Those skilled in the art can understand that the electronic device 3 can include more or fewer components than those shown, or combine certain components, or different components, for example, the electronic device can also include an input / output device, a network access device, a bus, and the like. Figure 3 The electronic device 3 is merely an example and does not constitute a limitation on the electronic device 3, which can include more or fewer components than those shown, or combine certain components, or different components, for example, the electronic device can also include an input / output device, a network access device, a bus, and the like.

[0128] The processor 301 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0129] The memory 302 can be an internal storage unit of the electronic device 3, for example, a hard disk or a memory of the electronic device 3. The memory 302 can also be an external storage device of the electronic device 3, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 3. Further, the memory 302 can include both the internal storage unit and the external storage device of the electronic device 3. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 can also be used to temporarily store data that has been output or will be output.

[0130] It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit. In addition, the specific name of each functional unit and module is only for easy distinction, and does not limit the protection scope of the present application. The specific working process of the unit and module in the above system can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0131] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can refer to the relevant description of other embodiments.

[0132] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or in combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0133] In the embodiments of the present application, it should be understood that the disclosed apparatus / computer device and method can be implemented in other manners. For example, the described apparatus / computer device embodiments are merely schematic. For example, the division of the modules or units can be different, and each can include multiple sub-modules or units. Some or all of the modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0134] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0135] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of software function unit.

[0136] If the integrated module / unit is implemented in the form of software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the above-mentioned embodiment methods can be completed by computer programs instructing related hardware, and the computer programs can be stored in a computer readable storage medium. When the processor executes the computer programs, the steps of the above-mentioned various method embodiments can be implemented. The computer program can include computer program code, which can be in the form of source code, object code, executable file or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier wave signal, telecommunication signal and software distribution medium, etc.

[0137] The above examples are only used to illustrate the technical solutions of the present application, but not limit the same; although the technical solutions of the present application are described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features thereof can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A grid-friendly energy storage converter autonomous grid control protection method, characterized in that, The method comprises the following steps: Collecting electrical quantities of the grid-connected point and the DC side, establishing a short-circuit capacity estimation value and a positive and negative sequence model, and generating a voltage phasor reference; Without relying on a phase-locked loop, enabling parallel control of a voltage inner loop and a current inner loop, generating a frequency given value and a voltage given value according to power and frequency droop and reactive power and voltage droop, and adaptively adjusting droop coefficients and inertia parameters according to a state of charge of the energy storage and the short-circuit capacity estimation value; Performing generalized impedance shaping in a control loop, configuring virtual impedance and selective filtering according to frequency bands, and updating an impedance template through online identification; Performing amplitude and rate constraints and compatibility checks on external power, reactive power, voltage or frequency instructions, and injecting the instructions that pass the checks into a droop loop under power change rate and frequency change rate constraints; Completing grid connection or reconnection in the order of frequency ramp, phase angle alignment and voltage amplitude convergence based on a reference phasor of the grid-connected point; Setting positive sequence, negative sequence and zero sequence fault current upper limits and time sequence templates in a symmetrical component domain, and establishing a unified priority with current limiting and DC side protection to synthesize limited fault currents; Switching between self-networking, grid-connected operation and protection current limiting in an event-triggered manner, and maintaining voltage phasor continuity, phase angle and power change rate limitation and smooth migration of the impedance template during the switching process; Outputting the frequency given value, the voltage given value, the sequence component limit value and the protection state instruction to a converter power bridge drive and a grid-connected switch control interface for control and protection execution of self-networking and grid-connected operation of the energy storage converter.

2. The method of claim 1, wherein, The method comprises the following steps: Outputting positive sequence voltage and current phasors by using a frequency change rate gated sliding phasor estimator; Obtaining positive sequence and zero sequence equivalent impedances by frequency band switchable disturbance injection and recursive online identification with a forgetting factor, and converting the short-circuit capacity estimation value according to the equivalent impedances; Forming a voltage phasor reference under phase angle integration and amplitude limiting by a phasor generator weighted by positive and negative sequences; When the frequency change rate or the identification deviation is out of limit, performing phasor freezing and parameter self-updating.

3. The method of claim 1, wherein, The method comprises the following steps: Building a droop and inertia coordinator to output a frequency given value and a voltage given value with active power, reactive power, state of charge of the energy storage, short-circuit capacity estimation value and frequency change rate as inputs; Segmenting and adjusting active power droop coefficients, reactive power droop coefficients and inertia parameters by an energy and short-circuit capacity joint mapper and setting a hysteresis dead zone; Configuring double-domain rate constraints of power change rate and phase angle change rate and frequency change rate gated integration; Introducing sequence component weighting and negative sequence gating for reactive power and voltage droop to limit the composition of the voltage given value; Generating a current reference by the voltage inner loop and following execution by the current inner loop without relying on a phase-locked loop.

4. The method of claim 1, wherein, The method comprises the following steps: An impedance template library is established by segmenting into low frequency, subsynchronous, harmonic and high frequency bands, virtual resistance, virtual inductance and admittance clipping parameters are configured for positive, negative and zero sequences respectively, and a switchable selective filter index is bound; A double-channel perturbation injection and recursive online identification with a forgetting factor are adopted to identify the equivalent impedance and resonance characteristics of each sequence component within the frequency variation rate threshold, and the template update amount is output; The short-circuit capacity estimation value and the resonance characteristics are used to drive the selective filter index switching, and the impedance template is smoothly updated by template versioning and continuous interpolation; In the grid-connected handshake, weak network escort and current limiting protection states, the medium and high frequency band parameters are frozen, only the low frequency band damping parameter is allowed to be updated, and the updated impedance template is connected to the voltage inner loop and the current inner loop.

5. The method of claim 1, wherein, The external power, reactive power, voltage or frequency instructions are subjected to amplitude and rate constraints and compatibility verification, and the verified instructions are injected into the droop loop under the constraints of power variation rate and frequency variation rate, including: The verification and injection of external active, reactive, voltage or frequency instructions are realized by an instruction sandbox, which includes a safety domain projector that performs convex set projection on the feasible region of active, reactive and frequency according to the energy storage state of charge and the short-circuit capacity estimation value; a rate gate that applies rate constraints to active, reactive and frequency and is linked with phase angle variation rate and voltage jump amplitude limiting; and a scheduling unit that performs compatibility discrimination based on priority exclusion rules and synchronously injects consistent instruction increments into the droop loop within the effective window.

6. The method of claim 1, wherein, The grid connection or reconnection is completed in the order of frequency ramp, phase angle slow alignment and voltage amplitude gradual convergence based on the reference phasor at the grid connection point, including: A phase angle sequence-preserving synchronization unit is constructed, taking the reference phasor at the grid connection point and the voltage phasor reference as input, and sequentially executing a frequency ramp generator, a phase angle slow aligner and an amplitude gradual converger in series; The frequency ramp generator outputs a monotonic ramp under the constraints of short-circuit capacity estimation value and energy storage state of charge, the phase angle slow aligner implements a monotonic phase angle increment and prohibits phase angle reversal under the constraints of phase angle variation rate and alignment window, and the amplitude gradual converger implements segmented gradual synthesis for the positive sequence channel and applies gate attenuation for the negative and zero sequence channels; the whole process is synchronized without enabling the phase-locked loop, and the grid connection permission instruction is issued when the alignment window, frequency deviation and negative sequence amplitude threshold are simultaneously satisfied.

7. The method of claim 1, wherein, The upper limits of positive, negative and zero sequence fault currents are set in the symmetrical component domain, and a unified priority is established with current limiting and DC side protection to synthesize the limited fault current, including: A sequence component fault current synthesis unit is set up, which determines the upper limits of positive, negative and zero sequence currents and applies gate weights to negative and zero sequences according to the short-circuit capacity estimation value and the DC side voltage state by a limit value mapper; Each sequence component reference is generated by a time sequence generator according to the templates of rising, maintaining and retreating, and the frequency variation rate and phase angle variation rate are used as thresholds; The synthesized current reference is output by a priority arbiter in the order of DC side protection priority, bridge arm current limiting second, sequence component upper limit last, and injected into the current inner loop, and restored in the order of retreating sequencing when the fault exits and consistent with the voltage inner loop boundary.

8. The method of claim 1, wherein, The event-triggered switching between self-networking, grid-connected operation and protection current limiting state maintains voltage phasor continuity, limited phase angle and power change rate and smooth migration of impedance template during the switching process, comprising: setting a state machine controller, a switching invariant constrainter and a template migrator; determining the switching condition by the state machine controller according to the frequency change rate, short-circuit capacity estimate, DC bus voltage and negative sequence amplitude, and issuing the switching instruction within the synchronization effective window; applying an upper limit to the voltage phasor, phase angle change rate and active power change rate by the switching invariant constrainter, and maintaining the continuity of the grid-connected handshake step and the current limiting protection step; performing continuous interpolation migration on the impedance template shaped by the generalized impedance by the template migrator, and freezing the medium and high frequency band parameters in the grid-connected handshake and current limiting protection state, and only allowing the low frequency band parameters to be updated.

9. A grid-friendly energy storage converter autonomous grid control protection device, characterized in that, comprising: a collection module for collecting electrical quantities at the grid-connected point and the DC side, establishing a short-circuit capacity estimate and a positive and negative sequence model, and generating a voltage phasor reference; a control module for enabling parallel control of the voltage inner loop and the current inner loop without relying on the phase-locked loop, generating frequency and voltage given according to power and frequency droop and reactive power and voltage droop, and adaptively adjusting the droop coefficient and inertia parameter according to the energy storage state of charge and the short-circuit capacity estimate; a configuration module for performing generalized impedance shaping in the control loop, configuring virtual impedance and selective filtering according to frequency band, and updating the impedance template through online identification; a verification module for amplitude and rate constraint and compatibility verification of external power, reactive power, voltage or frequency instructions, and injecting the verified instructions into the droop loop under the constraints of power change rate and frequency change rate; a grid-connected module for completing grid connection or reconnection in the order of frequency ramp, phase angle alignment and voltage amplitude convergence based on the reference phasor of the grid-connected point; a synthesis module for setting the upper limit of positive sequence, negative sequence and zero sequence fault current and the timing template in the symmetrical component domain, and establishing a unified priority with current limiting and DC side protection to synthesize the limited fault current; a switching module for event-triggered switching between self-networking, grid-connected operation and protection current limiting state, and maintaining voltage phasor continuity, limited phase angle and power change rate and smooth migration of impedance template during the switching process; an output module for outputting the frequency given, voltage given, sequence component limit and protection state instruction to the converter power bridge drive and grid-connected switch control interface for controlling and protecting the self-networking and grid-connected operation of the energy storage converter.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 9. The computer program is executed by the processor to realize the steps of the method of any one of claims 1 to 8. The computer program is executed by the processor to realize the steps of the method of any one of claims 1 to 8.

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