Source-downward MOS device based on planar MOS process and preparation method thereof

Abstract

The invention discloses a downward-source MOS device based on a plane MOS process and a preparation method, and relates to the technical field of semiconductor devices, the downward-source MOS device comprises a semiconductor substrate, an active region and a gate region, the active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region; a drain electrode and a source electrode are arranged in the active region, the drain electrode on one side is electrically connected to the front surface of the chip through a forward metal electrode, and the forward metal electrode is located in the gate region; the source electrode on the other side is communicated with the semiconductor substrate through the electrode connection area and forms good ohmic contact, and a substrate metal electrode is arranged at the bottom of the semiconductor substrate. According to the invention, the layout is reasonable, the structure is compact, the process cost is low, compared with a Diodes heterostructure, two mask steps of a main groove and a field plate groove are reduced, and stress and defects caused by groove filling are avoided; the chip is simple in structure and high in integration level, compared with an Infineon packaging-level source bottom, source interconnection is directly achieved in the chip, the multi-device stacking design is supported, and the occupied space of a bonding pad and a lead channel is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a source-down MOS device based on a planar MOS process and a preparation method thereof. BACKGROUND

[0002] MOS field effect transistor (MOSFET) is one of the most important power semiconductor devices in modern electronic devices, and plays a key role in power management, motor control, inverter and other applications. With the development of electronic devices towards miniaturization, high efficiency and high power density, higher requirements are put forward for the performance of MOSFET, especially in terms of on-resistance, switching speed and thermal management. The source-down structure as an innovative power MOSFET packaging and structure technology has attracted widespread attention in recent years.

[0003] The patent of Diodes Incorporated (such as US20210151596A) proposes a source-down configured field effect transistor, which realizes the source-down structure by setting a trench in the semiconductor chip and embedding conductive gate material and conductive field plate in the trench, but this scheme needs deep trench etching and filling, which requires higher equipment and process requirements. At the same time, a vertical field plate structure needs to be formed, which increases the manufacturing difficulty. The trench and field plate structure will increase the parasitic capacitance, which may affect the switching speed and frequency performance of the transistor. It is not compatible with the existing planar MOS process, and a new process flow and equipment need to be developed.

[0004] The source-down device of Infineon (such as OptiMOS TM series) adopts flip-chip technology to directly connect the source pad to the packaging substrate, which simplifies the chip structure, but is limited by the packaging parasitic parameters (such as lead inductance ~ 1.2nH). Its quality factor

FoM=Rds(on)·Qg

[0005] Therefore, how to provide a source-down MOS device and preparation method based on a planar MOS process, which adopts an embedded source interconnection structure to realize the source-down layout, and is compatible with the traditional planar MOS process, effectively reducing the packaging cost, has become a technical problem to be solved by the technical personnel in the field. SUMMARY

[0006] The purpose of the present application is to provide a source-down MOS device based on a planar MOS process, which solves the problems of deep trench etching, filling and other high difficulty and high cost required by the prior art.

[0007] To solve the above technical problems, the present application adopts the following technical solutions:

[0008] The present application is a source-down MOS device based on a planar MOS process, comprising a semiconductor substrate, an active region and a gate region, the active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region.

[0009] The active region is provided with a drain and a source, the drain on the upper side is electrically connected to the front surface of the chip through a forward metal electrode, and the forward metal electrode is located in the gate region; the source on the other side is in communication with the semiconductor substrate through an electrode connecting area and forms a good ohmic contact, and the electrode connecting area is located in a reverse type layer provided on the top of the semiconductor substrate; the bottom of the semiconductor substrate is provided with a substrate metal electrode for lead-out.

[0010] Preferably, the active region comprises the entire region composed of a reverse type layer and a drift layer, the electrode connecting area is epitaxially formed on the drift layer, and the reverse type layer is an isolation layer formed by epitaxy, diffusion or ion implantation.

[0011] Preferably, the semiconductor substrate adopts a single crystal semiconductor material, which is a heavily doped substrate layer, the reverse type layer is a highly doped isolation layer, and the drift layer is a lowly doped epitaxial layer.

[0012] Preferably, a plurality of well regions are provided on the drift layer, the source is located in the well region and corresponds to the position of the electrode connecting area below in one-to-one correspondence; the drain is located on the top of the drift layer and between any two adjacent sources.

[0013] Preferably, the gate region comprises a gate oxide layer, a gate and a gate insulating layer arranged in sequence, the gate oxide layer is located above the drift layer, the gate is located above the gate oxide layer and leaves a plurality of gate recesses corresponding to the drain and the source, the gate insulating layer is filled and covers the gate, the gate insulating layer is connected to completely close the gate recess corresponding to the source, the forward metal electrode is provided in the gate recess corresponding to the drain, and a second insulating layer is provided at the forward metal electrode.

[0014] Preferably, the material of the gate oxide layer is Thermal SiO2, and the thickness is designed to be 24 nm; the gate adopts polycrystalline silicon or a metal gate, and the metal gate is specifically Pt, Pd, NiSi or CoSi, and the thickness is designed to be 450 nm; the material of the gate insulating layer is SiO2 or SiOxNy, and the thickness is designed to be 1200 nm.

[0015] A method for manufacturing a source-down MOS device based on a planar MOS process, comprising the following steps:

[0016] Step one, manufacturing of the substrate, first, select P-type or N-type silicon wafer as the substrate material according to the manufacturing type, second, after the silicon wafer is selected, form a heavily doped substrate layer through doping process;

[0017] Step two, form a reverse type layer through epitaxy, diffusion or ion implantation, the reverse type layer is located above the semiconductor substrate, for realizing isolation of the semiconductor substrate and the drift layer;

[0018] Step three, form an electrode connection area through ion implantation, implant corresponding ions according to the product type to form multiple independent heavily doped electrode areas, which become the current channel for the source to communicate with the substrate;

[0019] Step four, form a drift layer through epitaxy, which is located between the source and the drain, for bearing high voltage;

[0020] Step five, form a well area through ion implantation or diffusion, which is located above the drift layer and corresponds to the electrode connection area one by one, providing a basis for forming the source area;

[0021] Step six, form a drain area through ion implantation, which is located at the top of the drift layer and between two adjacent well areas, form an independent highly doped area after ion implantation, for communicating with the positive metal electrode above;

[0022] Step seven, form a source area through ion implantation, which is located in the middle of the well area, form an independent highly doped area after ion implantation;

[0023] Step eight, form a gate oxide layer, which is an insulating medium between the gate and the active area, for preventing leakage;

[0024] Step nine, manufacture the gate, the gate is located above the gate oxide layer and corresponds to the drain and the source in the reserved multiple gate grooves;

[0025] Step ten, protect the gate through the first insulating layer;

[0026] Step eleven, form a positive metal electrode through the first layer of metallization;

[0027] Step twelve, protect the positive metal electrode through the second insulating layer;

[0028] Step thirteen, thin the back of the substrate;

[0029] Step fourteen, form a substrate metal electrode through back metallization.

[0030] Preferably, in step four, the drift layer is formed through a planar MOS process.

[0031] Preferably, in step thirteen, the back side of the substrate is thinned, and the thickness of the thinned liner is 325μm to 425μm.

[0032] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0033] This invention discloses a source-down MOS device based on planar MOS technology, comprising a semiconductor substrate, an active region and a gate region sequentially disposed on the upper part of the semiconductor substrate, the active region including an inversion layer and a drift layer; specifically, a drain and a source are disposed on the drift layer, the drain located on one side is electrically connected to the front side of the chip through a forward metal electrode, the forward metal electrode being located within the gate region; the source located on the other side is connected to the semiconductor substrate through an electrode connection region, and a substrate metal electrode for lead-out is disposed at the bottom of the semiconductor substrate.

[0034] 1) Embedded source interconnect: Unlike traditional LDMOS devices, the source is located at the bottom of the device. Through specific doping and structural design, the electrode connection region on the inversion layer forms a current channel, which enables the source to form a good ohmic contact with the substrate and reduces the on-resistance. The drain is located at the top of the device and forms a certain distance from the source to achieve the device's withstand voltage function.

[0035] 2) The gate region is located between the source region and the drain region and is isolated from the semiconductor substrate by the gate oxide layer. It is used to control the conduction and cutoff of the device.

[0036] 3) Compatible with traditional planar MOS processes: Utilizing existing MOS processes, such as drift layers, gate trenches, and doping steps, requires additional ion implantation and back-side metallization processes. This eliminates the need for complex heterostructures, reducing manufacturing costs.

[0037] 4) Double-sided heat dissipation optimization: The source electrode on the back side is in direct contact with the metal electrode on the substrate, which, combined with the drain electrode heat dissipation path on the front side, forms a double-sided heat dissipation structure, which significantly improves thermal management efficiency.

[0038] In summary, this invention has a reasonable layout, compact structure, and low process cost. Compared with the heterogeneous structure of Diodes, it reduces the masking steps of the main trench and field plate trench, avoiding stress and defects caused by trench filling. It has high integration. Compared with Infineon's package-level source bottom placement, the source interconnect is directly realized inside the chip, supporting multi-device stacking design and saving space occupied by pads and lead channels. Attached Figure Description

[0039] The present invention will be further described below with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of the source-down MOS device based on planar MOS technology according to the present invention;

[0041] Figure 2 This is a diagram showing the structural changes from step one to step three of the present invention;

[0042] Figure 3 This is a diagram showing the structural changes in steps four through seven of the present invention;

[0043] Figure 4 This is a diagram showing the structural changes in steps eight to ten of the present invention;

[0044] Figure 5 This is a diagram showing the structural changes in steps eleven to fourteen of the present invention;

[0045] Figure 6 This is a flowchart of the method for fabricating the source-down MOS device of the present invention.

[0046] Explanation of reference numerals in the attached figures: 1. Semiconductor substrate; 2. Inversion layer; 3. Electrode connection region; 4. Drift layer; 5. Well region; 6. Drain; 7. Source; 8. Gate oxide layer; 9. Gate; 10. Gate insulating layer; 11. Forward metal electrode; 12. Second insulating layer; 13. Substrate metal electrode. Detailed Implementation

[0047] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] like Figures 1-5 As shown, a source-down MOS device based on planar MOS technology includes a semiconductor substrate 1, an active region and a gate region, wherein the active region is formed on the surface of the semiconductor substrate and the gate region is located above the active region;

[0049] The active region is provided with a drain 6 and a source 7. The drain 6 located on the upper side is electrically connected to the front side of the chip through a positive metal electrode 11, which is located in the gate region. The source 7 located on the other side is connected to the semiconductor substrate 1 through an electrode connection region 3 and forms a good ohmic contact. The electrode connection region 3 is located in the inversion layer 2 provided on the top of the semiconductor substrate 1.

[0050] The bottom of the semiconductor substrate 1 is provided with a substrate metal electrode 13 for lead-out.

[0051] Specifically, the active region includes the entire region composed of the inversion layer 2 and the drift layer 4, the electrode connection region 3 is epitaxially formed to form the drift layer 4, and the inversion layer 2 is an isolation layer formed by epitaxy, diffusion or ion implantation.

[0052] The semiconductor substrate 1 is made of single-crystal semiconductor material and is a heavily doped substrate layer. The inversion layer 2 is a highly doped isolation layer, and the drift layer 4 is a lightly doped epitaxial layer.

[0053] Specifically, the drift layer 4 is provided with multiple well regions 5, the source electrode 7 is located in the well region 5 and corresponds one-to-one with the position of the electrode connection region 3 below; the drain electrode 6 is located on the top of the drift layer 4 and is located between any two adjacent source electrodes 7.

[0054] Specifically, the gate region includes a gate oxide layer 8, a gate 9, and a gate insulating layer 10 arranged sequentially. The gate oxide layer 8 is located above the drift layer 4. The gate 9 is located above the gate oxide layer 8, and multiple gate grooves are reserved therefor corresponding to the drain 6 and the source 7. The gate insulating layer 10 fills and covers the gate 9. After the gate insulating layer 10 is connected, the gate groove corresponding to the source 7 is completely sealed. The positive metal electrode 11 is disposed in the gate groove corresponding to the drain 6. A second insulating layer 12 is disposed at the positive metal electrode 11. The second insulating layer 12 is located above the gate insulating layer 10. The main function of the second insulating layer 12 is to achieve electrical isolation and prevent short circuit between the drain and adjacent conductors (such as the source, gate, or substrate). It can also play an environmental protection role, blocking corrosion or leakage caused by moisture, pollutants, or ion migration. The thickness and number of layers of the positive metal electrode 11 and the second insulating layer 12 can be further set according to actual needs.

[0055] Specifically, the gate oxide layer 8 is made of thermal SiO2 with a thickness of 24 nm; the gate 9 is made of polysilicon or a metal gate, specifically Pt, Pd, NiSi, or CoSi, with a thickness of 450 nm; the gate insulating layer 10 is made of SiO2 or SiO2. x N y The thickness is designed to be 1200nm.

[0056] like Figure 6 As shown, a method for fabricating a source-down MOS device based on planar MOS technology as described above specifically includes the following steps:

[0057] Step 1: Substrate fabrication. A P-type or N-type silicon wafer is selected to fabricate the semiconductor substrate 1. Typically, a P-type substrate is used to fabricate NMOS, and an N-type substrate is used to fabricate PMOS. Simultaneously, after selecting the silicon wafer, a heavily doped substrate layer is formed through doping processes (CZ method, epitaxy, ion implantation, or diffusion), with a doping concentration reaching 10⁻⁶. 19 ~10 20 cm -3The substrate layer serves as a support for the inversion layer 2, and its main functions are to reduce resistance, support epitaxial growth, and optimize device performance.

[0058] Step 2: Epitaxial growth, diffusion or ion implantation to form inversion layer 2. Inversion layer 2 is located above semiconductor substrate 1 and is used to isolate semiconductor substrate from drift layer. Since the resistance of heavily doped substrate layer is low and cannot withstand high voltage, inversion layer 2 can provide high-resistance drift region to balance conduction and withstand voltage.

[0059] Step 3: Ion implantation to form electrode connection region 3. According to the product type, corresponding ions are implanted at the designated position of the inversion layer 2 to form multiple independent heavily doped electrode regions, which become the current channel for the source 6 to connect with the semiconductor substrate 1, and at the same time, a good ohmic contact is formed between the two.

[0060] Step 4: Epitaxially forming drift layer 4, located between the source and drain, to withstand high voltage and optimize conduction characteristics. This layer belongs to the pre-prepared low-doped (lightly doped) region, with a specific doping concentration of approximately 10. 14 ~10 15 cm -3 Among them, the inversion layer 2 and the drift layer 4 together form the active region;

[0061] Step 5: Ion implantation or diffusion forms well region 5, located on drift layer 4 and positioned correspondingly to electrode connection region 3, providing a basis for source region formation. The doping concentration of well region 5 can reach 10. 16 ~10 17 cm -3 ;

[0062] Step 6: Ion implantation forms drain region 6, located at the top of the drift layer and between two adjacent well regions. After ion implantation, an independent highly doped region is formed, which is used to connect with the positive metal electrode above.

[0063] Step 7: Ion implantation forms source region 7, located in the middle of the well region. After ion implantation, an independent highly doped region is formed; specifically, the doping concentration of drain region 6 and source region 7 can reach 10. 19 ~10 20 cm -3 ;

[0064] Step 8: Formation of the gate oxide layer, which serves as an insulating medium between the gate and the active region to prevent leakage; specifically, Thermal SiO2 (silicon dioxide generated through a thermal oxidation process) is used, with a thickness designed to be 24nm.

[0065] Step 9: Gate fabrication. The gate is located above the gate oxide layer, and multiple gate recesses are reserved to correspond to the drain and source. Specifically, polysilicon or metal gates (such as TiN, TaN+W) are used.

[0066] Step 10: The first insulating layer protects the gate to prevent damage during subsequent processes.

[0067] Step 11: First layer metallization to form a positive metal electrode;

[0068] Step 12: The second insulating layer protects the positive metal electrode, achieving frontal protection. Firstly, it provides passivation protection to prevent oxidation, corrosion, or mechanical damage to the metal electrode. Secondly, it provides dielectric isolation to reduce parasitic capacitance between adjacent metal electrodes.

[0069] Step 13: Thinning the back side of the substrate, mainly to reduce the substrate thickness, thereby making the overall product thinner to meet packaging requirements;

[0070] Step 14: Metallize the back side to form a substrate metal electrode, providing a connection interface between the chip and the packaging substrate.

[0071] Specifically, in step four, the drift layer is formed using planar MOS technology, which simplifies the manufacturing process and reduces manufacturing costs.

[0072] Specifically, in step thirteen, the back side of the substrate is thinned to a thickness of 325μm to 425μm, which can reduce thermal resistance and improve heat dissipation; at the same time, it can meet packaging requirements and realize the fabrication of thin chips.

[0073] The source-side-down MOS device fabricated by this invention forms a double-sided heat dissipation channel by leading the source to the back of the chip and cooperating with the drain on the top. The source on the back of the chip can contact and connect with the substrate metal electrode, forming an efficient main heat dissipation path. The substrate metal electrode, made of copper or aluminum, serves as both part of the electrical connection and the main heat dissipation path. Simultaneously, the drain on the front can still serve as an auxiliary heat dissipation path. This double-sided heat dissipation design significantly improves thermal management efficiency and is crucial for meeting the miniaturization, high efficiency, and high power density requirements of modern electronic devices.

[0074] Specifically, taking PMOS (or NMOS) as an example, the detailed fabrication process is as follows:

[0075] Step 1: Substrate fabrication. Select an N-type (or P-type) silicon wafer and form a heavily doped substrate layer through epitaxy, one of the doping processes, i.e., form an N++ (or P++) substrate.

[0076] Step 2: An epitaxial P+ (or N+) inversion layer 2 is formed, which completely covers the substrate layer.

[0077] Step 3: Inject phosphorus (or boron) ions to form N+ (or P+) electrode connection region 3;

[0078] Step 4: Epitaxially form an N- (or P-) drift layer 4, located between the source and drain, to withstand high voltage;

[0079] Step 5: Ion implantation or diffusion to form a well region. Ions are implanted at designated locations in drift layer 4 to form a P+ (or N+) well region.

[0080] Step 6: Ion implantation to form a drain region. Phosphorus (or boron) ions are implanted at the top of the drift layer 4 and between two adjacent well regions 5 to form an independent highly doped region, which is the N+ (or P+) drain region.

[0081] Step 7: Ion implantation to form the source region. Phosphorus (or boron) ions are implanted into the trap region 5 to form a highly doped region, which is the N+ (or P+) source region.

[0082] Step 8: Formation of the gate oxide layer, which is made of Thermal SiO2 material with a thickness of 24nm;

[0083] Step 9: Gate fabrication, made of polycrystalline silicon, with multiple gate trenches reserved, the width of which is 650nm;

[0084] Step 10: The first insulating layer protects the gate, specifically made of SiO2 or SiOxNy material with a thickness of 1200nm;

[0085] Step 11: The first layer of metallization forms a positive metal electrode 11, which is formed by depositing metal into the gate groove corresponding to the drain region;

[0086] Step 12: The second insulating layer protects the positive metal electrode;

[0087] Step 13: Substrate backside thinning treatment;

[0088] Step 14: Metallize the back side to form the substrate metal electrode.

[0089] Specifically, in step four, the drift layer is formed using a planar MOS process.

[0090] Specifically, in step thirteen, the back side of the substrate is thinned, and the thickness of the thinned liner is 325μm to 425μm.

[0091] The product prepared by this method has a cell size of 8.8 μm to 11.6 μm; the specific doping concentration in each region is set reasonably according to the actual performance requirements.

[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0093] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A source-down MOS device based on planar MOS technology, characterized in that: It includes a semiconductor substrate (1), an active region and a gate region, wherein the active region is formed on the surface of the semiconductor substrate and the gate region is located above the active region; The active region is provided with a drain (6) and a source (7). The drain (6) located on the upper side is electrically connected to the front side of the chip through a positive metal electrode (11), which is located in the gate region. The source (7) located on the other side is connected to the semiconductor substrate (1) through an electrode connection region (3) and forms a good ohmic contact. The electrode connection region (3) is located in the inversion layer (2) provided on the top of the semiconductor substrate (1). The bottom of the semiconductor substrate (1) is provided with a substrate metal electrode (13) for lead-out.

2. The source-down MOS device based on planar MOS technology according to claim 1, characterized in that: The active region includes the entire region consisting of the inversion layer (2) and the drift layer (4), the electrode connection region (3) is epitaxially formed to form the drift layer (4), and the inversion layer (2) is an isolation layer formed by epitaxy, diffusion or ion implantation.

3. The source-down MOS device based on planar MOS technology according to claim 2, characterized in that: The semiconductor substrate (1) is made of single-crystal semiconductor material and is a heavily doped substrate layer. The inversion layer (2) is a highly doped isolation layer, and the drift layer (4) is a lightly doped epitaxial layer.

4. The source-down MOS device based on planar MOS technology according to claim 2, characterized in that: The drift layer (4) is provided with multiple well regions (5), the source electrode (7) is located in the well region (5) and corresponds one-to-one with the position of the electrode connection region (3) below; the drain electrode (6) is located on the top of the drift layer (4) and is located between any two adjacent source electrodes (7).

5. The source-down MOS device based on planar MOS technology according to claim 4, characterized in that: The gate region includes a gate oxide layer (8), a gate (9), and a gate insulating layer (10) arranged in sequence. The gate oxide layer (8) is located above the drift layer (4). The gate (9) is located above the gate oxide layer (8), and a plurality of gate grooves are reserved corresponding to the drain (6) and the source (7). The gate insulating layer (10) fills and covers the gate (9). After the gate insulating layer (10) is connected, the gate groove corresponding to the source (7) is completely closed. The positive metal electrode (11) is disposed in the gate groove corresponding to the drain (6), and a second insulating layer (12) is disposed at the positive metal electrode (11).

6. The source-down MOS device based on planar MOS technology according to claim 5, characterized in that: The gate oxide layer (8) is made of Thermal SiO2 and has a thickness of 24 nm; the gate (9) is made of polysilicon or metal, specifically Pt, Pd, NiSi or CoSi, and has a thickness of 450 nm; the gate insulating layer (10) is made of SiO2 or SiOxNy and has a thickness of 1200 nm.

7. A method for fabricating a source-down MOS device based on planar MOS technology as described in any one of claims 1-6, characterized in that: Includes the following steps: Step 1: Substrate fabrication. First, select a P-type or N-type silicon wafer as the substrate material according to the fabrication type. Second, after selecting the silicon wafer, form a heavily doped substrate layer through a doping process. Step 2: Epitaxy, diffusion or ion implantation to form an inversion layer. The inversion layer is located above the semiconductor substrate and is used to isolate the semiconductor substrate from the drift layer. Step 3: Ion implantation to form electrode connection regions. According to the product type, corresponding ions are implanted to form multiple independent heavily doped electrode regions, which become current channels for connecting the source and the substrate. Step 4: An epitaxial drift layer is formed between the source and drain electrodes to withstand high voltage. Step 5: Ion implantation or diffusion forms a trap region, located on the drift layer and with a position corresponding to the electrode connection region, providing a basis for source region formation; Step 6: Ion implantation forms a drain region, located at the top of the drift layer and between two adjacent well regions. After ion implantation, an independent highly doped region is formed, which is used to connect with the positive metal electrode above. Step 7: Ion implantation to form a source region, located in the middle of the trap region, forming an independent highly doped region after ion implantation; Step 8: Formation of the gate oxide layer, which serves as an insulating medium between the gate and the active region to prevent leakage. Step 9: Gate fabrication, wherein the gate is located above the gate oxide layer and the reserved gate recesses correspond to the drain and source. Step 10: The first insulating layer protects the gate. Step 11: First layer metallization to form a positive metal electrode; Step 12: The second insulating layer protects the positive metal electrode; Step 13: Thinning the back side of the substrate; Step 14: Metallize the back side to form the substrate metal electrode.

8. The preparation method according to claim 7, characterized in that: In step four, the drift layer is formed using a planar MOS process.

9. The preparation method according to claim 7, characterized in that: In step thirteen, the back side of the substrate is thinned, and the thickness of the thinned liner is 325μm to 425μm.

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