Semiconductor structure
By employing a specific combination of substrate, conductive layer, work function layer, and fill layer in the semiconductor structure, the electrical and reliability issues of recessed gates are solved, resulting in better electrical performance and reduced resistance.
Patent Information
- Application Number
- CN202410789386.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-04
- Filing Date
- 2024-06-19
- Publication Date
- 2025-12-09
AI Technical Summary
Existing semiconductor structures with recessed gates have shortcomings in terms of reliability and electrical performance.
The structure includes a substrate, a first conductive layer, a second conductive layer, a work function layer, a filling layer, and a dielectric layer. The work function layer has a U-shaped recess, the filling layer is located in the recess and is higher than the top surface of the work function layer, and the conductive layer and the work function layer serve as the gate of the recessed transistor to reduce resistance.
This design improves the electrical performance of the semiconductor structure, reduces resistance, and results in better performance.
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Figure CN121099679A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure with a recess gate. BACKGROUND
[0002] At present, a semiconductor structure with a recess gate (or called a buried gate) has been developed. However, how to improve the reliability and electrical performance of the semiconductor structure is a continuous effort. SUMMARY
[0003] The present invention provides a semiconductor structure with higher reliability and better electrical performance.
[0004] The present invention provides a semiconductor structure, comprising a substrate, a first conductive layer, a second conductive layer, a work function layer, a filling layer and a first dielectric layer. The first conductive layer is in the substrate. The second conductive layer is between the first conductive layer and the substrate. The work function layer is on the first conductive layer. The work function layer has a U-shaped profile and a recess. The filling layer is in the recess. The top surface of the filling layer is higher than the top surface of the work function layer. The first dielectric layer is between the second conductive layer and the substrate and between the work function layer and the substrate.
[0005] According to an embodiment of the present invention, in the semiconductor structure, the material of the first conductive layer is, for example, tungsten.
[0006] According to an embodiment of the present invention, in the semiconductor structure, the top surface of the first conductive layer and the top surface of the second conductive layer can be at the same level.
[0007] According to an embodiment of the present invention, in the semiconductor structure, the top surface of the first conductive layer can be lower than the top surface of the second conductive layer.
[0008] According to an embodiment of the present invention, in the semiconductor structure, the second conductive layer can also be between the work function layer and the first dielectric layer.
[0009] According to an embodiment of the present invention, in the semiconductor structure, the top surface of the second conductive layer and the top surface of the work function layer can be at the same level.
[0010] According to an embodiment of the present invention, in the semiconductor structure, the material of the second conductive layer is, for example, titanium nitride (TiN).
[0011] According to an embodiment of the present invention, in the semiconductor structure, the material of the work function layer can be a low work function material or an active material.
[0012] In one embodiment according to the present application, the low work function material is, for example, silicon.
[0013] In one embodiment according to the present application, the active material is, for example, titanium.
[0014] In one embodiment according to the present application, the top surface of the fill layer is level with the top surface of the substrate.
[0015] In one embodiment according to the present application, the top surface of the fill layer is lower than the top surface of the substrate.
[0016] In one embodiment according to the present application, the semiconductor structure further comprises a second dielectric layer. The second dielectric layer is on the top surface of the fill layer, the top surface of the work function layer, and the top surface of the second conductive layer.
[0017] In one embodiment according to the present application, the first dielectric layer is between the second dielectric layer and the substrate.
[0018] In one embodiment according to the present application, the top surface of the fill layer is higher than the top surface of the second conductive layer.
[0019] In one embodiment according to the present application, the material of the fill layer is a dielectric material or a conductive material.
[0020] In one embodiment according to the present application, the semiconductor structure further comprises a first doped region and a second doped region. The first doped region and the second doped region are in the substrate on both sides of the fill layer.
[0021] In one embodiment according to the present application, the top surface of the work function layer is higher than the bottom surface of the first doped region and the bottom surface of the second doped region.
[0022] In one embodiment according to the present application, the top surface of the second conductive layer is lower or higher than the bottom surface of the first doped region and the bottom surface of the second doped region.
[0023] In one embodiment according to the present application, the top surface of the fill layer is higher than the bottom surface of the first doped region and the bottom surface of the second doped region.
[0024] Based on the above, in the semiconductor structure proposed in this invention, a first conductive layer is located in the substrate. A second conductive layer is located between the first conductive layer and the substrate. A work function layer is located on the first conductive layer. The work function layer has a U-shaped cross-section and a recess. A filling layer is located in the recess. The top surface of the filling layer is higher than the top surface of the work function layer. A first dielectric layer is located between the second conductive layer and the substrate, and between the work function layer and the substrate. Since the first conductive layer, the second conductive layer, and the work function layer can be used as the gate of a recessed transistor, the resistance of the recessed gate can be reduced, thereby enabling the semiconductor structure to have better electrical performance.
[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figure 1 These are cross-sectional views of semiconductor structures according to some embodiments of the present invention;
[0027] Figure 2 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0028] Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention.
[0029] Symbol Explanation
[0030] 10: Semiconductor Structure
[0031] 100: Base
[0032] 102, 104: Conductive layer
[0033] 106: Work Function Layer
[0034] 108: Fill layer
[0035] 110, 116: Dielectric layer
[0036] 112, 114: Doped regions
[0037] S1~S5: Top surface
[0038] S6, S7: Bottom surface
[0039] H1: Overall height
[0040] R1: Depression Detailed Implementation
[0041] Embodiments are illustrated by way of example in the following detailed description and in connection with the accompanying drawings. Provided examples should not be taken as limiting the scope of the application, as the description continues. For convenience, same reference numbers can be used in different drawings to identify similar or identical elements. Additionally, the drawings are not necessarily drawn to scale. Indeed, for purposes of clarification, elements that are well known in the related art can have been omitted or simplified in the figures.
[0042] Figure 1 A cross-sectional view of a semiconductor structure according to some embodiments of the application.
[0043] Referring to Figure 1 , the semiconductor structure 10 includes a substrate 100, a conductive layer 102, a conductive layer 104, a work function layer 106, a fill layer 108, and a dielectric layer 110. In some embodiments, the semiconductor structure 10 can be a transistor with a recessed gate (buried gate) and can be applied to a dynamic random access memory (DRAM). In some embodiments, the substrate 100 can be a semiconductor substrate, such as a silicon substrate.
[0044] The conductive layer 102 is located in the substrate 100. In some embodiments, the material of the conductive layer 102 is, for example, tungsten. The conductive layer 104 is located between the conductive layer 102 and the substrate 100. In some embodiments, the top surface S1 of the conductive layer 102 and the top surface S2 of the conductive layer 104 can be level. In some embodiments, the material of the conductive layer 104 is, for example, titanium nitride.
[0045] The work function layer 106 is located on the conductive layer 102. The work function layer 106 can also be located on the conductive layer 104. The cross-sectional shape of the work function layer 106 is U-shaped and has a recess R1. In this embodiment, the material of the work function layer 106 can be a low work function material. In some embodiments, the low work function material is, for example, silicon.
[0046] The fill layer 108 is located in the recess R1. The top surface S3 of the fill layer 108 is higher than the top surface S4 of the work function layer 106. In this embodiment, the top surface S3 of the fill layer 108 and the top surface S5 of the substrate 100 can be level, but the application is not limited thereto. In other embodiments, the top surface S3 of the fill layer 108 can be lower than the top surface S5 of the substrate 100. In some embodiments, the top surface S3 of the fill layer 108 can be higher than the top surface S2 of the conductive layer 104. In some embodiments, the top surface S4 of the work function layer 106 can be higher than half of the overall height H1 of the fill layer 108. In this embodiment, the material of the fill layer 108 can be a dielectric material. In some embodiments, the material of the fill layer 108 is, for example, silicon dioxide.
[0047] The dielectric layer 110 is between the conductive layer 104 and the substrate 100, and between the work function layer 106 and the substrate 100. The dielectric layer 110 can be used as a gate dielectric layer. In some embodiments, the material of the dielectric layer 110 is, for example, silicon dioxide.
[0048] The semiconductor structure 10 can further include a doped region 112 and a doped region 114. The doped region 112 and the doped region 114 are in the substrate 100 on both sides of the fill layer 108. In some embodiments, the top surface S4 of the work function layer 106 can be higher than a bottom surface S6 of the doped region 112 and a bottom surface S7 of the doped region 114. In the present embodiment, the top surface S2 of the conductive layer 104 can be lower than the bottom surface S6 of the doped region 112 and the bottom surface S7 of the doped region 114. In some embodiments, the top surface S3 of the fill layer 108 can be higher than the bottom surface S6 of the doped region 112 and the bottom surface S7 of the doped region 114.
[0049] Based on the above embodiments, in the semiconductor structure 10, the conductive layer 102 is in the substrate 100. The conductive layer 104 is between the conductive layer 102 and the substrate 100. The work function layer 106 is on the conductive layer 102. The work function layer 106 has a U-shaped profile and a recess R1. The fill layer 108 is in the recess R1. The top surface S3 of the fill layer 108 is higher than the top surface S4 of the work function layer 106. The dielectric layer 110 is between the conductive layer 104 and the substrate 100, and between the work function layer 106 and the substrate 100. Since the conductive layer 102, the conductive layer 104 and the work function layer 106 can be used as the gate of a recessed transistor, the resistance of the recessed gate can be reduced, thereby making the semiconductor structure 10 have better electrical performance.
[0050] Figure 2 A cross-sectional view of a semiconductor structure according to another embodiment of the present application.
[0051] Please refer to Figure 1 and Figure 2 , Figure 2 the semiconductor structure 20 and Figure 1The differences in semiconductor structure 10 are as follows. In semiconductor structure 20, the top surface S1 of conductive layer 102 may be lower than the top surface S2 of conductive layer 104. In semiconductor structure 20, conductive layer 104 may also be located between work function layer 106 and dielectric layer 110. In semiconductor structure 20, the material of work function layer 106 may be an active material. When the material of work function layer 106 is an active material, the work function layer 106 (active material) can react with conductive layer 104 through a thermal fabrication process, thereby reducing the work function of the upper part of conductive layer 104. In some embodiments, the active material is, for example, titanium. In semiconductor structure 20, the top surface S2 of conductive layer 104 may be higher than the bottom surface S6 of doped region 112 and the bottom surface S7 of doped region 114. In semiconductor structure 20, the top surface S2 of conductive layer 104 and the top surface S4 of work function layer 106 may be at the same height. Furthermore, in Figure 1 and Figure 2 In this context, identical or similar components are represented by the same symbol, and their descriptions are omitted.
[0052] Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention.
[0053] Please refer to Figure 2 and Figure 3 , Figure 3 Semiconductor structure 30 and Figure 2 The differences between the semiconductor structure 20 and the semiconductor structure 30 are as follows. The material of the filling layer 108 in semiconductor structure 20 can be a dielectric material, while the material of the filling layer 108 in semiconductor structure 30 can be a conductive material. Thus, in semiconductor structure 30, the conductive layer 102, conductive layer 104, work function layer 106, and filling layer 108 can be used as the gate of a recessed transistor, thereby further reducing the resistance of the recessed gate. In semiconductor structure 30, the top surface S3 of the filling layer 108 can be lower than the top surface S5 of the substrate 100. Furthermore, semiconductor structure 30 may also include a dielectric layer 116. The dielectric layer 116 is located on the top surface S3 of the filling layer 108, the top surface S4 of the work function layer 106, and the top surface S2 of the conductive layer 104. The dielectric layer 110 can be located between the dielectric layer 116 and the substrate 100. In some embodiments, the material of the dielectric layer 116 is, for example, silicon dioxide. Furthermore, in Figure 2 and Figure 3 In this context, identical or similar components are represented by the same symbol, and their descriptions are omitted.
[0054] In summary, the semiconductor structure of the above embodiments includes a substrate, a first conductive layer, a second conductive layer, a work function layer, a filling layer and a first dielectric layer. The first conductive layer is located in the substrate. The second conductive layer is located between the first conductive layer and the substrate. The work function layer is located on the first conductive layer. The cross-sectional shape of the work function layer is U-shaped and has a recess. The filling layer is located in the recess. The top surface of the filling layer is higher than the top surface of the work function layer. The first dielectric layer is located between the second conductive layer and the substrate and between the work function layer and the substrate. Since the first conductive layer, the second conductive layer and the work function layer can be used as the gate of a recessed transistor, the resistance of the recessed gate can be reduced, thereby making the semiconductor structure have better electrical performance.
[0055] Although the present application has been disclosed with the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be defined by the appended claims.
Claims
1. A semiconductor structure, comprising: Base; A first conductive layer is located in the substrate. A second conductive layer is located between the first conductive layer and the substrate; A work function layer is located on the first conductive layer, wherein the work function layer has a U-shaped cross-section and has a recess; A filling layer is located in the recess, wherein the top surface of the filling layer is higher than the top surface of the work function layer; as well as A first dielectric layer is located between the second conductive layer and the substrate, and between the work function layer and the substrate.
2. The semiconductor structure of claim 1, wherein the material of the first conductive layer comprises tungsten.
3. The semiconductor structure of claim 1, wherein the top surface of the first conductive layer is at the same height as the top surface of the second conductive layer.
4. The semiconductor structure of claim 1, wherein the top surface of the first conductive layer is lower than the top surface of the second conductive layer.
5. The semiconductor structure of claim 1, wherein the second conductive layer is further located between the work function layer and the first dielectric layer.
6. The semiconductor structure of claim 1, wherein the top surface of the second conductive layer is at the same height as the top surface of the work function layer.
7. The semiconductor structure of claim 1, wherein the material of the second conductive layer comprises titanium nitride.
8. The semiconductor structure of claim 1, wherein the material of the work function layer comprises a low work function material or an active material.
9. The semiconductor structure of claim 8, wherein the low work function material comprises silicon.
10. The semiconductor structure of claim 8, wherein the active material comprises titanium.
11. The semiconductor structure of claim 1, wherein the top surface of the filling layer is at the same height as the top surface of the substrate.
12. The semiconductor structure of claim 1, wherein the top surface of the filling layer is lower than the top surface of the substrate.
13. The semiconductor structure of claim 12, further comprising: The second dielectric layer is located on the top surface of the filling layer, the top surface of the work function layer, and the top surface of the second conductive layer.
14. The semiconductor structure of claim 13, wherein the first dielectric layer is located between the second dielectric layer and the substrate.
15. The semiconductor structure of claim 1, wherein the top surface of the filling layer is higher than the top surface of the second conductive layer.
16. The semiconductor structure of claim 1, wherein the material of the filling layer comprises a dielectric material or a conductive material.
17. The semiconductor structure of claim 1, further comprising: The first doped region and the second doped region are located in the substrate on both sides of the filling layer.
18. The semiconductor structure of claim 17, wherein the top surface of the work function layer is higher than the bottom surface of the first doped region and the bottom surface of the second doped region.
19. The semiconductor structure of claim 17, wherein the top surface of the second conductive layer is lower than or higher than the bottom surface of the first doped region and the bottom surface of the second doped region.
20. The semiconductor structure of claim 17, wherein the top surface of the filling layer is higher than the bottom surface of the first doped region and the bottom surface of the second doped region.