Three-phase interleaving bridgeless totem pole PFC power converter

Abstract

The invention discloses a three-phase interleaved parallel bridgeless totem pole PFC power converter which comprises three pairs of high-frequency bridge arms, each pair of high-frequency bridge arms is formed by connecting two high-frequency switch tubes in series, and PWM carriers of the high-frequency switch tubes in the three pairs of high-frequency bridge arms are staggered by 120 degrees; the pair of low-frequency switching devices are switched on and off at the power grid frequency to realize synchronous rectification; three same input inductors; the two ends of each auxiliary inductor are connected to the midpoints of different high-frequency bridge arms respectively, the three auxiliary inductors are connected end to end, and zero-voltage soft switching of the high-frequency switching device is achieved through energy storage and release of the auxiliary inductors. Compared with a traditional three-phase interleaving bridgeless totem pole PFC circuit, the power converter can meet the high-power application requirement, a power device can achieve soft switching, the converter is allowed to operate under the high switching frequency, the parameter requirements of inductance and capacitance are reduced, the system size is reduced, and the power density of the system is improved.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a three-phase interleaved parallel bridgeless totem pole PFC power converter. Background Technology

[0002] The rapid development of the new energy industry has placed higher demands on the development, design, and control of electric vehicle chargers, including high power density, high efficiency, low cost, and high reliability. As the pre-converter in electric vehicle chargers, the AC-DC stage plays a crucial role in bidirectional energy flow, power factor correction, and current harmonic reduction.

[0003] While traditional boost AC-DC topologies are simple in structure and control, they suffer from severe conduction losses and ripple problems. With the development of wide-bandgap semiconductor devices, bridgeless totem-pole PFC (power factor correction) circuits have become widely used. However, bridgeless totem-pole PFC converters do not achieve soft switching, which limits the switching frequency and power density of high-frequency transistors. Furthermore, hard switching will lead to more severe electromagnetic interference.

[0004] To improve converter efficiency and reduce switching losses, a Chinese patent application, such as CN118337036A, provides a control method and system for achieving full-range ZVS (zero-voltage switching) of a totem-pole PFC. This method includes acquiring the input voltage, output voltage, zero-crossing signal of the input current, input voltage polarity signal, circuit parameters, and PI (proportional-integral) voltage loop output power of the totem-pole PFC circuit; calculating the additional conduction time of the synchronous rectifier diode and the conduction time of the main diode; calculating the peak current dead time and the valley current dead time; and controlling the operation of the main diode and synchronous rectifier diode of the totem-pole PFC circuit based on the additional conduction time of the synchronous rectifier diode, the conduction time of the main diode, the peak current dead time, the valley current dead time, and the input voltage polarity signal. This method can achieve full-range ZVS soft-turn-on of high-frequency diodes while avoiding excessive body diode conduction losses, and is easy to implement in engineering with low DSP computational resource overhead.

[0005] For example, Chinese patent application CN114710022A provides a method for extending the ZVS range and retaining margin based on totem pole PFC. By controlling the auxiliary switch to conduct additionally, it solves the problem that the main switch cannot achieve zero-voltage turn-on through natural resonance. In the process of digitalizing the converter, the traditional variable conduction time control under critical conduction mode (CRM) suffers from the problem that the large number of complex mathematical operations corresponding to the additional conduction time seriously affects the algorithm execution efficiency. The patent simplifies the algorithm by using the idea of ​​linear fitting, which reduces the implementation difficulty of digital control algorithm in the process of digitalizing the converter, improves the execution efficiency of the algorithm, and enhances the overall performance of the converter. The patented technology uses a reasonable linear approximation method to obtain a new simple linear expression for the additional conduction time while retaining the ZVS time margin, thus expanding the ZVS range and ensuring the reliability of ZVS implementation.

[0006] While the aforementioned existing technologies have achieved soft switching of high-frequency transistors in bridgeless totem-pole PFC converters, they are only applicable to critical conduction mode and transition mode (TCM). Critical conduction mode and intermittent conduction mode are only suitable for small and medium power applications. In high-power applications, continuous conduction mode (CCM) is still the main mode used. Therefore, it cannot solve the problem that the high-frequency transistors in the circuit cannot achieve zero-voltage turn-on in continuous conduction mode in high-power applications. Summary of the Invention

[0007] In view of the above, the present invention provides a three-phase interleaved parallel bridgeless totem pole PFC power converter, which enables the circuit to achieve zero-voltage turn-on of all high-frequency switching devices in continuous conduction mode and high power conditions, thereby improving the switching frequency of high-frequency switching devices and the overall power density of the converter.

[0008] A three-phase interleaved parallel bridgeless totem-pole PFC power converter includes: an AC power supply, six high-frequency switching transistors S1~S6, two low-frequency switching transistors S7~S8, three-phase input inductors L1~L3, and three auxiliary inductors L A1 ~L A3 The system includes a DC bus capacitor, a load, and a control system. The drain of capacitor S2 is connected to the drains of capacitors S4, S6, and S8, one end of the DC bus capacitor, and one end of the load. The source of capacitor S8 is connected to the drain of capacitor S7 and one end of the AC input power supply. The source of capacitor S7 is connected to the sources of capacitors S1, S3, and S5, the other end of the DC bus capacitor, and the other end of the load. The other end of the AC input power supply is connected to one end of capacitors L1, L2, and L3. The other end of capacitor L1 is connected to... A1 one end, L A3 One end of L2 is connected to the source of S2 and the drain of S1, and the other end of L2 is connected to L... A1 The other end, LA2 One end of L3 is connected to the source of S4 and the drain of S3, and the other end of L3 is connected to L... A2 The other end, L A3 The other end of the tube is connected to the source of S6 and the drain of S5; the high-frequency switching tubes S1 to S6 are all equipped with anti-parallel diodes and parallel capacitors (these capacitors are the output capacitors of the high-frequency switching tubes), and the low-frequency switching tubes S7 to S8 are all equipped with anti-parallel diodes. The control system provides switching control signals for the high-frequency switching tubes S1 to S6 and the low-frequency switching tubes S7 to S8.

[0009] Furthermore, the auxiliary inductor L A1 ~L A3 inductance value L A They are the same and satisfy the following conditions:

[0010] in: v dc This refers to the DC bus voltage of the power converter. D min This represents the minimum duty cycle of the power converter. T s For the switching cycle, i req_max This represents the maximum current flowing through a single input inductor.

[0011] Furthermore, the high-frequency switching transistors S1~S6 and the low-frequency switching transistors S7~S8 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors).

[0012] Furthermore, the high-frequency switching transistors S1~S6 are connected to form three pairs of high-frequency bridge arms, and three auxiliary inductors L A1 ~L A3 The ends are connected to form a triangle, and the three endpoints are respectively connected to the midpoints of different high-frequency bridge arms.

[0013] Furthermore, the control system is used to maintain the stability of the DC bus voltage while adjusting the input current waveform to follow the input voltage waveform, ensuring that the amplitude and phase of the input inductor current of each phase are uniform, and realizing zero-voltage switching of high-frequency switching transistors S1~S6.

[0014] Furthermore, the control system adopts a dual closed-loop control strategy to regulate the load voltage of the power converter. This control strategy includes an inner loop current control loop and an outer loop voltage control loop. It collects the AC side input current and input voltage, the current on the three-phase input inductors L1~L3 and the DC bus voltage, and calculates the target output voltage in the numerical domain through PI control. Then, based on the target output voltage, it generates switching control signals for high-frequency switching transistors S1~S6 through PWM (pulse width modulation) technology.

[0015] Furthermore, the PWM carriers of the high-frequency switching transistors in the three pairs of high-frequency bridge arms are staggered by 120° and are independently controlled by their respective half-bridge duty cycles to minimize ripple.

[0016] Furthermore, the control system is implemented using a programmable DSP (Digital Signal Processor).

[0017] Furthermore, the inductance values ​​of the input inductors L1~L3 L They are the same and are determined by the following expression:

[0018] in: v dc This refers to the DC bus voltage of the power converter. T s For the switching cycle, I ripple_max This represents the maximum current ripple value on the load.

[0019] Furthermore, the capacitance value of the DC bus capacitor C o Determined by the following expression:

[0020] in: v dc This refers to the DC bus voltage of the power converter. P outmax This represents the maximum output power of the power converter. f g The AC input voltage frequency of the power converter. U ripple_max This represents the maximum value of the secondary ripple voltage of the load.

[0021] Furthermore, the load is not limited to resistive loads, but may also include DC-DC converters such as LLC, nonlinear variable loads, capacitive loads, inductive loads, and mixed loads.

[0022] Compared with the prior art, the present invention has the following beneficial technical effects: 1. In the continuous conduction mode of the inductor current, the present invention realizes zero-voltage turn-on of each high-frequency transistor in the three-phase interleaved parallel bridgeless totem pole PFC circuit, thereby improving the switching frequency of the high-frequency transistor.

[0023] 2. In high-power applications, this invention enables zero-voltage turn-on of each high-frequency transistor in a three-phase interleaved parallel bridgeless totem pole PFC circuit, thereby improving the switching frequency of the high-frequency transistors.

[0024] 3. This invention reduces the size of the boost inductor, reduces the system volume, and increases the system power density. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the topology of the three-phase interleaved parallel bridgeless totem pole PFC power converter of the present invention.

[0026] Figure 2 This is a schematic diagram of the working timing of the three-phase interleaved parallel bridgeless totem pole PFC power converter of the present invention.

[0027] Figure 3 This is a block diagram of the control system for the three-phase interleaved parallel bridgeless totem pole PFC power converter of the present invention.

[0028] Figure 4 This is a schematic diagram of the circuit conduction state of the power converter of the present invention in mode 1.

[0029] Figure 5 This is a schematic diagram of the circuit conduction state of the power converter of the present invention in mode 2.

[0030] Figure 6 This is a schematic diagram of the circuit conduction state of the power converter of the present invention in mode 3.

[0031] Figure 7 This is a schematic diagram of the circuit conduction state of the power converter of the present invention in mode 4. Detailed Implementation

[0032] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] like Figure 1 As shown, this embodiment provides a three-phase interleaved parallel bridgeless totem-pole PFC power converter for operation in either rectifier mode (converting AC input to DC output) or inverter mode (converting DC input to AC output). The power converter includes three pairs of high-frequency bridge arms S1-S6, one pair of low-frequency bridge arms S7-S8, three interleaved parallel three-phase input inductors L1-L3, an AC power supply, and three auxiliary inductors L... A1 ~L A3The load R and the control system, wherein: Taking one phase as an example, the high-frequency bridge arm consists of a phase with an anti-parallel diode and a parallel capacitor C. oss2 The high-frequency upper transistor S2 and a diode with anti-parallel connection and a parallel capacitor C oss1 The high-frequency bridge arm consists of three high-frequency transistors: the lower transistor S1 connected in series, and the source of the upper high-frequency transistor S2 connected to the drain of the lower high-frequency transistor S1, with the resulting endpoint being the midpoint of the corresponding high-frequency bridge arm. The drains of the upper high-frequency transistors S2, S4, and S6 in the three pairs of high-frequency bridge arms are connected together and then connected to the upper end of the DC bus capacitor C. The sources of the lower high-frequency transistors S1, S3, and S5 in the three pairs of high-frequency bridge arms are connected together and then connected to the lower end of the DC bus capacitor C. The PWM carriers of the high-frequency switching transistors in the three pairs of high-frequency bridge arms are staggered by 120° and are independently controlled by their respective half-bridge duty cycles to minimize ripple.

[0034] The low-frequency bridge arm consists of a low-frequency upper transistor S8 with an anti-parallel diode and a low-frequency lower transistor S7 with an anti-parallel diode connected in series. The source of the low-frequency upper transistor S8 is connected to the drain of the low-frequency lower transistor S7. The drain of the low-frequency upper transistor S8 in the low-frequency bridge arm is connected to one end of the DC bus capacitor C, and the source of the low-frequency lower transistor S7 is connected to the other end of the DC bus capacitor C.

[0035] One end of the three inductors L1~L3 is a common terminal and they are interconnected; the other end is connected to the midpoint of the three pairs of high-frequency half-bridge arms. The load R is connected in parallel with the DC bus capacitor C. The three auxiliary inductors L A1 ~L A3 The ends are connected to form a triangle, and the three endpoints are respectively connected to the midpoints of different high-frequency bridge arms; one end of the AC power supply is connected to the common terminal of the three input inductors, and the other end is connected to the midpoint of the low-frequency bridge arm.

[0036] The control system is used to maintain the stability of the DC bus voltage, ensure the uniformity of the amplitude and phase of the inductor current in each phase, and achieve zero-voltage turn-on of the high-frequency transistors by controlling high-frequency and low-frequency switching devices to adjust the input current waveform to follow the input voltage waveform. For example... Figure 3 As shown, the control system in this embodiment adopts a dual closed-loop control strategy, which includes an inner loop current control loop and a phase-locked loop with a 100kHz interruption, and an outer loop voltage control loop with a 10kHz interruption, used to regulate the voltage on the converter load: The target output voltage is provided by performing PI calculations based on voltage and current read from the analog-to-digital converter port; the read values ​​include the total AC current. i in AC side voltage u g The current in each phase of the interleaved three-phase system and the voltage on the bus capacitor. v dc .

[0037] In this embodiment, the three-phase interleaved parallel bridgeless totem-pole PFC power converter adds an auxiliary inductor between the midpoints of each high-frequency bridge arm to achieve zero-voltage turn-on. Since the circuit operates similarly when transmitting power in the forward and reverse directions, this embodiment only describes the circuit's operating mode and the parameter determination method for the power devices during the positive half-cycle when power is transferred from the AC side to the DC side.

[0038] The assumptions are as follows: ① Except for the parallel capacitor and anti-parallel diode, the high-frequency switching transistors S1~S6 are all ideal devices; ② Due to the symmetry of the positive and negative half-cycles, only the positive half-cycle is analyzed, and due to the alternating symmetry between the three phases, four modes out of the 12 modes are grouped together and alternate between the phases, so only the first four modes are analyzed; ③ The low-frequency switching transistors S7~S8 are considered ideal devices; ④ The DC bus voltage... v dc If we consider it as a constant value, then the operating timing of the power converter in this embodiment is as follows: Figure 2 As shown: Mode 1 [t0~t1]: such as Figure 4 As shown, S2, S4, and S5 are on, and the inductor L... A1 L A2 L A3 The voltages at both ends are 0 and +V respectively. dc -v dc According to the inductor voltage-current relationship, i LA1 Keep constant, i LA2 Increase and i LA3 As the current decreases, the absolute values ​​of the slopes of the two changes are equal; the current in S2 decreases from i L1 Change to i L1 -i LA1 +i LA3 (Current decreases), S4 current from i L2 Increase to i L2 +i LA1 -i LA2 S5 current increases i L3 Large to i L3 +i LA2 -i LA3 .

[0039] Mode 2 [t1~t2]: such as Figure 5 As shown, after S5 is turned off at time t1, L3 resonates with the two parasitic capacitances of the third high-frequency half-bridge, C oss5 Charge to +V dc And C oss6 Discharge to 0; the drain-source voltage can resonate to zero, achieving zero-voltage turn-on of the high-frequency switch S6. At this time, L A2 and L A3 The voltage across the terminals gradually approaches zero, causing i to... LA2 and iLA3 The slope of the change gradually decreases to zero.

[0040] Mode 3 [t2~t3]: such as Figure 6 As shown, S2, S4, and S6 are turned on. Since the voltage across the three auxiliary inductors is zero, their current remains constant. At this time, i S3 The descent slope is significantly smaller than in the preceding and following stages, which is because i LA2 with i LA3 This is caused by the currents canceling each other out.

[0041] Pattern 4 [t3~t4]: such as Figure 7 As shown, S2 is turned off at time t3. Without an auxiliary inductor, the PFC inductor current is still relatively large in CCM operating mode. The freewheeling effect will cause current to flow through the body diode of the high-frequency switch S2, resulting in the drain-source voltage of S1 being clamped to the output DC voltage v. dc This forms a hard switch. After adding an auxiliary inductor, analysis using Kirchhoff's current law shows that the total current between the upper and lower transistors is i. L1 -i LA1 +i LA3 This current is much smaller than the value without an auxiliary inductor, even less than zero and reverses direction; the decrease in current causes the current in S1 to reverse, thereby causing the output capacitor C to... oss1 Discharge creates the voltage conditions for ZVS of the lower transistor in the high-frequency half-bridge.

[0042] like Figure 2 As shown, there is a reverse current in the switching transistor before it is turned on. This is a key condition for achieving zero-voltage switching, specifically requiring the following current relationship to be satisfied: when S2 is turned off, i must satisfy... L1 <i LA1 -i LA3 Similarly, when S4 is turned off, i must satisfy... L2 <i LA2 -i LA1 When S6 is turned off, i must be satisfied. L3 <i LA3 -i LA2 .

[0043] While a larger auxiliary inductor current is beneficial for achieving Zero-Switching Transmission (ZVS), an excessively large current can increase the current stress on the high-frequency switching transistors, significantly increasing conduction losses. The amplitude of the auxiliary inductor current is inversely proportional to the inductance value; therefore, while ensuring ZVS, the largest possible inductance value should be selected to reduce losses. D min To achieve zero-voltage turn-on, the algebraic sum of the currents of the two auxiliary inductors must exceed the maximum current of the PFC inductor connected to the common terminal of the high-frequency half-bridge. The auxiliary inductor value must meet the following range:

[0044] Input inductor design: When the inductor operates in CCM mode, the size of the PFC input inductor affects the magnitude of the current ripple, and the AC peak value of the input current is also affected when the inductors are interleaved and paralleled. I max for:

[0045] in: U in_rms Indicates the effective value of the AC input voltage. η For converter efficiency.

[0046] The design requires the current ripple to be 10% of the peak current under 25% load conditions. Since the circuit enters different operating modes at different duty cycles, its current ripple characteristics also change accordingly, specifically as follows:

[0047] Duty cycle D When the current ripple is set to 5 / 6, 1 / 2, and 1 / 6 respectively, the current ripple reaches the same maximum value. I ripple_max The specific value is:

[0048] Calculations show that the maximum peak input current is approximately 13.6A at 25% load. Substituting the maximum current ripple value into the above formula, the inductance value can be calculated. L It should be no less than 240μH. Considering the inductor saturation effect of higher power, the actual PFC inductor value is selected as 300μH.

[0049] Bus capacitor design: The DC-side output current serves to filter out secondary switching ripple and reduce secondary ripple. Considering the suppression of secondary ripple, the capacitor value is:

[0050] in: U ripple_max The maximum secondary ripple voltage is taken as 5% of the output voltage; according to the above formula, the capacitance value should not be less than 1.71mF.

[0051] The effective value of the capacitor's power frequency current ripple under full load is approximately:

[0052] The calculated effective value of the current ripple is 10.4A. Considering both the voltage ripple magnitude and the capacitor's power frequency current ripple withstand capability, a capacitor value of 2.5mF is selected.

[0053] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A three-phase interleaved parallel bridgeless totem-pole PFC power converter, characterized in that, include: AC power supply, six high-frequency switching transistors S1~S6, two low-frequency switching transistors S7~S8, three-phase input inductors L1~L3, and three auxiliary inductors L A1 ~L A3 The system includes a DC bus capacitor, a load, and a control system. The drain of capacitor S2 is connected to the drains of capacitors S4, S6, and S8, one end of the DC bus capacitor, and one end of the load. The source of capacitor S8 is connected to the drain of capacitor S7 and one end of the AC input power supply. The source of capacitor S7 is connected to the sources of capacitors S1, S3, and S5, the other end of the DC bus capacitor, and the other end of the load. The other end of the AC input power supply is connected to one end of capacitors L1, L2, and L3. The other end of capacitor L1 is connected to... A1 one end, L A3 One end of L2 is connected to the source of S2 and the drain of S1, and the other end of L2 is connected to L... A1 The other end, L A2 One end of L3 is connected to the source of S4 and the drain of S3, and the other end of L3 is connected to L... A2 The other end, L A3 The other end of the circuit is connected to the source of S6 and the drain of S5; the high-frequency switching transistors S1 to S6 are all equipped with anti-parallel diodes and parallel capacitors, and the low-frequency switching transistors S7 to S8 are all equipped with anti-parallel diodes. The control system provides switching control signals for the high-frequency switching transistors S1 to S6 and the low-frequency switching transistors S7 to S8.

2. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The auxiliary inductor L A1 ~L A3 inductance value L A They are the same and satisfy the following conditions: ; in: v dc This refers to the DC bus voltage of the power converter. D min This represents the minimum duty cycle of the power converter. T s For the switching cycle, i req_max This represents the maximum current flowing through a single input inductor.

3. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The high-frequency switching transistors S1~S6 and the low-frequency switching transistors S7~S8 are MOSFETs or IGBTs.

4. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The high-frequency switching transistors S1~S6 are connected to form three pairs of high-frequency bridge arms, and three auxiliary inductors L A1 ~L A3 The ends are connected to form a triangle, and the three endpoints are respectively connected to the midpoints of different high-frequency bridge arms.

5. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The control system is used to maintain the stability of the DC bus voltage while adjusting the input current waveform to follow the input voltage waveform, ensuring that the amplitude and phase of the input inductor current of each phase are uniform, and realizing zero-voltage switching of high-frequency switching transistors S1~S6.

6. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The control system adopts a dual closed-loop control strategy to regulate the load voltage of the power converter. The control strategy includes an inner loop current control loop and an outer loop voltage control loop. It collects the AC side input current and input voltage, the current on the three-phase input inductors L1~L3 and the DC bus voltage, and calculates the target output voltage in the numerical domain through PI control. Then, based on the target output voltage, it generates the switching control signals of high-frequency switching transistors S1~S6 through PWM technology.

7. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 4, characterized in that: The PWM carriers of the high-frequency switching transistors in the three pairs of high-frequency bridge arms are staggered by 120° and are independently controlled by their respective half-bridge duty cycles.

8. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The control system is implemented using a programmable DSP.

9. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The inductance values ​​of the input inductors L1~L3 L They are the same and are determined by the following expression: ; in: v dc This refers to the DC bus voltage of the power converter. T s For the switching cycle, I ripple_max This represents the maximum current ripple value on the load.

10. The three-phase interleaved parallel bridgeless totem-pole PFC power converter according to claim 1, characterized in that: The capacitance value of the DC bus capacitor C o Determined by the following expression: ; in: v dc This refers to the DC bus voltage of the power converter. P outmax This represents the maximum output power of the power converter. f g The AC input voltage frequency of the power converter. U ripple_max This represents the maximum value of the secondary ripple voltage of the load.

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