A polar code decoding simulation circuit implementation method, system, device and medium based on a memory-computing integrated device

Abstract

The application relates to a Polar code decoding simulation circuit implementation method, system, equipment and medium based on a memory-computing integrated device, and the method comprises the following steps: obtaining a Polar code sparse check matrix and a corresponding probability graph model according to a received Polar code; obtaining an initial log-likelihood ratio of each variable node in the probability graph model; dividing a memory-computing integrated device array into an input part, an output part, an iteration part and a check part according to the Polar code sparse check matrix, and configuring the resistance state of the cross nodes in each part; loading the initial log-likelihood ratio into the input part of the memory-computing integrated device array and keeping it, and the initial input of other parts is 0; checking and iteratively calculating the calculation results output by the iteration part, the check part and the output part in the memory-computing integrated device array by using a peripheral circuit, and outputting a final decoding result after the check condition is met. The application can be widely applied in the field of decoding technology.

Description

Technical Field

[0001] This invention belongs to the field of communications, specifically the field of signal decoding technology, and more specifically relates to a method, system, device, and medium for implementing a Polar code decoding analog circuit based on a memory computing unit. Background Technology

[0002] Polar codes are an emerging channel coding scheme that has been theoretically proven to reach the channel capacity limit through the principle of channel polarization and has been widely used in fifth-generation (5G) mobile communication standards. However, traditional Polar code decoding methods, including Successive Cancellation (SC), Successive Cancellation List (SCL), and Belief Propagation (BP), currently rely primarily on traditional digital circuits, such as Field-Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs) based on CMOS technology. These decoding architectures typically suffer from the following problems:

[0003] 1. It requires a large number of discrete fixed-point addition and subtraction operations, sign comparisons, and random memory access operations;

[0004] 2. Large-scale SRAM (Static Random Access Memory) access leads to higher power consumption costs;

[0005] 3. The large number of discrete computations during the decoding iteration process leads to low energy efficiency.

[0006] The aforementioned bottlenecks have gradually become the main factors contributing to power consumption in communication systems, and existing digital decoding implementations struggle to fundamentally improve the energy efficiency of communication basebands. To achieve more efficient Polar code decoding, it is urgent to explore innovative hardware architectures to effectively reduce decoding power consumption and improve decoding efficiency. Summary of the Invention

[0007] To address the problems of high power consumption and low energy efficiency in existing Polar code decoding, the present invention aims to provide a method, system, device, and medium for implementing Polar code decoding analog circuits based on in-memory computing devices. By utilizing the unique in-memory computing characteristics of in-memory computing devices, the energy consumption bottleneck of traditional digital decoding methods can be overcome, while improving decoding efficiency and energy efficiency.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a method for implementing a Polar code decoding analog circuit based on a memory computing device, comprising:

[0010] A bipartite factor graph is constructed based on the received Polar code, and redundant nodes in the bipartite factor graph are pruned and optimized to obtain the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model.

[0011] Obtain the initial log-likelihood ratio for each variable node in the probabilistic graphical model as the initial input;

[0012] The in-memory compute array is divided into input, output, iterative, and parity parts based on the sparse parity check matrix of the Polar code, and the resistance state of the cross nodes of each part is configured.

[0013] The initial input is loaded into the input section of the in-memory compute array and held thereafter, while the initial input for the other sections is 0.

[0014] The calculation results output by the iteration section, verification section and output section of the in-memory computing array are verified and iterated using peripheral circuits, and the final decoding result is output when the termination condition is met.

[0015] Secondly, the present invention provides a Polar code decoding analog circuit implementation system based on a memory computing device, comprising:

[0016] The preprocessing unit is used to construct a bipartite factor graph based on the received Polar code, and to prune and optimize redundant nodes in the bipartite factor graph to obtain the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model.

[0017] The initialization unit is used to obtain the initial log-likelihood ratio of each variable node in the probabilistic graphical model as the initial input;

[0018] The in-memory computing array configuration unit is used to divide the in-memory computing array into regions, namely the input part, output part, iteration part and parity part, according to the Polar code sparse parity matrix, and to configure the resistance state of the cross nodes of each part.

[0019] The loading unit is used to load the initial input into the input section of the in-memory compute array and keep it thereafter, while the initial input of other sections is 0;

[0020] The iterative output unit is used to verify and iteratively calculate the calculation results output by the iterative part, the verification part and the output part in the in-memory computing array using the peripheral circuit, and output the final decoding result when the termination condition is met.

[0021] Thirdly, the present invention provides a computer-readable storage medium for storing one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform the Polar code decoding analog circuit implementation method based on a memory computing device.

[0022] Fourthly, the present invention provides a computing device, comprising: one or more processors and a memory, wherein the memory stores one or more programs and is configured to be executed by the one or more processors, and the one or more programs include instructions for executing the Polar code decoding analog circuit implementation method based on the in-memory computing device.

[0023] The present invention has the following advantages due to the adoption of the above technical solutions:

[0024] 1. This invention transforms the decoding process into a message passing process between variable nodes and verification nodes based on a probabilistic graphical model, and utilizes the unique in-memory computing characteristics of in-memory computing devices to store static variables in the computation process. This can significantly reduce the energy consumption bottleneck of decoding operations in the digital domain, while improving decoding efficiency and increasing decoding throughput.

[0025] 2. This invention achieves matrix-vector multiplication through parallel analog domain operation and intrinsic computation by combining Kirchhoff's current law, which significantly reduces the number of random memory accesses and the power consumption of digital operations, breaks through the energy consumption bottleneck of traditional pure digital decoders, and achieves significant energy efficiency improvement and performance optimization.

[0026] Therefore, this invention can be widely applied in the field of signal decoding technology. Attached Figure Description

[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. In the drawings:

[0028] Figure 1 This is a flowchart of the Polar code decoding analog circuit implementation method based on in-memory computing provided in this embodiment of the invention;

[0029] Figure 2 This is a schematic diagram of the Polar code decoding analog circuit based on a memory computing unit provided in this embodiment of the invention;

[0030] Figure 3 This is a schematic diagram of the Min module provided in an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0032] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0033] In some embodiments of the present invention, a method for implementing a Polar code decoding analog circuit based on an in-memory computing unit is provided, comprising: creating a Polar code sparse parity-check matrix based on the Polar code and obtaining a probabilistic graphical model; dividing the in-memory computing unit array into regions and configuring the node resistance states based on the Polar code sparse parity-check matrix; iteratively updating the confidence between variable nodes and parity nodes based on the configured in-memory computing unit array, and outputting the decoding result. This invention can significantly reduce the number of random memory accesses and the power consumption of digital domain operations, breaking through the energy consumption bottleneck of traditional digital circuits.

[0034] Correspondingly, in other embodiments of the present invention, a Polar code decoding analog circuit implementation system, device and medium based on a memory computing device are provided.

[0035] Example 1

[0036] like Figure 1 As shown, this embodiment provides a method for implementing a Polar code decoding analog circuit based on a memory computing device, including the following steps:

[0037] S1. Construct a bipartite factor graph based on the received Polar code, and prune and optimize redundant nodes in the bipartite factor graph to obtain the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model.

[0038] Specifically, the process of obtaining the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model includes the following steps:

[0039] S11. Construct a bipartite factor graph based on the polarization encoding scheme (i.e., its generator matrix) of the received Polar code.

[0040] Polar codes are a typical type of non-systematic code, meaning that the codewords themselves do not explicitly contain the original information bits; instead, the original information bits are implicitly embedded in the encoded codeword through a linear transformation. Polar codes typically use the Kronecker product (…). Construct the generating matrix ,in, A classical polarization kernel of 2*2 can be represented as ; This is the number of Kronecker products, which is also equivalent to the "polarization depth" of the polar code; Given the code length, it can be represented as The actual encoding process is as follows: codeword ,in, It is an input bit sequence consisting of information bits and frozen bits.

[0041] This embodiment uses the (8,4) polar code as an example to introduce the process of constructing a bipartite factor graph for Polar codes. First, starting from the encoded polarization relation / butterfly network mapped by the generator matrix, each polarization process / butterfly intermediate node is considered a variable node (VN), and the local XOR and equality connection relationships are considered check nodes (CN). The original polarization relation / butterfly network is then flattened into a bipartite factor graph, resulting in the set of variable nodes and the set of factor variables, respectively:

[0042] The set of variable nodes includes: Channel Variable Node (VNCH): the N nodes on the rightmost side of the factor graph, with the initial value of the node information set to the channel output LLR value; Hidden Variable Node (VNH): the nodes in the intermediate layer of the polar code (stage=1,2,…,n-1), with no initial information, so the initial LLR is set to 0; Frozen Variable Node (VNF): the node at the frozen position in the leftmost input bit sequence.

[0043] The set of verification nodes includes XOR constraint nodes: degree 3, indicating that the bits of the three connected variable nodes satisfy the XOR constraint (modulo 2 sum is 0); and replica nodes: degree 2, indicating that the bits of the two connected variable nodes are equal.

[0044] The total number of variable nodes is There are [number] verification nodes. There are 15 nodes (of which XOR nodes and replica nodes each account for half).

[0045] S12. Prune redundant nodes in the bipartite factorization graph to reduce redundancy, and obtain the Polar code sparse parity-check matrix. .

[0046] In this embodiment, to reduce redundancy during the tiling process, the bipartite factor graph needs to be pruned. The following redundant nodes are deleted according to the pruning algorithm: frozen variable nodes, check nodes with a degree of 1, check nodes with a degree of 2, and hidden variable nodes with a degree of 1 or 2, to obtain a simplified bipartite factor graph.

[0047] Specifically, the pruning algorithm can follow the following process:

[0048] Delete VNF

[0049] while true do

[0050] Delete CN with degree 1 and its associated VN.

[0051] Delete CN with degree 2 and merge the VNH and VNCH connected to it.

[0052] Delete VNH with degree 1, and delete CN connected to it.

[0053] Delete VNHs with a degree of 2 and merge the CNs connected to them.

[0054] Delete CNs with a degree of 2 and merge the VNHs connected to them.

[0055] If the check matrix remains unchanged

[0056] return verification matrix

[0057] end if

[0058] end while

[0059] Based on a simplified bipartite factor graph, the check relationships corresponding to each check node are listed to construct the sparse check matrix of the Polar code. Among them, the sparse parity-check matrix of the Polar code. Each row corresponds to a check node (whether it's an XOR node or a copy node) in the simplified bipartite factorization graph, and each column corresponds to a variable node. When a variable node is connected to a check node, the Polar code sparse parity-check matrix... Set the corresponding element in the table to 1, otherwise set it to 0.

[0060] S13. Create a corresponding probabilistic graphical model based on the sparse parity-check matrix of the Polar code, and convert the Polar code decoding process into a message passing process between variable nodes and parity-check nodes.

[0061] Specifically, a probabilistic graphical model can be created based on the sparse parity-check matrix of a Polar code. This model can include multiple variable nodes, multiple parity-check nodes, and multiple undirected edges. Undirected edges connect variable nodes and parity-check nodes that are connected. Each variable node uniquely corresponds to a column vector in the Polar code sparse parity-check matrix, and each parity-check node uniquely corresponds to a row vector in the same matrix. If the row order in the Polar sparse parity-check matrix is ​​equal to... Column order equals If the element is 1, then the order of the first node is equal to... The order of the variable node and the second node is equal to The check nodes are connected, if the row order in the Polar code sparse check matrix is ​​equal to... Column order equals If the element is 0, then the order of the first node is equal to... The order of the variable node and the second node is equal to The verification nodes have no connection relationship. The first node's order is the sequence number of the variable node among all variable nodes, and the second node's order is the sequence number of the verification node among all verification nodes.

[0062] S2. Obtain the initial log-likelihood ratio of each variable node in the probabilistic graphical model as the initial input, i.e., obtain the initial transit message from each variable node to the verification node in the probabilistic graphical model. This can also be referred to as the initial confidence level passed from each variable node to the verification node.

[0063] This embodiment uses Binary Phase Shift Keying (BPSK) as an example to introduce the communication between the transmitter and decoder, as well as the decoding target of this embodiment. Specifically, it uses ( Taking Polar codes as an example, the code length of a Polar code is... The number of information bits is When the bitrate is fixed at 1 / 2, The sending end can transmit information in bits of 1000. The codeword is encoded into indivual Then, based on BPSK, it was modulated into a symbol And send it to the decoding end. Due to noise interference during transmission, the decoding end will receive a symbol , represented as The decoding task at the decoding end is to... indivual Restore to Thus, based on each Get the original from the sender Each code character.

[0064] Specifically, when acquiring the initial input, there are two types based on the variable node type: for VNCH nodes, based on the input received by the decoder... a symbol (i.e. Calculations are performed because a symbol Corresponding to There are 10 Channel Variable Nodes (VNCHs). Therefore, the specific formula for calculating the initial log-likelihood ratio for each VNCH is as follows:

[0065]

[0066] in, For the first The initial log-likelihood ratio of each variable node. For the first The set of sub-constellation symbols with bits 0 and 1. These are the symbols received by the decoding end. The symbols sent by the sending end. This represents noise power.

[0067] Taking BPSK as an example, let's assume the actual received signal is represented as follows: ,but .

[0068] For non-VNCH variable nodes, this invention assumes their initial log-likelihood ratio is 0, that is... ; thereby obtaining all The initial log-likelihood ratio of each variable node It can be considered as the initial message passed from the variable node to the verification node. .

[0069] The initial input can be calculated using other digital circuits, or it can be input directly from the outside without calculation. This invention does not impose any restrictions on this.

[0070] S3. Divide the in-memory compute array into regions based on the sparse parity check matrix of the Polar code to obtain the input part, output part, iteration part and parity part, and configure the resistance state of the cross nodes of each part.

[0071] Specifically, it includes the following steps:

[0072] S31. Divide the in-memory computing array into regions based on the sparse parity check matrix of the Polar code to obtain the input part, output part, iteration part and parity check part.

[0073] Among them, in-memory computing devices are integrated devices that have both storage and computing capabilities, such as resistive random access memory, phase-change memory, magnetic memory, and flash memory.

[0074] like Figure 2 As shown, assuming the Polar code sparse parity-check matrix... The number of rows and columns is The number of 1s in the sparse parity-check matrix is Therefore, when partitioning the in-memory compute array according to the codeword characteristics of the Polar code sparse parity-check matrix, the in-memory compute array can be divided into iterative parts (see...). Figure 2 The dark gray part in the in-memory computing array), the verification part (see...) Figure 2 The light gray portion of the in-memory compute array), the input portion (see...) Figure 2 (The pink part in the in-memory computing array) and the output part (see Figure 2 (The yellow part in the in-memory computing array). The iterative part is a square matrix with the number of rows and columns equal to... This refers to the number of undirected edges in the probabilistic graphical model; the validation part is concatenated with the iteration part along the column dimension, and the number of rows and columns in the validation part is the same as that in the iteration part; the output part is concatenated with the validation part along the column dimension, and the number of rows in the output part is equal to... The number of columns equals the code length. The input part is concatenated with the iteration part, the check part, and the output part from the row dimension, and the number of rows in the input part is equal to the number of all variable nodes, which is also the number of columns in the Polar code sparse check matrix. .

[0075] S32. Analyze the decoding process to determine the message passing process between variable nodes and verification nodes in the iteration part, verification part and output part of the in-memory computing array.

[0076] In this embodiment, based on the analysis of the Polar code decoding process, it can be roughly divided into two parts: first, based on the confidence level from the check node to the variable node in the previous iteration, the confidence level from the variable node to the check node and the posterior log-likelihood ratio of the variable node are calculated; second, based on the confidence level from the variable node to the check node, the confidence level from the check node to the variable node in the current iteration is calculated.

[0077] In this embodiment, the in-memory compute array is mainly used to calculate the confidence level from the variable node to the verification node and the posterior log-likelihood ratio of the variable node. Specifically, the iteration part is used to calculate the confidence level from the variable node to the verification node; the verification part is used to calculate the posterior log-likelihood ratio of the variable node after iteration; the output part is used to calculate the posterior log-likelihood ratio of the variable node, and some of its calculation results are consistent with those of the verification part. That is, each column of the output part represents the variable node corresponding to all VNCH nodes.

[0078] Based on the above analysis, the message passing process between the variable node and the verification node in the iterative part can be represented as:

[0079]

[0080] in, For variable nodes To the verification node Confidence level; For verification nodes To the variable node Confidence level; For all nodes with variables The set of connected verification nodes, i.e., variable nodes The verification relationship of the verification equations corresponding to all these verification nodes, verification nodes In the set Except for the check node Other verification nodes besides; For variable nodes The initial log-likelihood ratio.

[0081] The message passing process between variable nodes and verification nodes in the verification section can be represented as follows:

[0082]

[0083] in, For variable nodes The posterior log-likelihood ratio.

[0084] The message passing process between the variable nodes and the verification nodes in the output section is the same as that in the verification section, but it only needs to calculate the posterior log-likelihood ratio of the channel variable nodes.

[0085] S33. Represent the message transmission process of each part in the form of vector-matrix multiplication to obtain the configuration matrix corresponding to each part. After splicing the configuration matrices of each part, perform resistive configuration on the cross nodes of each part of the in-memory computing array.

[0086] In this embodiment, in order to utilize vector-matrix multiplication for computation in a memory computing array... and Simultaneously, in conjunction with the peripheral circuitry for subsequent calculations, the results of the iteration section, the verification section, and the output section need to be arranged into a vector form.

[0087] For the iteration part, firstly, each variable node needs to be... To the verification node Message delivery Arranged according to the second node order of the verification nodes, we can obtain Row vectors:

[0088]

[0089] in, For the sparse parity-check matrix of the Polar code; This refers to the order of a given variable node among all variable nodes. This refers to the order of a given check node among all check nodes. The elements in the table correspond to different variables. The node-to-node order is as follows: The confidence level of the verification node is calculated; by concatenating the row vectors, the result vector can be obtained. And vector The length is ,vector Each element in the vector represents the confidence level from a variable node to a verification node calculated using an undirected edge. In this embodiment, vectors are used respectively. and To represent vectors The node order of the variable node and check node corresponding to each element, for example, The 5th element is ,but The 5th element is , The 5th element is .

[0090] Secondly, each verification node needs to be... To the variable node confidence level Arrange them, similarly, using vectors. and To represent vectors The node order of the variable node and check node corresponding to each element is obtained. .

[0091] Finally, the message passing process between the variable nodes and the verification nodes in the above iterative part can be represented in vector-matrix multiplication form:

[0092]

[0093] in, Let the initial log-likelihood ratio vector be the matrix. Configure the function matrix for the first iteration, and The elements in are Size is ;matrix Configure the function matrix for the second iteration, and The elements in are Size is .

[0094] It can be seen that, due to vectors Depend on The arrangement is obtained, but in fact, the calculation required in formula (2) is... That is, to verify the node To the variable node The messages are excluded, only the verification nodes are retained. To the variable node The confidence level is determined by configuring the function matrix in the first iteration and the function matrix in the second iteration, in order to achieve the confidence level determined by the function matrix in the second iteration. arrive The final result vector is obtained.

[0095] Similarly, in order to perform vector-matrix multiplication computations in in-memory compute arrays... The results of the verification part also need to be arranged into a vector. The specific arrangement of the verification part is as follows: , Represents variable nodes The posterior log-likelihood ratio, It is a vector The first in Each element.

[0096] Therefore, the message passing process between variable nodes and verification nodes in the verification part can be represented by vector-matrix multiplication:

[0097]

[0098] in, To verify the configuration function matrix, and elements in Size is ,matrix Same as above.

[0099] make ,in Given the set of node orders representing channel variable nodes, the specific arrangement of the output part is as follows: , Represents variable nodes The posterior log-likelihood ratio, that is, the posterior log-likelihood ratio of the channel variable nodes that needs to be calculated in the output part.

[0100] Therefore, the message passing process between the variable nodes and the verification nodes in the output section can also be represented by vector-matrix multiplication:

[0101]

[0102] Among them, matrix Configure the function matrix for the first output, and elements in Size is ,matrix Configure the function matrix for the second output, and elements in Size is .

[0103] Finally, by concatenating the three equations from equation (5) to equation (7), we obtain:

[0104]

[0105] According to the splicing matrix The impedance state of the in-memory compute array is configured as follows: if an element in the splicing matrix has a value of 1, the corresponding cross node in the in-memory compute array is configured as a low-impedance state; if an element in the splicing matrix has a value of 0, the corresponding cross node in the in-memory compute array is configured as a high-impedance state. As input to the in-memory computing array, the load is applied, It serves as the common input for the iteration, verification, and output parts. The input to the input section yields the corresponding output. .

[0106] S4. Load the initial input into the input part of the in-memory compute array and keep it there. The initial input of other parts is 0. Calculate the initial input (that is, the initial confidence of the variable node to the verification node) using the configured in-memory compute array.

[0107] When the memory-in-memory array is a memristor, the initial input can be applied to the input part of the memory-in-memory array in the form of a voltage. This means that the input of the memory-in-memory array is set to a voltage value vector that is proportional to the initial log-likelihood ratio. Based on Kirchhoff's current law, the output in the form of current can be obtained in the column of the memory-in-memory array.

[0108] S5. Use peripheral circuits to verify and iterate the calculation results output by the iteration part, verification part and output part in the in-memory computing array, and output the final decoding result after the termination condition is met, that is, the preset number of iterations is reached or the verification condition is met.

[0109] Specifically, it includes the following steps:

[0110] S51. Design the peripheral circuitry to perform hard decision-making and verification on the calculation results output by the in-memory computing array.

[0111] In this embodiment, the peripheral circuit includes a Min module (such as...). Figure 3 The diagram shows a hard-decision module and a check module. The Min module calculates the message passing from the check node to the variable node in the iterative output and re-inputs the result into the iterative part in analog form. The hard-decision module performs a hard decision on the posterior log-likelihood ratio of each variable node output from the check part; if <0, it determines 1 (high level); if >0, it determines 0 (low level), and outputs the hard-decision result to the check module. The check module performs an XOR operation on the hard-decision result; if the result is 0, it represents the check condition (i.e., ...). , If the modulo operation is satisfied, the decoding iteration stops, and a hard decision is made on the posterior log-likelihood ratio of each variable node in the output part. The decision result is then output as the final decoding result. .

[0112] In this embodiment, since the outputs of variable nodes in the same verification equation are arranged in adjacent positions, they are connected to the same Min module, which performs the minimum sum operation. Specifically, the Min module has a multiple-input multiple-output structure. The level of each output is the product of the sign of the other output levels, multiplied by the minimum modulus of the other output levels, and then scaled by a resistor to achieve a coefficient. This completes the calculation of the confidence level from the verification node to the variable node.

[0113]

[0114] in, For verification nodes To the variable node Confidence level; These are normalization coefficients used to scale or weight the confidence level of the check node updates. The introduction of normalization coefficients aims to improve the performance of the Min-Sum decoding algorithm, making the minimum sum approximation closer to the accurate signal processing algorithm. For variable nodes To the verification node Confidence level; For all nodes with verification The set of connected variable nodes, that is, these variable nodes all belong to the first... Verification equations.

[0115] Alternatively, the verification module can be replaced by the following scheme: First, a cascaded multiplier is used to multiply the posterior log-likelihood ratios of all variable nodes. Then, a comparator is used to determine the output of the cascaded multiplier. If it is greater than 0, a low level is output; otherwise, a high level is output. The high or low level of the output determines whether the verification condition is met.

[0116] S52. After loading the initial input, the hard-decision module performs hard-decision on the posterior log-likelihood ratio of each variable node output by the verification section, and the verification module verifies the codeword after the hard-decision. If the termination condition is met, the iteration stops, and the final decoding result is output. Otherwise, proceed to step S52.

[0117] S53. Load the posterior log-likelihood ratio of each variable node output by the iteration part into the Min module, use the Min module to calculate the message passing from the verification node to the variable node, and input the calculation result back into the iteration part to complete the iteration.

[0118] S54. Repeat step S53. Stop iterating if the maximum set number of iterations is reached or the verification condition is met. Output the final decoding result. .

[0119] Example 2

[0120] Based on the Polar code decoding analog circuit implementation method based on in-memory computing provided in Embodiment 1, this embodiment provides a Polar code decoding analog circuit implementation system based on in-memory computing, which includes:

[0121] The preprocessing unit is used to construct a bipartite factor graph based on the received Polar code, and to prune and optimize redundant nodes in the bipartite factor graph to obtain the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model.

[0122] The initialization unit is used to obtain the initial log-likelihood ratio of each variable node in the probabilistic graphical model as the initial input;

[0123] The in-memory computing array configuration unit is used to divide the in-memory computing array into regions, namely the input part, output part, iteration part and parity part, according to the Polar code sparse parity matrix, and to configure the resistance state of the cross nodes of each part.

[0124] The loading unit is used to load the initial input into the input section of the in-memory compute array and keep it thereafter, while the initial input of other sections is 0;

[0125] The iterative output unit is used to verify and iteratively calculate the calculation results output by the iterative part, the verification part and the output part in the in-memory computing array using the peripheral circuit, and outputs the final decoding result after the termination condition is met, that is, the preset number of iterations is reached or the verification condition is met.

[0126] Furthermore, the preprocessing unit includes:

[0127] The binary factor graph construction module is used to construct a binary factor graph based on the polarization encoding method of the received Polar code.

[0128] The pruning optimization module is used to prune redundant nodes in the bipartite factor graph to reduce redundancy and obtain the Polar code sparse parity-check matrix.

[0129] The probabilistic graphical model creation module is used to create a corresponding probabilistic graphical model based on the sparse parity-check matrix of the Polar code, and to convert the Polar code decoding process into a message passing process between variable nodes and parity-check nodes. The variable nodes include channel variable nodes and non-signal variable nodes.

[0130] Furthermore, the in-memory computing array configuration unit includes:

[0131] The region partitioning module is used to partition the in-memory computing array into regions based on the sparse parity check matrix of the Polar code, resulting in the input part, output part, iteration part, and check part.

[0132] The message passing process determination module is used to analyze the decoding process and determine the message passing process of the iterative part, the verification part and the output part in the in-memory computing array.

[0133] The resistive configuration module is used to represent the message transmission process of each part in the form of vector-matrix multiplication, obtain the configuration matrix corresponding to each part, and then concatenate the configuration matrices of each part to perform resistive configuration on the cross nodes of each part of the in-memory computing array.

[0134] Furthermore, the iterative output unit includes:

[0135] The peripheral circuit design module is used to design the peripheral circuit, which includes a Min module, a hard decision module, and a verification module. The Min module calculates the message passing from the verification node to the variable node output by the iterative part and inputs the calculation result back into the iterative part in analog form. The hard decision module performs a hard decision on the posterior log-likelihood ratio of each variable node output by the verification part. If <0, it is decided as 1; if >0, it is decided as 0. The hard decision result is then output to the verification module. The verification module performs an XOR operation on the hard decision result. If the result is 0, it means that the verification condition is met. At this time, the decoding iteration stops, and the hard decision module performs a hard decision on the posterior log-likelihood ratio of each variable node in the output part, and outputs the decision result as the final decoding result.

[0136] The decision verification module is used to perform hard decision on the posterior log-likelihood ratio of each variable node output by the verification part after loading the initial input or updating the transmission message using the hard decision module, and to verify the codeword after hard decision using the verification module. If the verification condition is met, the iteration stops and the final decoding result is output; otherwise, the iteration module is entered.

[0137] The iteration module is used to load the posterior log-likelihood ratio of each variable node output by the iteration part into the Min module. The Min module is used to calculate the message passing from the verification node to the variable node, and the calculation result is input back into the iteration part to complete the iteration.

[0138] The output module stops iteration when a preset number of iterations is reached or a verification condition is met, and outputs the final decoding result. .

[0139] Example 3

[0140] This embodiment provides a processing device corresponding to the Polar code decoding analog circuit implementation method based on in-memory computing provided in Embodiment 1. The processing device can be applied to client processing devices, such as mobile phones, laptops, tablets, desktop computers, etc., to execute the method of Embodiment 1.

[0141] The processing device includes a processor, a memory, a communication interface, and a bus. The processor, memory, and communication interface are connected via the bus to enable communication between them. The memory stores computer programs that can run on the processing device. When the processing device runs the computer program, it executes the Polar code decoding analog circuit implementation method based on a memory-based computing device provided in Embodiment 1.

[0142] In some implementations, the memory may be high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device.

[0143] In other implementations, the processor can be any type of general-purpose processor, such as a central processing unit (CPU) or a digital signal processor (DSP), and there is no limitation here.

[0144] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0145] Those skilled in the art will understand that the structure of the above-described computing device is only a partial structure related to the present invention and does not constitute a limitation on the computing device to which the present invention is applied. A specific computing device may include more or fewer components, or combine certain components, or have different component arrangements.

[0146] Example 4

[0147] This embodiment provides a computer program product corresponding to the Polar code decoding analog circuit implementation method based on a memory computing device provided in Embodiment 1. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing the Polar code decoding analog circuit implementation method based on a memory computing device described in Embodiment 1 are loaded.

[0148] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination thereof.

[0149] The computer-readable storage medium provided in the above embodiments has a similar implementation principle and technical effect to the above method embodiments, and will not be described again here.

[0150] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0151] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0152] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for implementing a Polar code decoding analog circuit based on a memory computing device, characterized in that, include: A bipartite factor graph is constructed based on the received Polar code, and redundant nodes in the bipartite factor graph are pruned and optimized to obtain the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model. Obtain the initial log-likelihood ratio for each variable node in the probabilistic graphical model as the initial input; The in-memory compute array is divided into input, output, iterative, and parity parts based on the sparse parity check matrix of the Polar code, and the resistance state of the cross nodes of each part is configured. The initial input is loaded into the input section of the in-memory compute array and held thereafter, while the initial input for the other sections is 0. The calculation results output by the iterative part, the verification part and the output part of the in-memory computing array are verified and iteratively calculated using peripheral circuits, and the final decoding result is output when the termination condition is met. The step of constructing a bipartite factor graph based on the received Polar code and pruning redundant nodes in the bipartite factor graph to obtain the Polar code sparse parity-check matrix and the corresponding probabilistic graphical model includes: Construct a bipartite factor graph based on the polarization encoding scheme of the received Polar code; Redundancy is reduced by pruning redundant nodes in the bipartite factor graph to obtain the sparse parity-check matrix of the Polar code. Based on the sparse parity-check matrix of the Polar code, a corresponding probabilistic graphical model is created, and the Polar code decoding process is transformed into a message passing process between variable nodes and parity-check nodes. The variable nodes include channel variable nodes and non-channel variable nodes. The process of dividing the in-memory compute array into input, output, iterative, and parity parts based on the Polar code sparse parity-check matrix, and configuring the resistance states of the cross nodes of each part, includes: The in-memory computing array is divided into regions based on the sparse parity check matrix of the Polar code, resulting in the input part, output part, iteration part, and parity check part. The decoding process is analyzed to determine the message passing process between variable nodes and verification nodes in the iterative part, verification part, and output part of the in-memory computing array. The message passing process between variable nodes and verification nodes in each part is represented in the form of vector-matrix multiplication to obtain the configuration matrix corresponding to each part. After concatenating the configuration matrices of each part, the cross nodes of each part of the in-memory computing array are configured in a resistive state.

2. The method for implementing a Polar code decoding analog circuit based on a memory computing device as described in claim 1, characterized in that, The in-memory compute array is divided into regions based on the sparse parity-check matrix of the Polar code, resulting in an input section, an output section, an iteration section, and a parity section, including: Assuming a sparse parity-check matrix for Polar codes The number of rows and columns is The number of 1s in the sparse parity-check matrix is ,but: The iterative portion is configured as a square matrix, with the number of rows and columns equal to... ; The verification part is concatenated with the iteration part along the column dimension, and the number of rows and columns of the verification part is equal to the number of columns. ; The output portion is concatenated with the validation portion along the column dimension, and the number of rows in the output portion is equal to... The number of columns equals the code length. ; The input portion is concatenated with the iteration portion, the validation portion, and the output portion along the row dimension, and the number of rows in the input portion is equal to... .

3. The method for implementing a Polar code decoding analog circuit based on a memory computing device as described in claim 1, characterized in that, The message passing process between the variable node and the verification node in the iterative part is represented as follows: in, For variable nodes To the verification node Confidence level; For verification nodes To variable node Confidence level; For all nodes with variables The set of connected check nodes, variable nodes The verification relationship of the verification equations corresponding to all these verification nodes, verification nodes In the set Except for the check node Other verification nodes besides; For variable nodes The initial log-likelihood ratio; The message passing process between variable nodes and verification nodes in the verification section is represented as follows: in, For variable nodes The posterior log-likelihood ratio; The output section is the same as the verification section, but it only needs to calculate the posterior log-likelihood ratio of the channel variable nodes.

4. The method for implementing a Polar code decoding analog circuit based on a memory computing device as described in claim 3, characterized in that, The process of message passing between variable nodes and verification nodes in each part is represented in the form of vector-matrix multiplication to obtain the configuration matrix corresponding to each part. After concatenating the configuration matrices corresponding to each part, the cross nodes of each part of the in-memory computing array are configured in a resistive state, including: First, the message passing process between variable nodes and verification nodes in each part is equivalently converted into a vector-matrix multiplication form; The message passing process between the variable node and the verification node in the iterative part can be represented in vector-matrix multiplication form as follows: in, ,vector Each element in the algorithm represents the confidence level from a variable node to a check node calculated using an undirected edge. To the verification node confidence level The nodes are arranged in the order of the verification nodes, and are represented as follows: in, For the sparse parity-check matrix of the Polar code, This refers to the order of a given variable node among all variable nodes. This refers to the order of a given check node among all check nodes. The elements in the table correspond to different variables. The node-to-node order is as follows: The confidence level of the verification node; By verifying each node To variable node confidence level By arranging, and For vectors The node sequence of variable nodes and check nodes corresponding to each element in the table. and They are vectors and The first in One element, For verification nodes To variable node Confidence level; Let be the initial log-likelihood ratio vector. For variable nodes The initial log-likelihood ratio; matrix Configure the function matrix for the first iteration, and The elements in are Size is ;matrix Configure the function matrix for the second iteration, and The elements in are Size is ; The message passing process between variable nodes and verification nodes in the verification section can be represented in vector-matrix multiplication form as follows: in, The matrix is ​​obtained by arranging the outputs of the verification section. To verify the configuration function matrix, and elements in Size is ; make ,in Given the set of node orders representing channel variable nodes, the message passing process between variable nodes and check nodes in the output section can be represented in vector-matrix multiplication form as follows: in, The matrix is ​​obtained by arranging the outputs of the output section. Configure the function matrix for the first output, and elements in Size is ,matrix Configure the function matrix for the second output, and elements in Size is ; Next, the matrices corresponding to each part are concatenated to obtain: in, To splice the matrix; Finally, the impedance states of the cross nodes of each part of the in-memory computing array are configured according to the splicing matrix. When an element in the splicing matrix has a value of 1, the corresponding cross node in the in-memory computing array is configured as a low impedance state, and when an element in the splicing matrix has a value of 0, the corresponding cross node in the in-memory computing array is configured as a high impedance state.

5. The method for implementing a Polar code decoding analog circuit based on a memory computing device as described in claim 3, characterized in that, The process of using peripheral circuits to verify and iteratively calculate the calculation results output by the iterative and output parts of the in-memory computing array, and outputting the final decoding result when the termination condition is met, includes: ① Design the peripheral circuitry; The peripheral circuitry includes a Min module, a hard decision module, and a verification module. The Min module is used to calculate the confidence level from the verification node to the variable node output by the iteration part, and input the calculation result back into the iteration part in the form of an analog quantity; The hard decision module is used to make a hard decision on the posterior log-likelihood ratio of each variable node output by the verification part. If <0, it is decided as 1; if >0, it is decided as 0. The hard decision result is then output to the verification module. The verification module performs an XOR operation on the hard-decision results. If the result is 0, it indicates that the verification condition is met. At this point, the decoding iteration stops. The hard-decision module then performs a hard decision on the posterior log-likelihood ratio of each variable node in the output part, and outputs the decision result as the final decoding result. ; ② The hard-decision module performs hard-decision analysis on the posterior log-likelihood ratio of each variable node output by the verification part after loading the initial input or updating the confidence level. The verification module then verifies the codewords after the hard-decision analysis. If the verification conditions are met, the iteration stops, and the final decoding result is output. Otherwise proceed to step ③; ③ Load the posterior log-likelihood ratio of each variable node output by the iteration part into the Min module, use the Min module to calculate the confidence from the verification node to the variable node, and input the calculation result back into the iteration part to complete the iteration; The Min module contains the following calculation formula: in, For verification nodes To the variable node Confidence level; These are the normalization coefficients; For variable nodes To the verification node Confidence level; For all nodes with verification The set of connected variable nodes; ④ Repeat steps ② to ③. If the preset number of iterations is reached or the verification condition is met, stop the iteration and output the final decoding result. .

6. A Polar code decoding analog circuit implementation system based on a memory computing device, characterized in that, include: The preprocessing unit is used to construct a bipartite factor graph based on the received Polar code, and to prune and optimize redundant nodes in the bipartite factor graph to obtain the sparse parity-check matrix of the Polar code and the corresponding probabilistic graphical model. The initialization unit is used to obtain the initial log-likelihood ratio of each variable node in the probabilistic graphical model as the initial input; The in-memory computing array configuration unit is used to divide the in-memory computing array into regions, namely the input part, output part, iteration part and parity part, according to the Polar code sparse parity matrix, and to configure the resistance state of the cross nodes of each part. The loading unit is used to load the initial input into the input section of the in-memory compute array and keep it thereafter, while the initial input of other sections is 0; The iterative output unit is used to verify and iteratively calculate the calculation results output by the iterative part, the verification part and the output part in the in-memory computing array using the peripheral circuit, and output the final decoding result when the termination condition is met. The step of constructing a bipartite factor graph based on the received Polar code and pruning redundant nodes in the bipartite factor graph to obtain the Polar code sparse parity-check matrix and the corresponding probabilistic graphical model includes: Construct a bipartite factor graph based on the polarization encoding scheme of the received Polar code; Redundancy is reduced by pruning redundant nodes in the bipartite factor graph to obtain the sparse parity-check matrix of the Polar code. Based on the sparse parity-check matrix of the Polar code, a corresponding probabilistic graphical model is created, and the Polar code decoding process is transformed into a message passing process between variable nodes and parity-check nodes. The variable nodes include channel variable nodes and non-channel variable nodes. The process of dividing the in-memory compute array into input, output, iterative, and parity parts based on the Polar code sparse parity-check matrix, and configuring the resistance states of the cross nodes of each part, includes: The in-memory computing array is divided into regions based on the sparse parity check matrix of the Polar code, resulting in the input part, output part, iteration part, and parity check part. The decoding process is analyzed to determine the message passing process between variable nodes and verification nodes in the iterative part, verification part, and output part of the in-memory computing array. The message passing process between variable nodes and verification nodes in each part is represented in the form of vector-matrix multiplication to obtain the configuration matrix corresponding to each part. After concatenating the configuration matrices of each part, the cross nodes of each part of the in-memory computing array are configured in a resistive state.

7. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any of the methods in the Polar code decoding analog circuit implementation method based on a memory computing device as described in claims 1 to 5.

8. A computing device, characterized in that, include: One or more processors and a memory, wherein the memory stores one or more programs and is configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods in the Polar code decoding analog circuit implementation method based on in-memory computing as described in claims 1 to 5.

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