Method for selective growth of base regions in germanium-silicon heterojunction transistors

Abstract

The application discloses a method for selectively growing an inner base region of a germanium-silicon heterojunction transistor, which comprises the following steps: sequentially depositing a first dielectric layer, an outer base region polysilicon layer, a second dielectric layer and a third dielectric layer on a silicon substrate, and etching to form an inner base region window; forming a fourth dielectric layer on the inner sidewall of the inner base region window; partially etching the first dielectric layer at the bottom of the inner base region window; etching to obtain an inner base region growth window; and sequentially growing a Si buffer layer, a SiGe base region layer and a Si cap layer in the inner base region growth window. In the application, the SiGe epitaxial inner base region is selectively grown in a self-aligned manner, so that a smaller inner base region area and a more stable connection effect between the inner base region and the outer base region can be realized, and the frequency characteristics and stability of the SiGe heterojunction transistor are further improved, so that the application technical field with more extensive and higher requirements is met, and the electrical performance of a chip is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing processes, and in particular relates to a method for selectively growing the inner base region of a germanium-silicon heterojunction transistor. Background Technology

[0002] SiGe bipolar and SiGe BiCMOS processes replace silicon-doped base regions with Ge-Si materials (e.g., Si) by introducing SiGe heterojunction technology. 1-X Ge X The formation of SiGe heterojunction transistors (SiGe HBTs) significantly improves the high-frequency and noise characteristics of bipolar transistors compared to conventional silicon-based bipolar and BiCMOS processes, making them widely used in high-speed and low-noise applications such as high-speed amplifiers, RF amplifiers, logarithmic amplifiers, and low-noise amplifiers. SiGe epitaxial base region growth, with its high mobility and low-noise material properties, is a key technology for SiGe bipolar and SiGe BiCMOS processes. While selective SiGe epitaxial growth is more challenging than non-selective SiGe epitaxial growth, its unique self-aligned growth method can reduce device size, lower contact resistance between inner and outer base regions, and reduce parasitic junction capacitance, thereby further optimizing and improving device performance. Therefore, it is necessary to develop a process for selectively growing the inner base region of SiGe heterojunction transistors to improve the frequency characteristics of SiGe HBT devices. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method for selectively growing the inner base region of a germanium-silicon heterojunction transistor.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0005] A method for selectively growing the inner base region of a germanium-silicon heterojunction transistor includes the following steps:

[0006] S100. Take a silicon substrate, wherein at least two field oxygen isolation regions are formed between the internal spaces of the silicon substrate, and a first dielectric layer, an outer base region polysilicon layer, a second dielectric layer and a third dielectric layer are sequentially deposited on the silicon substrate.

[0007] S200, the third dielectric layer, the second dielectric layer, and the outer base region polysilicon layer are etched downwards to form an inner base region window, and a fourth dielectric layer is formed on the inner sidewall of the inner base region window; the inner base region window is located in the region between two adjacent field oxygen isolation regions;

[0008] S300. Anisotropic dry etching is used to partially etch the first dielectric layer at the bottom of the inner base region window, while retaining a first dielectric layer of predetermined thickness at the bottom of the inner base region window.

[0009] S400. The first dielectric layer at the bottom of the inner base region window is etched by wet etching to expose a flat silicon substrate surface, thereby obtaining the inner base region growth window; the two ends of the inner base region growth window extend outward to below the polycrystalline silicon layer of the outer base region.

[0010] S500, Si buffer layer, SiGe base region layer and Si capping layer are selectively grown sequentially inside the growth window of the inner base region.

[0011] Furthermore, the first dielectric layer is made of silicon oxide, the outer base region polycrystalline silicon layer is made of highly doped polycrystalline silicon, the second dielectric layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, the third dielectric layer is made of silicon nitride, and the fourth dielectric layer is made of silicon nitride.

[0012] Furthermore, in step S300, the silicon substrate is first annealed in a furnace tube at 800°C to 900°C to densify the first dielectric layer.

[0013] Furthermore, the deposition thickness of the first dielectric layer is 150nm to 300nm. In step S300, the predetermined thickness of the first dielectric layer retained at the bottom of the inner base region window after dry etching is 20nm to 100nm; and the predetermined thickness of the first dielectric layer retained at the bottom of the inner base region window is less than half of the original deposition thickness.

[0014] Furthermore, the growth thickness of the Si buffer layer is 20nm to 40nm, the growth thickness of the SiGe base layer is 60nm to 120nm, and the growth thickness of the Si capping layer is 40nm to 80nm.

[0015] Furthermore, step S500 includes the following sub-steps:

[0016] S510. Place the silicon substrate with the inner base region growth window formed in the epitaxial equipment, form a vacuum environment and remove the native oxide layer of the inner base region growth window;

[0017] S520. A gaseous Si source is introduced into the epitaxial device, and a Si buffer layer is selectively grown at the bottom of the growth window in the inner base region.

[0018] S530. In the epitaxial equipment, a gaseous Si source and a gaseous Ge source are introduced, and a SiGe base layer is selectively grown on the Si buffer layer.

[0019] S540. A gaseous Si source is introduced into the epitaxial device to selectively grow a Si capping layer on the SiGe base layer, thereby forming the inner base region.

[0020] Furthermore, in step S510, the growth window of the inner base region is rapidly baked at 850°C to 950°C using H2 gas to remove the natural oxide layer of the growth window of the inner base region.

[0021] Furthermore, in step S520, at a growth temperature of 850°C to 900°C, SiH2Cl2 gas is used as a Si source to grow the Si buffer layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

[0022] Furthermore, in step S530, at a growth temperature of 750°C to 800°C, SiH2Cl2 gas and GeH4 gas are used as Si source and Ge source, respectively, to grow the SiGe base layer, and HCl gas with a flow rate of 120 sccm to 240 sccm is used to suppress Si nucleation in the second and third dielectric layers.

[0023] Furthermore, in step S540, at a growth temperature of 850°C to 900°C, SiH2Cl2 gas is used as the Si source to grow the Si capping layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

[0024] In this invention, by setting reasonable process conditions for different SiGe epitaxial layers, selective growth of SiGe epitaxial layers on silicon and polysilicon layers is achieved in a specific window structure of SiGe heterojunction transistors, thereby realizing the self-aligned fabrication of the SiGe base region. Compared with non-selective SiGe epitaxial growth processes, selective SiGe epitaxial growth processes are more difficult. Conventional SiGe bipolar processes and SiGe BiCMOS processes mainly use non-selective SiGe epitaxial growth processes. The process method provided by this invention selectively grows the SiGe epitaxial inner base region based on self-alignment, which can achieve a smaller inner base region area and a more stable connection effect between the inner and outer base regions, further improving the frequency characteristics and stability of SiGe heterojunction transistors to meet the needs of a wider range of higher-demand application fields and improve the electrical performance of chips. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0026] Figure 1 This is a flowchart of an embodiment of the method for selectively growing the inner base region of a germanium-silicon heterojunction transistor according to the present invention.

[0027] Figure 2 This is a schematic diagram of the structure after forming a first dielectric layer, an outer base region polycrystalline silicon layer, a second dielectric layer, and a third dielectric layer on a silicon substrate.

[0028] Figure 3 This is a schematic diagram of the structure after the formation of the inner base region window and the fourth dielectric layer.

[0029] Figure 4 This is a schematic diagram of the structure after partially etching the first dielectric layer.

[0030] Figure 5 This is a schematic diagram of the structure after the growth window of the inner base region has been formed.

[0031] Figure 6 This is a schematic diagram of the structure after the Si buffer layer is formed.

[0032] Figure 7 This is a schematic diagram of the structure after the SiGe base layer is formed.

[0033] Figure 8 This is a schematic diagram of the structure after the Si capping layer is formed.

[0034] The diagrams in the instruction manual are labeled as follows:

[0035] Silicon substrate-1; field oxygen isolation region-2; first dielectric layer-3; outer base region polycrystalline silicon layer-4; second dielectric layer-5; third dielectric layer-6; fourth dielectric layer-7; Si buffer layer-11; SiGe base region layer-12; Si capping layer-13; inner base region window-8; inner base region growth window-9. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] like Figure 1 As shown, a preferred embodiment of a method for selectively growing the inner base region of a germanium-silicon heterojunction transistor includes the following steps:

[0038] S100, such as Figure 2As shown, a silicon substrate 1 is taken, and at least two field oxygen isolation regions 2 are formed internally between the silicon substrate 1. A first dielectric layer 3, an outer base region polycrystalline silicon layer 4, a second dielectric layer 5, and a third dielectric layer 6 are sequentially deposited on the silicon substrate 1. The first dielectric layer 3, the second dielectric layer 5, and the third dielectric layer 6 are not limited in material and growth method, as long as the process of this embodiment can be realized. For example, the first dielectric layer 3 can be made of silicon oxide, the second dielectric layer 5 can be made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, and the third dielectric layer 6 can be made of silicon nitride. This step may include the following sub-steps:

[0039] S110. A first dielectric layer 3 is formed on the silicon substrate 1 by depositing silicon oxide, wherein the deposition thickness of the first dielectric layer 3 is preferably 150 nm to 300 nm.

[0040] S120. An outer base region polysilicon layer 4 is formed on the first dielectric layer 3 by depositing polysilicon. The outer base region polysilicon layer 4 is used to form the outer base region of a transistor device. The outer base region polysilicon layer 4 uses highly doped polysilicon to reduce the resistance of the outer base region. It can be formed by in-situ doping of polysilicon deposition, or by depositing polysilicon in a conventional manner followed by impurity implantation and annealing.

[0041] S130, A second dielectric layer 5 is formed on the outer base region polycrystalline silicon layer 4 by depositing silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

[0042] S140. A third dielectric layer 6 is formed on the second dielectric layer 5 by depositing silicon nitride.

[0043] S200, such as Figure 3 As shown, the third dielectric layer 6, the second dielectric layer 5, and the outer base region polysilicon layer 4 are etched downwards to form the inner base region window 8. The inner base region window 8 is located in the region between two adjacent field oxide isolation regions 2. The inner base region window 8 can be formed by etching using processes such as photolithography. The specific process is a conventional technique and will not be described in detail here.

[0044] Subsequently, a fourth dielectric layer 7 is formed on the inner sidewall of the inner base region window 8. The fourth dielectric layer 7 is not limited to any particular material or growth method, as long as the process of this embodiment can be implemented. For example, the fourth dielectric layer 7 can be made of silicon nitride. The method for forming the fourth dielectric layer 7 on the inner sidewall of the inner base region window 8 can be as follows: first, silicon nitride is deposited as a whole to form the fourth dielectric layer 7, and then the fourth dielectric layer 7 at the bottom of the inner base region window 8 is etched away, while the fourth dielectric layer 7 on the inner sidewall of the inner base region window 8 is retained; the fourth dielectric layer 7 outside the inner base region window 8 is generally also removed simultaneously.

[0045] The fourth dielectric layer 7 at the bottom of the inner base region window 8 can be removed by anisotropic etching back. This allows the fourth dielectric layer 7 on the sidewall of the inner base region window 8 to be retained while removing the fourth dielectric layer 7 at the bottom of the inner base region window 8. This prevents the second dielectric layer 5 outside the inner base region window 8 from being damaged during subsequent wet etching of the first dielectric layer 3 in the inner base region window 8. It also prevents the sidewall of the outer base region polysilicon layer 4 from being grown during the selective growth of the Si buffer layer 11, SiGe base region layer 12, and Si capping layer 13 in the inner base region growth window 9, which would damage the window morphology and affect subsequent processes.

[0046] S300, such as Figure 4 As shown, anisotropic dry etching is used to partially etch the first dielectric layer 3 at the bottom of the inner base region window 8, leaving a first dielectric layer 3 of a predetermined thickness at the bottom of the inner base region window 8. In this S300 step, the predetermined thickness of the first dielectric layer 3 retained at the bottom of the inner base region window 8 after dry etching is preferably 20nm to 100nm; and the predetermined thickness of the first dielectric layer 3 retained at the bottom of the inner base region window 8 is less than half of the original deposition thickness.

[0047] In this step, the silicon substrate 1 can be annealed in a furnace tube at 800℃~900℃ to densify the first dielectric layer 3, thereby improving the density of the first dielectric layer 3. This prevents the etching rate of the first dielectric layer 3 from being too fast and unstable during the subsequent wet etching of the fourth dielectric layer 7 in the inner base region window 8, which would cause abnormal morphology at the end of the inner base region growth window 9. It can also improve the flatness of the silicon substrate 1 at the bottom of the inner base region window 8, as well as the relatively steep sidewall morphology of the first dielectric layer 3 at the two ends of the inner base region growth window 9, which is beneficial to the growth effect of the Si buffer layer 11, the SiGe base region layer 12, and the Si capping layer 13.

[0048] Before wet etching, anisotropic dry etching is used to partially etch the first dielectric layer 3. This maximizes the contact area between the sidewalls of the first dielectric layer 3 and the etching solution in the inner base region window 8, improving the sidewall morphology of the first dielectric layer 3 at the relatively steep ends of the inner base region growth window 9 after wet etching. This also benefits the growth of the Si buffer layer 11, the SiGe base layer 12, and the Si capping layer 13. Simultaneously, a certain thickness of the first dielectric layer 3 is retained to prevent damage to the silicon substrate 1.

[0049] S400, such as Figure 5As shown, the first dielectric layer 3 at the bottom of the inner base region window 8 is etched using wet etching to expose a flat silicon substrate 1 surface, resulting in an ideal inner base region growth window 9 for SiGe self-aligned selective growth. In this step, an HF solution with a ratio of 7:1 to 50:1 can be used for wet etching. The inner base region growth window 9 extends outwards at both ends to below the outer base region polysilicon layer 4, and the ends of the inner base region growth window 9 have relatively steep sidewall morphologies of the first dielectric layer 3.

[0050] S500, Si buffer layer 11, SiGe base layer 12, and Si capping layer 13 are selectively grown sequentially inside the growth window 9 in the inner base region. This step may include the following sub-steps:

[0051] S510. The silicon substrate 1 after the formation of the inner base region growth window 9 is placed in an epitaxial device to form a vacuum environment and remove the native oxide layer of the inner base region growth window 9. In this embodiment, H2 gas is used to rapidly bake the inner base region growth window 9 at 850°C to 950°C to remove the native oxide layer of the inner base region growth window 9.

[0052] S520, such as Figure 6 As shown, a gaseous Si source is introduced into the epitaxial device, and a Si buffer layer 11 is selectively grown at the bottom of the growth window 9 in the inner base region; the growth thickness of the Si buffer layer 11 is preferably 20 nm to 40 nm. In this embodiment, SiH2Cl2 gas is used as the Si source to grow the Si buffer layer 11, so as to achieve stable growth of the Si buffer layer 11 inside the growth window 9 in the inner base region; and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second dielectric layer 5 and the third dielectric layer 6. In this step, a growth temperature of 850℃ to 900℃ is used to achieve stable growth of the Si buffer layer 11 at the end of the growth window 9 in the inner base region.

[0053] S530, such as Figure 7 As shown, a gaseous Si source and a gaseous Ge source are introduced into the epitaxial device, and a SiGe base layer 12 is selectively grown on the Si buffer layer 11; the growth thickness of the SiGe base layer 12 is preferably 60 nm to 120 nm. In this embodiment, SiH2Cl2 gas and GeH4 gas are used as the Si source and Ge source, respectively, for the growth of the SiGe base layer 12, and HCl gas with a flow rate of 120 sccm to 240 sccm is used to suppress Si nucleation in the second dielectric layer 5 and the third dielectric layer 6. A growth temperature of 750℃ to 800℃ is used in this step to achieve stable growth of the SiGe base layer 12 at the end of the inner base region growth window 9.

[0054] S540, such as Figure 8As shown, a gaseous Si source is introduced into the epitaxial device, and a Si capping layer 13 is selectively grown on the SiGe base layer 12 to form the inner base region. The growth thickness of the Si capping layer 13 is preferably 40 nm to 80 nm. Since the thickness of the first dielectric layer 3 is reduced after densification by annealing, the Si buffer layer 11, the SiGe base layer 12, and the Si capping layer 13 will fill the inner base region growth window 9.

[0055] In this embodiment, SiH2Cl2 gas is used as the Si source for the growth of the Si capping layer 13 to achieve selective growth of the Si capping layer 13 on the SiGe base layer 12; and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second dielectric layer 5 and the third dielectric layer 6. A growth temperature of 850℃ to 900℃ is used in this step to achieve stable growth of the Si capping layer 13 at the end of the growth window 9 in the inner base region.

[0056] The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor in this embodiment has at least the following advantages:

[0057] (1) By introducing the third dielectric layer 6 and the fourth dielectric layer 7, the second dielectric layer 5 and the outer base region polysilicon layer 4 are blocked, thus avoiding damage to the second dielectric layer 5 during wet etching of the first dielectric layer 3, and growth on the sidewall of the outer base region polysilicon layer 4 during SiGe selective growth.

[0058] (2) The first dielectric layer 3 is etched by anisotropic dry etching and low-ratio HF solution wet etching, which further optimizes the etching rate of the first dielectric layer 3 at different positions at the end of the inner base region growth window 9. This results in a relatively steep sidewall morphology of the first dielectric layer 3, forming a more ideal inner base region growth window 9, which is beneficial to the effective connection between the outer base region polysilicon layer 4 and the selective SiGe inner base region.

[0059] (3) Using an appropriate flow rate of HCl gas, self-aligned selective growth can be achieved in the growth window 9 of the inner base region, further reducing the base region size and lowering the parasitic junction capacitance.

[0060] (4) By using SiH2Cl2 gas and GeH4 gas as Si source and Ge source respectively, the Si buffer layer 11 can be grown at 850℃ to 900℃, the SiGe base layer 12 at 750℃ to 800℃, and the Si capping layer 13 at 850℃ to 900℃, forming a more ideal SiGe growth connection between the outer base region polycrystalline silicon layer 4 and the silicon substrate, reducing the contact resistance between the outer base region and the inner base region, and improving the frequency characteristics of the SiGe HBT device.

[0061] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for selectively growing the inner base region of a germanium-silicon heterojunction transistor, characterized in that, Includes the following steps: S100. Take a silicon substrate, wherein at least two field oxygen isolation regions are formed between the internal spaces of the silicon substrate, and a first dielectric layer, an outer base region polysilicon layer, a second dielectric layer and a third dielectric layer are sequentially deposited on the silicon substrate. S200, the third dielectric layer, the second dielectric layer, and the outer base region polysilicon layer are etched downwards to form an inner base region window, and a fourth dielectric layer is formed on the inner sidewall of the inner base region window; the inner base region window is located in the region between two adjacent field oxygen isolation regions; S300. Anisotropic dry etching is used to partially etch the first dielectric layer at the bottom of the inner base region window, while retaining a first dielectric layer of predetermined thickness at the bottom of the inner base region window. S400. The first dielectric layer at the bottom of the inner base region window is etched by wet etching to expose a flat silicon substrate surface, thereby obtaining the inner base region growth window; the two ends of the inner base region growth window extend outward to below the polycrystalline silicon layer of the outer base region. S500, Si buffer layer, SiGe base region layer and Si capping layer are selectively grown sequentially inside the growth window of the inner base region.

2. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 1, characterized in that: The first dielectric layer is made of silicon oxide, the outer base region polycrystalline silicon layer is made of highly doped polycrystalline silicon, the second dielectric layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, the third dielectric layer is made of silicon nitride, and the fourth dielectric layer is made of silicon nitride.

3. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 1, characterized in that: In step S300, the silicon substrate is first annealed in a furnace tube at 800°C to 900°C to densify the first dielectric layer.

4. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 1, characterized in that: The deposition thickness of the first dielectric layer is 150nm to 300nm. In step S300, the predetermined thickness of the first dielectric layer retained at the bottom of the inner base region window after dry etching is 20nm to 100nm; and the predetermined thickness of the first dielectric layer retained at the bottom of the inner base region window is less than half of the original deposition thickness.

5. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 1, characterized in that: The growth thickness of the Si buffer layer is 20nm to 40nm, the growth thickness of the SiGe base layer is 60nm to 120nm, and the growth thickness of the Si capping layer is 40nm to 80nm.

6. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in any one of claims 1 to 5, characterized in that, The S500 step includes the following sub-steps: S510. Place the silicon substrate with the inner base region growth window formed in the epitaxial equipment, form a vacuum environment and remove the native oxide layer of the inner base region growth window; S520. A gaseous Si source is introduced into the epitaxial device, and a Si buffer layer is selectively grown at the bottom of the growth window in the inner base region. S530. In the epitaxial equipment, a gaseous Si source and a gaseous Ge source are introduced, and a SiGe base layer is selectively grown on the Si buffer layer. S540. A gaseous Si source is introduced into the epitaxial device to selectively grow a Si capping layer on the SiGe base layer, thereby forming the inner base region.

7. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 6, characterized in that: In step S510, the growth window of the inner base region is rapidly baked at 850°C to 950°C using H2 gas to remove the natural oxide layer of the growth window of the inner base region.

8. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 6, characterized in that: In step S520, at a growth temperature of 850℃ to 900℃, SiH2Cl2 gas is used as a Si source to grow the Si buffer layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

9. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 6, characterized in that: In step S530, at a growth temperature of 750℃~800℃, SiH2Cl2 gas and GeH4 gas are used as Si source and Ge source, respectively, to grow the SiGe base layer, and HCl gas with a flow rate of 120sccm~240sccm is used to suppress Si nucleation in the second dielectric layer and the third dielectric layer.

10. The method for selectively growing the inner base region of a germanium-silicon heterojunction transistor as described in claim 6, characterized in that: In step S540, at a growth temperature of 850℃ to 900℃, SiH2Cl2 gas is used as the Si source to grow the Si capping layer, and HCl gas with a flow rate of 80 sccm to 160 sccm is used to suppress Si nucleation in the second and third dielectric layers.

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