Novel high-precision phase discrimination circuit
By combining a current pump circuit, an RC network, and a MOSFET drive circuit, the problem of low accuracy in existing phase detection circuits is solved, achieving high-precision phase detection and phase locking, which is suitable for high-requirement phase-locked loop applications.
Patent Information
- Application Number
- CN202511673182.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2025-12-16
AI Technical Summary
The existing phase detection process is not accurate enough to meet the requirements of high-precision detection, especially when phase locking is required, it cannot maintain the high precision of phase difference.
By employing a combination of current pump circuit, RC network and MOSFET drive circuit, a fixed current is injected or pulled into the RC network. High-precision phase detection is achieved by utilizing current pump technology and unique phase detection logic. The phase-locked loop is achieved by combining integral characteristics and phase-shifting circuit.
It achieves high-precision phase detection, high phase discrimination accuracy, and output with integral characteristics, which can maintain the phase difference within 0.01°, making it suitable for demanding phase-locked loop applications.
Smart Images
Figure CN121150692A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog signal processing, and specifically relates to a novel high-precision phase detection circuit. Background Technology
[0002] In analog signal processing, phase holding, or phase-locked loop (PLL), is often required. The prerequisite for PLL is phase detection, or phase measurement. Due to the technical difficulty of phase detection, it is difficult to achieve high-precision detection of small-angle phase differences. Therefore, the accuracy of previous phase detection processes was not high. In fact, it was sufficient to keep the phase difference within a certain range, which met the requirements of most PLL applications. For example, some PLLs are actually for frequency locking, i.e., keeping up with the frequency. However, some applications require high phase detection accuracy, and existing phase detection technologies cannot meet the high-precision detection requirements. Summary of the Invention
[0003] To address the problem of low accuracy in existing phase detection circuits, a novel high-precision phase detection circuit is proposed.
[0004] A novel high-precision phase detection circuit includes:
[0005] Current pump circuit, RC network and MOSFET drive circuit;
[0006] The input terminal of the current pump circuit is connected to the output terminal of the digital circuit. The current pump circuit is used to inject or pull a fixed current into the resistor-capacitor network according to the phase difference of the output signal of the digital circuit.
[0007] The input terminal of the RC network is connected to the output terminal of the current pump circuit. The RC network is used to convert the fixed current injected or pulled out by the current pump circuit into voltage and input it to the field-effect transistor drive circuit.
[0008] The input terminal of the field-effect transistor (FET) driver circuit is connected to the output terminal of the resistor-capacitor (RC) network. The FET driver circuit drives the LED according to the input voltage.
[0009] The beneficial effects of this invention are as follows: This invention proposes a novel high-precision phase detection circuit with high phase detection accuracy and no dead zone. When current is injected into or pulled out of the RC network, the time difference between the injected and pulled current acting on the RC network causes a change in the gate voltage of the RC network and the connected MOSFET. The phase detection result is amplified by the MOSFET and output, achieving good results in practical applications. Utilizing current pump (charge pump) technology and unique phase detection logic and circuitry, the circuit achieves high phase detection sensitivity and accuracy, and the output exhibits integral characteristics. Attached Figure Description
[0010] Figure 1 A circuit diagram of a novel high-precision phase detection circuit according to a specific embodiment of this application;
[0011] Figure 2A new high-precision phase detection circuit waveform diagram for the specific embodiment of the present application;
[0012] Figure 3 A new high-precision phase detection circuit modified circuit diagram for the specific embodiment of the present application. DETAILED DESCRIPTION
[0013] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with embodiments and drawings. Herein, the illustrative embodiments of the present application and the description thereof are used to explain the present application, but not as a limitation of the present application.
[0014] A new high-precision phase detection circuit, comprising:
[0015] a current pump circuit, a resistance-capacitance network and a field effect tube driving circuit;
[0016] The input end of the current pump circuit is connected with the output end of the digital circuit, and the current pump circuit is used for injecting or drawing out a fixed current to the resistance-capacitance network according to the phase difference of the output signal of the digital circuit;
[0017] The input end of the resistance-capacitance network is connected with the output end of the current pump circuit, and the resistance-capacitance network is used for converting the fixed current injected or drawn out by the current pump circuit into a voltage and inputting the voltage to the field effect tube driving circuit;
[0018] The input end of the field effect tube driving circuit is connected with the output end of the resistance-capacitance network, and the field effect tube driving circuit drives the light emitting tube according to the input voltage.
[0019] Specifically, when the analog signal processing is performed, the phase needs to be kept in many cases, i.e. phase locking, and the prerequisite of phase locking is phase detection, and there are many ways for phase detection. The present application proposes a high-precision phase detection circuit, which uses current pump technology to make the phase detection precision high and the gain high, and has integral characteristics, and good effects are achieved in actual project applications.
[0020] In the high-precision inductive synchro angle measuring system, the phase of the two-phase excitation power supply's sine and cosine (2KHZ) output signals needs to be kept unchanged (0.01° in electric angle), and the distortion error of the two signals needs to be small, so multi-stage filtering is used, including band-pass filtering. The combined effect of various factors and filtering links causes the two-phase signals to drift with time and temperature, and the phase of the two-phase sine wave also changes uncontrollably. Through the phase detection link (phase detection), the phase drift difference of the two-phase signals is detected, that is, the phase difference of the two-phase sine and cosine signals originally being 90°, after the phase drift, the phase difference is no longer 90°, but an angle near 90°. The phase detection result is used to drive the phase shift controllable gain constant amplifier to move the phase of the two sine signals, so that the phase difference of the two phases is still 90°, and the phase detection accuracy is within 0.01° (2KHZ electric phase). The practical application of the present application shows that the phase difference of the two-phase waveform output is extremely small, and the phase difference with the standard 90° phase is approximately 0° (2KHZ electric angle).
[0021] In the above application, the phase difference detection, i.e. phase detection, is an important link. The integral characteristic combined with the phase shift circuit link makes the static difference with the reference phase difference 0° (2KHZ electric angle).
[0022] Further, the current pump circuit includes a capacitor C1, a resistor R1, a transistor G1, a transistor G2, a resistor R3, a zener D1, a capacitor C3, a capacitor C2, a resistor R2, a transistor G3, a transistor G4, a resistor R4, a zener D2, a capacitor C4 and a resistor R5.
[0023] The transistor G1 and the transistor G4 are NPN type transistors, and the transistor G2 and the transistor G3 are PNP type transistors.
[0024] One end of the capacitor C1 and one end of the resistor R1 are connected to the first output end of the digital circuit, and the other end of the capacitor C1 and the other end of the resistor R1 are connected to the base of the transistor G1. The emitter of the transistor G1 is connected to the ground. The collector of the transistor G1 is connected to one end of the resistor R3 and the emitter of the transistor G2. The other end of the resistor R3, one end of the zener D1 and one end of the capacitor C3 are connected to the positive voltage. The other end of the zener D1 and the other end of the capacitor C3 are connected to the base of the transistor G2.
[0025] The one end of the capacitor C2 and the one end of the resistor R2 are connected with the second output end of the digital circuit, the other end of the capacitor C2 and the other end of the resistor R2 are connected with the emitter of the transistor G3, the base of the transistor G3 is connected with the ground, the collector of the transistor G3 is connected with the emitter of the transistor G4 and the one end of the resistor R4, the other end of the resistor R4, the other end of the voltage stabilizing tube D2 and the other end of the capacitor C4 are connected with the negative pole of the voltage, the one end of the voltage stabilizing tube D2 and the one end of the capacitor C4 are connected with the base of the transistor G4;
[0026] The other end of the capacitor C3 is connected with the one end of the resistor R5, the other end of the resistor R5 is connected with the one end of the capacitor C4, the collector of the transistor G2 is connected with the collector of the transistor G2.
[0027] Further, the resistance-capacitance network comprises a resistor R6, a capacitor C5, a capacitor C6 and a resistor R8;
[0028] The one end of the resistor R6 and the one end of the capacitor C5 are connected with the collector of the transistor G2 and the collector of the transistor G2, the other end of the resistor R6 is connected with the capacitor C6 and the one end of the resistor R8, the other end of the capacitor C5, the other end of the capacitor C6 and the other end of the resistor R8 are connected with the ground.
[0029] Further, the field effect transistor driving circuit comprises a light emitting tube D3, a field effect transistor G5 and a resistor R7;
[0030] The gate of the field effect transistor G5 is connected with the one end of the resistor R8, the drain of the field effect transistor G5 is connected with the cathode of the light emitting tube, the anode of the light emitting tube is connected with the positive pole of the voltage, the source of the field effect transistor G5 is connected with the one end of the resistor R7, the other end of the resistor R7 is connected with the ground.
[0031] Specifically, referring to Figure 1 , the part in the dashed box 1 is the current pump circuit, the part in the dashed box 2 is the resistance-capacitance network, and the part in the dashed box 3 is the field effect transistor driving circuit;
[0032] In combination with the specific case that the first output end and the second output end of the digital circuit input to the two points A and B of the current pump circuit respectively, the current pump circuit injects or draws a fixed current to the resistance-capacitance network, and the voltage corresponding to the point of the gate of the field effect transistor G5 will change, and the phase detection information is contained in the change of the relative time of the injected or drawn current, but in order to make the link work normally, the time of the injected or drawn current is very short, so the linear segment of the phase detection circuit in Figure 1 has a range.
[0033] In Figure 1In the above, when the capacitance of capacitor C6 is greater than that of capacitor C5, and the resistance of resistor R6 is not very large, for example, capacitor C6 = 1μF, capacitor C5 = 0.1μF, and resistor R = 2KΩ, without going into detailed derivation, the current entering the RC network and the gate voltage of the MOSFET G5 have low-pass characteristics. Capacitor C6 and resistor R8 determine the time constant of this low-pass circuit.
[0034] exist Figure 1 In the process, because the gate input resistance of the field-effect transistor G5 is large, the load of the RC network is almost infinite. For the RC network 2, the gate voltage output to the field-effect transistor G5 has almost no load effect.
[0035] In the field-effect transistor (FET) driver circuit, during phase detection, the current generated by the current pump circuit is injected and pulled out by the RC network. The resulting node voltage is used as the gate input voltage of the FET in the driver circuit. This voltage drives the LED D3, causing a change in the photoresistor in the optocoupler resistor containing D3. This, in turn, shifts the phase of the signal in the phase-shifting circuit, achieving phase locking. It should be noted that the phase-shifting circuit is not included in the... Figure 1 middle.
[0036] Furthermore, when the first output terminal of the digital circuit outputs a high level and the second output terminal outputs a low level, transistor G2 is turned off and transistor G4 is turned on. The fixed current pulled out by the current pump circuit from the RC network is... ;
[0037] ,in, This is the regulated voltage value of Zener diode D2. This is the voltage between the base and emitter of the NPN transistor G4. This is the current amplification factor of transistor G4, and the value is very large.
[0038] Specifically, when the first output terminal of the digital circuit inputs a high level to point A of the current pump circuit, and the second output terminal of the digital circuit inputs a low level to point B of the current pump circuit, transistor G1 saturates, causing transistor G2 to be in reverse-biased cutoff state. At the same time, B is at a low level, transistor G3 is cut off, and transistor G4 is working. If this process is quite short, a fixed current is pulled out from the RC network. .
[0039] Furthermore, when the first output terminal of the digital circuit outputs a low level and the second output terminal outputs a high level, transistor G2 is turned on and transistor G4 is turned off. The fixed current injected into the RC network by the current pump circuit is... ;
[0040] ,in, This is the regulated voltage value of Zener diode D1. This is the voltage between the base and emitter of the PNP transistor G2. This is the current amplification factor of transistor G2, and the value is very large.
[0041] Specifically, when the first output terminal of the digital circuit inputs a low level to point A of the current pump circuit, and the second output terminal of the digital circuit inputs a high level to point B of the current pump circuit, transistor G1 is cut off, causing transistor G2 to be in the working state. At the same time, B is at a high level, and transistor G3 is in the cut-off state. If this process is relatively short, transistor G2 injects a fixed current into the RC network 2. .
[0042] When the first output terminal of the digital circuit inputs a high level to point A of the current pump circuit, and the second output terminal of the digital circuit inputs a high level to point B of the current pump circuit... Figure 1 The entire circuit exhibits high impedance to the RC network, remaining unchanged. The first output of the digital circuit inputs a low level to point A of the current pump circuit, and the second output of the digital circuit inputs a low level to point B of the current pump circuit. Figure 1 A logic state that is prohibited in a circuit.
[0043] Furthermore, the voltage between the base and emitter of the NPN transistor G4 .
[0044] Furthermore, the voltage between the base and emitter of the PNP transistor G2 .
[0045] Specifically, refer to Figure 2 , Figure 2 Waveforms A and B represent respectively Figure 1 Input waveforms at points A and B of the medium current pump circuit. Figure 2 In the diagram, C represents the phase detection square wave; I is the rising or falling edge of the signal square wave; and II and III are reference signals. During phase detection, edge I changes, serving as the reference for II and III, and these changes occur over time intervals, leading to… Figure 1 The injection and extraction times of the medium-resistance-capacitor network are different, resulting in different gate voltages of the field-effect transistor G5 and thus different drain currents. This causes the brightness of the LED D3 to change. In the actual circuit, D3 is the LED in the optocoupler resistor. By changing the brightness of D3, the resistance value of the optocoupler is changed, thereby changing the phase and achieving the purpose of phase locking.
[0046] Figure 1 The circuit shown and Figure 2 The logic input shown can form an integral operation of the phase difference by injecting or pulling a fixed current into or out of the RC network 2, i.e., current pumping technology, and combined with the phase shifting stage, achieve the purpose of phase locking.
[0047] Figure 1 The circuit shown has high phase detection accuracy, theoretically has no dead zone, and the switching process of the devices does not affect the phase detection result; because Figure 1 In the process of injecting and extracting current into and from the RC network 2, combined with Figure 2 A change in the position of signal I will inevitably lead to a change in the time span of II-I and I-III. This change will affect the injected or pulled current. Figure 1 The duration of the RC network in the circuit ultimately causes a change in the gate voltage of the field-effect transistor G5, resulting in the output phase detection result.
[0048] Example:
[0049] This application discloses a novel high-precision phase detection circuit that can also be used... Figure 3 The circuit shown demonstrates that, in this case, the phase detection result voltage output is represented by the gate voltage of the field-effect transistor G5, exhibiting low-pass characteristics.
[0050] Figure 3 In the diagram, the part enclosed by dashed box 1 is the current pump circuit, the part enclosed by dashed box 2 is the RC network, and the part enclosed by dashed box 3 is the field-effect transistor drive circuit.
[0051] The current pump circuit includes capacitor C1, resistor R1, transistor G1, transistor G2, resistor R3, Zener diode D1, capacitor C3, capacitor C2, resistor R2, transistor G3, transistor G4, resistor R4, Zener diode D2, capacitor C4, and resistor R5.
[0052] Transistors G1 and G4 are NPN type transistors, while transistors G2 and G3 are PNP type transistors;
[0053] One end of capacitor C1 and one end of resistor R1 are connected to the first output terminal of the digital circuit. The other end of capacitor C1 and the other end of resistor R1 are connected to the base of transistor G1. The emitter of transistor G1 is connected to ground. The collector of transistor G1 is connected to one end of resistor R3 and the emitter of transistor G2. The other end of resistor R3, one end of Zener diode D1, and one end of capacitor C3 are connected to the positive terminal of the voltage. The other end of Zener diode D1 and the other end of capacitor C3 are connected to the base of transistor G2.
[0054] One end of capacitor C2 and one end of resistor R2 are connected to the second output terminal of the digital circuit. The other end of capacitor C2 and the other end of resistor R2 are connected to the emitter of transistor G3. The base of transistor G3 is connected to ground. The collector of transistor G3 is connected to the emitter of transistor G4 and one end of resistor R4. The other end of resistor R4, the other end of Zener diode D2, and the other end of capacitor C4 are connected to the negative terminal of the voltage. One end of Zener diode D2 and one end of capacitor C4 are connected to the base of transistor G4.
[0055] The other end of capacitor C3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to one end of capacitor C4; the collector of transistor G2 is connected to the collector of transistor G2.
[0056] The RC network includes resistor R6, capacitor C5, and capacitor C6;
[0057] One end of resistor R6 and one end of capacitor C5 are connected to the collector of transistor G2. The other end of resistor R6 is connected to one end of capacitor C6. The other ends of capacitor C5 and capacitor C6 are connected to ground.
[0058] The field-effect transistor driver circuit includes: LED D3, field-effect transistor G5, and resistor R7;
[0059] The gate of the field-effect transistor G5 is connected to one end of the resistor R8, the drain of the field-effect transistor G5 is connected to the cathode of the light-emitting diode, the anode of the light-emitting diode is connected to the positive terminal of the voltage, the source of the field-effect transistor G5 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to ground.
[0060] When the capacitance of capacitor C6 is greater than that of capacitor C5, and the resistance of resistor R6 is not very large, for example, capacitor C6 = 1μF, capacitor C5 = 0.1μF, and resistor R = 2KΩ, then the Laplace transform transfer function between the current entering the RC network and the gate voltage of the field-effect transistor G5 is:
[0061] ,in, This is the gate voltage of the field-effect transistor G5. For the current entering the RC network, Let C6 be the capacitance value, and S be the Laplace transform operator.
[0062] Therefore, Figure 3 The process shown has integral properties.
[0063] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.
Claims
1. A novel high-precision phase detection circuit, characterized in that, include: Current pump circuit, RC network and MOSFET drive circuit; The input terminal of the current pump circuit is connected to the output terminal of the digital circuit. The current pump circuit is used to inject or pull a fixed current into the resistor-capacitor network according to the phase difference of the output signal of the digital circuit. The input terminal of the RC network is connected to the output terminal of the current pump circuit. The RC network is used to convert the fixed current injected or pulled out by the current pump circuit into voltage and input it to the field-effect transistor drive circuit. The input terminal of the field-effect transistor (FET) driver circuit is connected to the output terminal of the resistor-capacitor (RC) network. The FET driver circuit drives the LED according to the input voltage.
2. The novel high-precision phase detection circuit according to claim 1, characterized in that: The current pump circuit includes capacitor C1, resistor R1, transistor G1, transistor G2, resistor R3, Zener diode D1, capacitor C3, capacitor C2, resistor R2, transistor G3, transistor G4, resistor R4, Zener diode D2, capacitor C4, and resistor R5. Transistors G1 and G4 are NPN type transistors, while transistors G2 and G3 are PNP type transistors; One end of capacitor C1 and one end of resistor R1 are connected to the first output terminal of the digital circuit. The other end of capacitor C1 and the other end of resistor R1 are connected to the base of transistor G1. The emitter of transistor G1 is connected to ground. The collector of transistor G1 is connected to one end of resistor R3 and the emitter of transistor G2. The other end of resistor R3, one end of Zener diode D1, and one end of capacitor C3 are connected to the positive terminal of the voltage. The other end of Zener diode D1 and the other end of capacitor C3 are connected to the base of transistor G2. One end of capacitor C2 and one end of resistor R2 are connected to the second output terminal of the digital circuit. The other end of capacitor C2 and the other end of resistor R2 are connected to the emitter of transistor G3. The base of transistor G3 is connected to ground. The collector of transistor G3 is connected to the emitter of transistor G4 and one end of resistor R4. The other end of resistor R4, the other end of Zener diode D2, and the other end of capacitor C4 are connected to the negative terminal of the voltage. One end of Zener diode D2 and one end of capacitor C4 are connected to the base of transistor G4. The other end of capacitor C3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to one end of capacitor C4; the collector of transistor G2 is connected to the collector of transistor G2.
3. The novel high-precision phase detection circuit according to claim 1, characterized in that: The RC network includes resistor R6, capacitor C5, capacitor C6, and resistor R8; One end of resistor R6 and one end of capacitor C5 are connected to the collector of transistor G2. The other end of resistor R6 is connected to one end of capacitor C6 and resistor R8. The other ends of capacitor C5, capacitor C6 and resistor R8 are connected to ground.
4. The novel high-precision phase detection circuit according to claim 1, characterized in that: The field-effect transistor driver circuit includes: LED D3, field-effect transistor G5, and resistor R7; The gate of the field-effect transistor G5 is connected to one end of the resistor R8, the drain of the field-effect transistor G5 is connected to the cathode of the light-emitting diode, the anode of the light-emitting diode is connected to the positive terminal of the voltage, the source of the field-effect transistor G5 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to ground.
5. A novel high-precision phase detection circuit according to claim 2, characterized in that: When the first output terminal of the digital circuit outputs a high level and the second output terminal outputs a low level, transistor G2 is turned off and transistor G4 is turned on. The fixed current pulled out by the current pump circuit from the RC network is... ; ,in, This is the regulated voltage value of Zener diode D2. This is the voltage between the base and emitter of the NPN transistor G4. This is the current amplification factor of transistor G4.
6. A novel high-precision phase detection circuit according to claim 2, characterized in that: When the first output terminal of the digital circuit outputs a low level and the second output terminal outputs a high level, transistor G2 is turned on and transistor G4 is turned off. The fixed current injected into the RC network by the current pump circuit is... ; ,in, This is the regulated voltage value of Zener diode D1. This is the voltage between the base and emitter of the PNP transistor G2. This is the current amplification factor of transistor G2.
7. A novel high-precision phase detection circuit according to claim 5, characterized in that: The voltage between the base and emitter of NPN transistor G4 .
8. A novel high-precision phase detection circuit according to claim 6, characterized in that: The voltage between the base and emitter of the PNP transistor G2 .