Laboratory constant-illumination-intensity sunlight illumination management system

Abstract

The invention discloses a laboratory constant-illumination-intensity sunlight illumination management system, belongs to the technical field of illumination management, and solves the problems that an ADC sampling clock of an irradiance feedback signal is modulated by switching noise and picosecond-level random jitter is generated, so that the phase collapse of a control loop is caused by ADC sampling jitter; and the problem that the service life of the lamp is shortened due to high-frequency self-oscillation caused by misjudgment of the phase of the digital PID controller and acceleration of lamp electrode sputtering is solved. According to the invention, an ultra-stable 156.25 MHz main clock signal is generated and is differentiated into four paths of 90-degree phase difference sampling clocks to drive a time-interleaved ADC array to execute anti-jitter four-phase sampling, clock jitter parameters are quantified in real time, a future jitter trend is predicted, and a compensation voltage is output to a phase modulation compensation module to generate an anti-phase correction signal to be injected into a compensation node of a clock distribution network; and finally, the digital correction engine executes complex exponential weighted average and finite impulse response filtering processing on the four-channel sampling data, outputs a control signal with small fluctuation, and recovers the service life of the xenon lamp.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of light management, in particular to a laboratory constant irradiance sunlight illumination management system. BACKGROUND

[0002] Laboratory constant irradiance sunlight illumination, also known as a solar simulator, is a device that can simulate the characteristics of solar radiation. It can achieve a spectral distribution, irradiance, and spatial uniformity similar to sunlight by adjusting the light source. The core is to accurately reproduce the lighting conditions of natural sunlight. It is widely used in photovoltaic device performance testing, material light aging experiments, biological photosynthesis research, and other fields. It can provide a stable and controllable lighting environment for experiments, effectively avoiding the disadvantages of natural sunlight affected by weather, time, and other factors, and ensuring the reliability and repeatability of experimental data.

[0003] However, in the process of maintaining constant irradiance sunlight illumination in the solar simulator control system, the precision of the irradiance feedback loop faces severe challenges.

[0004] When the high-frequency noise of the power stage switching device invades the ADC sampling clock path through common impedance or spatial coupling, it will induce deterministic jitter of the clock signal, with a peak value of 50-200 picoseconds. This micro-time sequence deviation causes the phase shift of the feedback signal sampling point, which triggers a false phase lead determination in the digital PID controller. The actual control system of the PID controller thus outputs an error correction signal, ultimately forming a positive feedback loop and exciting a high-frequency self-oscillation of 1-10 kHz. This oscillation not only causes a dramatic fluctuation of the light intensity modulation depth of ±15%, making the "constant irradiance" state exist in name only, but more critically, its high-frequency energy focuses on the electrode of the xenon lamp in the solar simulator, accelerating the sputtering of tungsten material, and causing the lamp life to decrease from the conventional 1000 hours to within 200 hours, with a decay amplitude of up to 80%.

[0005] Therefore, a laboratory constant irradiance sunlight illumination management system is proposed to solve or alleviate the above problems. SUMMARY

[0006] The purpose of the present application is to solve the shortcomings in the prior art and propose a laboratory constant irradiance sunlight illumination management system.

[0007] To achieve the above purpose, the present application adopts the following technical solutions:

[0008] A laboratory constant irradiance sunlight illumination management system, comprising a low-jitter clock source module, a clock distribution network module, a jitter monitoring front-end module, an adaptive prediction engine module, a phase modulation compensation module, a time-interleaved analog-to-digital converter array module, a digital correction engine module, a PID controller, and a solar simulator.

[0009] The low-jitter clock source module is used to generate a 156.25MHz main clock signal, the clock distribution network module is connected to the low-jitter clock source module, the clock distribution network module is used to generate four-phase sampling clock and monitoring clock with a phase difference of 90°, the time-interleaved analog-to-digital converter array module is connected to the clock distribution network module, the time-interleaved analog-to-digital converter array module is used to perform four-phase sampling, the jitter monitoring front-end module is connected to the clock distribution network module, the jitter monitoring front-end module is used to quantize clock jitter in real time, the adaptive prediction engine module is connected to the jitter monitoring front-end module, the adaptive prediction engine module is used to perform long short-term memory network prediction, the phase modulation compensation module is connected to the adaptive prediction engine module and the clock distribution network module, the phase modulation compensation module is used to generate a phase correction signal, the digital correction engine module is connected to the time-interleaved analog-to-digital converter array module, the digital correction engine module is used for data processing and control output, and the PID controller is connected to the digital correction engine module and the solar simulator. The PID controller receives signal data from the digital correction engine module to control the solar simulator.

[0010] Preferably, the low-jitter clock source module comprises an LT3045-5 voltage stabilizer, an ADP7118 low-dropout linear voltage stabilizer, a constant-temperature crystal oscillator, a first phase-locked loop, a second phase-locked loop, a third phase-locked loop, a first TMP117 temperature sensor, and an ADN8834 thermoelectric cooler controller. The input end of the LT3045-5 voltage stabilizer is connected to a power supply, the power supply end of the LT3045-5 voltage stabilizer is connected to the power supply end of the constant-temperature crystal oscillator through an LC filter, the clock output end of the constant-temperature crystal oscillator is connected to the reference clock input end of the first phase-locked loop through a first capacitor, the input end of the ADP7118 low-dropout linear voltage stabilizer is connected to a power supply, the power supply end of the ADP7118 low-dropout linear voltage stabilizer is connected to the power supply end of the second phase-locked loop, the radio frequency output end of the second phase-locked loop is connected to the frequency input end of the third phase-locked loop through an LC filter, the differential clock output positive end and the differential clock output negative end of the third phase-locked loop are set as the output ends of the low-jitter clock source module to output differential clock, the serial data line and the serial clock line of the first TMP117 temperature sensor are connected to the corresponding communication interfaces of the ADN8834 thermoelectric cooler controller, and the positive drive output end and the negative drive output end of the ADN8834 thermoelectric cooler controller are both connected to the thermoelectric cooling interface of the constant-temperature crystal oscillator.

[0011] Preferably, the clock distribution network module comprises an ADCLK954 clock buffer, an ADA4940 differential receiver, a first DS1023S programmable delay chip, a second DS1023S programmable delay chip, a third DS1023S programmable delay chip, the differential clock input positive terminal and the negative terminal of the ADCLK954 clock buffer are connected with the output terminal of the low-jitter clock source module, the first single-ended clock output terminal of the ADCLK954 clock buffer is connected to the non-inverting input terminal of the ADA4940 differential receiver through a first resistor, the inverting input terminal of the ADA4940 differential receiver is grounded through a second resistor, the output terminal of the ADA4940 differential receiver outputs a monitoring clock to the jitter monitoring front-end module, the second single-ended clock output terminal of the ADCLK954 clock buffer is connected to the clock input terminal of the first AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module, the third single-ended clock output terminal of the ADCLK954 clock buffer is connected to the signal input terminal of the first DS1023S programmable delay chip, and a compensation injection node is arranged between the third single-ended clock output terminal of the ADCLK954 clock buffer and the signal input terminal of the first DS1023S programmable delay chip, the compensation injection node is connected with the radio frequency output terminal of the phase modulation compensation module through a coupling capacitor, the signal output terminal of the first DS1023S programmable delay chip is connected to the clock input terminal of the second AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module, the fourth single-ended clock output terminal of the ADCLK954 clock buffer is connected to the signal input terminal of the second DS1023S programmable delay chip, the signal output terminal of the second DS1023S programmable delay chip is connected to the clock input terminal of the third AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module, the fifth single-ended clock output terminal of the ADCLK954 clock buffer is connected to the signal input terminal of the third DS1023S programmable delay chip, and the signal output terminal of the third DS1023S programmable delay chip is connected to the clock input terminal of the fourth AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module.

[0012] Preferably, the time-interleaved analog-to-digital converter array module comprises an ADA4807 operational amplifier, an ADG1612 analog switch, a first AD4003 analog-to-digital converter, a second AD4003 analog-to-digital converter, a third AD4003 analog-to-digital converter, a fourth AD4003 analog-to-digital converter, an LTC6655 reference source, a signal output end of the ADA4807 operational amplifier is connected to a common end of the ADG1612 analog switch through a third resistor, an inverting input end of the ADA4807 operational amplifier is connected with a gain end thereof through a fourth resistor, a first channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the first AD4003 analog-to-digital converter, a second channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the second AD4003 analog-to-digital converter, a third channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the third AD4003 analog-to-digital converter, a fourth channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the fourth AD4003 analog-to-digital converter, a conversion start end of the first AD4003 analog-to-digital converter, the second AD4003 analog-to-digital converter, the third AD4003 analog-to-digital converter and the fourth AD4003 analog-to-digital converter is connected to a conversion control end of a digital correction engine, a serial data output end of the first AD4003 analog-to-digital converter is connected to a first data input end of the digital correction engine, a serial data output end of the second AD4003 analog-to-digital converter is connected to a second data input end of the digital correction engine, a serial data output end of the third AD4003 analog-to-digital converter is connected to a third data input end of the digital correction engine, a serial data output end of the fourth AD4003 analog-to-digital converter is connected to a fourth data input end of the digital correction engine, and an output end of the LTC6655 reference source is connected to a reference voltage input end of the first AD4003 analog-to-digital converter, the second AD4003 analog-to-digital converter, the third AD4003 analog-to-digital converter and the fourth AD4003 analog-to-digital converter.

[0013] Preferably, the jitter monitoring front-end module comprises an ADCMP605 high-speed comparator, an LM6172 voltage feedback amplifier, a bipolar transistor, an LF398 sample and hold, a TDC7201 time-to-digital converter, a signal output end of the ADCMP605 high-speed comparator is connected to an inverting input end of the LM6172 voltage feedback amplifier through a fifth resistor, an output end of the LM6172 voltage feedback amplifier is connected to a base of the bipolar transistor, a collector of the bipolar transistor is connected to an analog input end of the LF398 sample and hold through a sixth resistor, an emitter of the bipolar transistor is grounded, a signal output end of the LF398 sample and hold is connected to a stop signal input end of the TDC7201 time-to-digital converter, a chip select output end of the TDC7201 time-to-digital converter is connected to a chip select input end of the adaptive prediction engine, a serial clock output end of the TDC7201 time-to-digital converter is connected to a clock input end of the adaptive prediction engine, and a serial data output end of the TDC7201 time-to-digital converter is connected to a data input end of the adaptive prediction engine.

[0014] Preferably, the adaptive prediction engine module comprises an STM32H743VI microcontroller, an AD9106 digital-to-analog converter, an IS61WV51216 static random access memory, and a second TMP117 temperature sensor, a data bus output end of the STM32H743VI microcontroller is connected to a parallel data input end of the AD9106 digital-to-analog converter, a write enable output end of the STM32H743VI microcontroller is connected to a write control input end of the AD9106 digital-to-analog converter, a data input / output end of the IS61WV51216 static random access memory is connected to a memory data bus of the STM32H743VI microcontroller, a serial data line of the second TMP117 temperature sensor is connected to a serial data input / output end of the STM32H743VI microcontroller, a serial clock line of the second TMP117 temperature sensor is connected to a serial clock output end of the STM32H743VI microcontroller, and an analog voltage output end of the AD9106 digital-to-analog converter outputs a compensation control signal.

[0015] Preferably, the phase modulation compensation module comprises an ADA4897 operational amplifier, an ADL5380 quadrature demodulator and an HMC928 voltage-controlled phase shifter, the non-inverting input end of the ADA4897 operational amplifier is connected to the analog voltage output end of the AD9106 digital-to-analog converter in the adaptive prediction engine module, the signal output end of the ADA4897 operational amplifier is connected to the in-phase modulation input end of the ADL5380 quadrature demodulator, the local oscillator input end of the ADL5380 quadrature demodulator receives a main clock signal, the radio frequency output end of the ADL5380 quadrature demodulator is connected to the radio frequency input end of the HMC928 voltage-controlled phase shifter, the radio frequency output end of the HMC928 voltage-controlled phase shifter is set as a compensation signal output end, and the control voltage end of the HMC928 voltage-controlled phase shifter is connected to the AD9106 digital-to-analog converter in the adaptive prediction engine module through the seventh resistor.

[0016] Preferably, the digital correction engine module comprises an XC7A100T field programmable gate array, an MT41K256M16 memory and a DAC8881 digital-to-analog converter, the first serial data input end of the XC7A100T field programmable gate array is connected to the data output end of the first AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module, the second serial data input end of the XC7A100T field programmable gate array is connected to the data output end of the second AD4003 analog-to-digital converter, the third serial data input end of the XC7A100T field programmable gate array is connected to the data output end of the third AD4003 analog-to-digital converter, the fourth serial data input end of the XC7A100T field programmable gate array is connected to the data output end of the fourth AD4003 analog-to-digital converter, the memory data bus of the XC7A100T field programmable gate array is connected to the corresponding data bus of the MT41K256M16 memory, the digital-to-analog conversion control end of the XC7A100T field programmable gate array is connected to the serial data input end of the DAC8881 digital-to-analog converter through the eighth resistor, and the analog voltage output end of the DAC8881 digital-to-analog converter is connected to the input end of the PID controller.

[0017] The present application has the following beneficial effects:

[0018] The application generates a super-stable 156.25MHz main clock signal through a low-jitter clock source, differentiates into four 90° phase difference sampling clock through a clock distribution network, drives a time-interleaved ADC array to perform anti-jitter four-phase sampling, simultaneously quantizes clock jitter parameters in real time through a jitter monitoring front end, predicts future jitter trends based on a long-short term memory network algorithm through an adaptive prediction engine and outputs a compensation voltage to a phase modulation compensation module to generate an opposite correction signal to inject into a compensation node of the clock distribution network, finally, a complex exponential weighted average and finite impulse response filtering process is performed on four-channel sampling data through a digital correction engine, a control signal with a fluctuation of less than ±0.5% is output to directly connect to a solar simulator power controller, the life of a xenon lamp is restored, and a high-cost femtosecond clock scheme is not needed. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0020] Figure 1 The structure diagram of the present application.

[0021] In the figure, 1 is a low-jitter clock source module; 2 is a clock distribution network module; 3 is a jitter monitoring front end module; 4 is an adaptive prediction engine module; 5 is a phase modulation compensation module; 6 is a time-interleaved ADC array module; 7 is a digital correction engine module; 8 is a PID controller; and 9 is a solar simulator. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0024] It should be noted that similar reference numerals and letters refer to similar items throughout the accompanying drawings, and once an item is defined in one drawing, it is not necessary to further define and explain it in subsequent drawings.

[0025] In the description of the application, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly understood by those skilled in the art, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the application.

[0026] In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0027] In the description of the application, it should be noted that unless otherwise specified and limited, the terms "arrangement", "installation", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0028] A laboratory constant illumination sunlight illumination management system, such as Figure 1As shown, it comprises a low-jitter clock source module 1, a clock distribution network module 2, a jitter monitoring front-end module 3, an adaptive prediction engine module 4, a phase modulation compensation module 5, a time-interleaved analog-to-digital converter array module 6, a digital correction engine module 7, a PID controller 8, and a solar simulator 9; the low-jitter clock source module 1 is used to generate a 156.25MHz main clock signal, the clock distribution network module 2 is connected to the low-jitter clock source module 1, and the clock distribution network module 2 is used to generate four sampling clocks and monitoring clocks with a phase difference of 90°; the time-interleaved analog-to-digital converter array module 6 is connected to the clock distribution network module 2, and the time-interleaved analog-to-digital converter array module 6 is used to perform four-phase sampling; the jitter monitoring front-end module 3 is connected to the clock distribution network module 2, and the jitter monitoring front-end module 3 is used to quantize the clock jitter in real time; the adaptive prediction engine module 4 is connected to the jitter monitoring front-end module 3, and the adaptive prediction engine module 4 is used to perform long short-term memory network prediction; the phase modulation compensation module 5 is connected to the adaptive prediction engine module 4 and the clock distribution network module 2, and the phase modulation compensation module 5 is used to generate a phase correction signal; the digital correction engine module 7 is connected to the time-interleaved analog-to-digital converter array module 6, and the digital correction engine module 7 is used for data processing and control output; the PID controller 8 is connected to the digital correction engine module 7 and the solar simulator 9, and the PID controller 8 receives signal data from the digital correction engine module 7 to control the solar simulator 9.

[0029] The low-jitter clock source module 1 comprises an LT3045-5 voltage stabilizer, an ADP7118 low-dropout linear voltage stabilizer, a constant-temperature crystal oscillator, a first phase-locked loop, a second phase-locked loop, a third phase-locked loop, a first TMP117 temperature sensor, and an ADN8834 thermoelectric cooler controller 8; the input end of the LT3045-5 voltage stabilizer is connected to a power supply, the power supply end of the LT3045-5 voltage stabilizer is connected to the power supply end of the constant-temperature crystal oscillator through an LC filter, the clock output end of the constant-temperature crystal oscillator is connected to the reference clock input end of the first phase-locked loop through a first capacitor, the input end of the ADP7118 low-dropout linear voltage stabilizer is connected to a power supply, the power supply end of the ADP7118 low-dropout linear voltage stabilizer is connected to the power supply end of the second phase-locked loop, the radio frequency output end of the second phase-locked loop is connected to the frequency input end of the third phase-locked loop through an LC filter, the differential clock output positive end and the differential clock output negative end of the third phase-locked loop are set as the output ends of the low-jitter clock source module 1 to output differential clocks, the serial data line and the serial clock line of the first TMP117 temperature sensor are connected to the corresponding communication interfaces of the ADN8834 thermoelectric cooler controller 8, and the positive driving output end and the negative driving output end of the ADN8834 thermoelectric cooler controller 8 are both connected to the thermoelectric cooling interface of the constant-temperature crystal oscillator, wherein the first phase-locked loop is an LMK04832 clock regulator, the second phase-locked loop is an ADF5355 microwave broadband frequency synthesizer, and the third phase-locked loop is an ADF4371 microwave broadband frequency synthesizer.

[0030] The clock distribution network module 2 comprises an ADCLK954 clock buffer, an ADA4940 differential receiver, a first DS1023S programmable delay chip, a second DS1023S programmable delay chip, a third DS1023S programmable delay chip, the differential clock input positive end and the negative end of the ADCLK954 clock buffer are connected with the output end of the low-jitter clock source module 1, the first single-ended clock output end of the ADCLK954 clock buffer is connected to the positive phase input end of the ADA4940 differential receiver through a first resistor, the inverting input end of the ADA4940 differential receiver is grounded through a second resistor, the output end of the ADA4940 differential receiver outputs a monitoring clock to the jitter monitoring front-end module 3, the second single-ended clock output end of the ADCLK954 clock buffer is connected to the clock input end of the first AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module 6, the third single-ended clock output end of the ADCLK954 clock buffer is connected to the signal input end of the first DS1023S programmable delay chip, and a compensation injection node is arranged between the third single-ended clock output end of the ADCLK954 clock buffer and the signal input end of the first DS1023S programmable delay chip, the compensation injection node is connected with the radio frequency output end of the phase modulation compensation module 5 through a coupling capacitor, the signal output end of the first DS1023S programmable delay chip is connected to the clock input end of the second AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module 6, the fourth single-ended clock output end of the ADCLK954 clock buffer is connected to the signal input end of the second DS1023S programmable delay chip, the signal output end of the second DS1023S programmable delay chip is connected to the clock input end of the third AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module 6, the fifth single-ended clock output end of the ADCLK954 clock buffer is connected to the signal input end of the third DS1023S programmable delay chip, and the signal output end of the third DS1023S programmable delay chip is connected to the clock input end of the fourth AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module 6.

[0031] The time-interleaved analog-to-digital converter array module 6 comprises an ADA4807 operational amplifier, an ADG1612 analog switch, a first AD4003 analog-to-digital converter, a second AD4003 analog-to-digital converter, a third AD4003 analog-to-digital converter, a fourth AD4003 analog-to-digital converter, an LTC6655 reference source, a signal output end of the ADA4807 operational amplifier is connected to a common end of the ADG1612 analog switch through a third resistor, an inverting input end of the ADA4807 operational amplifier is connected to a gain end thereof through a fourth resistor, a first channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the first AD4003 analog-to-digital converter, a second channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the second AD4003 analog-to-digital converter, a third channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the third AD4003 analog-to-digital converter, a fourth channel output end of the ADG1612 analog switch is connected to an analog voltage input end of the fourth AD4003 analog-to-digital converter, a conversion start end of the first AD4003 analog-to-digital converter, the second AD4003 analog-to-digital converter, the third AD4003 analog-to-digital converter and the fourth AD4003 analog-to-digital converter is connected to a conversion control end of the digital correction engine, a serial data output end of the first AD4003 analog-to-digital converter is connected to a first data input end of the digital correction engine, a serial data output end of the second AD4003 analog-to-digital converter is connected to a second data input end of the digital correction engine, a serial data output end of the third AD4003 analog-to-digital converter is connected to a third data input end of the digital correction engine, a serial data output end of the fourth AD4003 analog-to-digital converter is connected to a fourth data input end of the digital correction engine, and an output end of the LTC6655 reference source is connected to a reference voltage input end of the first AD4003 analog-to-digital converter, the second AD4003 analog-to-digital converter, the third AD4003 analog-to-digital converter and the fourth AD4003 analog-to-digital converter.

[0032] The jitter monitoring front-end module 3 includes an ADCMP605 high-speed comparator, an LM6172 voltage feedback amplifier, a bipolar transistor, an LF398 sample and hold, a TDC7201 time-to-digital converter, the signal output end of the ADCMP605 high-speed comparator is connected to the inverting input end of the LM6172 voltage feedback amplifier through the fifth resistor, the output end of the LM6172 voltage feedback amplifier is connected to the base of the bipolar transistor, the collector of the bipolar transistor is connected to the analog input end of the LF398 sample and hold through the sixth resistor, the emitter of the bipolar transistor is grounded, the signal output end of the LF398 sample and hold is connected to the stop signal input end of the TDC7201 time-to-digital converter, the chip select output end of the TDC7201 time-to-digital converter is connected to the chip select input end of the adaptive prediction engine, the serial clock output end of the TDC7201 time-to-digital converter is connected to the clock input end of the adaptive prediction engine, and the serial data output end of the TDC7201 time-to-digital converter is connected to the data input end of the adaptive prediction engine.

[0033] The adaptive prediction engine module 4 includes an STM32H743VI microcontroller, an AD9106 digital-to-analog converter, an IS61WV51216 static random access memory, and a second TMP117 temperature sensor, the data bus output end of the STM32H743VI microcontroller is connected to the parallel data input end of the AD9106 digital-to-analog converter, the write enable output end of the STM32H743VI microcontroller is connected to the write control input end of the AD9106 digital-to-analog converter, the data input and output end of the IS61WV51216 static random access memory is connected to the memory data bus of the STM32H743VI microcontroller, the serial data line of the second TMP117 temperature sensor is connected to the serial data input and output end of the STM32H743VI microcontroller, the serial clock line of the second TMP117 temperature sensor is connected to the serial clock output end of the STM32H743VI microcontroller, and the analog voltage output end of the AD9106 digital-to-analog converter outputs a compensation control signal.

[0034] The phase modulation compensation module 5 includes an ADA4897 operational amplifier, an ADL5380 quadrature demodulator, and an HMC928 voltage-controlled phase shifter. The non-inverting input terminal of the ADA4897 operational amplifier is connected to the analog voltage output terminal of the AD9106 digital-to-analog converter in the adaptive prediction engine module 4. The signal output terminal of the ADA4897 operational amplifier is connected to the in-phase modulation input terminal of the ADL5380 quadrature demodulator. The local oscillator input terminal of the ADL5380 quadrature demodulator receives a main clock signal. The radio frequency output terminal of the ADL5380 quadrature demodulator is connected to the radio frequency input terminal of the HMC928 voltage-controlled phase shifter. The radio frequency output terminal of the HMC928 voltage-controlled phase shifter is set as a compensation signal output terminal. The control voltage terminal of the HMC928 voltage-controlled phase shifter is connected to the AD9106 digital-to-analog converter in the adaptive prediction engine module 4 through the seventh resistor.

[0035] The digital correction engine module 7 includes an XC7A100T field programmable gate array, an MT41K256M16 memory, and a DAC8881 digital-to-analog converter. The first serial data input terminal of the XC7A100T field programmable gate array is connected to the data output terminal of the first AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module 6. The second serial data input terminal of the XC7A100T field programmable gate array is connected to the data output terminal of the second AD4003 analog-to-digital converter. The third serial data input terminal of the XC7A100T field programmable gate array is connected to the data output terminal of the third AD4003 analog-to-digital converter. The fourth serial data input terminal of the XC7A100T field programmable gate array is connected to the data output terminal of the fourth AD4003 analog-to-digital converter. The memory data bus of the XC7A100T field programmable gate array is connected to the corresponding data bus of the MT41K256M16 memory. The digital-to-analog conversion control terminal of the XC7A100T field programmable gate array is connected to the serial data input terminal of the DAC8881 digital-to-analog converter through the eighth resistor. The analog voltage output terminal of the DAC8881 digital-to-analog converter is connected to the input terminal of the PID controller 8.

[0036] When the laboratory constant illumination sunlight illumination management system is working,

[0037] The oven-controlled crystal oscillator in the low-jitter clock source module 1 generates a 100MHz base frequency signal. The signal is input to the reference clock input terminal of the first phase-locked loop for primary noise shaping. The signal is transmitted to the reference clock input terminal of the second phase-locked loop through the coupling capacitor for bandwidth compression. The signal is further transmitted to the frequency input terminal of the third phase-locked loop through the LC filter for final purification. Finally, the 156.25MHz ultra-low jitter clock signal is output from the differential clock output positive and negative terminals of the third phase-locked loop.

[0038] This signal is directly fed into the differential clock input of the clock distribution network module 2, and the ADCLK954 clock buffer converts the single input into five outputs.

[0039] The first single-ended clock output is connected to the non-inverting input of the ADA4940 differential receiver, and the monitoring clock is generated from the signal output end. The second to fifth outputs drive four sampling channels respectively. The second output is directly connected to the clock input of the first AD4003 analog-to-digital converter. The third output is connected to the signal input of the first DS1023S programmable delay chip. The fourth output is connected to the DS1023S programmable delay chip. The fifth output is connected to the third DS1023S programmable delay chip. The output of each delay chip is connected to the clock input of the corresponding analog-to-digital converter, thereby constructing a strict four-phase sampling clock system.

[0040] At the same time, the irradiance feedback signal of the solar simulator 9 is converted into a voltage signal by a photoelectric sensor and input into the time-interleaved analog-to-digital converter array module 6. The ADA4807 operational amplifier buffers with unit gain and then connects the common terminal of the ADG1612 analog switch through a resistor. The ADG1612 analog switch is controlled by the channel selection signal of the digital correction engine module 7 to distribute the signal to the analog voltage input terminals of the four analog-to-digital converters in turn. Each converter performs time-interleaved sampling under the drive of the sampling clock with a phase difference of 90°. When the level disturbance caused by switch noise occurs, the four channels make the jitter influence cancel out statistically due to the difference in sampling time. The four-phase sampling anti-jitter algorithm is to multiply the voltage values collected by the four analog-to-digital converters by complex phase rotation factors respectively. The first channel is multiplied by a 0-degree phase factor, the second channel is multiplied by a negative 90-degree phase factor, the third channel is multiplied by a negative 180-degree phase factor, and the fourth channel is multiplied by a negative 270-degree phase factor. The corrected voltage value is obtained by dividing the sum by four. This algorithm is calculated in real time by the coordinate rotation digital computer hardware module in the XC7A100T field programmable gate array, reducing the equivalent sampling jitter.

[0041] In the clock monitoring link, the monitoring clock signal output by the clock distribution network module 2 is input into the signal input of the ADCMP605 high-speed comparator of the jitter monitoring front-end module 3. The signal output end triggers the slope generator constructed by the LM6172 voltage feedback amplifier. The output end of the LM6172 voltage feedback amplifier drives the constant current source composed of bipolar transistors to generate a voltage proportional to the time deviation at the analog input end of the LF398 sample holder. The TDC7201 time-to-digital converter captures this voltage and converts it into picosecond-level jitter data, which is transmitted to the adaptive prediction engine module 4 through the serial peripheral interface.

[0042] The STM32H743VI microcontroller kernel runs a long short-term memory network prediction algorithm, 128 groups of historical jitter data are taken as input layers, a future 50 ns jitter trend is calculated through three layers of hidden layers, and 12-bit prediction values are output to the parallel data input end of the digital-to-analog converter.

[0043] More specifically, the long short-term memory network prediction model is obtained by multiplying three groups of preset weight parameters and historical jitter data sequences, respectively inputting to an S-shaped growth function to calculate the values of a forget gate, an input gate and an output gate, and then combining a hyperbolic tangent function to update the cell state, and finally obtaining the jitter prediction value at the future time by the product of the output gate and the hyperbolic tangent function of the updated cell state.

[0044] The prediction value is output to the phase modulation compensation module 5 through the analog voltage output end of the AD9106 digital-to-analog converter, the voltage signal is amplified by the ADA4897 operational amplifier and then drives the in-phase modulation input end of the ADL5380 quadrature demodulator, at the same time, the main clock signal is injected into the local oscillator input end of the ADL5380 quadrature demodulator, the generated phase modulation wave is converted into a time delay compensation amount opposite to the predicted jitter through the HMC928 voltage-controlled phase shifter, and finally fed back to the compensation injection node of the clock distribution network module 2 through the radio frequency compensation output end, forming a feedforward correction closed loop, and the compensation mechanism can suppress the jitter caused by the switching noise.

[0045] The digital correction engine module 7 synchronously processes the serial data of the four analog-to-digital converters, the XC7A100T field programmable gate array receives the serial data output end signals of each converter, first applies a complex exponential phase weight to the four-channel data, and then compensates the channel mismatch through a 128-order finite impulse response filter, and finally outputs a control signal with a jitter standard deviation of <0.5% to the PID controller 8.

[0046] This process eliminates the phase misjudgment caused by picosecond-level jitter of the sampling clock, suppresses the amplitude of the high-frequency self-excited oscillation, and greatly reduces the sputtering rate of the xenon lamp electrode.

[0047] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A laboratory constant solar irradiance illumination management system, characterized by, The low-jitter clock source module (1), the clock distribution network module (2), the jitter monitoring front-end module (3), the adaptive prediction engine module (4), the phase modulation compensation module (5), the time-interleaved analog-to-digital converter array module (6), the digital correction engine module (7), the PID controller (8), and the solar simulator (9) are included. The low-jitter clock source module (1) is used to generate a 156.25MHz main clock signal, the clock distribution network module (2) is connected to the low-jitter clock source module (1), the clock distribution network module (2) is used to generate four sampling clocks and monitoring clocks with a phase difference of 90°, the time-interleaved analog-to-digital converter array module (6) is connected to the clock distribution network module (2), the time-interleaved analog-to-digital converter array module (6) is used to perform four-phase sampling, the jitter monitoring front-end module (3) is connected to the clock distribution network module (2), the jitter monitoring front-end module (3) is used to quantize the clock jitter in real time, the adaptive prediction engine module (4) is connected to the jitter monitoring front-end module (3), the adaptive prediction engine module (4) is used to perform long short-term memory network prediction, the phase modulation compensation module (5) is connected to the adaptive prediction engine module (4) and the clock distribution network module (2), the phase modulation compensation module (5) is used to generate a phase correction signal, the digital correction engine module (7) is connected to the time-interleaved analog-to-digital converter array module (6), the digital correction engine module (7) is used for data processing and control output, the PID controller (8) is connected to the digital correction engine module (7) and the solar simulator (9), and the PID controller (8) receives signal data from the digital correction engine module (7) to control the solar simulator (9).

2. A laboratory constant solar irradiance illumination management system according to claim 1, characterized in that, The low-jitter clock source module (1) comprises an LT3045-5 voltage stabilizer, an ADP7118 low-dropout linear voltage stabilizer, a constant-temperature crystal oscillator, a first phase-locked loop, a second phase-locked loop, a third phase-locked loop, a first TMP117 temperature sensor, and an ADN8834 thermoelectric cooler controller (8), the input end of the LT3045-5 voltage stabilizer is connected to electricity, the power supply end of the LT3045-5 voltage stabilizer is connected to the electricity connection end of the constant-temperature crystal oscillator through an LC filter, the clock output end of the constant-temperature crystal oscillator is connected to the reference clock input end of the first phase-locked loop through a first capacitor, the input end of the ADP7118 low-dropout linear voltage stabilizer is connected to electricity, the power supply end of the ADP7118 low-dropout linear voltage stabilizer is connected to the electricity connection end of the second phase-locked loop, the radio frequency output end of the second phase-locked loop is connected to the frequency input end of the third phase-locked loop through an LC filter, the differential clock output positive end and the differential clock output negative end of the third phase-locked loop are set as the output end of the low-jitter clock source module (1) to output a differential clock, the serial data line and the serial clock line of the first TMP117 temperature sensor are connected to the corresponding communication interfaces of the ADN8834 thermoelectric cooler controller (8), and the positive driving output end and the negative driving output end of the ADN8834 thermoelectric cooler controller (8) are both connected to the thermoelectric cooling interface of the constant-temperature crystal oscillator.

3. A laboratory constant solar irradiance illumination management system according to claim 1, wherein, The clock distribution network module (2) comprises an ADCLK954 clock buffer, an ADA4940 differential receiver, a first DS1023S programmable delay chip, a second DS1023S programmable delay chip, a third DS1023S programmable delay chip, the differential clock input positive and negative terminals of the ADCLK954 clock buffer are connected with the output terminal of the low-jitter clock source module (1), the first single-ended clock output terminal of the ADCLK954 clock buffer is connected to the non-inverting input terminal of the ADA4940 differential receiver through a first resistor, the inverting input terminal of the ADA4940 differential receiver is grounded through a second resistor, the output terminal of the ADA4940 differential receiver outputs a monitoring clock to the jitter monitoring front-end module (3), the second single-ended clock output terminal of the ADCLK954 clock buffer is connected to the clock input terminal of the first AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module (6), the third single-ended clock output terminal of the ADCLK954 clock buffer is connected to the signal input terminal of the first DS1023S programmable delay chip, and a compensation injection node is arranged between the third single-ended clock output terminal of the ADCLK954 clock buffer and the signal input terminal of the first DS1023S programmable delay chip, the compensation injection node is connected with the radio frequency output terminal of the phase modulation compensation module (5) through a coupling capacitor, the signal output terminal of the first DS1023S programmable delay chip is connected to the clock input terminal of the second AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module (6), the fourth single-ended clock output terminal of the ADCLK954 clock buffer is connected to the signal input terminal of the second DS1023S programmable delay chip, the signal output terminal of the second DS1023S programmable delay chip is connected to the clock input terminal of the third AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module (6), the fifth single-ended clock output terminal of the ADCLK954 clock buffer is connected to the signal input terminal of the third DS1023S programmable delay chip, and the signal output terminal of the third DS1023S programmable delay chip is connected to the clock input terminal of the fourth AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module (6).

4. A laboratory constant solar irradiance illumination management system according to claim 1, wherein, The time-interleaved analog-to-digital converter array module (6) comprises an ADA4807 operational amplifier, an ADG1612 analog switch, a first AD4003 analog-to-digital converter, a second AD4003 analog-to-digital converter, a third AD4003 analog-to-digital converter, a fourth AD4003 analog-to-digital converter, and an LTC6655 reference source, wherein the signal output end of the ADA4807 operational amplifier is connected to the common end of the ADG1612 analog switch through a third resistor, the inverting input end of the ADA4807 operational amplifier is connected to the gain end thereof through a fourth resistor, the first channel output end of the ADG1612 analog switch is connected to the analog voltage input end of the first AD4003 analog-to-digital converter, the second channel output end of the ADG1612 analog switch is connected to the analog voltage input end of the second AD4003 analog-to-digital converter, the third channel output end of the ADG1612 analog switch is connected to the analog voltage input end of the third AD4003 analog-to-digital converter, the fourth channel output end of the ADG1612 analog switch is connected to the analog voltage input end of the fourth AD4003 analog-to-digital converter, the conversion start end of the first AD4003 analog-to-digital converter, the second AD4003 analog-to-digital converter, the third AD4003 analog-to-digital converter, and the fourth AD4003 analog-to-digital converter is connected to the conversion control end of the digital correction engine, the serial data output end of the first AD4003 analog-to-digital converter is connected to the first data input end of the digital correction engine, the serial data output end of the second AD4003 analog-to-digital converter is connected to the second data input end of the digital correction engine, the serial data output end of the third AD4003 analog-to-digital converter is connected to the third data input end of the digital correction engine, the serial data output end of the fourth AD4003 analog-to-digital converter is connected to the fourth data input end of the digital correction engine, and the output end of the LTC6655 reference source is connected to the reference voltage input end of the first AD4003 analog-to-digital converter, the second AD4003 analog-to-digital converter, the third AD4003 analog-to-digital converter, and the fourth AD4003 analog-to-digital converter.

5. A laboratory constant solar irradiance illumination management system according to claim 1, wherein, The jitter monitoring front-end module (3) comprises an ADCMP605 high-speed comparator, an LM6172 voltage feedback amplifier, a bipolar transistor, an LF398 sample and hold, a TDC7201 time-to-digital converter, the signal output end of the ADCMP605 high-speed comparator is connected to the inverting input end of the LM6172 voltage feedback amplifier through the fifth resistor, the output end of the LM6172 voltage feedback amplifier is connected to the base of the bipolar transistor, the collector of the bipolar transistor is connected to the analog input end of the LF398 sample and hold through the sixth resistor, the emitter of the bipolar transistor is grounded, the signal output end of the LF398 sample and hold is connected to the stop signal input end of the TDC7201 time-to-digital converter, the chip select output end of the TDC7201 time-to-digital converter is connected to the chip select input end of the adaptive prediction engine, the serial clock output end of the TDC7201 time-to-digital converter is connected to the clock input end of the adaptive prediction engine, and the serial data output end of the TDC7201 time-to-digital converter is connected to the data input end of the adaptive prediction engine.

6. A laboratory constant solar irradiance illumination management system according to claim 1, wherein, The adaptive prediction engine module (4) comprises an STM32H743VI microcontroller, an AD9106 digital-to-analog converter, an IS61WV51216 static random access memory and a second TMP117 temperature sensor, the data bus output end of the STM32H743VI microcontroller is connected to the parallel data input end of the AD9106 digital-to-analog converter, the write enable output end of the STM32H743VI microcontroller is connected to the write control input end of the AD9106 digital-to-analog converter, the data input and output end of the IS61WV51216 static random access memory is connected to the memory data bus of the STM32H743VI microcontroller, the serial data line of the second TMP117 temperature sensor is connected to the serial data input and output end of the STM32H743VI microcontroller, the serial clock line of the second TMP117 temperature sensor is connected to the serial clock output end of the STM32H743VI microcontroller, and the analog voltage output end of the AD9106 digital-to-analog converter outputs a compensation control signal.

7. A laboratory constant solar irradiance illumination management system according to claim 1, wherein, The phase modulation compensation module (5) comprises an ADA4897 operational amplifier, an ADL5380 quadrature demodulator and an HMC928 voltage-controlled phase shifter, the non-inverting input end of the ADA4897 operational amplifier is connected with the analog voltage output end of the AD9106 digital-to-analog converter in the adaptive prediction engine module (4), the signal output end of the ADA4897 operational amplifier is connected with the in-phase modulation input end of the ADL5380 quadrature demodulator, the local oscillator input end of the ADL5380 quadrature demodulator receives a main clock signal, the radio frequency output end of the ADL5380 quadrature demodulator is connected with the radio frequency input end of the HMC928 voltage-controlled phase shifter, the radio frequency output end of the HMC928 voltage-controlled phase shifter is set as a compensation signal output end, and the control voltage end of the HMC928 voltage-controlled phase shifter is connected with the AD9106 digital-to-analog converter in the adaptive prediction engine module (4) through the seventh resistor.

8. A laboratory constant solar irradiance illumination management system according to claim 1, wherein, The digital correction engine module (7) comprises an XC7A100T field programmable gate array, an MT41K256M16 memory and a DAC8881 digital-to-analog converter, the first serial data input end of the XC7A100T field programmable gate array is connected with the data output end of the first AD4003 analog-to-digital converter in the time-interleaved analog-to-digital converter array module (6), the second serial data input end of the XC7A100T field programmable gate array is connected with the data output end of the second AD4003 analog-to-digital converter, the third serial data input end of the XC7A100T field programmable gate array is connected with the data output end of the third AD4003 analog-to-digital converter, the fourth serial data input end of the XC7A100T field programmable gate array is connected with the data output end of the fourth AD4003 analog-to-digital converter, the memory data bus of the XC7A100T field programmable gate array is connected with the corresponding data bus of the MT41K256M16 memory, the digital-to-analog conversion control end of the XC7A100T field programmable gate array is connected with the serial data input end of the DAC8881 digital-to-analog converter through the eighth resistor, and the analog voltage output end of the DAC8881 digital-to-analog converter is connected with the input end of the PID controller (8).

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