Chip control circuit and method for adaptive frequency and voltage regulation

Abstract

The application relates to the technical field of integrated circuits, and provides a chip control circuit and method for adaptive frequency modulation and voltage modulation, which comprises a timing monitoring module, a critical path replication submodule and a daisy chain delay submodule connected to the timing monitoring module, the critical path replication submodule is used for simulating an actual critical data path in a chip, the daisy chain delay submodule is used for applying a configurable delay amount on the timing of an output data signal, so as to simulate the timing performance after different time points, a first flip-flop is used for transmitting the data signal, a sampling flip-flop module is used for sampling the data signal output by the timing monitoring module, a comparison logic module is used for generating a multi-bit timing margin indication code through a comparison result, and the timing margin indication code is used for adaptively adjusting the working frequency or working voltage of the chip. Through accurate monitoring and adaptive adjustment of the timing of the chip, all design margins can be utilized, the energy utilization efficiency is improved, and therefore, the ultimate low power consumption is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a chip control circuit and method for adaptive frequency and voltage scaling. BACKGROUND

[0002] In the field of chip design, PPA (Performance, Power, Area) is three key factors. With the continuous development of chip technology, the improvement of chip performance gradually encounters a bottleneck, at which time the power consumption problem becomes increasingly important. Lower power design becomes a key requirement throughout all aspects of chip design, aiming to reduce the energy consumption of the chip, improve energy efficiency, and prolong the endurance time of the device.

[0003] The traditional dynamic voltage and frequency scaling (DVFS) technology is a frequency and voltage scaling method based on a fixed voltage-frequency correspondence, which adopts an open-loop design. Although this design is easy to implement, it has obvious low efficiency problems. For example, for general-purpose computing on graphics processing units (GPGPU) processors, the working scenario is provided by the host, and the GPGPU cannot predict the next working scenario in advance. Therefore, DVFS cannot accurately adjust the voltage and frequency according to the real-time working state of the chip, and cannot achieve the ultimate low power consumption.

[0004] In addition, in this open-loop design, in order to ensure that the chip can operate normally under various possible working conditions, the designer needs to reserve a certain design margin, which makes the chip unable to fully exert its ultimate performance of the circuit, causing waste of energy. SUMMARY

[0005] The present application provides a chip control circuit and method for adaptive frequency and voltage scaling, which adopts an AVFS (Adaptive Voltage and Frequency Scaling) closed-loop power control technology, can monitor the timing state of the chip in real time, and adaptively adjusts the working frequency and working voltage of the chip according to the generated timing margin indication code, thereby improving the energy utilization efficiency.

[0006] The application provides a chip control circuit with adaptive frequency and voltage adjustment, comprising: a timing monitoring module, comprising a critical path replication sub-module and a daisy chain delay sub-module connected in sequence, the critical path replication sub-module being used for simulating an actual critical data path in the chip; the daisy chain delay sub-module comprising a plurality of delay units connected in sequence, and being used for applying a delay amount on a timing of an output data signal; the delay amount being configurable to simulate timing performance at different time points; a first flip-flop, with an output end connected to an input end of the timing monitoring module, and being used for transmitting a data signal to the timing monitoring module under driving of a clock signal; a sampling flip-flop module, with an input end connected to an output end of the timing monitoring module, and being used for sampling the data signal delayed by the timing monitoring module under driving of the clock signal to obtain a plurality of sampling outputs; a comparison logic module, with input ends connected to an output end of the first flip-flop and the plurality of output ends of the sampling flip-flop module, respectively, and being used for generating a multi-bit timing margin indication code through a comparison result; and the timing margin indication code being capable of representing a delay state of the timing monitoring module, and being used for adaptively adjusting a working frequency or a working voltage of the chip.

[0007] According to the chip control circuit with adaptive frequency and voltage adjustment provided by the application, the delay unit is an inverter.

[0008] According to the chip control circuit with adaptive frequency and voltage adjustment provided by the application, the sampling flip-flop module comprises a plurality of sampling flip-flops, and a fixed delay unit is arranged between signal input paths of adjacent sampling flip-flops, so that there is a preset time difference in time when the data signal reaches input ends of the sampling flip-flops, and the data signal delayed by the timing monitoring module is sampled in time.

[0009] According to the chip control circuit with adaptive frequency and voltage adjustment provided by the application, the comparison logic module comprises a plurality of XOR units, each XOR unit being used for comparing output data of the first flip-flop with output data of a corresponding sampling flip-flop in the sampling flip-flop module to generate one bit of the timing margin indication code.

[0010] The chip control circuit for adaptive frequency and voltage adjustment provided in the application comprises a fixed delay unit, a plurality of exclusive OR units, a plurality of sampling flip-flops, and a timing monitoring module.

[0011] The chip control circuit for adaptive frequency and voltage adjustment provided in the application comprises a fixed delay unit, a plurality of exclusive OR units, a plurality of sampling flip-flops, and a timing monitoring module.

[0012] The chip control method for adaptive frequency and voltage adjustment provided in the application comprises the following steps: gradually adjusting the delay amount of the timing monitoring module under a preset working voltage; monitoring the timing margin indication code output by the comparison logic module until the circuit is in a critical working state; and determining the maximum working frequency under the preset working voltage based on the clock period of the current circuit and the delay amount of the timing monitoring module.

[0013] The chip control method for adaptive frequency and voltage adjustment provided in the application comprises the following steps: gradually adjusting the delay amount of the timing monitoring module under a preset working voltage; monitoring the timing margin indication code output by the comparison logic module until the circuit is in a critical working state; and determining the maximum working frequency under the preset working voltage based on the clock period of the current circuit and the delay amount of the timing monitoring module.

[0014] According to the chip control method for adaptive frequency and voltage adjustment provided in the application, after generating the frequency-voltage relationship table based on the plurality of preset working voltages and the maximum working frequencies corresponding to each preset working voltage, the method further comprises: reading initial working parameters from the frequency-voltage relationship table in response to a low-power-consumption task; and performing frequency reduction or voltage reduction processing on the initial working parameters in combination with the timing margin indication code until the timing margin indication code indicates a critical state, to determine the target working parameters of the low-power-consumption task, so as to achieve the lowest power consumption.

[0015] According to the chip control method for adaptive frequency and voltage adjustment provided in the application, after generating the frequency-voltage relationship table based on the plurality of preset working voltages and the maximum working frequencies corresponding to each preset working voltage, the method further comprises: reading initial working parameters from the frequency-voltage relationship table in response to a high-power-consumption task; and performing frequency increase or voltage increase processing on the initial working parameters in combination with the timing margin indication code until the timing margin indication code indicates a critical state, to determine the target working parameters of the high-power-consumption task.

[0016] The chip control circuit and method for adaptive frequency and voltage adjustment provided in the application comprise: a timing monitoring module comprising a critical path replication submodule and a daisy chain delay submodule connected in sequence, the critical path replication submodule being configured to simulate an actual critical data path in the chip; the daisy chain delay submodule comprising a plurality of delay units connected in sequence, the daisy chain delay submodule being configured to apply a delay amount to an output data signal in terms of timing; the delay amount being configurable to simulate timing performance at different time points; and a comparison logic module having input ends connected to an output end of a first flip-flop and a plurality of output ends of a sampling flip-flop module, respectively, and configured to generate a multi-bit timing margin indication code through a comparison result; the timing margin indication code being configured to represent a delay state of the timing monitoring module and to adaptively adjust a working frequency or a working voltage of the chip. In this way, the application can monitor the timing state of the chip in real time and adaptively adjust the working frequency and the working voltage of the chip according to the generated timing margin indication code, so that the chip can better adapt to various complex and changeable working scenarios; the design margin is fully utilized to improve energy utilization efficiency, thereby achieving extreme low power consumption; in addition, the configurable delay amount enables the timing monitoring module to adapt to different chip working scenarios and requirements, and the timing state under the corresponding conditions can be accurately monitored by adjusting the delay amount, so that more flexible and accurate adaptive frequency and voltage adjustment control is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0018] Figure 1 is one of the structural schematic diagrams of the chip control circuit for adaptive frequency modulation and voltage regulation provided by the embodiments of the present application.

[0019] Figure 2 is the second structural schematic diagram of the chip control circuit for adaptive frequency modulation and voltage regulation provided by the embodiments of the present application.

[0020] Figure 3 is the flowchart of the chip control method for adaptive frequency modulation and voltage regulation provided by the embodiments of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be described clearly and completely in the following with reference to the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.

[0022] In the description of the embodiments of the present application, it should be noted that the terms "first", "second", "third" are only used for description purpose, and cannot be understood as indicating or implying relative importance. Unless otherwise specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0023] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0024] The embodiments of the present application provide a chip control circuit for adaptive frequency and voltage regulation, which can utilize all design margins and improve energy utilization efficiency, thereby achieving extremely low power consumption.

[0025] Please refer to Figure 1 , Figure 1 is one of the structure schematic diagrams of the chip control circuit for adaptive frequency and voltage regulation provided by the embodiments of the present application.

[0026] In the embodiments, the chip control circuit for adaptive frequency and voltage regulation includes a timing monitoring module 110, a first flip-flop 120, a sampling flip-flop module 130 and a comparison logic module 140. These modules cooperate with each other to generate a timing margin indication code by monitoring and analyzing the chip timing, thereby realizing adaptive adjustment of the chip working frequency or working voltage.

[0027] The timing monitoring module 110 includes a critical path replication sub-module 111 and a daisy chain delay sub-module 112 connected in series. The critical path replication sub-module 111 is used to simulate the actual critical data path in the chip. The daisy chain delay sub-module 112 includes a plurality of delay units connected in series. The daisy chain delay sub-module 112 is used to apply a delay amount in time to the output data signal. The delay amount can be configured to simulate the timing performance at different time points.

[0028] The first flip-flop 120 has an output end connected to an input end of the timing monitoring module 110, and is used to emit a data signal to the timing monitoring module 110 under the driving of a clock signal.

[0029] The sampling flip-flop module 130 has an input end connected to an output end of the timing monitoring module 110, and is used to sample the data signal delayed by the timing monitoring module 110 under the driving of a clock signal, to obtain a plurality of sampling outputs.

[0030] A comparison logic module 140 is connected to the output of the first flip-flop 120 and the outputs of the sampling flip-flop module 130, respectively, for generating a multi-bit timing margin indicator code by comparing the results.

[0031] In the embodiment, the critical path replica submodule 111 is used to simulate the actual critical data path in the chip.

[0032] The critical path replica submodule 111 simulates the transmission process of the signal on the actual critical data path in the chip by replicating the circuit structure of the actual critical data path. When the chip is working normally, the actual critical data path transmits various data signals, and the critical path replica submodule 111 also processes the same data signals at the same time. Therefore, by monitoring the signal transmission of the critical path replica submodule 111, the timing performance of the actual critical data path can be indirectly understood.

[0033] The daisy chain delay submodule 112 is composed of a plurality of sequentially connected delay units. Optionally, the delay unit can be an inverter. The daisy chain delay submodule 112 is used to apply a delay amount to the output data signal in terms of timing, and the delay amount is configurable. Therefore, the timing performance of the chip at different time points can be simulated, so that the timing characteristics of the chip can be more comprehensively evaluated.

[0034] For example, when the data signal enters the daisy chain delay submodule 112, the signal will be delayed after passing through each delay unit. Since the delay units in the embodiment are sequentially connected, the signal will accumulate a total delay amount after passing through a plurality of delay units. Moreover, the delay amount is configurable, and by adjusting the number of delay units participating in the signal delay or changing the parameters of the delay units, the timing performance at different time points can be simulated.

[0035] The first flip-flop 120 works under the drive of a clock signal. The clock signal is a periodic signal that provides a time reference for the operation of the register.

[0036] The input of the sampling flip-flop module 130 is connected to the output of the timing monitoring module 110. The sampling flip-flop module 130 also works under the drive of the clock signal. The sampling process is to obtain the current state of the data signal at a certain time and store it in the sampling flip-flop module 130.

[0037] The input ends of the comparison logic module 140 are respectively connected to the output end of the first flip-flop 120 and the plurality of output ends of the sampling flip-flop module 130. The comparison logic module 140 can compare the original data signal output by the first flip-flop 120 and the plurality of sampling data signals output by the sampling flip-flop module 130 to determine the state change of the data signal after being delayed by the timing monitoring module 110.

[0038] According to the comparison result, the comparison logic module 140 can generate a multi-bit timing margin indication code. The timing margin indication code can be used to represent the delay state of the timing monitoring module 110, thereby providing a basis for adaptively adjusting the working frequency or working voltage of the chip.

[0039] In the above, in the chip control circuit for adaptive frequency and voltage adjustment provided in the embodiments of the present application, the timing margin of the chip is monitored in real time, and the working frequency or working voltage can be adaptively adjusted according to the actual working state of the chip. When the timing margin of the chip is large, the working frequency can be appropriately increased to improve the processing speed of the chip; when the timing margin of the chip is small, the working frequency or voltage can be reduced to ensure the stability of the chip; different working scenarios have different performance requirements for the chip. Through adaptive frequency and voltage adjustment, the power consumption of the chip can be reduced on the premise of meeting the performance requirements.

[0040] In addition, the delay amount of the control circuit can be configured to simulate different timing scenarios. This enables chip designers to more flexibly evaluate the timing characteristics of the chip during the design process and optimize the design scheme of the chip; by simulating the critical data path of the chip and the timing performance at different time points, potential timing problems of the chip can be found in time, and once the timing margin is found to be insufficient, the working frequency or voltage can be adjusted in time to avoid chip failure caused by timing problems and improve the reliability and stability of the chip.

[0041] Unlike the DVFS open-loop design mentioned in the related art, the present embodiment applies AVFS, which can make accurate adjustments according to the actual working condition of the chip and fully exploit the ultimate performance of the circuit. Therefore, the chip can run at the lowest power consumption in different working scenarios, achieving extreme low power consumption and greatly improving energy utilization efficiency and prolonging the endurance time of the device.

[0042] Since the timing state of the chip is affected by multiple factors such as temperature, voltage, and process, the control circuit can monitor and adapt to these changes in real time. For example, when the temperature of the chip rises, causing the performance of the transistor to decrease and the signal delay to increase, the control circuit can compensate for this change by adjusting the working frequency or voltage to ensure that the chip can stably operate in different working environments and improve the reliability and stability of the chip.

[0043] For the processor like GPGPU which cannot predict the working scene, the embodiment can dynamically adjust according to the real-time timing monitoring result, so that the chip can better adapt to various complex and changeable working scenes. Whether in high load or low load, the chip can maintain stable performance, avoid performance fluctuation caused by changes in working scene, and improve the overall performance and adaptability of the chip.

[0044] In some embodiments, the sampling flip-flop module includes a plurality of sampling flip-flops, and fixed delay units are arranged between the signal input paths of adjacent sampling flip-flops, so that there is a preset time difference in the time when the data signal reaches the input end of each sampling flip-flop, to time-share sample the data signal delayed by the timing monitoring module.

[0045] The sampling flip-flop module is composed of a plurality of sampling flip-flops, and fixed delay units are arranged between the signal input paths of adjacent sampling flip-flops. These delay units have stable and known delay characteristics. When the data signal delayed by the timing monitoring module is transmitted, a fixed time delay is generated every time a fixed delay unit is passed, and a preset time difference is formed in the time when the data signal reaches the input end of each sampling flip-flop.

[0046] For example, assuming that the first sampling flip-flop receives the data signal at time t1, after passing through a fixed delay unit, the second sampling flip-flop will receive the data signal at t1+Δt (Δt is the delay time of the fixed delay unit). In this way, under the synchronous control of the clock signal, each sampling flip-flop will sample the data signal at its corresponding time point, thereby realizing time-share sampling.

[0047] In some embodiments, the comparison logic module includes a plurality of XOR units, each XOR unit being configured to compare the output data of the first flip-flop with the output data of a corresponding sampling flip-flop in the sampling flip-flop module to generate one bit of the timing margin indicator code.

[0048] The comparison logic module includes a plurality of XOR units, each XOR unit having two input ports. One port is connected to the output end of the first flip-flop to obtain the original data signal, and the other port is connected to the output end of a corresponding sampling flip-flop in the sampling flip-flop module to obtain the data signal after delay and sampling.

[0049] Each XOR unit will perform XOR operation on its two input signals. The rule of XOR operation is that when the two input signals are the same, the output is 0; when the two input signals are different, the output is 1.

[0050] The output of each XOR unit constitutes one bit of the timing margin indication code. The outputs of the plurality of XOR units are combined to form a multi-bit timing margin indication code. The indication code can reflect the difference between the data signal after different delays and the original signal, thereby representing the delay state of the timing monitoring module.

[0051] In the embodiment, the difference between the original data signal and the sampled data signal after different delays can be accurately compared through XOR operation. Each bit of the timing margin indication code corresponds to the sampling result at a specific time point, and the combination of the multi-bit indication code can describe the change of the data signal at different delay stages in detail, thereby providing accurate data for accurately evaluating the timing margin of the chip.

[0052] In some embodiments, the fixed delay unit includes a first fixed delay unit and a second fixed delay unit; the input end of the first fixed delay unit is connected to the output end of the timing monitoring module; and the output end of the first fixed delay unit is connected to the input end of the second fixed delay unit.

[0053] The plurality of XOR units includes a first XOR unit, a second XOR unit, and a third XOR unit; the first XOR unit, the second XOR unit, and the third XOR unit are respectively connected to the output end of the first flip-flop.

[0054] The plurality of sampling flip-flops includes a first sampling flip-flop, a second sampling flip-flop, and a third sampling flip-flop; the first sampling flip-flop is respectively connected to the output end of the timing monitoring module, a clock signal, and the first XOR unit; the second sampling flip-flop is respectively connected to the output end of the first fixed delay unit, the clock signal, and the second XOR unit; and the third sampling flip-flop is respectively connected to the output end of the second fixed delay unit, the clock signal, and the third XOR unit.

[0055] In some embodiments, when the timing margin indication code is 000 or 001, it indicates that the current timing margin is sufficient, and the control module of the chip is instructed to increase the working frequency or reduce the working voltage.

[0056] When the timing margin indication code is 011 or 111, it indicates that the current timing margin is in a critical state, and the control module of the chip is instructed to maintain the current working frequency and working voltage.

[0057] As mentioned in the above embodiments, the comparison logic module compares the output data of the first flip-flop with the output data of the corresponding sampling flip-flop in the sampling flip-flop module through the plurality of XOR units to generate the timing margin indication code. Each bit of the timing margin indication code reflects the difference between the data signal after delay and sampling and the original data signal at a specific delay time point.

[0058] Specifically, when the timing margin indication code is 000, the data signals sampled by the three sampling flip-flops are the same as the original data signal output by the first flip-flop in the corresponding exclusive-OR operation, that is, the data signal has not changed substantially after different delays, indicating that the timing margin of the current chip is very sufficient. When the timing margin indication code is 001, the data signal of only one sampling point is different from the original signal, which still indicates that the timing margin is relatively sufficient.

[0059] At this time, the control module of the chip can make corresponding adjustments according to this information. Increasing the working frequency can make the chip process more tasks in unit time, thereby improving the performance of the chip; reducing the working voltage can reduce the power consumption of the chip and improve the energy utilization efficiency.

[0060] When the timing margin indication code is 011, the data signals of two sampling points are different from the original signal. When the timing margin indication code is 111, the data signals of the three sampling points are all different from the original signal, which indicates that the data signal has changed greatly after delay, indicating that the timing margin of the current chip is in a critical state, close to the edge of timing error.

[0061] At this time, the control module of the chip will maintain the current working frequency and working voltage. Because in the critical state, any adjustment of frequency or voltage may cause the chip to have timing errors and affect the normal operation of the chip, so maintaining the status is to ensure the stability of the chip.

[0062] In the above, the embodiment dynamically adjusts based on the timing margin indication code, so that the chip can respond in real time according to its timing state. This adaptive adjustment mechanism enhances the adaptability of the chip to different workloads and environmental conditions, and improves the overall performance and reliability of the chip.

[0063] In the embodiment, AVFS is adopted, and the underlying of AVFS relies on the timing monitor for monitoring. Specifically, the working state of the function circuit (Function) is reflected by monitoring the sampling between two registers. If the monitoring circuit works normally, it indicates that the current working condition still has room for further reduction, for example, the working voltage or frequency can be reduced; when the monitoring circuit is abnormal, it means that the critical condition has been reached, and the working condition cannot be further reduced, otherwise it may affect the normal operation of the system.

[0064] The monitoring circuit is in a continuous working state, which combines voltage (Voltage) and temperature (Temperature) as two key factors to build a closed-loop power control system. The system can perform real-time and dynamic closed-loop power control on the system on chip (SoC) according to the monitored information, so as to optimize the power consumption under the premise of ensuring the system performance.

[0065] Please refer to Figure 2 , Figure 2 Figure 2 is a structural schematic diagram of a chip control circuit for adaptive frequency and voltage adjustment provided by the embodiment of the present application.

[0066] The fixed delay unit includes a first fixed delay unit and a second fixed delay unit; the delay time of the first fixed delay unit and the second fixed delay unit is 30 ps.

[0067] The input end of the first fixed delay unit is connected to the output end of the timing monitoring module 210; the output end of the first fixed delay unit is connected to the input end of the second fixed delay unit. The timing monitoring module 210 includes a critical path (corresponding to the critical path replication submodule described above) and a daisy chain delay submodule.

[0068] The plurality of exclusive OR units includes a first exclusive OR unit P[2], a second exclusive OR unit P[1], and a third exclusive OR unit P[0]; the first exclusive OR unit P[2], the second exclusive OR unit P[1], and the third exclusive OR unit P[0] are respectively connected to the output end of the first flip-flop.

[0069] The plurality of sampling flip-flops includes a first sampling flip-flop, a second sampling flip-flop, and a third sampling flip-flop; the first sampling flip-flop is respectively connected to the output end of the timing monitoring module 210, a clock signal, and the first exclusive OR unit P[2]; the second sampling flip-flop is respectively connected to the output end of the first fixed delay unit, a clock signal, and the second exclusive OR unit P[1]; the third sampling flip-flop is respectively connected to the output end of the second fixed delay unit, a clock signal, and the third exclusive OR unit P[0].

[0070] In addition, an inverter I[0] can also be arranged between the first flip-flop and the plurality of exclusive OR units of the comparison logic module; the inverter I[0] is used to make the value of the first flip-flop change every clock cycle, for example, the value of the first flip-flop Q i is 0 in the previous clock cycle, and the value of the first flip-flop Q i+1 is 1 in the next clock cycle, so as to achieve the purpose of real-time comparison.

[0071] In the embodiment, the flip-flop FF includes a data input end (D), a clock input end (CLK), and an output end (Q). The clock input end (CLK) of different flip-flops is connected to the signal output by different registers.

[0072] For example, the first flip-flop is connected to the reg0 signal output by the first register; the first sampling flip-flop is connected to the reg1 signal output by the second register; the second sampling flip-flop is connected to the reg2 signal output by the third register; and the third sampling flip-flop is connected to the reg3 signal output by the fourth register.

[0073] In hardware circuit, the highest working frequency that it can reach is determined by the highest frequency of critical path. The critical path is mainly composed of two parts, namely clock path and data path.

[0074] Since in practical application, the actual highest frequency of hardware circuit needs to be known exactly, the real critical path needs to be processed accordingly so as to be measured.

[0075] Specifically, the original critical path is copied as a critical path copy sub-module, wherein the critical path includes critical clock path and critical data path. Through copying, relevant detection can be carried out without affecting the normal work of the original circuit.

[0076] A configurable daisy chain delay sub-module is added behind the copied critical data path, which can be composed of inverters (inv) and 64-level inverters are inserted.

[0077] The purpose of inserting the delay chain is to simulate the transmission of the signal after a certain time. Since each inverter introduces a certain delay, the maximum delay time of 64-level inverters is 640ps.

[0078] When the prospect detection circuit cannot work normally, but the function circuit (function) can work normally, this can be used as an early warning signal, indicating that there may be a timing risk in the circuit. At this time, the adaptive voltage and frequency scaling (AVFS) closed-loop power control system can be used to adjust the working conditions of the circuit, such as adjusting the voltage or frequency, to avoid circuit failure caused by timing problems.

[0079] In combination with the accompanying drawings Figure 2A trigger (flop) is placed at the source point (source) as a launch. The trigger generates a signal at each clock cycle to start the transmission of data in the critical path. Three triggers are placed in sequence at the destination point (dest), and a delay of 30 ps is manually set between each trigger at the destination point. The triggers act as capture units to capture the signal after transmission in the critical path. By setting different delays, the timing conditions after 30 ps and 60 ps can be respectively previewed, and the transmission characteristics of the signal in the critical path can be more comprehensively understood.

[0080] For the subsequent three triggers, an exclusive-OR logic operation is performed on each trigger. The exclusive-OR logic detects whether the signals at the source point (source) and the destination point (dest) are consistent. Such detection is performed at each clock cycle, so that the transmission of the signal in the critical path can be monitored in real time to determine whether an error occurs.

[0081] In this embodiment, the timing margin indication code Pass[2:0] can be used to indicate whether there is still a margin for the current sampling. The timing margin indication code Pass[2:0] can be regarded as a 3-bit state flag, and each bit corresponds to the detection result of a trigger. Through the 3-bit flag, the timing margin of the signal under different delay conditions can be intuitively understood.

[0082] In the above, the embodiment can find potential timing problems in advance by copying the critical path, inserting a delay chain, and setting a launch capture unit, provide a time window for timely adjusting the working conditions, and avoid errors caused by timing faults in the circuit; by setting different delays and performing multi-level exclusive-OR logic detection, the transmission of the signal can be monitored at multiple time points, the timing characteristics of the circuit can be more comprehensively understood, and more accurate basis can be provided for AVFS closed-loop power control; the timing margin is represented by Pass[2:0], which can present the timing conditions in a quantitative manner, so that the system can accurately adjust the working conditions according to the margin conditions, and balance the performance and power consumption.

[0083] The embodiment of the present application also provides a chip control method for adaptive frequency and voltage adjustment.

[0084] Please refer to Figure 3 , Figure 3 which is a flowchart of the chip control method for adaptive frequency and voltage adjustment provided by the embodiment of the present application. In this embodiment, the chip control method for adaptive frequency and voltage adjustment can include steps S310 to S330, and each step is specifically as follows.

[0085] S310: Under a preset working voltage, gradually adjust the delay amount of the timing monitoring module.

[0086] Before starting the adaptive frequency and voltage scaling process, the chip can first set a preset operating voltage. The preset operating voltage can be the default operating voltage of the chip, or a voltage value determined in advance according to previous operation experience, application scenarios, and other factors.

[0087] Using the chip control circuit with adaptive frequency and voltage scaling described above, the timing monitoring module is used to simulate the critical path inside the chip and apply a configurable delay to the data signal. By adjusting the delay amount, the delay of the signal transmission inside the chip under different working conditions can be simulated, so as to observe the timing margin change of the chip subsequently.

[0088] S320: Monitor the timing margin indicator code output by the comparison logic module until the circuit is in a critical working state.

[0089] Using the chip control circuit with adaptive frequency and voltage scaling described above, the comparison logic module compares the original data signal output by the first flip-flop with the data signal output by the sampling flip-flop module after different delays and sampling to generate a timing margin indicator code.

[0090] During the process of gradually adjusting the delay amount of the timing monitoring module, the timing margin indicator code is continuously monitored. When the indicator code reaches a specific value (such as 011 or 111 mentioned in the above embodiment), it indicates that the current circuit is in a critical working state. In the critical working state, the timing margin of the chip is close to the limit, and there is no need to change the working parameters.

[0091] S330: Determine the maximum operating frequency under the preset operating voltage based on the clock period of the current circuit and the delay amount of the timing monitoring module.

[0092] During the chip manufacturing process, manufacturing process deviations are inevitable problems. Differences in doping concentration, diffusion depth, and etching degree will cause performance differences between different batches of chips, or even between different wafers in the same batch.

[0093] Even under the same process corner conditions, the maximum frequency that each chip can achieve is not the same. Some chips may have a maximum frequency higher than the frequency at the chip design signoff, while others may have a maximum frequency lower than the design frequency.

[0094] Therefore, it is necessary to accurately grasp the maximum operating frequency (Fmax) of each chip. On the one hand, it is beneficial to distinguish and screen products and apply different performance chips to suitable scenarios; on the other hand, it can calibrate the frequency-voltage table (F-VF table) of the chip, so that the adaptive voltage frequency scaling (AVFS) function can be accurately implemented, effectively reducing the dynamic power consumption of the chip.

[0095] In the embodiment, according to the relationship between the clock period and the delay amount, the maximum working frequency at which the chip can stably work under the preset working voltage can be calculated. The maximum working frequency is the reciprocal of the clock period, and by accurate calculation, the upper limit of the performance of the chip under the preset working voltage can be determined, thereby providing data support for subsequent adaptive frequency and voltage adjustment.

[0096] In the chip, when the function circuit works normally, the setup time constraint condition is met: Tdata < Tclk + T.

[0097] Wherein, Tdata represents the data transmission time; Tclk represents the clock period; and T represents the working time of the circuit.

[0098] In order to determine the maximum working frequency of the circuit, the delay of the data path can be changed by adjusting the daisy chain delay sub-module. The daisy chain delay sub-module is continuously adjusted until the circuit reaches the critical working condition, that is, the state of just not being able to work normally, at which time the timing margin indicator code is displayed as 111.

[0099] Under the critical working condition, the setup time constraint becomes: Tdata + Tdaisy = Tclk + T.

[0100] Wherein, Tdaisy is the delay amount introduced by the daisy chain delay sub-module. According to the relationship between the clock period and the frequency Tclk = 1 / f, the critical setup time formula is transformed, and the maximum working frequency Fmax calculation formula of the circuit is obtained: Fmax = 1 / (T-Tdaisy).

[0101] The above, the method of the embodiment of the application can accurately find the critical working state of the chip under the preset working voltage by gradually adjusting the delay amount and monitoring the timing margin indicator code. The maximum working frequency determined based on the clock period and the delay amount under this state can accurately reflect the upper limit of the performance of the chip under the voltage, thereby avoiding the performance waste or stability problem caused by inaccurate estimation; after the maximum working frequency under the preset working voltage is determined, the chip control circuit can adaptively adjust the working frequency of the chip within the maximum working frequency range according to the actual working demand and performance requirement. At the same time, in combination with the maximum working frequency data under different working voltages, the selection of the working voltage can be further optimized, thereby realizing the best balance between the performance and power consumption of the chip.

[0102] In some embodiments, after the maximum working frequency under the preset working voltage is determined based on the clock period of the current circuit and the delay amount of the timing monitoring module, the step can further include:

[0103] The plurality of preset operating voltages and the maximum operating frequencies corresponding to the plurality of preset operating voltages are obtained; a frequency-voltage relationship table is generated based on the plurality of preset operating voltages and the maximum operating frequencies corresponding to the plurality of preset operating voltages; and the frequency-voltage relationship table is used to adaptively adjust the operating frequency or the operating voltage of the chip.

[0104] In the above embodiment, the maximum operating frequency of the chip under a preset operating voltage has been determined. In order to more comprehensively understand the performance of the chip under different voltages, a plurality of preset operating voltages can be obtained, and for each preset operating voltage, steps S310-S330 in the previous adaptive frequency and voltage adjustment chip control method are repeated to determine the maximum operating frequency corresponding to the preset operating voltage.

[0105] The plurality of preset operating voltages and the maximum operating frequencies corresponding to the plurality of preset operating voltages are obtained; a frequency-voltage relationship table is generated based on the plurality of preset operating voltages and the maximum operating frequencies corresponding to the plurality of preset operating voltages; and the frequency-voltage relationship table is used to adaptively adjust the operating frequency or the operating voltage of the chip.

[0106] The frequency-voltage relationship table directly shows the maximum operating frequency that the chip can achieve under different operating voltages, and reflects the corresponding relationship between the operating frequency and the operating voltage of the chip. The control module of the chip can dynamically adjust the operating frequency or the operating voltage of the chip according to the actual operating load and performance requirements, and refer to the frequency-voltage relationship table.

[0107] For example, when the chip needs to process a high-load task and has a high performance requirement, the control module can select an operating voltage from the relationship table that can provide a high enough operating frequency to improve the performance of the chip; when the device is in a low-load running state, the control module can reduce the operating voltage according to the relationship table, and appropriately reduce the operating frequency to reduce power consumption and prolong the endurance time of the device.

[0108] It should be noted that the calibration of the frequency-voltage relationship table (F-Vt table) is important for performance optimization and power consumption control of the chip. By calibrating the table, the corresponding suitable threshold voltage can be found for different operating frequencies, so as to reduce power consumption while meeting performance requirements.

[0109] For example, a working frequency is selected, which can be less than the maximum operating frequency measured before. A suitable operating frequency is selected to simulate different working scenarios of the chip in actual application. In cooperation with a PVT (process, voltage, temperature) sensor, the threshold voltage (vt) is adjusted to test the limit threshold voltage environment under which the chip can normally work at the target frequency without affecting the performance of the chip. The PVT sensor can monitor the process, voltage and temperature changes of the chip in real time, and provide a reference for the adjustment of the threshold voltage.

[0110] Multiple sets of tests are performed to record the corresponding limit threshold voltage at different operating frequencies. Through analysis and processing of these test data, a frequency-voltage relationship table (F-Vt table) is calibrated, which can reflect the minimum threshold voltage required by the chip at different operating frequencies to achieve a balance between performance and power consumption.

[0111] Further, the calibrated frequency-voltage relationship table (F-Vt table) can be written into a flash memory as a static parameter under laboratory test conditions. The related parameters of the frequency-voltage relationship table (F-Vt table) can be read and used in the subsequent working process of the chip. In actual application, the chip can look up the corresponding threshold voltage from the table according to the current operating frequency, thereby realizing adaptive voltage adjustment.

[0112] In some embodiments, after the frequency-voltage relationship table is generated based on multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage, the step can further include:

[0113] In response to a low-power task, the initial operating parameters are read from the frequency-voltage relationship table; in combination with the timing margin indication code, the initial operating parameters are subjected to frequency reduction or voltage reduction processing until the timing margin indication code indicates a critical state, and the target operating parameters of the low-power task are determined to achieve the lowest power consumption.

[0114] In this embodiment, when the chip detects that it is currently facing a low-power task, such as when the device is in standby mode, or performing a simple background program in a scenario where the performance requirement is not high, this operation can be triggered.

[0115] The chip control module reads the initial operating parameters from the previously generated frequency-voltage relationship table.

[0116] The timing margin indication code can reflect the current timing margin state of the chip in real time. When performing frequency reduction or voltage reduction processing, the chip control module continuously monitors this indication code. The control module gradually reduces the operating frequency or operating voltage. Each adjustment is checked against the timing margin indication code output by the logic module. If the indication code still indicates that the timing margin is sufficient (such as 000 or 001 as mentioned earlier), the frequency reduction or voltage reduction operation continues; if the indication code shows that the timing margin is approaching a critical state, the amplitude of the frequency reduction or voltage reduction is appropriately adjusted to ensure the smoothness of the adjustment process.

[0117] When the adjustment reaches a critical state indicated by the timing margin indication code (such as 011 or 111), it means that the timing margin of the chip has approached the limit at this time. At this time, the current operating frequency and operating voltage are determined as the target operating parameters of the low-power task. Under this parameter, the chip can meet the basic performance requirements of the low-power task and also reduce the power consumption to the lowest.

[0118] For example, when the GPGPU starts a low-power process, in order to reduce power consumption and optimize energy efficiency, the working frequency and working condition thereof need to be adjusted, and the process is as follows:

[0119] 1. Calculate the target frequency: according to the calculation complexity and data processing amount of the low-power process, calculate the working frequency required for normal operation of the process.

[0120] 2. Reduce the working frequency: reduce the GPGPU frequency to the target frequency. Since power consumption is positively correlated with frequency, this can directly reduce power consumption.

[0121] 3. Read the minimum working condition: read the minimum working condition corresponding to the target frequency from the calibrated frequency-voltage relationship table.

[0122] 4. Initial adjustment: considering that there is an error between the frequency-voltage relationship table and the actual situation, in order to ensure the stability of the adjustment, first adjust the working condition to 1.1 times the corresponding value in the table.

[0123] 5. Approach the minimum condition: gradually reduce the working condition to approach the minimum value. During the process, attention should be paid to the timing margin indicator code of the Timingmonitor (timing monitoring module) circuit. If it shows unqualified, the working condition should be appropriately increased.

[0124] 6. Exhaust the margin: continue to adjust and exhaust all timing margins to press the GPGPU to the minimum working condition, thereby reducing power consumption to the maximum extent while meeting the process requirements.

[0125] In some embodiments, after generating the frequency-voltage relationship table based on multiple preset working voltages and the maximum working frequencies corresponding to each preset working voltage, the steps can further include:

[0126] In response to a high-power task, read the initial working parameters from the frequency-voltage relationship table; and perform frequency or voltage boosting on the initial working parameters in combination with the timing margin indicator code until the timing margin indicator code indicates a critical state, and determine the target working parameters of the high-power task.

[0127] In this embodiment, when the chip receives a task with high load and extremely high requirement for computing performance, such as running a large game, video editing, or performing complex scientific calculations, this operation can be triggered.

[0128] Similar to the above embodiment, by frequency and voltage boosting, the chip can significantly improve the computing power and data processing speed during high-power tasks, ensuring efficient completion of the task.

[0129] Exemplarily, when the GPGPU suddenly starts a high-power-consumption process, if the current bandwidth cannot meet the demand of the process, the GPGPU needs to be frequency-boosted, and the process is as follows:

[0130] 1. Reading the maximum working frequency (Fmax): from the calibrated frequency-voltage relationship table, the Fmax corresponding to the current working condition is read.

[0131] 2. Judging the processing mode according to the Fmax:

[0132] 2.1. If the Fmax can meet the bandwidth demand of the process, the working frequency of the GPGPU is increased under the current working condition. Considering that there is an error between the frequency-voltage relationship table and the actual situation, the frequency data is corrected in combination with the actual working condition (such as temperature, voltage fluctuation), and gradually adjusted to the target frequency that meets the process demand. During the process, the timing margin indicator code of the Timing monitor (timing monitoring module) circuit needs to be paid attention to, so as to ensure that the timing is qualified, and to avoid data transmission errors or circuit failure.

[0133] 2.2. If the Fmax cannot meet the bandwidth demand, the working voltage and frequency of the GPGPU are increased at the same time, a closed-loop control is adopted, the performance indicators (such as bandwidth, timing) and working conditions (such as temperature, voltage) of the GPGPU are monitored in real time, and the voltage and frequency are dynamically adjusted to ensure stability and reliability.

[0134] The chip control circuit and method for adaptive frequency and voltage adjustment provided in the embodiments of the present application can accurately reflect the transmission of the key signals in the chip by simulating the actual critical data path in the chip through the critical path replication sub-module. The daisy chain delay sub-module can apply a configurable delay amount to the output data signal to simulate the timing performance at different time points. The sampling flip-flop module can sample the data signal after delay, and the comparison logic module can generate the timing margin indicator code, so as to monitor the timing state of the chip in real time. In this way, the timing problem of the chip during the working process can be found in time, and adjustment can be made quickly to ensure the stable operation of the chip. According to the generated timing margin indicator code, the working frequency or working voltage of the chip can be adjusted adaptively. When the chip is in a relatively relaxed working condition, that is, the timing margin is large, the working frequency and working voltage of the chip can be appropriately reduced, so as to reduce the power consumption. When the chip needs to run at high performance, the working frequency and voltage can be increased in time to meet the performance demand. This adaptive adjustment method can ensure the performance of the chip while significantly reducing the average power consumption of the chip and improving the energy utilization efficiency.

[0135] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0136] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software products, and the computer software products can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and include a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0137] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip control circuit for adaptive frequency and voltage modulation, characterized in that, include: The timing monitoring module includes a critical path replication submodule and a daisy-chain delay submodule connected together. The critical path replication submodule is used to simulate the actual critical data path in the chip. The daisy-chain delay submodule includes multiple delay units connected in sequence. The daisy-chain delay submodule is used to apply a timing delay to the output data signal. The delay can be configured to simulate the timing performance at different time points. The first trigger has its output connected to the input of the timing monitoring module, and is used to transmit a data signal to the timing monitoring module under the drive of a clock signal. A sampling trigger module, whose input is connected to the output of the timing monitoring module, is used to sample the data signal delayed by the timing monitoring module under the drive of the clock signal to obtain multiple sampled outputs; The comparison logic module has its input terminals connected to the output terminals of the first flip-flop and multiple output terminals of the sampling flip-flop module, respectively, and is used to generate a multi-bit timing margin indicator code based on the comparison result. The timing margin indicator code can characterize the delay state of the timing monitoring module and is used to adaptively adjust the chip's operating frequency or operating voltage. The sampling trigger module includes multiple sampling triggers, and a fixed delay unit is set between the signal input paths of adjacent sampling triggers, so that there is a preset time difference in the time when the data signal arrives at the input terminal of each sampling trigger, so as to perform time-division sampling on the data signal after being delayed by the timing monitoring module. Each bit of the timing margin indicator corresponds to the sampling result at a specific time point, and multiple bits of the indicator are used to describe the changes in the data signal at different delay stages.

2. The adaptive frequency and voltage modulation chip control circuit according to claim 1, characterized in that, The delay unit is an inverter.

3. The adaptive frequency and voltage modulation chip control circuit according to claim 1, characterized in that, The comparison logic module includes multiple XOR units, each XOR unit being used to compare the output data of the first trigger with the output data of a corresponding sampling trigger in the sampling trigger module to generate one bit of the timing margin indicator code.

4. The adaptive frequency and voltage modulation chip control circuit according to claim 3, characterized in that, The fixed delay unit includes a first fixed delay unit and a second fixed delay unit; the input terminal of the first fixed delay unit is connected to the output terminal of the timing monitoring module; the output terminal of the first fixed delay unit is connected to the input terminal of the second fixed delay unit. The plurality of XOR units include a first XOR unit, a second XOR unit, and a third XOR unit; the first XOR unit, the second XOR unit, and the third XOR unit are respectively connected to the output terminal of the first flip-flop; The plurality of sampling triggers include a first sampling trigger, a second sampling trigger, and a third sampling trigger; the first sampling trigger is connected to the output of the timing monitoring module, the clock signal, and the first XOR unit, respectively; the second sampling trigger is connected to the output of the first fixed delay unit, the clock signal, and the second XOR unit, respectively; and the third sampling trigger is connected to the output of the second fixed delay unit, the clock signal, and the third XOR unit, respectively.

5. The adaptive frequency and voltage modulation chip control circuit according to any one of claims 1 to 4, characterized in that, When the timing margin indicator code is 000 or 001, it indicates that the current timing margin is sufficient, and instructs the chip's control module to increase the operating frequency or decrease the operating voltage. When the timing margin indicator code is 011 or 111, it indicates that the current timing margin is in a critical state, and instructs the chip's control module to maintain the current operating frequency and operating voltage.

6. A chip control method for adaptive frequency and voltage modulation, characterized in that, Using the adaptive frequency and voltage modulation chip control circuit as described in any one of claims 1 to 5, the adaptive frequency and voltage modulation chip control method includes: Under the preset operating voltage, gradually adjust the delay of the timing monitoring module; Monitor the timing margin indicator code output by the comparison logic module until the characterization circuit is in a critical operating state; Based on the current circuit's clock cycle and the delay of the timing monitoring module, the maximum operating frequency under the preset operating voltage is determined.

7. The adaptive frequency and voltage modulation chip control method according to claim 6, characterized in that, After determining the maximum operating frequency under the preset operating voltage based on the clock period of the current circuit and the delay of the timing monitoring module, the method further includes: Obtain multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage; Based on the multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage, a frequency-voltage relationship table is generated; the frequency-voltage relationship table is used to adaptively adjust the operating frequency or operating voltage of the chip.

8. The adaptive frequency and voltage modulation chip control method according to claim 7, characterized in that, After generating the frequency-voltage relationship table based on the multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage, the process further includes: In response to a low-power task, initial operating parameters are read from the frequency-voltage table; By combining the timing margin indicator code, the initial operating parameters are down-frequency or down-voltage processed until the timing margin indicator code indicates a critical state, and the target operating parameters of the low-power task are determined to achieve the lowest power consumption.

9. The adaptive frequency and voltage modulation chip control method according to claim 7, characterized in that, After generating the frequency-voltage relationship table based on the multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage, the process further includes: In response to high-power tasks, initial operating parameters are read from the frequency-voltage relationship table; The initial operating parameters are frequency-increased or voltage-increased based on the timing margin indicator code until the timing margin indicator code indicates a critical state, thereby determining the target operating parameters for the high-power task.

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