Multi-protocol configurable interface circuit

Abstract

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a multi-protocol configurable interface circuit. Background Technology

[0002] Traditional chips, if they need to support multiple communication protocols (such as SPI, I2C, etc.), require independent hardware modules for each protocol, leading to a significant increase in the number of chip pins, circuit complexity, and cost. Furthermore, the pin functions of different protocols are fixed, making dynamic reuse impossible and hindering dynamic adaptation to non-standard or future-added protocols. In embedded systems, the MCU needs to communicate with various peripherals to achieve data transmission, control, and interaction. Traditional microcontroller solutions typically use fixed peripheral modules, which are hardware-implemented for specific protocols, consuming significant hardware resources, lacking flexibility, and struggling to adapt to diverse application requirements.

[0003] To address this issue, a multi-protocol interface module on the market uses software configuration to operate shifters, timers, and pins to support various serial communication protocols and waveform generation. However, when dealing with complex protocols and multi-stage states, the software needs to update registers multiple times to simulate the protocol, which is error-prone and reduces transmission efficiency. This multi-protocol interface module includes an input selector, multiple shift registers, and corresponding 32-bit buffers. Its workflow is roughly as follows: First, basic configuration is performed through the shift registers. After configuration, in transmit mode, the timer generates a protocol clock signal based on the configuration information and transmits this signal to the shift registers. The software determines whether a protocol stage change is needed based on the specific protocol requirements. If a protocol change is required, the software reconfigures the registers after the last complete data transmission. The entire process involves using the timer clock to control the data in the buffer to be output through the registers. However, when implementing complex states of complex protocols, the software needs to frequently update the registers, and the 32-bit buffer also frequently consumes CPU resources, resulting in low data transmission efficiency in high-speed scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a multi-protocol configurable interface circuit, which adopts a hardware design that focuses on state machine state transitions and shift registers combined with a cache module to realize clock and data transmission, thereby reducing software intervention and CPU usage, improving overall efficiency, reducing hardware resources, and increasing hardware flexibility.

[0005] This invention provides a multi-protocol configurable interface circuit, comprising:

[0006] The system includes multiple channel modules, multiple counter modules, an input / output module, and a configuration register; each channel module includes a state machine, a shift register, and a buffer module.

[0007] The configuration register obtains configuration information through the system bus, and the configuration information includes: which protocol is selected and the parameters corresponding to the selected protocol;

[0008] The configuration register transmits the configuration information to the channel module, the counter module, and the input / output module. The counter module generates the shift signal required by the shift register within the channel module based on the configuration information. The input / output module selects the corresponding pins and determines the function of each pin based on the configuration information, and connects the corresponding channel to the pin. Each channel module also determines the mode and required state machine state of its respective channel based on the configuration information. Then, based on the mode and state, it controls the internal shift register and buffer module to complete the data transmission of the selected protocol.

[0009] Furthermore, the protocols include any one of the following: SPI, I2C, UART, I2S, and PWM protocols.

[0010] Furthermore, the configuration register provides configuration signals for the channel module, the counter module, and the input / output module. If it acts as a receiver, external signals provide start / stop signals to the state machines within the counter module and the channel module through the input / output module, and the shift register receives and processes the serial signals from the input / output module. If it acts as a transmitter, it provides start / stop signals to the state machine and the counter based on the state of the buffer module, and the shift register converts the parallel data within the buffer module into serial outputs to the input / output module.

[0011] Furthermore, the input processing within the channel module includes: receiving signals through the pins selected by the input / output module, entering the shift register under state control and shift conditions to complete serial-to-parallel conversion, and then storing the data in the buffer module. If the buffer module reaches the threshold for the number of received data, a DMA request is initiated to move the data out of the buffer module, thus completing the data reception.

[0012] Furthermore, the output processing within the channel module includes: if the amount of data in the cache module is less than a threshold, a request is initiated to the DMA. Then, after sufficient data is stored in the cache module, it will enter the shift register under state control and shift conditions to complete the parallel-to-serial conversion, and then output a signal through the pin selected by the input / output module.

[0013] Furthermore, the clocks for various protocols are generated by combining the shift register, clock format signal, and shift condition. The clock format signal controls the polarity of the clock, and the shift condition controls the duty cycle of the clock.

[0014] Furthermore, the state machine includes four operating modes: clock mode: generating clock signals for various protocols; transmit / receive mode: converting serial to parallel data; sequence detection mode: matching protocol frame headers or custom sequences.

[0015] Furthermore, when operating in the clock mode, the configuration register first configures the division factor of the counter module and the clock format and operating mode of the channel module. Then, the counter module generates a shift condition signal based on the division factor and sends it to the shift register in the channel module. The clock format includes four styles: 00, 01, 10, and 11, which respectively represent a clock generated by the shift register with all low levels, a clock with low levels followed by high levels, a clock with high levels followed by low levels, and a clock with all high levels. Therefore, the shift register generates the clock required by the selected protocol by using the shift condition signal and the clock format, in conjunction with the state machine state.

[0016] Furthermore, when operating in the transmission mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module, and determines the required state machine state. The buffer module in the channel module pre-loads the data to be transmitted. Then, the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register retrieves data from the buffer module according to the corresponding state and shift condition to complete the parallel-to-serial conversion and output the data.

[0017] Furthermore, when operating in the receiving mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module, and determines the required state machine state; then the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register converts the serial signal into parallel data according to the corresponding state and shift condition and puts it into the buffer module to complete the data reception.

[0018] Furthermore, when operating in the sequence detection mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module and the data to be detected, and determines the required state machine state; then, the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register converts the serial signal into parallel data according to the corresponding state and shift condition and matches it with the pre-configured data to be detected. If a match is found, a matching signal is generated for subsequent use.

[0019] Furthermore, when the selected protocol is the SPI protocol, the configuration register initializes the operating modes of the four channel modules, namely MOSI transmit, MISO receive, SCK clock, and CS chip select; the state machine switches the data transmission direction from IDLE to ADDR transmit address, and the DATA phase switches the data transmission direction according to the read and write instructions; the shift register generates the SCK clock and transmit / receive data according to the polarity and phase of the SPI protocol based on the shift conditions generated by the counter module.

[0020] Furthermore, the process of completing a read / write operation of the SPI protocol includes: the configuration register obtains configuration data through the system bus, selects the IDLE, ADDR, and DATA states corresponding to the SPI protocol for the state machine, configures the working attributes of the four channel modules and one counter module, and writes the data to be transmitted into the buffer module of the channel module configured in MOSI transmission mode;

[0021] After receiving a start signal, the channel module configured in MOSI transmission mode will first transition from the IDLE state to the ADDR state according to the state machine. The shift register will then complete the address data transmission in the ADDR state based on the shift signal provided by the counter module. After the address data transmission is complete, the state machine will transition from the ADDR state to the DATA state. If it is a read operation, the shift register will not transmit valid data, and the MOSI signal will remain high impedance. If it is a write operation, the shift register will convert the parallel data in the cache module into serial data and send it to the external MOSI bus through the corresponding pin of the input / output module until the cache module is empty.

[0022] Furthermore, the state transitions of the state machines of the four channel modules are consistent. First, they transition from the IDLE state to the ADDR state. In the ADDR state, the shift register in the channel module configured in SCK clock mode will output the clock signal according to the clock format. In the ADDR state, the shift register in the channel module configured in CS chip select mode will output the chip select signal according to the clock format. In the ADDR state, the shift register in the channel module configured in MISO receive mode will not work. After the ADDR state ends, the state machine transitions from the ADDR state to the DATA state.

[0023] In the case of a read operation, the shift register in the channel module configured for MISO receive mode will convert the serial signal on the external MISO into a parallel signal and store it in the buffer module in the channel in the DATA state; in the case of a write operation, the shift register in the channel module configured for MISO receive mode will not operate in the DATA state.

[0024] Furthermore, when the selected protocol is the I2C protocol, the process of completing a write operation of the I2C protocol includes: the configuration register obtains configuration data through the system bus, selects the IDLE, START, ID, ACK, ADDR, DATA and STOP states for the state machine, and configures two channel modules and two counting modules; the two channel modules are the SCL channel module and the SDA channel module; of the two counting modules, one provides shift conditions for the SCL channel and the other provides shift conditions for the SDA channel; then the data to be transmitted is written into the buffer module of the SDA channel module; after the SCL channel module and the SDA channel module receive the start signal, they can transition from the IDLE state according to the state machine.

[0025] Furthermore, completing a read operation of the I2C protocol includes: the configuration register obtains the data to be configured through the system bus, selects the IDLE, START, ID, DUMMY, ACK, ADDR, DATA, and STOP states for the state machine, the DUMMY state is used in conjunction with the START state to complete the RESTART process in the I2C read, and configures the working attributes of 3 channel modules and 2 counting modules. The 3 channel modules are the SCL channel module, the transmit SDA channel module, and the receive SDA channel module; of the 2 counting modules, one provides shift conditions for the SCL channel, and the other provides shift conditions for the transmit SDA channel module and the receive SDA channel module; then the data to be transmitted is written into the buffer module of the transmit SDA channel module.

[0026] Furthermore, when the selected protocol is the UART protocol, the process of completing a write operation of the UART protocol includes: the configuration register obtains the data to be configured through the system bus, selects the IDLE, START, DATA and STOP states for the state machine, configures the working attributes of a TX channel module and a counting module, and writes the data to be transmitted into the buffer module of the TX channel module;

[0027] After the TX channel module receives the start signal, the state machine first transitions from the IDLE state to the START state. In the START state, the shift register directly shifts and outputs a low-level signal. Then, the state machine transitions from the START state to the DATA state. In this state, the shift register serially outputs the parallel data in the buffer module according to the shift condition signal provided by the counter. Then, the state machine transitions from the DATA state to the STOP state. In the STOP state, the shift register directly outputs a high-level signal.

[0028] A data transfer is completed by transitioning between states such as START→DATA→STOP. If a parity bit is required, a DUMMY state can be added for parity checking.

[0029] Furthermore, the process of completing a read operation of the UART protocol includes: the configuration register obtains the data to be configured through the system bus, selects the IDLE, START, DATA, and STOP states for the state machine, and configures the working attributes of an RX channel module and a counting module;

[0030] After the RX channel module receives a start signal, it will first transition from the IDLE state to the START state according to the state machine. The shift register will not perform any processing in the START state. Then, the state machine will transition from the START state to the DATA state. At this time, the shift register will convert the serial data into parallel data and store it in the buffer module according to the shift condition signal provided by the counter. Then, the state machine will transition from the DATA state to the STOP state. The shift register will not perform any processing in the STOP state.

[0031] A data reception is completed by transitioning through states such as START→DATA→STOP. If a parity bit is required, a DUMMY state can be added for parity checking.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] This invention provides a multi-protocol configurable interface circuit, comprising: multiple channel modules, multiple counter modules, an input / output module, and a configuration register; each channel module includes a state machine, a shift register, and a buffer module. The configuration register obtains configuration information via the system bus, including the selected protocol and the corresponding parameters. The configuration register transmits the configuration information to the channel modules, counter modules, and input / output modules; the counter modules generate the shift signals required by the shift registers within the channel modules based on the configuration information; the input / output modules select the corresponding pins and determine the functions of each pin based on the configuration information, and connect the corresponding channels and pins; each channel module also determines its own channel mode and the required state machine state based on the configuration information; then, based on the mode and state, it controls the internal shift registers and buffer modules to complete the data transmission of the selected protocol.

[0034] This invention primarily uses state machine state transitions to implement various protocols. The clock signal is implemented by shifting using a shift register. It is suitable for scenarios requiring a large number of communication protocol interfaces and high flexibility. The hardware design focuses on using state machine state transitions and shift registers in conjunction with a buffer module to implement clock and data transmission, reducing software intervention and CPU usage, improving overall efficiency; it also reduces hardware resources and increases hardware flexibility. Attached Figure Description

[0035] Figure 1a This is a schematic diagram of a multi-protocol configurable interface circuit architecture according to an embodiment of the present invention.

[0036] Figure 1b This is a schematic diagram of a multi-protocol configurable interface circuit framework according to an embodiment of the present invention.

[0037] Figure 2 This is a flowchart illustrating the overall operation of a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0038] Figure 3 This is a flowchart of the input processing within the channel module of the multi-protocol configurable interface circuit in an embodiment of the present invention.

[0039] Figure 4 This is a flowchart illustrating the output processing within the channel module of a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0040] Figure 5 This is a circuit diagram of a shift register generating a protocol clock in a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0041] Figure 6 This is a state machine state transition diagram in a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0042] Figure 7 This is a schematic diagram of the clock mode of the channel module in the multi-protocol configurable interface circuit of this invention.

[0043] Figure 8 This is a schematic diagram of the transmission mode of the channel module in the multi-protocol configurable interface circuit of this invention.

[0044] Figure 9 This is a schematic diagram of the receiving mode of the channel module in the multi-protocol configurable interface circuit of this invention.

[0045] Figure 10 This is a schematic diagram of the sequence detection mode of the channel module in the multi-protocol configurable interface circuit of this invention.

[0046] Figure 11aThis is a timing diagram of the SPI write operation of the multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0047] Figure 11b This is a timing diagram of the SPI read operation of the multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0048] Figure 12a This is a timing diagram of the I2C write operation of the multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0049] Figure 12b This is a timing diagram of the I2C read operation of a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0050] Figure 13 This is a timing diagram of the UART read / write operation of a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0051] Figure 14 This is a schematic diagram comparing the traditional solution with the present invention.

[0052] Figure 15 This is a schematic diagram comparing a multi-protocol interface module on the market with the present invention. Detailed Implementation

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0054] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0055] In this invention, the modules of the controller according to the invention can be implemented using software, hardware, firmware, or a combination thereof. When a module is implemented using software, its function can be implemented through computer program flow. For example, the module can be implemented using code segments (such as code segments in languages ​​like C and C++) stored in a storage device (such as a hard disk, memory, etc.), wherein the corresponding function of the module can be implemented when the code segment is executed by a processor. When a module is implemented using hardware, its function can be implemented by setting a corresponding hardware structure. For example, the module's function can be implemented by hardware programming a programmable device such as a field-programmable gate array (FPGA), or by designing an application-specific integrated circuit (ASIC) including multiple transistors, resistors, capacitors, and other electronic devices. When a module is implemented using firmware, the module's function can be written into a read-only memory such as an EPROM or EEPROM in the form of program code, and the corresponding function of the module can be implemented when the program code is executed by a processor.

[0056] This invention provides a multi-protocol configurable interface circuit, such as... Figure 1a and Figure 1b As shown, it includes: multiple channel modules, multiple counter modules, an input / output module, and a configuration register; the channel modules include a state machine, a shift register, and a buffer module;

[0057] The configuration register obtains configuration information via the system bus. The configuration information includes: which protocol is selected and the parameters corresponding to the selected protocol.

[0058] The configuration register transmits configuration information to the channel module, counter module, and input / output module. The counter module generates the shift signal required by the shift register within the channel module based on the configuration information. The input / output module selects the corresponding pins and determines the function of each pin based on the configuration information, and connects the corresponding channels and pins. Each channel module also determines the mode and required state machine state of its own channel based on the configuration information. Then, based on the mode and state, it controls the internal shift register and buffer module to complete the data transmission of the selected protocol.

[0059] Specifically, the configuration register configures the global parameters of the selected protocol and the switching between different protocol modes. The selected protocol includes any one of the following: SPI, I2C, UART, I2S, and PWM protocols.

[0060] The channel module supports multi-protocol data transmission and reception (such as MOSI / MISO signal processing for SPI). The counter module generates shift condition signals to control clock division or PWM waveform generation (such as UART baud rate generation). The input / output module dynamically maps protocol signal ports, and also provides start / stop signals to the counter module based on the input / output signals of the pins or the status of the buffer module within the channel module.

[0061] Figure 2 This is a flowchart illustrating the overall operation of a multi-protocol configurable interface circuit according to an embodiment of the present invention. Figure 3 This is a flowchart of the input processing within the channel module of the multi-protocol configurable interface circuit in an embodiment of the present invention. Figure 4 This is a flowchart illustrating the output processing within the channel module of a multi-protocol configurable interface circuit according to an embodiment of the present invention. Figure 5 This is a circuit diagram of a shift register generating a protocol clock in a multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0062] like Figure 2 As shown, after power-on or reset, the signals in the configuration register are first set by software and then transmitted to the channel module, counter module, and input / output module. The counter module generates the shift signal required by the shift register in the channel module according to the configured information. The input / output module selects the corresponding pins and determines the function of each pin (such as MOSI, MISO, etc.) according to the configured information, and connects the corresponding channels and pins. It also provides start / stop signals to the counter module according to the input / output signals of the pins or the status of the buffer module in the channel module. Each channel module also determines the mode and required state machine state of its own channel according to the configured information. Then, it controls the internal shift register and buffer module to complete the protocol data transmission according to the mode and state.

[0063] The configuration register provides configuration signals for the channel module, counter module, and input / output module. If it is used as a receiver, external signals provide start / stop signals for the state machines in the counter module and channel module through the input / output module. The shift register receives and processes the serial signals from the input / output module. If it is used as a transmitter, it provides start / stop signals for the state machine and counter through the state of the buffer module. The shift register (shifter) converts the parallel data in the buffer module into serial outputs to the input / output module.

[0064] like Figure 3 As shown, the input processing within the channel module includes: receiving signals through pins selectable by the input / output module, entering the shift register to complete serial-to-parallel conversion under state control and shift conditions, and then storing the data in the buffer module. If the buffer module reaches the threshold for the number of received data, a DMA request is initiated to move the data out of the buffer module, thus completing the data reception.

[0065] like Figure 4 As shown, the output processing within the channel module includes: if the amount of data in the buffer module is less than the threshold, a request is sent to the DMA. After sufficient data is stored in the buffer module, it will enter the shift register under state control and shift conditions to complete the parallel-to-serial conversion. Then, the signal is output through the pin selected by the input / output module.

[0066] like Figure 5 As shown, the present invention generates clocks for various protocols by combining a shift register, a clock format (CF) signal, and a shift condition. The CF signal controls the polarity of the clock, and the shift condition controls the duty cycle of the clock.

[0067] Figure 6 This is a state machine state transition diagram in a multi-protocol configurable interface circuit according to an embodiment of the present invention. For example... Figure 6 As shown, the states of the state machine include IDLE (idle state), START (start state), ID (identifier state), ADDR (address state), ACK (acknowledgment state), DATA (data state), DUMMY (pseudo state), and STOP (stop state). The required states can be determined by configuring registers for different protocols. For example, to implement I2C, all of the above states are needed; to implement UART, only IDLE, START, DATA, and STOP states are required. In other words, the state machine states can be configured in specific combinations to implement a particular protocol, reducing software intervention.

[0068] IDLE (Idle State) is the initial state of the state machine. The bus is idle and no communication activity is taking place. The state machine waits for a "start transmission" trigger signal, typically keeping the bus signals at an idle level. START (Start State) indicates the start of a communication transaction; the master device initiates the start condition. ID (Identifier State) indicates the sending of a specific command or identifier byte. ADDR (Address State) indicates the sending device address. ACK (Acknowledge State): After sending a byte (such as an address byte or data byte), the sender (master or slave device) releases the data line, and the receiver needs to pull the data line low during the next clock pulse as an acknowledgement. DATA (Data State): After a successful address match, the data transmission phase begins. Data can be from master to slave (write operation) or from slave to master (read operation). DUMMY (Pseudo State) is a very useful "trick" state, typically used to switch the direction of data transmission (e.g., switching from a write operation to a read operation); the master device may send a "virtual" clock pulse or read operation, not to obtain real data, but to fulfill the timing requirements of the direction switch. Only then will the device prepare the actual data. STOP indicates the end of a communication transaction.

[0069] Figure 7 This is a schematic diagram of the clock mode of the channel module in the multi-protocol configurable interface circuit of this invention. Figure 8 This is a schematic diagram of the transmission mode of the channel module in the multi-protocol configurable interface circuit of this invention. Figure 9 This is a schematic diagram of the receiving mode of the channel module in the multi-protocol configurable interface circuit of this invention. Figure 10 This is a schematic diagram of the sequence detection mode of the channel module in the multi-protocol configurable interface circuit of this invention.

[0070] The state machine's state transition diagram adapts to different protocol timings (such as I2C address transmission and ACK confirmation) through state transitions. The state machine has four main operating modes: Clock mode: generates clock signals such as SCK for SPI and BCK for I2S; Transmit / Receive mode: converts serial to parallel data (such as UART TX / RX signal processing); Sequence detection mode: matches the SENT protocol frame header or a custom sequence.

[0071] like Figure 7As shown, when operating in clock mode, the configuration register first configures the division factor of the counter module and the clock format and operating mode of the channel module. Then, the counter module generates a shift condition signal based on the division factor and sends it to the shift register in the channel module. The clock format includes several styles: 00, 01, 10, and 11, which respectively represent a clock with all low levels, a clock with low levels followed by high levels, a clock with high levels followed by low levels, and a clock with all high levels generated by the shift register. Therefore, the shift register can generate the clock required by the protocol by using the above shift conditions and clock format, in conjunction with the state machine state.

[0072] like Figure 8 As shown, when operating in transmit mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module, and determines the required state machine state. The buffer module in the channel module puts the data to be transmitted in advance. Then, the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register then retrieves data from the buffer module according to the corresponding state and shift condition to complete the parallel-to-serial conversion and output the data.

[0073] like Figure 9 As shown, when operating in receive mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module, and determines the required state machine state; then the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register then converts the serial signal into parallel data and puts it into the buffer module to complete the data reception according to the corresponding state and shift condition.

[0074] like Figure 10 As shown, when working in sequence detection mode, the configuration register first configures the frequency division coefficient of the counter module and the working mode of the channel module and the data to be detected, and determines the required state machine state; then the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register will convert the serial signal into parallel data according to the corresponding state and shift condition and match it with the pre-configured data to be detected. If they match, a matching signal is generated for subsequent use.

[0075] The state machine of this invention is a programmable state machine. A programmable state machine provides a general hardware framework that can be implemented to achieve different state machine functions through "programming" or "configuration" without redesigning the circuit. A programmable state machine is a hardware state machine engine whose states, transitions, and actions can be defined by software (usually configuration files or microcode).

[0076] This invention utilizes a programmable hardware architecture combining a programmable state machine and shift registers to simulate multiple protocols with a single circuit, reducing hardware resource redundancy, chip area, and power consumption. It supports user-defined protocol timing, pin reuse, and improved pin utilization. By dynamically defining protocol timing (such as clock edges and start bits) and data processing logic through the state machine, it can be configured to detect specific sequences (such as SENT protocol frames) or generate custom waveforms, supporting new or non-standard protocols without hardware modifications. By updating the multiplexing register, physical pins are dynamically mapped to different protocol signals (e.g., SPI's SCK and UART's TX share the same pin), maximizing pin utilization. The clock generation unit supports configurable frequency division and duty cycle adjustment, and the state machine directly controls signal transitions, providing precise timing for the protocol and reducing latency and jitter.

[0077] In the past, the shift register in a multi-protocol interface module on the market could only store 32 bits of data, and would request DMA (Direct Memory Access) whenever it was empty or full. However, the cache module used in this invention can be FIFO (First In First Out) or SRAM, whose capacity is much larger than the 32-bit cache corresponding to the shift register. Combined with DMA, it can effectively reduce the intervention of the CPU and effectively improve the data transmission efficiency in high-speed scenarios.

[0078] This invention incorporates a state machine to support multiple protocols. When implementing a specific protocol, it can be achieved by setting the configuration register once via software after the system is powered on or reset. For some complex protocols with multiple phases, such as the DATA and ACK phases of I2C, if a multi-protocol interface module on the market is used, frequent software intervention is required to update the configuration register. However, with this invention, once the configuration is set up at the beginning, no software intervention is required afterward. The entire process is achieved by the pre-defined state in the hardware, resulting in higher data transmission efficiency.

[0079] Figure 11a This is a timing diagram of the SPI write operation of the multi-protocol configurable interface circuit according to an embodiment of the present invention. Figure 11b This is a timing diagram of the SPI read operation of the multi-protocol configurable interface circuit according to an embodiment of the present invention.

[0080] SPI is a high-speed, full-duplex, synchronous serial communication bus widely used to connect microcontrollers to peripherals such as sensors, memory, SD cards, and displays. SPI typically requires 4 wires or 4 channels: MOSI: Master Data Output, Slave Data Input; MISO: Master Data Input, Slave Data Output; SCK: Serial Clock, generated and controlled by the master device; CS: Chip Select, controlled by the master device.

[0081] like Figure 11a and Figure 11bAs shown, the multi-protocol configurable interface circuit of this embodiment is configured with the SPI protocol. The configuration register initializes the channels (MOSI transmit, MISO receive, SCK clock, chip select signal CS). The state machine transitions from IDLE to ADDR to send the address; during the DATA phase, the data transmission direction is switched according to read / write instructions. The shift register, through the shift conditions generated by the counter module, generates the SCK clock and transmit / receive data according to the SPI protocol polarity and phase (CPOL / CPHA).

[0082] By configuring the operating modes of different channel modules, the process of completing a read / write operation of the SPI protocol includes: the configuration register obtains configuration data (configuration information) through the system bus, selects the IDLE, ADDR, and DATA states corresponding to the SPI protocol for the state machine, configures the operating attributes of the four channel modules and one counting module, and writes the data to be transmitted into the buffer module of the channel module configured in transmit mode (MOSI). The state machine in the transmit mode (MOSI) channel module checks whether the state of the buffer module in that module is empty. If it is empty, it continues to wait for the arrival of data in the buffer module; otherwise, it generates a start signal for the other three channel modules and the counting module.

[0083] When a channel module configured in transmit mode (MOSI) receives a start signal, it will first transition from the IDLE state to the ADDR state according to the state machine. In the ADDR state, the shift register will complete the transmission of address data according to the shift signal provided by the counter module. After the address data transmission is completed, the state machine will transition from the ADDR state to the DATA state. If it is a read operation, the shift register will not transmit valid data, and the MOSI signal will remain high impedance. If it is a write operation, the shift register will convert the parallel data in the buffer module into serial data and send it to the external MOSI bus through the corresponding pins of the input / output module until the buffer module is empty.

[0084] After the other three channel modules receive the start signal, their state machine transitions will be consistent with those of the channel module configured for transmit mode (MOSI). First, they transition from the IDLE state to the ADDR state. In the ADDR state, the shift registers in the channel module configured for clock mode (SCK) will output the clock signal according to CF. In the ADDR state, the shift registers in the channel module configured for chip select mode (CS) will output the chip select signal according to CF. The shift registers in the channel module configured for receive mode (MISO) will not operate in the ADDR state. After the ADDR state ends, the state machine transitions from the ADDR state to the DATA state. The shift registers in the channel module configured for clock mode (SCK) will continue to output the clock signal according to CF in the DATA state, and the shift registers in the channel module configured for chip select mode (CS) will continue to output the chip select signal according to CF in the DATA state. For read operations, the shift register in the channel module configured in receive mode (MISO) will convert the serial signal on the external MISO into a parallel signal and store it in the buffer module in the channel in the DATA state; for write operations, the shift register in the channel module configured in receive mode (MISO) will not operate in the DATA state.

[0085] When the amount of data in the buffer module of a channel module configured for transmit mode (MOSI) decreases to a given threshold, the channel raises the DMA request signal, and the system bus adds data to the buffer module until it is refilled or the given threshold is reached, at which point the DMA request signal is lowered. Similarly, when the amount of data in the buffer module of a channel module configured for receive mode (MISO) increases to a given upper limit threshold, the channel raises the DMA request signal, and the system bus removes data from the buffer module until the data in the buffer module is emptied or the amount of data decreases to a given threshold, at which point the DMA request signal is lowered.

[0086] If all data in the buffer module of a channel module configured in transmit mode (MOSI) has been transmitted and no data has been replenished to the buffer module within a set time, then a complete write transfer is considered complete, and the channel module will generate an end signal to the other three channel modules and the counter module. If the counter module detects the end signal of the external protocol bus, then a complete read transfer is considered complete, and the counter module will generate an end signal to the other channel modules. After all channel modules receive the end signal, the state machine will jump to the IDLE or STOP state, and the shift register will complete the corresponding output in the corresponding state.

[0087] Figure 12a This is a timing diagram of the I2C write operation of the multi-protocol configurable interface circuit according to an embodiment of the present invention. Figure 12bThis is a timing diagram of the I2C read operation of a multi-protocol configurable interface circuit according to an embodiment of the present invention. I2C is a very popular synchronous, serial, half-duplex communication bus, known for its simple hardware connection (requiring only two wires). I2C has only two bidirectional signal lines: SDA: serial data line, used for data transmission; SCL: serial clock line, generated by the master device, used for data synchronization.

[0088] like Figure 12a As shown, by configuring the operating modes of different channel modules, the write operation process of an I2C protocol includes: the configuration register obtains configuration data through the system bus, selects the corresponding I2C protocol states IDLE, START, ID, ACK, ADDR, DATA, and STOP for the state machine, and configures the operating attributes of two channel modules (one SCL channel and one transmit SDA channel) and two counting modules (one providing shift conditions for the SCL channel and one providing shift conditions for the SDA channel). Then, the data to be transmitted is written into the buffer module of the channel module configured in transmit mode (SDA). The state machine in the channel module configured in transmit mode (SDA) checks whether the state of the buffer module in this module is empty. If it is empty, it continues to wait for the arrival of data in the buffer module; otherwise, it generates a start signal to the other channel module configured in clock mode (SCL) and the two counting modules.

[0089] When the two counter modules receive the start signal, they will perform periodic counting according to the configured frequency division coefficient and generate shift condition signals for the corresponding channel modules. The channel modules configured for transmit mode (SDA) and clock mode (SCL) can transition from the IDLE state according to the state machine after receiving the start signal. The shift register of the SCL channel will generate the clock signal according to the shift signal and clock format (CF) provided by the counter module in different states (CF is 01 in the example, that is, the clock format is low first and then high, and the duty cycle is controlled by the corresponding counter module). The shift register of the SDA channel will also serially output the parallel data in the buffer module according to the shift signal provided by the counter module in different states (as shown in the example, the shift conditions of the SCL and SDA channels are different and can be freely and flexibly configured to meet timing requirements). In the ACK state of the SDA channel, the SDA bus status will be detected and the detection signal will be synchronized to other channels and counter modules. Then, each module will perform corresponding logic processing according to the detection signal.

[0090] like Figure 12bAs shown, the process of completing an I2C read operation includes: the configuration register obtains the data to be configured through the system bus, selects the corresponding I2C protocol states IDLE, START, ID, DUMMY, ACK, ADDR, DATA, and STOP for the state machine (compared to the write operation, there is an additional DUMMY state to work with the START state to complete the RESTART process in I2C read), and configures the working attributes of three channel modules (one SCL channel, one transmit SDA channel, and one receive SDA channel) and two counting modules (one provides shift conditions for the SCL channel, and one provides shift conditions for the two SDA channels). Then, the data to be transmitted is written into the buffer module of the channel module configured for transmit mode (SDA). The state machine in the channel module configured for transmit mode (SDA) checks whether the buffer module in this module is empty. If it is empty, it continues to wait for the arrival of data in the buffer module; otherwise, it generates a start signal for the other two channel modules (SCL channel and receive mode SDA channel) and the two counting modules.

[0091] Similarly, when the two counter modules receive the start signal, they will perform periodic counting according to the configured frequency division coefficient and generate shift condition signals to the corresponding channel modules (except that one of them will simultaneously transmit the shift condition to both channels of SDA). The channel modules configured for transmit mode (SDA), receive mode (SDA), and clock mode (SCL) can transition from the IDLE state according to the state machine after receiving the start signal. The shift register of the SCL channel will generate the clock signal in different states based on the shift signal and clock format (CF) provided by the counter module (in the example, CF is 01, meaning the clock format is low-to-high, and the duty cycle is determined by the corresponding counter). (Module control); In transmit mode, the shift register of the SDA channel will serially output the parallel data in the buffer module according to the shift signal provided by the counter module in the ID and ADDR states. In receive mode, the shift register of the SDA channel will convert the serial data into parallel data and store it in the buffer module according to the shift signal provided by the counter module in the DATA state. In transmit mode, the ACK state after the ID and ADDR states of the SDA channel will detect the SDA bus status and synchronize the detection signal to other channels and the counter module. Then, each module will perform corresponding logic processing according to the detection signal. However, in the ACK state after the DATA state, ACK / NAC will be sent as needed.

[0092] When the amount of data in the buffer module of a channel module configured for transmit mode (SDA) decreases to a given threshold, the channel raises the DMA request signal, and the system bus adds data to the buffer module until it is refilled or the given threshold is reached, at which point the DMA request signal is lowered. Similarly, when the amount of data in the buffer module of a channel module configured for receive mode (SDA) increases to a given upper limit threshold, the channel raises the DMA request signal, and the system bus removes data from the buffer module until it is emptied or the amount of data decreases to a given threshold, at which point the DMA request signal is lowered.

[0093] Figure 13 This is a timing diagram of the read / write operation of the UART (Multi-Protocol Configurable Interface) circuit, an embodiment of the present invention. UART is a common asynchronous serial communication protocol. UART communication is simple, with only two data lines: TX (transmit data line) and RX (receive data line).

[0094] like Figure 13 As shown, by configuring the operating modes of different channel modules, the write operation process of a UART protocol includes: the configuration register obtains the data to be configured through the system bus, selects the corresponding UART protocol states IDLE, START, DATA, and STOP for the state machine, configures the operating attributes of a channel module (TX channel) and a counting module (providing baud rate), and writes the data to be transmitted into the buffer module of the channel module configured in transmit mode (TX). The state machine in the channel module configured in transmit mode (TX) checks whether the buffer module in this module is empty. If it is empty, it continues to wait for the arrival of data in the buffer module; otherwise, it generates a start signal for the counting module.

[0095] Once the channel module configured for transmit (TX) receives a start signal, its state machine first transitions from the IDLE state to the START state. During the START state, the shift register directly shifts and outputs a low-level signal. Then, the state machine transitions from the START state to the DATA state, where the shift register serially outputs the parallel data from the buffer module based on the shift condition signal provided by the counter. Next, the state machine transitions from the DATA state to the STOP state, where the shift register directly outputs a high-level signal. This state transition from START to DATA to STOP completes one data transmission cycle. If a parity bit is required, a DUMMY state can be added for parity checking. The entire transmission cycle ends when no new data is added to the buffer module and all data in the buffer module has been transmitted.

[0096] The process of completing a UART protocol read operation includes: the configuration register obtains the data to be configured through the system bus, selects the corresponding UART protocol states (IDLE, START, DATA, STOP) for the state machine, and configures the operating attributes of a channel module (RX channel) and a counter module (providing baud rate). At this time, the start signal is generated by the first falling edge of the signal in the channel module configured as receive mode (RX) and sent to the counter module.

[0097] When a channel module configured for receive mode (RX) receives a start signal, its state machine first transitions from the IDLE state to the START state. The shift register does not perform any processing in the START state. Then, the state machine transitions from the START state to the DATA state. In this state, the shift register converts serial data into parallel data based on the shift condition signal provided by the counter and stores it in the buffer module. Next, the state machine transitions from the DATA state to the STOP state, and the shift register does not perform any processing in the STOP state. This process of START→DATA→STOP completes one data reception cycle. If a parity bit is required, a DUMMY state can be added for parity checking. The entire data reception cycle ends when the channel module in receive mode (RX) does not detect a falling edge at the end of the STOP state.

[0098] When the amount of data in the buffer module of a channel module configured for transmit (TX) drops to a given threshold, the channel raises the DMA request signal, and the system bus adds data to the buffer module until it is refilled or the given threshold is reached, at which point the DMA request signal is lowered. Similarly, when the amount of data in the buffer module of a channel module configured for receive (RX) grows to a given upper limit threshold, the channel raises the DMA request signal, and the system bus removes data from the buffer module until it is emptied or the amount of data drops to a given threshold, at which point the DMA request signal is lowered.

[0099] Figure 14 This is a schematic diagram comparing the traditional solution with the present invention. Figure 14 As shown, traditional microcontroller solutions typically employ fixed peripheral modules (such as independent SPI / UART controllers). These peripheral modules are hardware-implemented for specific protocols, consuming significant hardware resources, lacking flexibility, and struggling to adapt to diverse application requirements. Fixed peripheral modules lead to wasted chip area and an inability to dynamically support new protocols. Software simulation consumes CPU resources and suffers from poor real-time performance. This invention features innovative hardware abstraction, abstracting protocol timing into state machine transition logic and achieving "one set of hardware for multiple protocols" through the configuration of shift registers. Resource-optimized design: reduces the number of fixed protocol modules, lowering chip cost and area. Strong adaptability: supports scenarios using standard or custom protocols.

[0100] Figure 15 This diagram illustrates a comparison between a commercially available multi-protocol interface module and the present invention. The present invention features innovative hardware abstraction, abstracting protocols as state machine transition logic and achieving "one set of hardware for multiple protocols" through the configuration of shift registers. It boasts optimized resource design, reducing the number of fixed protocol modules, lowering chip cost and area; minimal software and CPU intervention, thus improving the corresponding protocol interface speed. It is highly adaptable, supporting non-standard or custom protocol scenarios.

[0101] This invention primarily uses state machine state transitions to implement various protocols. The clock signal is implemented by shifting using a shift register. It is suitable for scenarios requiring a large number of communication protocol interfaces and high flexibility. The hardware design focuses on using state machine state transitions and shift registers in conjunction with a buffer module to implement clock and data transmission, reducing software intervention and CPU usage, improving overall efficiency; it also reduces hardware resources and increases hardware flexibility.

[0102] In summary, this invention provides a multi-protocol configurable interface circuit, comprising: multiple channel modules, multiple counter modules, an input / output module, and a configuration register; each channel module includes a state machine, a shift register, and a buffer module. The configuration register obtains configuration information via the system bus, including the selected protocol and its corresponding parameters. The configuration register transmits the configuration information to the channel modules, counter modules, and input / output modules; the counter modules generate the shift signals required by the shift registers within the channel modules based on the configuration information; the input / output modules select the corresponding pins and determine their functions based on the configuration information, connecting the corresponding channels and pins; each channel module determines its own channel mode and required state machine state based on the configuration information; and then controls the internal shift registers and buffer modules to complete the data transmission of the selected protocol based on the mode and state. This invention primarily uses state machine state transitions to implement various protocols. The clock signal is implemented by shifting the shift register. It is suitable for scenarios requiring a large number of communication protocol interfaces and high flexibility. The hardware design focuses on state machine state transitions and shift registers combined with a cache module to realize clock and data transmission, which reduces software intervention and CPU usage, improves overall efficiency, reduces hardware resources, and improves hardware flexibility.

[0103] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0104] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A multi-protocol configurable interface circuit, characterized in that, include: Multiple channel modules, multiple counter modules, one input / output module, and one configuration register; The channel module includes a state machine, a shift register, and a buffer module; The configuration register obtains configuration information through the system bus, and the configuration information includes: which protocol is selected and the parameters corresponding to the selected protocol; The configuration register transmits the configuration information to the channel module, the counter module, and the input / output module. The counter module generates the shift signal required by the shift register within the channel module based on the configuration information. The input / output module selects the corresponding pins and determines the function of each pin based on the configuration information, and connects the corresponding channel to the pin. Each channel module also determines the mode and required state machine state of its respective channel based on the configuration information. Then, based on the mode and state, it controls the internal shift register and buffer module to complete the data transmission of the selected protocol.

2. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, The selected protocol includes any one of the following: SPI, I2C, UART, I2S, and PWM protocol.

3. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, The configuration register provides configuration signals for the channel module, the counter module, and the input / output module. If it is used as a receiver, external signals provide start / stop signals to the state machines in the counter module and the channel module through the input / output module. The shift register receives and processes the serial signals from the input / output module. If it is used as a transmitter, the state of the buffer module provides start / stop signals to the state machine and the counter, and the shift register converts the parallel data in the buffer module into serial outputs to the input / output module.

4. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, The input processing within the channel module includes: receiving signals through the pins selected by the input / output module, entering the shift register under state control and shift conditions to complete serial-to-parallel conversion, and then storing the data in the buffer module. If the buffer module reaches the threshold for the number of received data, a DMA request is initiated to move the data out of the buffer module, thus completing the data reception.

5. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, The output processing within the channel module includes: if the amount of data in the cache module is less than a threshold, a request is initiated to the DMA. Then, after sufficient data is stored in the cache module, it will enter the shift register under state control and shift conditions to complete the parallel-to-serial conversion, and then output a signal through the pin selected by the input / output module.

6. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, The clocks for various protocols are generated by combining the shift register, clock format signal, and shift condition. The clock format signal controls the polarity of the clock, and the shift condition controls the duty cycle of the clock.

7. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, The state machine includes four operating modes: clock mode: generating clock signals for various protocols; transmit / receive mode: converting serial to parallel data; and sequence detection mode: matching protocol frame headers or custom sequences.

8. The multi-protocol configurable interface circuit as described in claim 7, characterized in that, When operating in the clock mode, the configuration register first configures the division factor of the counter module and the clock format and operating mode of the channel module. Then, the counter module generates a shift condition signal based on the division factor and sends it to the shift register in the channel module. The clock format includes four styles: 00, 01, 10, and 11, which respectively represent a clock generated by the shift register with all low levels, a clock with low levels followed by high levels, a clock with high levels followed by low levels, and a clock with all high levels. Therefore, the shift register generates the clock required by the selected protocol by using the shift condition signal and the clock format, in conjunction with the state machine state.

9. The multi-protocol configurable interface circuit as described in claim 7, characterized in that, When operating in the transmission mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module, and determines the required state machine state. The buffer module in the channel module pre-loads the data to be transmitted. Then, the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register retrieves data from the buffer module according to the corresponding state and shift condition to complete the parallel-to-serial conversion and output the data.

10. The multi-protocol configurable interface circuit as described in claim 7, characterized in that, When operating in the receiving mode, the configuration register first configures the frequency division coefficient of the counter module and the operating mode of the channel module, and determines the required state machine state; then the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register converts the serial signal into parallel data according to the corresponding state and shift condition and puts it into the buffer module to complete the data reception.

11. The multi-protocol configurable interface circuit as described in claim 7, characterized in that, When operating in the sequence detection mode, the configuration register first configures the frequency division coefficient of the counter module, the operating mode of the channel module, and the data to be detected, and determines the required state machine state. Then, the counter module generates a shift condition signal according to the frequency division coefficient and sends it to the shift register in the channel module. The shift register converts the serial signal into parallel data according to the corresponding state and shift condition and matches it with the pre-configured data to be detected. If a match is found, a matching signal is generated for subsequent use.

12. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, When the selected protocol is SPI, the configuration register initializes the operating modes of the four channel modules, namely MOSI transmit, MISO receive, SCK clock, and CS chip select; the state machine switches the data transmission direction from IDLE to ADDR transmit address, and the DATA phase switches the data transmission direction according to the read and write instructions; the shift register generates the SCK clock and transmit / receive data according to the polarity and phase of the SPI protocol based on the shift conditions generated by the counter module.

13. The multi-protocol configurable interface circuit as described in claim 12, characterized in that, The process of completing a read / write operation of the SPI protocol includes: the configuration register obtains configuration data through the system bus, selects the IDLE, ADDR and DATA states corresponding to the SPI protocol for the state machine, configures the working attributes of the four channel modules and one counter module, and writes the data to be transmitted into the buffer module of the channel module configured in MOSI transmission mode; After receiving a start signal, the channel module configured in MOSI transmission mode will first transition from the IDLE state to the ADDR state according to the state machine. The shift register will then complete the address data transmission in the ADDR state based on the shift signal provided by the counter module. After the address data transmission is complete, the state machine will transition from the ADDR state to the DATA state. If it is a read operation, the shift register will not transmit valid data, and the MOSI signal will remain high impedance. If it is a write operation, the shift register will convert the parallel data in the cache module into serial data and send it to the external MOSI bus through the corresponding pin of the input / output module until the cache module is empty.

14. The multi-protocol configurable interface circuit as described in claim 13, characterized in that, The state machines of the four channel modules have consistent state transitions. First, they transition from the IDLE state to the ADDR state. In the ADDR state, the shift register in the channel module configured with SCK clock mode will output the clock signal according to the clock format. In the ADDR state, the shift register in the channel module configured with CS chip select mode will output the chip select signal according to the clock format. In the ADDR state, the shift register in the channel module configured with MISO receive mode will not operate in the ADDR state. After the ADDR state ends, the state machine transitions from the ADDR state to the DATA state. In the case of a read operation, the shift register in the channel module configured for MISO receive mode will convert the serial signal on the external MISO into a parallel signal and store it in the buffer module in the channel in the DATA state; in the case of a write operation, the shift register in the channel module configured for MISO receive mode will not operate in the DATA state.

15. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, When the selected protocol is I2C, the process of completing a write operation of the I2C protocol includes: the configuration register obtains configuration data through the system bus, selects the IDLE, START, ID, ACK, ADDR, DATA and STOP states for the state machine, and configures two channel modules and two counting modules; the two channel modules are the SCL channel module and the SDA channel module; one of the two counting modules provides shift conditions for the SCL channel and the other provides shift conditions for the SDA channel; then the data to be transmitted is written into the buffer module of the SDA channel module; after the SCL channel module and the SDA channel module receive the start signal, they can transition from the IDLE state according to the state machine.

16. The multi-protocol configurable interface circuit as described in claim 15, characterized in that, The process of completing a read operation of the I2C protocol includes: the configuration register obtains the data to be configured through the system bus, selects the IDLE, START, ID, DUMMY, ACK, ADDR, DATA and STOP states for the state machine, the DUMMY state is used in conjunction with the START state to complete the RESTART process in the I2C read, and configures the working attributes of 3 channel modules and 2 counting modules. The 3 channel modules are the SCL channel module, the transmit SDA channel module and the receive SDA channel module; of the 2 counting modules, one provides shift conditions for the SCL channel, and the other provides shift conditions for the transmit SDA channel module and the receive SDA channel module; then the data to be transmitted is written into the buffer module of the transmit SDA channel module.

17. The multi-protocol configurable interface circuit as described in claim 1, characterized in that, When the selected protocol is the UART protocol, the process of completing a write operation of the UART protocol includes: the configuration register obtains the data to be configured through the system bus, selects the IDLE, START, DATA and STOP states for the state machine, configures the working attributes of a TX channel module and a counting module, and writes the data to be transmitted into the buffer module of the TX channel module; After the TX channel module receives the start signal, the state machine first transitions from the IDLE state to the START state. In the START state, the shift register directly shifts and outputs a low-level signal. Then, the state machine transitions from the START state to the DATA state. In this state, the shift register serially outputs the parallel data in the buffer module according to the shift condition signal provided by the counter. Then, the state machine transitions from the DATA state to the STOP state. In the STOP state, the shift register directly outputs a high-level signal. A data transfer is completed by transitioning between states such as START→DATA→STOP. If a parity bit is required, a DUMMY state can be added for parity checking.

18. The multi-protocol configurable interface circuit as described in claim 17, characterized in that, The process of completing a read operation of the UART protocol includes: the configuration register obtains the data to be configured through the system bus, selects the IDLE, START, DATA, and STOP states for the state machine, and configures the working attributes of an RX channel module and a counting module; After the RX channel module receives a start signal, it will first transition from the IDLE state to the START state according to the state machine. The shift register will not perform any processing in the START state. Then, the state machine will transition from the START state to the DATA state. At this time, the shift register will convert the serial data into parallel data and store it in the buffer module according to the shift condition signal provided by the counter. Then, the state machine will transition from the DATA state to the STOP state. The shift register will not perform any processing in the STOP state. A data reception is completed by transitioning through states such as START→DATA→STOP. If a parity bit is required, a DUMMY state can be added for parity checking.

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