Semiconductor structure, preparation method thereof and high-voltage MOS (Metal Oxide Semiconductor) device

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and a high-voltage MOS device. The semiconductor structure comprises a substrate; a source region, a drain region and a channel active region between the source region and the drain region are formed in the substrate; the field oxide layer is located between the channel active region and the source-drain region and defines the boundary of the channel active region; the gate oxide layer covers the channel active region and the field oxide layer; wherein the surface of the gate oxide layer is provided with a recess at a position corresponding to the junction of the adjacent boundaries of the channel active region; the thickness of the gate oxide layer at the sunken position is smaller than that of the gate oxide layer at other positions; the gate layer is located on the surface of the gate oxide layer; wherein a through hole is formed in a position, corresponding to the recess, of the gate layer. In this way, electric leakage and breakdown caused by the fact that the gate oxide layer at the sunken position is thin can be reduced to a certain extent, and reliability is improved.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor device technology, and in particular to a semiconductor structure and its fabrication method, and a high-voltage MOS device. Background Technology

[0002] Currently, in high-voltage MOS devices, when the operating voltage is high, such as when the drain voltage exceeds 20V, a field oxide layer is usually introduced between the gate and the drain to disperse the surface electric field of the depletion region of the drain PN junction, thereby increasing the width of the depletion region and thus improving the breakdown voltage performance of the MOS device.

[0003] However, through testing, technicians discovered that high-voltage MOS devices in existing technologies are prone to leakage current and even gate breakdown, resulting in poor reliability. Summary of the Invention

[0004] In view of this, several embodiments of this application aim to provide a semiconductor structure and its fabrication method, as well as a high-voltage MOS device, which can reduce leakage current and gate breakdown, and improve reliability.

[0005] One embodiment of this application provides a semiconductor structure, including: a substrate; an active drain region and a channel active region located between the source and drain regions formed in the substrate; a field oxide layer located between the channel active region and the source and drain regions, defining the boundary of the channel active region; a gate oxide layer covering the channel active region and the field oxide layer; wherein, a recess is formed on the surface of the gate oxide layer at a position corresponding to the intersection of adjacent boundaries of the channel active region; the thickness of the gate oxide layer at the recess position is less than the thickness of the gate oxide layer at other positions; a gate layer located on the surface of the gate oxide layer; wherein, a through-hole is formed in the gate layer at a position corresponding to the recess.

[0006] Optionally, the gate layer defines an uncovered area on the surface of the gate oxide layer through the opening; the recess is located within the uncovered area.

[0007] Optionally, adjacent boundaries of the active region of the channel intersect to form a boundary point; the aperture has a central axis perpendicular to the substrate surface, and the central axis passes through the boundary point.

[0008] Optionally, the semiconductor structure corresponds to a target design file that conforms to manufacturing process rules after Boolean operation; wherein, the shape and size of the opening in the target design file can be adjusted together through the Boolean operation.

[0009] Optionally, the ratio of the area occupied by the opening on the surface of the gate layer to the total area of ​​the gate layer surface falls within the range of 1% to 5%.

[0010] Optionally, the outline shape of the opening formed on the surface of the gate layer is circular or hexagonal.

[0011] Optionally, the outline shape of the opening formed on the surface of the gate layer is rectangular, and the ratio of the length to the width of the rectangle falls within the range of 2.5 to 3.5.

[0012] Another embodiment of this application provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; the substrate comprising a substrate and a field oxide layer; wherein a channel active region defined by the field oxide layer is formed in the substrate; forming a gate oxide layer on the surface of the substrate; wherein a recess is formed on the surface of the gate oxide layer at a position corresponding to the intersection of an adjacent boundary of the channel active region; the thickness of the gate oxide layer at the recess position is less than the thickness of the gate oxide layer at other positions; depositing a gate material on the surface of the gate oxide layer, and forming an opening through the gate material at a position corresponding to the recess by photolithography and etching processes to obtain a gate layer.

[0013] Optionally, the fabrication method further includes: forming a contact etch stop layer, an interlayer dielectric layer, and a contact structure penetrating the contact etch stop layer and the interlayer dielectric layer on the gate layer; wherein the contact etch stop layer seals the opening between the interlayer dielectric layer and the gate layer.

[0014] Another embodiment of this application provides a high-voltage MOS device, comprising the semiconductor structure as described in any of the foregoing embodiments or fabricated using the method for fabricating the semiconductor structure as described in any of the foregoing embodiments.

[0015] The various embodiments provided in this application have an unexpected effect: by forming source / drain regions and a channel active region between the source / drain regions on the substrate, and introducing a field oxide layer between the channel active region and the source / drain regions to define the boundary of the channel active region, a recess is formed on the surface of the gate oxide layer covering the channel active region and the field oxide layer at the position corresponding to the intersection of the adjacent boundary of the channel active region. Then, by forming through-holes in the gate layer formed on the surface of the gate oxide layer at the position corresponding to the recess on the surface of the gate oxide layer, the electric field intensity distribution at the intersection of the adjacent boundary of the channel active region can be reduced, and electric field concentration can be avoided. This reduces leakage and breakdown caused by the thin gate oxide layer at the recess position to a certain extent, thereby improving reliability. Attached Figure Description

[0016] Figure 1a This is a schematic diagram of the planar structure of a symmetrical high-voltage MOSFET in related technologies.

[0017] Figure 1bThis is a schematic diagram of the planar structure of an asymmetric high-voltage MOSFET in related technologies.

[0018] Figure 2 for Figure 1b A cross-sectional schematic diagram of an asymmetric high-voltage MOSFET.

[0019] Figure 3 and Figure 4 This is a schematic diagram of the etching process used to form trenches in the semiconductor structure fabrication method provided in this application embodiment.

[0020] Figure 5 and Figure 6 This is a schematic diagram of oxide layer growth and oxide filling in the semiconductor structure fabrication method provided in the embodiments of this application.

[0021] Figure 7 and Figure 8 This is a schematic diagram of the formation of a field oxide layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0022] Figure 9 and Figure 10 This is a schematic diagram of the substrate formation process in the method for fabricating the semiconductor structure provided in this application embodiment.

[0023] Figure 11 This is a schematic diagram of the formation of a gate oxide layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0024] Figure 12 This is a schematic diagram of the deposition of gate material in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0025] Figure 13 and Figure 14 This is a schematic diagram of the formation of a gate layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0026] Figure 15 This is a schematic diagram illustrating the formation of a contact etch stop layer, an interlayer dielectric layer, and a contact structure in the semiconductor structure fabrication method provided in this application embodiment.

[0027] Figure 16a This is a schematic diagram of the planar structure of a symmetrical high-voltage MOSFET provided in an embodiment of this application.

[0028] Figure 16b This is a schematic diagram of the planar structure of an asymmetric high-voltage MOSFET provided in an embodiment of this application.

[0029] Figure 17 and Figure 18 The figures show the test results of gate current and gate voltage for high-voltage NMOS and high-voltage PMOS using the semiconductor structures provided in the embodiments of this application.

[0030] Explanation of reference numerals in the attached figures: 101. Trench; 102. Substrate oxide layer; 103. Pad oxide layer; 104. Silicon nitride mask; 105. Oxide; 106. Field oxide layer; 107. Masking layer; 110. Substrate; 111. Substrate; 112. Channel active region; 113. Source / drain region; 120. Gate oxide layer; 121. Recess; 122. Gate material; 130. Gate layer; 131. Opening; 140. Contact etch stop layer; 150. Interlayer dielectric layer; 160. Contact structure; 170. Metal layer; 115. Source; 116. Drain; 117. Contact metal; 200. Semiconductor structure; 210. Uncovered area; 220. Boundary point. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0032] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0033] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in embodiments of this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0035] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0036] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0037] In related technologies, high-voltage MOSFETs (high-voltage metal-oxide-semiconductor field-effect transistors) suitable for high-voltage operating scenarios require the addition of a field oxide layer 13 (i.e., STI) between the gate 10 and the source 11 and drain 12 to improve the voltage withstand performance of the high-voltage MOSFET. Figure 1a and Figure 1b Symmetrical high-voltage MOSFETs and asymmetric high-voltage MOSFETs are shown respectively, such as... Figure 1a , Figure 1b As shown, regardless of whether it is a symmetrical high-voltage MOSFET or an asymmetrical high-voltage MOSFET, the active region 14 of the channel between its source 11 and drain 12 has a boundary point 15 formed by the intersection of adjacent boundaries.

[0038] However, due to the process characteristics of the field oxide layer 13 and the gate oxide layer 16 covering the gate 10, the thickness of the gate oxide layer 16 at the boundary point 15 where it connects to the field oxide layer 13 is relatively thin. Specifically, refer to... Figure 2 , Figure 2 for Figure 1b The diagram shown is a cross-sectional view of the high-voltage MOSFET at boundary point 15 along the source and drain arrangement direction. Figure 2 It can be seen that, at the boundary point 15, the thickness T2 at the junction of the gate oxide layer 16 and the field oxide layer 13 is significantly smaller than the gate oxide layer thickness T1 at other locations.

[0039] The thinner sections of the aforementioned MOSFET exhibit weaker reliability under high-voltage operating conditions. For example, when the electric field intensifies, defects such as voids (pinholes or blind vias), cracks, impurities, and fibers may appear, leading to gas discharge, electrothermal decomposition, and ultimately dielectric leakage or even breakdown. Electric field concentration is particularly likely at the boundary points of the active region of the channel, resulting in a localized increase in electric field strength and making it easier for defects to appear in thinner sections of the gate oxide layer. In TDDB (Time-Dependent Dielectric Breakdown) testing, these defects can form a conductive path from the gate to the substrate after a certain period, generating a larger current and ultimately causing breakdown.

[0040] Therefore, it is necessary to provide a semiconductor structure that can improve the reliability of high-voltage MOSFETs.

[0041] Please see Figures 3 to 15 One embodiment of this application provides a method for fabricating a semiconductor structure. The semiconductor structure may be a component of a high-voltage MOSFET. Specifically, the method for fabricating the semiconductor structure may include the following steps.

[0042] S110: Provides a substrate.

[0043] In this embodiment, reference Figure 10 The substrate 110 may include a substrate 111 and a field oxide layer 106. A channel active region 112, defined by the field oxide layer 106, is formed in the substrate 111. The channel active region 112 is located between adjacent field oxide layers 106. One side of the field oxide layer 106 is the channel active region 112, and the other side is the source / drain region 113.

[0044] In some embodiments, the substrate may be provided with reference to Figures 3 to 10 The process steps are implemented. Specifically, firstly, such as... Figure 3 and Figure 4 As shown, trenches 101 are formed on the surface of a silicon wafer using photolithography and etching processes. Then, as... Figure 5 and Figure 6 As shown, a liner oxide layer 102 is grown on the sidewall of the trench, and an oxide layer 105 is filled in the trench 101 using a TEOS deposition process. A pad oxide layer 103 and a silicon nitride mask 104 are provided on the silicon wafer surface. Next, as... Figure 7 and Figure 8 As shown, excess oxide 105 is removed by CMP process, and the pad oxide layer 103 and silicon nitride mask 104 are removed to form a field oxide layer 106, i.e., STI, located within the trench 101. Finally, as... Figure 9 and Figure 10As shown, a masking layer 107 is formed on the surface of the silicon wafer and the field oxide layer 106, and the substrate 110 is obtained after ion implantation.

[0045] S120: A gate oxide layer is formed on the substrate surface.

[0046] In some embodiments, such as Figure 11 As shown, the photoresist and masking layer 107 during the ion implantation process can be removed first, and then the gate oxide layer 120 can be re-formed on the surface of the substrate 110 to prevent the masking layer 107 from being damaged by ion implantation as part of the gate oxide layer 120.

[0047] refer to Figure 11 In some embodiments, during the formation of the gate oxide layer 120 via a thermal oxidation process, oxygen diffuses along the silicon surface at high temperature and reacts to generate silicon dioxide. However, because a corner is formed at the intersection of adjacent boundaries of the channel active region 112, the oxygen diffusion and reaction rates at this location differ from those at other locations during the oxidation process. Furthermore, the field oxide layer 106 also exhibits a certain degree of depression at this location after CMP. Consequently, a depression 121 is formed on the surface of the gate oxide layer 120 at the location corresponding to the intersection of adjacent boundaries of the channel active region 112. This depression is relatively thinner than those at other locations; that is, the thickness of the gate oxide layer 120 at the depression 121 is less than the thickness of the gate oxide layer 120 at other locations.

[0048] S130: Deposit gate material on the surface of the gate oxide layer, and form an opening through the gate material at the position corresponding to the recess through photolithography and etching processes to obtain the gate layer.

[0049] In some embodiments, such as Figure 12 As shown, a gate material 122, such as polysilicon, is deposited on the surface of the gate oxide layer 120 using a chemical vapor deposition process, followed by... Figure 13 and Figure 14 As shown, a gate layer 130 is formed by etching a photoresist on the surface of the gate material 122 at a position corresponding to the recess 121. The gate layer 130 has a through-hole 131 formed at a position corresponding to the recess 121.

[0050] In some embodiments, the method for fabricating a semiconductor structure may further include: forming a contact etch stop layer, an interlayer dielectric layer, and a contact structure penetrating the contact etch stop layer and the interlayer dielectric layer on a gate layer.

[0051] Specifically, in some embodiments, in Figure 14 Based on the structure shown, subsequent manufacturing processes can be carried out to form, such as... Figure 15 The structure shown is illustrated. Where, reference... Figure 15A source 115 and a drain 116 are formed on both sides of the active region 112 of the channel, respectively. Contact metal 117, such as NiSi, is formed on the surface of the source, drain, and gate layer 130, and a contact structure 160 is formed on the contact metal 117. A contact etch stop layer 140 (CESL) and an interlayer dielectric layer 150 (ILD) are also provided on the gate layer 130 and the surfaces of the source and drain. The contact structure 160 penetrates the interlayer dielectric layer 150 and is connected to the metal layer 170 disposed on the interlayer dielectric layer 150 to form a conduction path.

[0052] In some embodiments, the contact etch stop layer 140 seals the opening 131 between the interlayer dielectric layer 150 and the gate layer 130. Specifically, as shown... Figure 15 As shown, the space inside the opening 131 can be filled with an insulating material, such as the same material as the interlayer dielectric layer 150, silicon nitride, etc. In some embodiments, the space inside the opening 131 may not be filled with material, and an air gap is formed under the sealing effect of the contact etch stop layer 140, thereby reducing parasitic capacitance.

[0053] In this embodiment, an unexpected effect is that source / drain regions 113 and a channel active region 112 located between the source / drain regions 113 are formed on the substrate 111, and a field oxide layer 106 is introduced between the channel active region 112 and the source / drain regions 113 to define the boundary of the channel active region 112. This results in a recess 121 being formed on the surface of the gate oxide layer 120 covering the channel active region 112 and the field oxide layer 106 at a position corresponding to the intersection of the adjacent boundary of the channel active region 112. Consequently, in the gate layer 130 formed on the surface of the gate oxide layer 120, an opening 131 penetrating the gate layer 130 is formed at a position corresponding to the recess 121 on the surface of the gate oxide layer 120. This reduces the electric field intensity distribution at the intersection of the adjacent boundary of the channel active region 112, avoids electric field concentration, and thus reduces leakage and breakdown caused by the thin gate oxide layer 120 at the position of the recess 121 to a certain extent, thereby improving reliability.

[0054] Please refer to Figure 14 , Figure 16a and Figure 16b Another embodiment of this application provides a semiconductor structure 200, including a substrate 111, a field oxide layer 106, a gate oxide layer 120, and a gate layer 130. In some embodiments, the semiconductor structure 200 can be fabricated using the semiconductor structure fabrication method described in the foregoing embodiments, and the semiconductor structure 200 can also be a component of a high-voltage MOSFET.

[0055] In this embodiment, the substrate 111 can serve as the basic structure of the semiconductor structure 200, not only providing mechanical support but also influencing the electrical properties of the semiconductor structure 200, such as threshold voltage and carrier mobility, through doping with ions. Specifically, the substrate 111 can be made of silicon (Si), or, depending on the requirements, of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN).

[0056] In this embodiment, an active drain region 113 and a channel active region 112 located between the source and drain regions 113 can be formed in the substrate 111. The source and drain regions 113 can be heavily doped to form source or drain electrodes. The channel active region 112 is part of the active region and can serve as a portion of the active region used to form a carrier flow channel.

[0057] In this embodiment, the field oxide layer 106 can achieve lateral electrical isolation and is used to adjust the electric field distribution, thereby improving the voltage withstand capability of the high-voltage MOSFET. Specifically, as shown... Figure 14 As shown, the field oxide layer 106 can be connected to the bottom of the gate oxide layer 120 and extends from the surface of the substrate 111 to the bottom.

[0058] In this embodiment, the field oxide layer 106 is located between the channel active region 112 and the source / drain region 113, and defines the boundary of the channel active region 112. Specifically, as shown... Figure 14 As shown, the active channel region 112 is the region in the substrate 111 located between adjacent field oxide layers 106. The region in the substrate 111 located outside the field oxide layer 106 is the source / drain region 113.

[0059] In this embodiment, the gate oxide layer 120 covers the channel active region 112 and the field oxide layer 106, and is connected to the field oxide layer 106 to jointly form the gate dielectric layer. Wherein, reference... Figure 14 As mentioned above, due to the process characteristics of fabricating the field oxide layer 106 and the gate oxide layer 120, a depression 121 is formed on the surface of the gate oxide layer 120 at the position corresponding to the intersection with the adjacent boundary of the channel active region 112. As a result, the gate oxide layer 120 at the position of the depression 121 is relatively thin, and its thickness is less than that of the gate oxide layer 120 at other positions.

[0060] In this embodiment, the gate layer 130 is located on the surface of the gate oxide layer 120. The gate layer 130 has a through-hole 131, the position of which corresponds to the position of the recess 121, such that the projection of the gate layer 130 onto the surface of the gate oxide layer 120 does not overlap with at least a portion of the surface of the recess 121. Specifically, refer to... Figure 16a and Figure 16bFrom the perspective of the planar structure, it can be seen that the position of the opening 131 formed by the gate layer 130 corresponds to the intersection of the adjacent boundary of the channel active region 112 in the direction perpendicular to the substrate 111.

[0061] An unexpected effect is that by forming a through-hole 131 in the gate layer 130 at a position corresponding to the recess 121 on the surface of the gate oxide layer 120, the gate material 122 is absent in at least a portion of the relatively thin area of ​​the gate oxide layer 120. This reduces the electric field intensity distribution at that position, avoids electric field concentration, and thus reduces leakage and breakdown caused by the thin gate oxide layer 120 at the recess 121 position to a certain extent, thereby improving reliability.

[0062] Optionally, the gate layer 130 defines an uncovered region 210 on the surface of the gate oxide layer 120 through an opening 131, and the recess 121 is located within the uncovered region 210. That is, the projection of the gate layer 130 onto the surface of the gate oxide layer 120 does not overlap with the surface of the recess 121 at all. In this way, the electric field intensity in the thinner region of the gate oxide layer 120 can be further reduced.

[0063] In some embodiments, adjacent boundaries of the active region 112 of the channel intersect to form a boundary point 220. The aperture 131 has a central axis perpendicular to the substrate surface, and this central axis passes through the boundary point 220. Aligning the central axis of the aperture 131 of the gate layer 130 corresponding to the boundary point 220 with the boundary point 220 can further optimize the local electric field distribution and alleviate electric field concentration by improving the electric field symmetry near the boundary point 220. When the central axis passes through the boundary point 220, a symmetrical potential gradient can be formed at this location, causing the electric field originally concentrated at the tip of the boundary point 220 to diffuse uniformly to the surrounding area. This significantly reduces the electric field intensity near the boundary point 220, suppresses carrier tunneling and oxide trap formation, and further improves the stability and gate breakdown voltage of the semiconductor structure 200 under high-voltage operating conditions.

[0064] In some embodiments, the ratio of the area occupied by the aperture 131 on the surface of the gate layer 130 to the total area of ​​the gate layer 130 falls within the range of 1% to 5%. Setting the ratio of the area occupied by the aperture 131 on the surface of the gate layer 130 to the total area within the range of 1% to 5% can achieve a balance between electric field distribution control and structural stability. Since if the aperture 131 is set too large, it may not only excessively weaken the gate's control over the channel, causing problems such as a drop in threshold voltage, but also affect the overall mechanical strength of the gate layer 130. Therefore, setting the aperture 131 size within the above range achieves electric field regulation, alleviates electric field concentration, while taking into account the performance and mechanical strength of the gate structure, and prevents material peeling or stress mismatch problems caused by excessively large apertures 131 during the process. Furthermore, the 1% to 5% aperture 131 ratio has high compatibility with existing photolithography and etching processes, balancing manufacturing yield and cost control, making it highly practical.

[0065] In some embodiments, the outline shape of the aperture 131 formed on the surface of the gate layer 130 is circular or hexagonal. Thus, when the aperture 131 is circular or hexagonal, stress concentration caused by etching can be reduced, stress distribution can be uniform, and edge effects can be reduced.

[0066] In some embodiments, the outline shape of the aperture 131 formed on the surface of the gate layer 130 is rectangular, and the ratio of the length to the width of the rectangle falls within the range of 2.5 to 3.5. Thus, when the shape of the aperture 131 is rectangular or square, the shape is more regular, which is beneficial for the alignment and control of photolithography and etching processes, and facilitates subsequent process optimization.

[0067] To illustrate the technical effects of this application, the technicians conducted experiments, measuring the gate current IG and gate voltage VG of high-voltage NMOS and high-voltage PMOS respectively. The experimental results are as follows: Figure 17 and Figure 18 As shown. Figure 17 and Figure 18 Examples 1 to 3 show the IG-VG curves for gate layer 130 with rectangular openings 131 of different sizes, respectively, while the comparative example shows the IG-VG curves for gate layer 130 without openings 131. The experimental results show that when the linear scan voltage VG is 40V, the gate leakage current is significantly reduced, and the gate breakdown voltage can be increased from 72V to over 80V.

[0068] In some embodiments, the semiconductor structure 200 corresponds to a target design file that conforms to manufacturing process rules after Boolean operation.

[0069] Because the initial design files (GDS) of the semiconductor structure 200 obtained by technicians before fabrication often do not conform to the manufacturing process rules in actual production, it is necessary to consider the errors in the actual production process and perform Boolean operations (Auto Generation) on the initial design files to optimize them and obtain target design files that conform to the manufacturing process rules. Only then can the manufacturing process be implemented based on the target design files. For example, for the gate layer 130 in the initial design file, Boolean operations can be used to calculate the boundaries of each region to optimize it and make it conform to the manufacturing process rules in actual production.

[0070] In some embodiments, the shape and size of the aperture 131 can be adjusted in the target design file using Boolean operations, without modifying the initial design file or adding a photomask, thus reducing process costs.

[0071] Another embodiment of this application provides a high-voltage MOS device, including the semiconductor structure as described in the foregoing embodiments, or prepared using the semiconductor structure preparation method described in the foregoing embodiments.

[0072] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0073] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0074] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0075] It is understood that in the description of this application, when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it may mean that it is directly above another layer or region, or that it contains other layers or regions between itself and another layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" another layer or region.

[0076] The above description is merely a specific embodiment of this application, but the protection scope of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: A substrate; an active drain region and a channel active region located between the source drain regions are formed in the substrate; A field oxide layer is located between the active region of the channel and the source / drain region, and defines the boundary of the active region of the channel. A gate oxide layer covers the active region of the channel and the field oxide layer; wherein, a depression is formed on the surface of the gate oxide layer at a position corresponding to the intersection of the adjacent boundary of the active region of the channel; the thickness of the gate oxide layer at the depression position is less than the thickness of the gate oxide layer at other positions; A gate layer is located on the surface of the gate oxide layer; wherein the gate layer has a through-hole formed at a position corresponding to the recess.

2. The semiconductor structure according to claim 1, characterized in that, The gate layer defines an uncovered area on the surface of the gate oxide layer through the opening; the recess is located within the uncovered area.

3. The semiconductor structure according to claim 1, characterized in that, The adjacent boundaries of the active region of the channel intersect to form a boundary point; the opening has a central axis perpendicular to the substrate surface, and the central axis passes through the boundary point.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure corresponds to a target design file that conforms to the manufacturing process rules after Boolean operation; wherein, the shape and size of the opening in the target design file can be adjusted by the Boolean operation.

5. The semiconductor structure according to claim 3, characterized in that, The ratio of the area occupied by the opening on the surface of the gate layer to the total area of ​​the gate layer surface falls within the range of 1% to 5%.

6. The semiconductor structure according to claim 3 or 4, characterized in that, The aperture forms a circular or hexagonal outline on the surface of the gate layer.

7. The semiconductor structure according to claim 3 or 4, characterized in that, The opening forms a rectangular outline on the surface of the gate layer, and the ratio of the length to the width of the rectangle falls within the range of 2.5 to 3.

5.

8. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided; the substrate includes a substrate and a field oxide layer; wherein a channel active region defined by the field oxide layer is formed in the substrate; A gate oxide layer is formed on the surface of the substrate; wherein, a depression is formed on the surface of the gate oxide layer at a position corresponding to the intersection of the adjacent boundary of the channel active region; the thickness of the gate oxide layer at the depression position is less than the thickness of the gate oxide layer at other positions; A gate material is deposited on the surface of the gate oxide layer, and an opening through the gate material is formed at the position corresponding to the recess by photolithography and etching processes to obtain the gate layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The preparation method further includes: A contact etch stop layer, an interlayer dielectric layer, and a contact structure penetrating the contact etch stop layer and the interlayer dielectric layer are formed on the gate layer; wherein the contact etch stop layer seals the opening between the interlayer dielectric layer and the gate layer.

10. A high-voltage MOS device, characterized in that, It includes the semiconductor structure as described in any one of claims 1 to 7, or is prepared using the method for preparing the semiconductor structure as described in any one of claims 8 to 9.

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