Rank interleaving for system element mode operations in dynamic random access memory (DRAM) memory devices

Abstract

This disclosure provides systems, methods, and devices for supporting a memory system that processes data and metadata within memory of a memory device. In a first aspect, a method of controlling a memory device includes performing a first request in a first rank of the memory device during a first time period, where the first time period includes a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, where the second time period includes a second data access portion and a second metadata access portion, wherein performing the first request in the first rank and performing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 495,215, filed October 26, 2023, entitled “RANK INTERLEAVING FOR SYSTEM META MODE OPERATIONS IN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) MEMORY DEVICE,” and also claims the benefit of U.S. Provisional Patent Application No. 63 / 505,997, filed June 2, 2023, entitled “RANK INTERLEAVING FOR SYSTEM META MODE OPERATIONS IN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) MEMORY DEVICE,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to computer information systems, and more specifically, to memory systems for storing data. Certain features enable and provide improved memory capabilities for processing data and metadata stored in the same memory device. Background Technology

[0003] Computing devices (e.g., laptops, mobile phones, etc.) may include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions. A memory system is a crucial component of a computing device. A processor may be coupled to a memory system to perform the aforementioned computing functions. For example, a processor may fetch instructions from a memory system to perform computing functions and / or store temporary data involved in performing these computing functions within the memory system. Summary of the Invention

[0004] The following summary outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This summary is not an exhaustive overview of all the intended features of this disclosure, nor is it intended to identify key or essential elements of all aspects of this disclosure, nor to define the scope of any or all aspects of this disclosure. The sole purpose of this summary is to present, in a general form, some concepts of one or more aspects of this disclosure as a prelude to the more detailed description that follows.

[0005] In some aspects, different types of information (such as data and metadata) can be stored in the same memory of the memory system to enhance the operational efficiency of the memory system. Specifically, in the system meta-schema, data and associated metadata can be stored in the same row of memory. Furthermore, the memory system can include multiple ranks of memory for storing data and metadata, such as multiple blocks or partitions of the memory's storage capacity. To facilitate efficient use of limited memory bandwidth, data access operations (such as reading data or metadata from multiple ranks of the memory system, and / or reading and / or writing metadata to multiple ranks of the memory system) can be interleaved. Such interleaving can, for example, include initiating a first data access operation for a first rank and subsequently initiating a second data access operation for a second rank. Such interleaving can include executing at least a portion of a data access operation of the first rank of the memory system in parallel with at least a portion of a second data access operation of the second rank of the memory system. Specifically, an operation for accessing metadata at one rank of the memory system can be performed in parallel with an operation for accessing data at another rank of the memory system.

[0006] Specific embodiments of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. Interleaving data access operations for different ranks of the memory system can enhance the efficiency of cache and bus capacity utilization in the memory system. In some aspects, such interleaving can provide cache access efficiency of up to and exceeding 86 percent.

[0007] These aspects can be manifested as a sequence of commands sent from the host to the memory system. Commands sent by the host may include commands to read capabilities from the memory system, configure settings in the memory system, read data from one or more specified addresses in the memory system, and / or write data from one or more specified addresses to the memory system.

[0008] An apparatus according to at least one embodiment includes a memory system configured to communicate with a host. The memory system may include one or more memory controllers configured to control a memory device. For example, the memory device may include a memory array configured to store data. The one or more memory controllers may be configured to provide data stored in the memory array to the host for further processing by the host's processor or other components. The one or more memory controllers may also be configured to receive data from the host for storage in the memory device, such as in the memory array. In some embodiments, the memory device may include a plurality of volatile memory cells organized in rows and columns, such as in dynamic random access memory (DRAM) or static random access memory (SRAM). In other embodiments, the memory device may include a plurality of non-volatile memory cells, or a combination of volatile and non-volatile memory cells.

[0009] An apparatus according to at least one other embodiment includes a host device having one or more memory controllers configured to communicate with a memory system to receive data stored in a memory array and / or store data in the memory array. The host device may be, for example, a user equipment (UE) device, such as a cellular phone, tablet computing device, personal computer, server, smartwatch, or Internet of Things (IoT) device.

[0010] In one aspect of this disclosure, a method for operating a memory device includes: receiving a first request for the memory device and a second request for the memory device by one or more memory controllers; executing the first request by the one or more memory controllers in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; and executing the second request by the one or more memory controllers in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank.

[0011] In an additional aspect of this disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to receive and schedule operations for execution by a multi-rank memory device. The processor may be a processor in a host computer, a controller, or other logic circuitry. Alternatively, the processor may be a controller embedded in the memory device. The processor is also configured to perform the operations described herein.

[0012] In an additional aspect of this disclosure, an apparatus includes components for receiving, by one or more memory controllers, a first request for a memory device and a second request for a memory device; components for executing, by one or more memory controllers, the first request in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; and components for executing, by one or more memory controllers, the second request in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank.

[0013] In an additional aspect of this disclosure, an apparatus includes one or more memory controllers of a memory system. The one or more memory controllers are configured to perform operations including: receiving a first request for a memory device and a second request for a memory device; executing the first request in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; and executing the second request in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank interleave the first request and the second request between the first rank and the second rank.

[0014] In an additional aspect of this disclosure, an apparatus includes a host device configured to communicate with a memory module via a channel. The host device includes one or more memory controllers coupled to the channel. The one or more memory controllers are configured to perform operations including: receiving a first request and a second request for the memory device; executing the first request in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; and executing the second request in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank includes interleaving the first and second requests between the first and second rank.

[0015] An apparatus according to at least one embodiment includes a memory configured to communicate with a host. The memory may include a memory array configured to store data. The memory is configured to provide data stored in the memory array to the host when performing computational functions. In some aspects, the registers of the memory device may be configured to store data and metadata separately in different groups of registers. The metadata register may temporarily store information during transmission between the host device and the memory device to be retrieved from the memory array of the memory device in response to a read command, or to be stored in the memory array of the memory device in response to a write command.

[0016] In one aspect of this disclosure, a memory device includes: a memory array comprising a first portion and a second portion; and a memory input / output (I / O) module. The memory I / O module is coupled to the memory array and configured to communicate with a host via a channel including a plurality of connections, the plurality of connections including at least one data connection and at least one non-data connection and including at least one first register and at least one second register. The memory I / O module is configured to perform operations including: receiving data from the host via at least one data connection into at least one first register; receiving metadata from the host via at least one non-data connection into at least one second register; storing data in the first portion of the memory array; and storing metadata in the second portion of the memory array. The memory I / O module is further configured to perform operations including: retrieving data from the first portion of the memory array into at least one first register; retrieving metadata from the second portion of the memory array into at least one second register; transmitting data from at least one first register to the host via at least one data connection; and transmitting metadata from at least one second register to the host via at least one non-data connection.

[0017] In an additional aspect of this disclosure, an apparatus (such as a wireless device) includes at least one processor and one or more memories coupled to the at least one processor. The at least one processor is configured to communicate with a memory system via one or more memory controllers coupled to a channel, the channel coupling the processor to the memory system. The processor may be a processor, controller, or other logic circuitry in a host computer.

[0018] In an additional aspect of this disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein with respect to various aspects of this disclosure.

[0019] The memory system of this disclosure can be embedded within a processor on a semiconductor die or as part of a different semiconductor die. The memory system can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash memory, or NOR flash memory, etc.

[0020] The methods and apparatuses presented in this disclosure are given as non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, LPDDR memory operates according to the LPDDR specification issued by the Joint Electron Device Engineering Committee (JEDEC). One such LPDDR specification could be LPDDR5. Another such LPDDR specification could be LPDDR6.

[0021] The term "one or more error-correcting codes" (ECC) in this disclosure can refer to error detection, error correction, or both. ECC is not limited to a particular type of decoding. In some examples, ECC may include Hamming codes and / or parity codes.

[0022] Other aspects, features, and specific embodiments will become apparent to those skilled in the art when they review the following description of particular exemplary aspects in conjunction with the accompanying drawings. Although features may be discussed hereinafter with reference to certain aspects and drawings, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed having certain advantageous features, one or more such features may also be used depending on the various aspects. Similarly, although exemplary aspects may be discussed hereinafter as aspects of an apparatus, system, or method, exemplary aspects can be implemented in various apparatuses, systems, and methods.

[0023] This method can be embedded as computer program code in a computer-readable medium, the computer program code including instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including a first network adapter configured to transmit data, such as recorded images or videos or as streaming data, via a first network connection among a plurality of network connections. The processor may be coupled to the first network adapter and memory for storing data to support processing and communication operations performed by the processor. The network adapter may support communication on a wireless communication network such as a 5G NR communication network. The processor may cause data stored in the memory to be transmitted via the wireless communication network.

[0024] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose of this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and manner of operation) and the associated advantages will be better understood from the following description when considered in conjunction with the accompanying drawings. Each figure in the drawings is provided for illustrative and descriptive purposes and not as a limitation of the definitions in the claims.

[0025] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or devices may be implemented via integrated chip implementations and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to use cases or applications, applicability to various types of the described innovations is possible. The scope of implementations ranges from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily involve multiple components (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.) for analog and digital purposes. The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0026] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numeral and a second numeral for differentiation between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0027] Figure 1 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0028] Figure 2 A block diagram of an example computing system, comprising a host, a memory system, and a channel that couples the host and memory system using another specific implementation of a channel, is shown according to one or more aspects of this disclosure.

[0029] Figure 3A and Figure 3B A waveform illustrating the transmission of data via an example channel during a write operation according to certain aspects of this disclosure is shown.

[0030] Figure 4A and Figure 4B A waveform illustrating the transmission of data via an example channel during a read operation according to certain aspects of this disclosure is shown.

[0031] Figure 5A This is a block diagram illustrating an example configuration of a metadata register according to one or more aspects of this disclosure.

[0032] Figure 5B This is a block diagram illustrating an example configuration of a metadata register according to one or more aspects of this disclosure.

[0033] Figure 6 This is a block diagram illustrating a multi-rank configuration of a memory device coupled to a memory controller according to one or more aspects of this disclosure.

[0034] Figure 7 This is a flowchart illustrating a method of accessing rows in a memory device according to one or more aspects of this disclosure.

[0035] Figure 8 This is a flowchart illustrating a method of interleaving operations between ranks in a memory device according to one or more aspects of this disclosure.

[0036] Figure 9 This is a block diagram illustrating the interleaved operation of data and metadata between rank in a memory device according to one or more aspects of this disclosure.

[0037] Figure 10 This is a table illustrating examples of LPDDR address bit mappings according to one or more aspects of this disclosure.

[0038] Figure 11A It is the first part of a hash table for address mapping according to one or more aspects of this disclosure.

[0039] Figure 11BIt is the second part of the hash table for address mapping according to one or more aspects of this disclosure.

[0040] Figure 12A This is an example block diagram of a write buffer and a first part of a write scheduler for scheduling write operations, according to one or more aspects of this disclosure.

[0041] Figure 12B This is an example block diagram of the second part of a write buffer and a write scheduler for scheduling write operations, according to one or more aspects of this disclosure.

[0042] The same reference numerals and names in different figures denote the same elements. Detailed Implementation

[0043] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to limit the scope of this disclosure. Rather, the detailed description includes specific details for providing a thorough understanding of the subject matter of the invention. It will be apparent to those skilled in the art that these specific details are not necessary in every situation, and in some cases, well-known structures and components are shown in block diagram form for clarity of presentation.

[0044] This disclosure provides systems, apparatus, methods, and computer-readable media supporting data processing, including techniques for supporting data communication between a host and a memory device. The host may send data and accompanying metadata for storage in a memory array of the memory device. The memory device may include registers for receiving a copy of the metadata stored in the memory array before sending the data and associated metadata to the host in response to a read command, and for accumulating the metadata sent by the host along with the data for writing to the memory array. The metadata register of the memory device may be organized to associate metadata with data without using two separate addresses for the data and metadata. Examples of metadata stored with the data include error-correcting codes (ECC) to protect the data from errors and / or signatures to protect the data from tampering. However, the purpose of metadata is not limited to protecting data. To enhance the efficiency and reduce the cost of the memory system, in the system meta-schema, both data and metadata may be stored in the same memory array of the memory system. In some aspects, data and metadata may be stored in the same row or page of the memory array of the memory system, wherein a portion of that row or page is allocated for data storage and a portion of that row or page is allocated for metadata storage. Accessing metadata stored in the same row or page as the data in memory can reduce the amount of memory bandwidth available for reading and / or writing data, because metadata access operations can utilize bandwidth that would otherwise be available for reading data from and / or writing data to memory. In some cases, this can result in a 20% to 30% loss in memory utilization, with only about 55% of the maximum DDR bandwidth used for reading and writing data. This reduction in efficiency can be attributed at least in part to metadata write operations, which are primarily partial writes and utilize a large portion of the read / write bandwidth of the memory device, including the memory array. To facilitate more efficient reading of data and metadata from memory configured in system meta mode and more efficient writing of data and metadata to that memory, metadata and data can be read from or written to the memory array by interleaving operations between the rank of the memory device, thereby reducing the overhead associated with reading additional metadata bits and / or writing additional metadata bits to the memory array.

[0045] Specific embodiments of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure reduces overhead by allowing metadata operations in one rank of the memory device to overlap with data operations in another rank of the memory device. Such reduction can enhance the operational efficiency of the memory device, thereby allowing for faster reading and writing of data and metadata.

[0046] As the demand for computing devices to perform more functions at higher speeds continues to grow, so too does the error rate of data stored in memory. As the amount of data stored in memory and transferred between blocks increases, so too does the number of errors. One example of preventing such errors is the use of error-correcting codes (ECC) associated with the data. Schemes to improve error detection / correction when accessing memory without overburdening the host or memory are beneficial for improving system performance. ECC can be attached during transmission over a channel, such as using link ECC. ECC can also be attached for storage within memory arrays, such as utilizing system ECC. In some examples, inline ECC parity bits can be added to high-density on-chip SRAM to store some data, thereby implementing end-to-end system ECC in the host and enhancing overall data reliability. However, such high-density on-chip SRAM is very expensive in terms of overall system cost, and high-density SRAM is susceptible to soft errors associated with SRAM cells. ECC data is an example of metadata that can be stored along with data in one or more rank units of a memory system.

[0047] Figure 1 Example memory devices that can be incorporated into various aspects of this disclosure are shown, including performing transactions (e.g., read operations and / or write operations) in multiple rank of the memory device in an interleaved manner to reduce the impact of accessing metadata. Figure 1 An example is illustrated of a device 100 comprising a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150. Device 100 may be, for example, a computing system (e.g., a server, data center, desktop computer), a mobile computing device (e.g., a laptop computer, a mobile phone, a vehicle, etc.), an Internet of Things (IoT) device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital video camera, a camera-equipped wireless communication device, a mobile phone (such as a mobile phone, cellular or satellite radio phone), a personal digital assistant (PDA), a panel or tablet computer, a gaming device, a computing device (such as a webcam, a video surveillance camera, or other device with digital imaging or video capabilities)), and / or a multimedia system (e.g., a television, a CD player, a streaming media device).

[0048] Host 110 may include at least one processor, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), multimedia engine, and / or neural processing unit (NPU). Host 110 may be configured to couple to and communicate with memory 150 (e.g., memory 150-1 to 150-4) via channel 190 (e.g., channels 190-1 to 190-4) when performing computational functions such as data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc. For example, memory 150-1 to 150-4 may store instructions or data for the host to perform computational functions.

[0049] Host 110 may include a memory controller 130, which may include controller PHY modules 134-1 to 134-4. Each of the controller PHY modules 134-1 to 134-4 may be coupled to a corresponding memory in memory 150-1 to 150-4 via a corresponding channel 190-1 to 190-4. In some embodiments, each of the controller PHY modules 134-1 to 134-4 may be a different memory controller 130-1 to 130-4. For ease of reference, read and write operations are referenced from the perspective of host 110. For example, in a read operation, host 110 may receive stored data from one or more of the memories 150-1 to 150-4 via one or more of the channels 190-1 to 190-4. During a write operation, host 110 may provide data to be written to one or more of the memories 150-1 to 150-4 for storage via one or more of channels 190-1 to 190-4. Memory controller 130 may be configured to control various aspects of communication to and from memories 150-1 to 150-4, such as the logic layer. Controller PHY modules 134-1 to 134-4 may be configured to control the electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) of signals provided or received on channels 190-1 to 190-4, respectively.

[0050] In some examples, memories 150-1 to 150-4 may be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, memories 150-1 to 150-4 may be different types of memory, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM, respectively. Host 110, memories 150-1 to 150-4, and / or channels 190-1 to 190-4 may operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of channels 190-1 to 190-4 may include 16 bits of data (e.g., 16 DQs). In some examples, each of channels 190-1 to 190-4 may operate on 32 bits of data (e.g., 32 DQs). Figure 1 The diagram shows four channels; however, the device 100 may include more or fewer channels, such as eight or sixteen channels.

[0051] Figure 2 Additional details of one aspect of an embodiment of a device 100 for providing access to a memory system, such as one of memory 150-1 to 150-4 including logic and control circuitry, are shown. Figure 2 The configuration of host 110 and memory system 250 is illustrated. Figure 2 An example is shown that has a host 110, a memory system 250, and a channel 190. Figure 1 Another representation of the device 100. Channel 190 between host 110 and memory system 250 may include multiple connections, some carrying data (e.g., user data or application data) and some carrying non-data (e.g., address and other signaling information). For example, non-data connections in channel 190 may include a data clock (e.g., WCK) for providing data to the respective memory system 250 and a read data strobe (e.g., RDQS) for receiving data from the respective memory system 250 on a bit-by-bit basis. Channel 190 may also include commands and addresses (e.g., CA[0:n]) and an associated CA clock for providing commands (e.g., read or write commands) to memory system 250.

[0052] Host 110 may include at least one processor 120, which may include a CPU 122, a GPU 123, and / or an NPU 124. Host 110 may also include a memory controller 130 having a controller PHY module 134. Memory controller 130 may be coupled to at least one processor 120 via a bus system 115 to perform various computing functions. The term "bus system" may specify that the elements coupled to the "bus system" can exchange information directly or indirectly between them. In different embodiments, "bus system" may encompass multiple physical connections and intermediate levels, such as buffers, latches, registers, etc. Modules may be implemented in hardware, software, or a combination of hardware and software.

[0053] Memory controller 130 can send and / or receive data blocks to other modules, such as at least one processor 120 and / or memory system 250. Memory system 250 may include memory controller 180 with a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on the connection of channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Figure 3A , Figure 3B , Figure 4A ,and Figure 4B The example illustrates an example technique for communication over channel 190 between memory I / O module 160 and memory controller 130.

[0054] The memory system 250 may also include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) for storing values. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via channel 190 and memory I / O module 160. The memory array 175 may be divided into multiple libraries, where each library is organized into multiple pages. In some aspects, the memory array 175 may be divided into multiple ranks. For example, each rank may include one or more libraries, where each library includes one or more pages.

[0055] Application data or user data may be processed by processor 120, and memory controller 130 is instructed to store such data and / or retrieve such data from memory system 250. For example, data may be generated during the execution of an application (such as a spreadsheet program that calculates values ​​based on other data). As another example, data may be generated during the execution of an application by receiving user input to, for example, a spreadsheet program. As yet another example, data may be generated during the execution of a game application, which generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0056] Host 110 is coupled to memory system 250 via channel 190, exemplified for one bit of data DQ[0:7]. Channel 190 and signaling between host 110 and memory system 250 may be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As illustrated, channel 190 includes signal connections for DQ, Read Data Strobe (RDQS), Data Mask (DM), Data Clock (WCK), Command and Address (CA[0:n]), and Command and Address Clock (CK). Host 110 may use Read Data Strobe (RDQS) to strobe data (e.g., time the data) to receive data on DQ during a read operation. Memory system 250 may use Data Mask (DM) to mask portions of the data to prevent them from being written during a write operation. Memory system 250 may use Data Clock (WCK) to sample data on DQ for a write operation. Memory system 250 may use Command and Address Clock (CK) to time CA (e.g., receive). Signal connections for each of the signaling components may include pins at host 110, pins at memory system 250, and one or more conductive traces of electrical connection pins. One or more conductive traces may be portions of a single integrated circuit (IC) on a silicon chip containing processor 120, and memory system 250 may be portions of a stacked package (PoP) containing processor 120 and memory system 250, or portions of a printed circuit board (PCB) coupled to both processor 120 and memory system 250. In some aspects, channel 190 between host 110 and memory system 250 may include 12 DQ pins for 12-bit data DQ[11:0], and no DM pins. Both data and metadata may be transmitted on the DQ pins, transmitting 32 bits of data and 4 bits of metadata over 24 beats (24BL). In some cases, such as when transmitting ECC metadata via channel 190, only two of the four available bits may be transmitted, since every 32 bits of ECC data may include 2 bits of metadata.

[0057] The memory system 250 may include a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on channel 190. For example, the memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190.

[0058] Information transmitted across channel 190 may be stored in registers in memory I / O module 160 of memory 150 as a temporary or short-term storage location prior to long-term storage in memory array 175. Memory I / O module 160 may include a first register and a second register for storing data (e.g., user data or application data) and metadata, respectively. As an example, multiple metadata registers 181A-181N may store metadata. The contents of registers 181A-181N may then be transferred to memory array 175. In some embodiments, the contents of registers 181A-181N may be transmitted serially shortly after receipt to complete individual write commands. In some embodiments, the contents of registers 181A-181N may be accumulated from multiple write commands received at memory 150 and metadata transferred to memory array 175 when certain criteria are met. Data is then automatically written to a first portion of the memory array without any additional write commands from the host. Figures 5A to 5B as well as Figure 6 The image shows some example configurations of metadata registers 181A-181N.

[0059] The metadata registers 181A-181N can be associated with the memory addresses of the memory array 175 using different technologies. Figure 5A An example memory address mapping is shown. For example, by dividing column spaces corresponding to 0x3C to 0x3F, certain addresses within a page can be assigned to metadata. Metadata registers 181A-181N can include n metadata registers dedicated to each column location, and each of the n registers dedicated to each column location can be dedicated to one of n libraries. That is, column space 0x3C has a first group of 518A n metadata registers, column space 0x3D has a second group of 518B n metadata registers, column space 0x3E has a third group of 518C n metadata registers, and column space 0x3F has a fourth group of 518D n metadata registers. In this example configuration, metadata registers 181A-181N can have a total of 4n registers. Figure 5BIn another example shown, metadata registers 181A-181N may include a single register for each library, with a total of n registers for n libraries. Therefore, metadata registers 181A-181N may include a single set of metadata registers 520, and column spaces 0x3C to 0x3F may be associated with a single set of n metadata registers 520, rather than separate sets of metadata registers per column space. Using a single set of metadata registers for column spaces 0x3C to 0x3F reduces memory die size overhead by using a single metadata register per library.

[0060] return Figure 2 The memory system 250 may also include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells) for storing information. For example, each page of each library in the memory array 175 may include multiple cells. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via channel 190. Furthermore, the memory array 175 may be configured to store metadata associated with the stored data, such as ECC (e.g., system or array ECC).

[0061] Operations for storing and retrieving information from memory array 175, according to some embodiments of this disclosure, can be performed via signals on the various lines of control channel 190. (See reference...) Figure 3A and Figure 3B An example implementation of signaling for write operations is shown and described. References Figure 4A and Figure 4B An example implementation of the signaling used for the read operation is shown and described.

[0062] Figure 3A and Figure 3B A waveform illustrating data transmission via an example channel during a write operation according to certain aspects of this disclosure is shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is marked DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (rising edge of CK_c and falling edge of CK_t), a CAS command can be provided by host 110 for a write operation to memory system 250. At T1, a write command can be provided by host 110 to memory system 250.

[0063] After the write time delay (WL), host 110 can switch data clocks WCK0_t and WCK0_c to provide timing for memory system 250 to receive data for writing on the DQ signal connection. In Tc0 through Tc2, memory system 250 can serially receive 16 bits of data on each of the DQ[0:7] signal connections and timing it with data clocks WCK0_t and WCK0_c. Memory system 250 can serially receive a 16-bit data mask DM0 (e.g., based on data clocks WCK0_t and WCK0_c) to mask certain portions of the received data from write operations. In some examples, 16 bits of data and a 16-bit data mask DM0 can be received by memory system 250, where each bit of data mask DM0 masks the corresponding bit of received data. In Tc0 through Tc2, the RDQS_t signal connection can be Hi-Z conditional. During a read operation, the RDQS_t signal connection can be configured to provide a read data strobe (RDQS) from the memory system 250 to the host 110.

[0064] Figure 4A and Figure 4B A waveform illustrating data transmission via an example channel during a read operation according to certain aspects of this disclosure is shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is marked DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (rising edge of CK_c and falling edge of CK_t), a CAS command can be provided by host 110 for a read operation on memory system 250. At T1, a read command can be provided by host 110 to memory system 250.

[0065] After the time period read delay (RL), memory system 250 can switch the read data strobe RDQS to provide host 110 with timing for receiving data for read operations on the DQ signal connections. During Tc0 to Tc2, host 110 can serially receive 16 bits of data on each of the DQ[0:7] signal connections and be timed by the read data strobes RDQS_t and RDQS_c. Therefore, in this example, 16 bits of data are received by host 110.

[0066] In Tc0 to Tc2, the data masking DM0 signal connection can be in Hi-Z condition. During write operations, the DM signal connection can be configured to provide a data mask from host 110 to memory system 250, which is timed by WCK0_t and WCK0_c.

[0067] Figure 6 This is a block diagram illustrating a multi-rank configuration of a memory device coupled to a memory controller according to one or more aspects of this disclosure. A system-on-a-chip (SoC) may be a host device 110 for coupling with memory devices 150-1, 150-2. In some aspects, each of memory devices 150-1, 150-2 may correspond to a rank of the memory system. Different memory devices 150-1, 150-2 may share bus lines, such as data lines and address lines. In some embodiments, the multi-rank configuration may include a bus interface to a shared SoC, such as bus interface 606. In some embodiments, each rank of the memory system may include a die, while in other embodiments, the memory system may include a single die having multiple rank. A memory rank may, for example, be a block or group of data storage units in the memory device. For example, each rank may include one or more DRAM cells in a memory module. In some aspects, each rank may include multiple memory libraries of the memory device. Therefore, for example, memory devices 608 and 612 may include a memory array comprising a first rank 604A and a second rank 604B, and each rank may correspond to a subarray of the memory array. (Reference) Figure 6 The memory device may include multiple dies, such as a first die 608 and a second die 612. The first die 608 may include a first memory rank 604A, such as a first memory array corresponding to the first memory rank 604A. The second die 612 may include a second memory rank 604B, such as a second memory array corresponding to the second memory rank 604A. In some aspects, the first memory rank 604A and the second memory rank 604B may be included on a single memory die of the memory device. The first memory die 608 and the second memory die 612 may be connected to the host 110 via a shared bus 606. The first memory rank 604A may correspond to a first memory array including 16 memory banks, and the second memory rank 604B may correspond to a second memory array including 16 memory banks. For example, the first die 608 of the memory device may include the first memory rank 604A, which may correspond to... Figure 1 The memory device 150-1. The second die 612 of the memory device may include a second memory rank 604B, which may correspond to... Figure 1The memory device 150-2. Memory ranks (such as memory ranks 604A and 604B) may have different chip select (CS) lines to allow the memory controller 130 to specifically address each rank 604A and 604B. Each memory die 608, 612 may also include logic circuitry to support operations performed by the memory controller 130 on memory arrays corresponding to the first memory rank 604A and the second memory rank 604B. For example, logic circuitry 602A-602B may control the corresponding memory array ranks 604A-604B. In some aspects, logic circuitry 602A-602B and memory ranks 604A-604B may reside on a single die. In some embodiments, each rank 604A-604B may have separate metadata registers to separately buffer metadata (e.g., ECC) from data buffered by the corresponding memory rank. Therefore, for example, the first logic unit 602A may include one or more metadata registers for buffering metadata from the first rank 604A, and the second logic unit 602B may include one or more metadata registers for buffering metadata from the second rank 604B. The first logic unit 602A may be connected to the first rank 604A via a first internal bus 610A, and the second logic unit 602B may be connected to the second rank 604B via a second internal bus 602B. Figure 6 The memory device, including the first die 608 and the second die 612, can be configured to operate in a system meta-mode, wherein a portion of the rank (such as a portion of each row of one or more memory arrays associated with the rank) is allocated for storing metadata, and a portion of the rank (such as a portion of each row of one or more memory arrays associated with the rank) is allocated for storing data. Therefore, as... Figure 6 As shown, associated data and metadata can be read from or written to each of the memory array ranks 604A-604B. In some aspects, in system meta mode, the output from the memory device including the first die 608 and the second die 612 can be 32 bits of data and 2 bits of metadata (e.g., ECC metadata).

[0068] In system meta-mode, during operation of the memory device including first die 608 and second die 612, one or more of the following may occur: metadata is transferred along with data; metadata and data are co-addressed in the same row; a metadata register is introduced to transfer metadata to / from a DDR row; and / or the metadata register is controlled by new RD_meta and WR_meta commands (which may also be referred to as READ META and WRITE META commands). The RD_meta command may, for example, be used to read metadata from the memory array associated with rank 604A-604B into the metadata register of logic units 602A-602B, and the WR_meta command may, for example, be used to write metadata from the metadata register of logic units 602A-602B into the memory array associated with rank 604A-604B. Therefore, as discussed herein, the memory device including the first die 608 and the second die 612 can be configured in system meta mode to store relevant data and metadata in the same row of the memory array of the memory device (such as the memory array associated with the first rank 604A or the memory array associated with the second rank 604B). Figure 7 An example of row access operations for operating a memory device comprising a first die 608 and a second die 612 in system meta-mode is shown. Figure 7This is a flowchart illustrating a method 700 for accessing a row in a memory device according to one or more aspects of this disclosure. At block 702, a column of a memory array (such as a memory array associated with a first rank) may be initiated. At block 704, it may be determined whether the next data access operation (such as the next read or write operation) includes metadata loaded into a metadata register of the memory device (such as the metadata register of logic 602A). If the metadata has not yet been loaded into the metadata register, at block 706, the memory device may read the metadata from the memory array into the metadata register. Then, at block 708, the memory device may perform the next data access operation. If the metadata has already been read into the metadata register, the memory device may continue from the determination in block 704 to the execution of the data access operation in block 708. At block 710, it may be determined whether the previous data access operation was the final data access operation for that row. If the previous data access operation 708 was not the final data access operation for that row, the method may repeat blocks 704, 706, and / or 708 for the remaining data access operations for that row. If the preceding data access operation 708 is the last data access operation, then in box 712, it can be determined whether all metadata registers associated with the memory array are clean. For example, a metadata register can be considered clean when its contents have been written to the memory array, and dirty when its contents have not yet been written to the memory array. If a metadata register is determined to be unclean in box 712, then in box 714, the next dirty metadata register can be written to the memory array. The method can then return to box 712, and boxes 712 and 714 can be repeated until it is determined that all metadata registers associated with the memory array are clean. When it is determined that all metadata registers are clean in box 712, the memory device can proceed to the precharge operation in box 716. Therefore, when data and metadata are stored in the same row of the memory array in system meta-mode, data and metadata can be read from the device's memory and / or written to the device's memory.

[0069] Storing metadata in the same memory device as the corresponding data can lead to performance degradation. The size of the metadata (e.g., in bits) is smaller than the corresponding data, resulting in some inefficiencies in accessing the metadata. For example, when the metadata size is smaller than the word size of the memory device, storing metadata may require reading the word to retrieve previously stored metadata, modifying a portion of the metadata word, and writing a combination of previously stored metadata and new metadata. Therefore, metadata write operations may also involve performing read operations and other processing. Thus, writing metadata to memory configured to operate in system meta mode (such as DDR memory) can significantly reduce available bandwidth. For example, a series of 64-bit write (WR 64B) operations at a random address in DDR memory can utilize close to 100% of the DDR bandwidth without metadata access. When accessing metadata, each WR 64B operation will require an additional 32-bit read (RD 32B) operation for the metadata, an operation to update the 4B metadata corresponding to the 64B data, and then a WR 32B operation to store the updated metadata back into the memory array. In system meta-mode, reading metadata in conjunction with data write commands is a function that stores metadata in the same row as the data. Therefore, the DDR bandwidth required to access both data and metadata stored in system meta-mode can be twice that required to access data stored separately from metadata. Furthermore, the READ-to-WRITE bus switch further reduces DDR access efficiency by approximately 20%. Therefore, when operating in system meta-mode, available DDR bandwidth can be reduced by as much as (and in some cases, even more than) 30%. Thus, in some cases, DDR bandwidth utilization when accessing metadata using regular READ and WRITE commands can be approximately 50% to 60%, compared to 70% to 80% when metadata is not accessed. When a single rank is accessed, using system meta-mode commands READ META and WRITE META to read and write metadata may not compensate for this problem because the internal bus (such as...) Figure 6 The bandwidth of the 610A or 610B may be limited in a similar way.

[0070] The inefficiencies that occur when the memory system is operating in system meta-mode (where data and metadata are stored in the same row or page of the memory system) can be reduced by interleaving operations between libraries of multi-rank memory devices (such as devices with two ranks (double-rank), four ranks (quadruple-rank), or eight ranks (octruple-rank)). For example, refer to Figure 6Because metadata access using the READ META or WRITE META commands does not transmit data on the external bus 606, but only on the internal buses 610A-610B, conflicts between metadata access and data access can be reduced or eliminated by accessing data in the first rank simultaneously with accessing metadata in the second rank. As an example, refer to... Figure 6 The data stored in the first rank 604A can be accessed by the logic unit 602A via the bus 610A, while the metadata stored in the second rank 604B can be accessed via the second bus 610B.

[0071] In an example interleaving operation, a first request and a second request may be interleaved between a first rank and a second rank in the memory device. Thus, as described herein, interleaving requests for different memory ranks may refer to initiating requests in an interleaved manner, wherein a request for the first rank is initiated, followed by a request for the second rank. In some aspects, a request for the first rank may be initiated after a request for the second rank is initiated. Therefore, requests for different ranks can be interleaved. In some aspects, such interleaving may include initiating a request for the second rank before completing a request for the first rank and / or initiating a second request for the first rank before completing a request for the second rank. Figure 8 The example describes an interleaved operation between ranks performed by a memory controller (such as the memory controller of a host device and / or the memory controller of a memory device). Figure 8This is a flowchart illustrating a method 800 of interleaving operations between rank of a memory device according to one or more aspects of this disclosure. At block 802, a memory controller may receive a first request for the memory device and a second request for the memory device. The first request may be, for example, a first data access request. Specifically, the first request may be, for example, a first request to read data and metadata from or write data and metadata to the first rank of the memory device (such as a first memory array associated with the first rank of the memory device). Similarly, the second request may be, for example, a second data access request, and may be a second request to read data and metadata from or write data and metadata to the second rank of the memory device (such as a second memory array associated with the second rank of the memory device). In some aspects, the memory controller may be configured to access the memory device in system meta-mode. In some aspects, the memory device may include multiple DRAM modules, and the memory controller may be configured to access the DRAM modules by storing data in a first portion of a memory location and storing metadata in a second portion of the memory location. In some aspects, the metadata may include ECC metadata. In some aspects, the memory device may include LPDDR memory modules, and the memory controller may be configured to communicate with the LPDDR memory modules. In some respects, the memory controller can be connected to a write buffer to allow efficient scheduling of write requests without conflicting with the next request in the same rank.

[0072] In block 804, the memory controller may execute a first request in a first rank of the memory device during a first time period. The first time period may, for example, include a first data access portion and a first metadata access portion. For example, in response to the first request to access data and metadata stored in the first rank of the memory device, the memory device may access the data stored in the first rank of the memory device during a first portion of the first time period and access the metadata stored in the first rank of the memory device during a second portion of the first time period.

[0073] In block 806, the memory controller may execute a second request in a second rank of the memory device during a second time period. The second time period may, for example, include a second data access portion and a second metadata access portion. For example, in response to a second request to access data and metadata stored in the second rank of the memory device, the memory device may access data stored in the first rank of the memory device during a first portion of the second time period and access metadata stored in the first rank of the memory device during a second portion of the second time period. When executing the first request and the second request, the memory controller may interleave the first request and the second request between the first rank and the second rank. For example, to interleave the first request and the second request, the memory controller may execute one or more operations according to the first request in parallel with executing one or more operations according to the second request. As a particular example, the execution of the second request by the memory controller may be timed such that at least one of the following occurs: (1) the first data access portion of the first time period and the second metadata access portion of the second time period at least partially overlap, or (2) the first metadata access portion of the first time period and the second data access portion of the second time period at least partially overlap. Therefore, the memory controller can execute the first request and the second request, wherein metadata access at one memory rank is performed in parallel with data access at another memory rank.

[0074] In some aspects, the first request may include a write operation, and the second request may include a read operation. A first data access portion of the first request may include a first data write in a first rank, and a second metadata access portion may include a first metadata read in a second rank. The first and second requests may be timed by a memory controller such that the first data write in the first rank and the first metadata read in the second rank at least partially overlap in time. In some aspects, a first time period during which the first request is executed may further include a third metadata access portion, which includes the first metadata write operation in the first rank. In some aspects, therefore, the first request may include a request for a first metadata read operation in the first rank, a request for a first data read or write operation in the first rank, and a request for a first metadata write operation in the first rank. The first metadata write operation in the first rank may at least partially overlap with the second data access portion of the second time period in the second rank. In some aspects, executing the first request in the first rank may include opening a minimum number of libraries in the first rank for executing the first request.

[0075] In some aspects, the memory controller may execute a third request in a first rank of the memory device during a third time period following a first time period. Executing a first request in the first rank may include accessing a first set of libraries in the first rank, and executing a third request in the first rank may include accessing a second set of libraries in the first rank that is mutually exclusive with the first set of libraries. Metadata access operations (such as metadata read or metadata write operations) in a rank of memory may overlap in time with any metadata or data access operations (such as metadata or data read or metadata or data write operations) in another rank of memory.

[0076] Figure 9 This is a block diagram illustrating interleaved operations involving data and metadata between ranks of a memory device according to one or more aspects of this disclosure. A first portion of a series of interleaved operations 950 may include a first time period 910, a second time period 920, and a third time period 930, along with other time periods for interleaved operations of reading and writing data and metadata. The first time period 910 may include a first metadata access portion 912 for performing a first metadata access operation, a first data access portion 914 for performing a first data access operation, and another metadata access portion 916 for performing another metadata access operation. The second time period 920 may include a second metadata access portion 922 for performing a second metadata access operation and a second data access portion 924 for performing a second data access operation. The third time period 930 may include a third metadata access portion 932 for performing a third metadata access operation and a third data access portion 934 for performing a third data access operation. Operations in staggered time periods 910, 920, and 930 can be performed by arranging operations such that the operation in the first time period 910 accesses the first rank (RANK0), the operation in the second time period 920 accesses the second rank (RANK1), and the operation in the third time period 930 accesses the first rank (RANK0). In this example, the first time period 910 corresponding to the write operation may include a first portion for reading metadata in section 912, a second portion for writing data in section 914, and a third portion for writing metadata corresponding to the read metadata and the written data in section 916. In this example, the second time period 920 corresponding to the read operation may include a first portion for reading metadata in section 922 and a second portion for reading data in section 924.

[0077] Interleaving between ranks of memory devices can be scheduled to allow metadata operations to at least partially overlap with data operations within the same memory device by performing overlapping operations on different ranks. Operations in the second time period 920 can be scheduled such that data access portions 914 and metadata access portions 916 of the first time period 910 at least partially overlap with metadata access portions 922 of the second time period 920. Although the example interleaving between time periods 910 and 920 is between a write operation on RANK 0 and a read operation on RANK 1, the interleaving can be applied to other operation arrangements. For example, when the memory controller is scheduling two read operations as the second time period 920 and the third time period 930, the data access portion 924 of the second time period 920 can overlap with the metadata access portion 916 of the first time period 910 and the metadata access portion 932 of the third time period 930. The memory controller 130 can also schedule operations on the same rank (such as operations 910 and 930) such that pages initiated for each of the operations between consecutive operations on a single rank are mutually exclusive. When time periods 910 and 930 are sufficiently close in time, scheduling of mutexed pages on a single rank can be performed, ensuring that pages accessed in the first time period 910 cannot be closed before pages accessed in the third time period 930 are opened. This is particularly important when the first operation is a set of write operations and the second operation is a set of read operations. The memory controller can be configured to avoid scheduling write operations on libraries that can be used by a subsequent set of read operations. The memory controller's write scheduler can predictively schedule such read and write operations using write buffers organized into 32 queues, making information about subsequent operations available to the memory controller in the corresponding library. Thus, the memory controller can determine which libraries are likely to experience upcoming read operations within a specific time threshold and avoid scheduling such libraries for write operations that would conflict with upcoming read operations. In scheduling interleaved read and write operations, when performing a read operation on data, the memory controller can be configured to schedule a command to read metadata before the command to read the associated data, although such commands can be scheduled simultaneously. Similarly, when performing a write operation on data, the memory controller can be configured to schedule a command to read metadata before the command to write the data. Furthermore, when performing a write operation on data, the memory controller can be configured to schedule a command to write associated metadata after the command to write data. However, in some cases, the memory controller can schedule commands to write data and commands to write metadata to occur simultaneously. For example... Figure 9 As shown, the transition time between write data operation and read data operation can be called tW2R_DR, the transition time between read data operation and write data operation can be called tR2W_DR, and the transition time between read data operation and subsequent read data operation can be called tR2R_DR.

[0078] In some implementations, rank selection bit hashing can be performed to distribute incoming DDR operations across two or more rank segments, thereby further enhancing efficiency. Interleaving DRAM access batches between rank segments can benefit high DDR utilization in situations where metadata access is present, such as when the memory is configured to operate in system meta-mode. The memory controller may include a queue of operations waiting to be scheduled to DRAM. The memory controller may schedule read operation batches and write operation batches. These batches should be scheduled alternately across different rank segments. The transaction queue may contain transactions for multiple rank segments (such as for two rank segments in a device with two memory rank segments) to allow the memory controller to select the batch of operations to be performed on a different rank segment after scheduling a batch of operations in the first rank. As an example, the bit used to select the rank may be positioned directly below the row bit, such as bit 15 in a dual-rank DRAM system, as shown below the row bit. Figure 10 The first part 1002 and the second part 1004 of the physical address bit assignment mapping are shown. As another example, the rank bit and row bit can be hashed to further randomize the distribution of cross-rank access operations, such as... Figures 11A to 11B The first part 1100 and the second part 1110 of the hash table used for address mapping are shown. For example, as Figures 11A to 11B As shown, the poly37 hash can be used from GF(2): x 5 + x 2 The hash matrix is ​​derived from the primitive polynomial of +1.

[0079] In some implementations, write operations can be accumulated in a buffer and subsequently evicted to the memory controller in DRAM valid order. Figures 12A to 12B Example block diagrams 1200 and 1220 are shown for a write buffer and a write scheduler for efficient scheduling of write operations. Write buffer 1202 may, for example, be a partition of a system cache organized as a set of queues, with one queue per rank per library. For example, a write buffer for an LPDDR5 or LPDDR6 dual-rank system may include 32 queues, such as... Figure 12AThe write buffer 1202 is shown. Write transactions can be received by the write buffer 1202 and placed in a queue. The write scheduler 1204 can schedule write operations from the write buffer 1202 by, for example, selecting a batch of write operations with a different rank than the previous batch; minimizing the number of libraries initiated during a batch of write operations; and formulating a preference for write operations to libraries that do not conflict with pending read operations. Using such organization, the write scheduler 1204 can simultaneously observe candidate write operations in each library and can select write transactions that can be scheduled with maximum efficiency in the desired rank without penalizing read operations already existing in the memory controller. The write scheduler 1204 can send one or more selected buffered write commands to the memory controller of the memory device, such as the memory controller of a DRAM device.

[0080] Wireless communication devices may include at least such as Figure 1 and Figure 2 The illustrated memory system is configured to receive and output data, including ECC or other metadata, from a memory array and to interleave operations at different ranks of the memory device including the memory array to reduce the overhead associated with storing metadata along with the data in the memory array. A memory system according to any aspect disclosed herein may be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, or avionics systems.

[0081] In one or more aspects, the techniques for memory storage and retrieval may include additional aspects, such as any single aspect or any combination of aspects described below, or related to one or more other programs or devices described elsewhere herein. In a first aspect, supporting data operations may include an apparatus configured to perform operations including: receiving a first request for a memory device and a second request for the memory device by one or more memory controllers; executing the first request by one or more memory controllers in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; and executing the second request by one or more memory controllers in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank.

[0082] Additionally, the apparatus may perform or operate according to one or more aspects described below. In some embodiments, the apparatus includes a wireless device, such as a UE. In some embodiments, the apparatus includes a remote server (such as a cloud-based computing solution) that receives image data, processes it, and determines output image frames. In some embodiments, the apparatus may include at least one processor and memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the apparatus. In some other embodiments, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon, and the program code may be executable by a computer to cause the computer to perform the operations described herein with reference to the apparatus. In some embodiments, the apparatus may include one or more components configured to perform the operations described herein. In some embodiments, a method of wireless communication may include one or more operations described herein with reference to the apparatus. In some embodiments, the apparatus may include one or more memory controllers configured to perform the operations described herein with respect to the apparatus. In some embodiments, the apparatus may include a host device configured to communicate with a memory module via a channel. The host device may include one or more memory controllers coupled to the channel and configured to perform the operations described herein with respect to the device.

[0083] In the second aspect, in conjunction with the first aspect, the execution of the second request by one or more memory controllers is timed such that at least one of the following occurs: (1) the first data access portion overlaps at least partially with the second metadata access portion, or (2) the first metadata access portion overlaps at least partially with the second data access portion.

[0084] In the third aspect, in conjunction with one or more of the first or second aspects, the first request includes a write operation and the second request includes a read operation, wherein the first data access portion of the first request includes a first data write in a first rank and the second metadata access portion includes a first metadata read in a second rank, wherein the first data write in the first rank and the first metadata read in the second rank at least partially overlap.

[0085] In the fourth aspect, in conjunction with one or more of the first to third aspects, the first time period also includes a third metadata access portion, which includes a first metadata write in the first rank, and the first metadata write in the first rank at least partially overlaps with the second data access portion of the second time period in the second rank.

[0086] In the fifth aspect, in combination with one or more of the first to fourth aspects, performing the first request in the first rank includes opening a minimum number of libraries in the first rank for performing the first request.

[0087] In a sixth aspect, in conjunction with one or more of the first to fifth aspects, the apparatus is further configured to perform an operation comprising: executing a third request in a first rank of the memory device by one or more memory controllers during a third time period following a first time period, wherein executing the first request in the first rank comprises accessing a first set of libraries in the first rank, and executing the third request in the first rank comprises accessing a second set of libraries mutually exclusive with the first set of libraries.

[0088] In the seventh aspect, in conjunction with one or more of the first to sixth aspects, one or more memory controllers are configured to access memory devices in system meta-mode.

[0089] In the eighth aspect, in conjunction with one or more of the first to seventh aspects, the memory device includes a plurality of dynamic random access memory (DRAM) modules, and the one or more memory controllers are configured to access the DRAM modules by storing data in a first portion of the memory location and storing metadata in a second portion of the memory location.

[0090] In the ninth aspect, in combination with one or more of the first through eighth aspects, the metadata includes error correction codes (ECC).

[0091] In the tenth aspect, in conjunction with one or more of the first to ninth aspects, one or more memory controllers are configured to communicate with a low-power double data rate (LPDDR) memory module.

[0092] In the description of the embodiments herein, numerous specific details (such as examples of specific components, circuits, and processes) are set forth to provide a thorough understanding of this disclosure. As used herein, the term "coupled" means a direct connection or a connection via one or more intermediate components or circuits. Additionally, specific terminology is set forth in the following description and for purposes of explanation in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that practicing the teachings disclosed herein may not require these specific details. In other instances, known circuits and devices are illustrated in block diagram form to avoid obscuring the teachings of this disclosure.

[0093] Certain portions of the following detailed description are presented using other symbolic representations of procedures, logic blocks, processes, and data bit operations within computer memory. In this disclosure, procedures, logic blocks, processes, etc., are conceived as a self-consistent sequence of steps or instructions that lead to a desired result. These steps are those that require physical manipulation of physical quantities. Although not strictly necessary, these physical quantities typically take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated within a computer system.

[0094] In the accompanying drawings, a single block can be described as performing one or more functions. The one or more functions performed by this block can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps are described below in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Moreover, the example device may include components other than those shown, including well-known components such as processors, memory, etc.

[0095] Unless otherwise specifically stated, it will be apparent from the following discussion that, throughout this application, the use of terms such as “access,” “receive,” “transmit,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” “set,” “generate,” etc., refers to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system.

[0096] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some parts of this disclosure. Although the description and examples herein use the term "device" to describe various aspects of this disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or part of a device for performing the described operations.

[0097] Certain components in a device or apparatus described as “parts for access,” “parts for receiving,” “parts for transmitting,” “parts for using,” “parts for selecting,” “parts for determining,” “parts for normalizing,” “parts for multiplying,” or other similarly named terms referring to one or more operations on data (such as image data) may refer to processing circuitry (e.g., application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the described functions by means of hardware, software, or a combination of hardware configured by software.

[0098] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0099] This article is about at least Figure 1 and Figure 2 The components, functional blocks, and modules described include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, hardware code, etc., or any combination thereof. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other terms. Furthermore, the features discussed herein can be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0100] Those skilled in the art will recognize that one or more blocks (or operations) described with reference to the accompanying drawings included in this description may be combined with one or more blocks (or operations) described with reference to another drawing. For example, Figures 3A to 3B One or more boxes (or operations) can be connected with Figure 1 or Figure 2 A combination of one or more boxes (or operations). As another example, Figure 7 or Figure 8 One or more boxes (or operations) can be connected with Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A to 5B ,or Figure 6 A combination of one or more boxes (or operations).

[0101] Those skilled in the art will also recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein is merely illustrative, and that components, methods, or interactions of various aspects of this disclosure may be combined or performed in ways other than those illustrated and described herein.

[0102] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the specific implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0103] Hardware and data processing means for implementing the various exemplary logic units, logic blocks, modules, and circuits described herein can be implemented or executed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic units, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some embodiments, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processes and methods may be performed by circuitry specific to a given function.

[0104] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware, including the structures disclosed in this specification and their structural equivalents or any combination thereof. Specific implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0105] If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that can reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any medium that can be implemented to transfer a computer program from one location to another. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible to a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operation of a method or algorithm may reside as a set of code and instructions or any combination of code and instructions on a machine-readable medium and a computer-readable medium that may be incorporated into a computer program product.

[0106] Various modifications to the specific embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles disclosed herein, and the novel features thereof.

[0107] Additionally, those skilled in the art will readily recognize that, for the convenience of describing the accompanying drawings, contrasting terms such as “upper” and “lower” or “front” and “back” or “top” and “bottom” or “forward” and “backward” are sometimes used, indicating relative positions on a correctly oriented page corresponding to the orientation of the drawings, and may not reflect the correct orientation of any device as implemented.

[0108] As used herein, the term "coupled to," in various tenses of the verb "couple," can mean that element A is directly connected to element B, or that other elements can be connected between elements A and B (i.e., element A and element B are indirectly connected) to perform certain intended functions. In the context of electrical components, the term "coupled to" can also be used herein to mean that conductors, traces, or other conductive materials are used to electrically connect elements A and B (and any components electrically connected between them). In some examples, the term "coupled to" means the transfer of electrical energy between elements A and B to perform certain intended functions.

[0109] In some examples, the term "electrical connection" means having current or being configured to have current flowing between components A and B. For example, in addition to wires, traces, or other conductive materials and components, components A and B may also be connected via resistors, transistors, or inductors. Furthermore, for radio frequency functions, components A and B may be "electrically connected" via capacitors.

[0110] Certain features described in this specification in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even originally claimed in this way, one or more features from the claimed combination may be removed from that combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0111] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring such operations to be performed in the indicated specific order or sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the figures may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be combined with the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any illustrated operation. In some contexts, multitasking and parallel processing are advantageous. Moreover, the separation of the various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, some other embodiments also fall within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result.

[0112] As used herein (including the claims), the term "or" in a list of two or more items means that any one of the listed items may be used alone, or any combination of two or more listed items may be used. For example, if a composition is described as containing component A, B, or C, the composition may contain A alone; B alone; C alone; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein (including the claims), "or" in a list of items beginning with "at least one of" indicates a separate list, such that a list such as "at least one of A, B, or C" refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination of any of these items.

[0113] As will be understood by those skilled in the art, the term “substantially” is defined as most, but not necessarily all, of the specified content (and includes the specified content; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any specific implementation of the disclosure, the term “substantially” may be used in place of “[percentage]” of the specified content, where percentage includes 0.1%, 1%, 5%, or 10%.

[0114] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: One or more memory controllers, the one or more memory controllers being configured to perform operations including the following: Receive a first request for the memory device and a second request for the memory device; The first request is executed in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; as well as The second request is executed in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion. Executing the first request in the first rank and executing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank.

2. The apparatus of claim 1, wherein the execution of the second request by the one or more memory controllers is timed such that at least one of the following occurs: (1) the first data access portion and the second metadata access portion at least partially overlap, or (2) the first metadata access portion and the second data access portion at least partially overlap.

3. The apparatus of claim 2, wherein the first request includes a write operation and the second request includes a read operation, wherein the first data access portion of the first request includes a first data write in the first rank and the second metadata access portion includes a first metadata read in the second rank, wherein the first data write in the first rank and the first metadata read in the second rank at least partially overlap.

4. The apparatus of claim 3, wherein the first time period further includes a third metadata access portion, the third metadata access portion including a first metadata write in the first rank, and wherein the first metadata write in the first rank at least partially overlaps with the second data access portion of the second time period in the second rank.

5. The apparatus of claim 3, wherein executing the first request in the first rank comprises opening a minimum number of libraries in the first rank for executing the first request.

6. The apparatus of claim 3, further comprising the execution of a third request by the one or more memory controllers in a first rank of the memory device during a third time period following the first time period, wherein executing the first request in the first rank includes accessing a first set of libraries in the first rank, and executing the third request in the first rank includes accessing a second set of libraries mutually exclusive with the first set of libraries.

7. The apparatus of claim 1, wherein the one or more memory controllers are configured to access the memory device in system meta-mode.

8. The apparatus of claim 1, wherein the memory device comprises a plurality of dynamic random access memory (DRAM) modules, wherein the one or more memory controllers are configured to access the DRAM modules by storing data in a first portion of a memory location and storing metadata in a second portion of the memory location.

9. The apparatus of claim 1, wherein the metadata includes error correction codes (ECC).

10. The apparatus of claim 1, wherein the one or more memory controllers are configured to communicate with a low-power double data rate (LPDDR) memory module.

11. A method, the method comprising: One or more memory controllers receive a first request for a memory device and a second request for the memory device; The first request is executed by one or more memory controllers in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; as well as The second request is executed by one or more memory controllers in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion. Executing the first request in the first rank and executing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank.

12. The method of claim 11, wherein the execution of the second request by the one or more memory controllers is timed such that at least one of the following occurs: (1) the first data access portion overlaps at least partially with the second metadata access portion, or (2) the first metadata access portion overlaps at least partially with the second data access portion.

13. The method of claim 12, wherein the first request includes a write operation and the second request includes a read operation, and wherein the first data access portion of the first request includes a first data write in the first rank and the second metadata access portion includes a first metadata read in the second rank, wherein the first data write in the first rank and the first metadata read in the second rank at least partially overlap.

14. The method of claim 13, wherein the first time period further includes a third metadata access portion, the third metadata access portion including a first metadata write in the first rank, and wherein the first metadata write in the first rank at least partially overlaps with the second data access portion of the second time period in the second rank.

15. The method of claim 13, wherein executing the first request in the first rank comprises opening a minimum number of libraries in the first rank for executing the first request.

16. The method of claim 13, further comprising executing a third request by the one or more memory controllers in a first rank of the memory device during a third time period following the first time period, wherein executing the first request in the first rank includes accessing a first set of libraries in the first rank, and executing the third request in the first rank includes accessing a second set of libraries mutually exclusive with the first set of libraries.

17. The method of claim 11, wherein the one or more memory controllers are configured to access the memory device in system meta-mode.

18. The method of claim 11, wherein the memory device comprises a plurality of dynamic random access memory (DRAM) modules, wherein the one or more memory controllers are configured to access the DRAM modules by storing data in a first portion of a memory location and storing metadata in a second portion of the memory location.

19. The method of claim 11, wherein the metadata includes error correction codes (ECC).

20. The method of claim 11, wherein the one or more memory controllers are configured to communicate with a low-power double data rate (LPDDR) memory module.

21. An apparatus comprising: The host device is configured to communicate with the memory module via a channel. The host device includes one or more memory controllers coupled to the channel, the one or more memory controllers being configured to perform operations including: Receive a first request for the memory device and a second request for the memory device; The first request is executed in a first rank of the memory device during a first time period, wherein the first time period includes a first data access portion and a first metadata access portion; as well as The second request is executed in a second rank of the memory device during a second time period, wherein the second time period includes a second data access portion and a second metadata access portion. Executing the first request in the first rank and executing the second request in the second rank includes interleaving the first request and the second request between the first rank and the second rank.

22. The apparatus of claim 21, wherein the execution of the second request by the one or more memory controllers is timed such that at least one of the following occurs: (1) the first data access portion and the second metadata access portion at least partially overlap, or (2) the first metadata access portion and the second data access portion at least partially overlap.

23. The apparatus of claim 22, wherein the first request includes a write operation and the second request includes a read operation, wherein the first data access portion of the first request includes a first data write in the first rank and the second metadata access portion includes a first metadata read in the second rank, wherein the first data write in the first rank and the first metadata read in the second rank at least partially overlap.

24. The apparatus of claim 23, wherein the first time period further includes a third metadata access portion, the third metadata access portion including a first metadata write in the first rank, and wherein the first metadata write in the first rank at least partially overlaps with the second data access portion of the second time period in the second rank.

25. The apparatus of claim 23, wherein executing the first request in the first rank comprises opening a minimum number of libraries in the first rank for executing the first request.

26. The apparatus of claim 23, further comprising the execution of a third request by the one or more memory controllers in a first rank of the memory device during a third time period following the first time period, wherein executing the first request in the first rank includes accessing a first set of libraries in the first rank, and executing the third request in the first rank includes accessing a second set of libraries mutually exclusive with the first set of libraries.

27. The apparatus of claim 21, wherein the one or more memory controllers are configured to access the memory device in system meta-mode.

28. The apparatus of claim 21, wherein the memory device comprises a plurality of dynamic random access memory (DRAM) modules, wherein the one or more memory controllers are configured to access the DRAM modules by storing data in a first portion of a memory location and storing metadata in a second portion of the memory location.

29. The apparatus of claim 21, wherein the metadata includes error correction codes (ECC).

30. The apparatus of claim 21, wherein the one or more memory controllers are configured to communicate with a low-power double data rate (LPDDR) memory module.

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