Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device. The display substrate comprises a display area and a first frame area, the display area comprises a plurality of sub-pixels and data lines in a plurality of data signal lines, the first frame area comprises a bending area, and in the bending area, in the first direction, data connecting lines of the data signal lines and a plurality of first power supply connecting structures are arranged at intervals. And at least one data connecting line is arranged between two adjacent first power supply connecting structures. According to the technical scheme provided by the embodiment of the invention, the technical problem of display screen splitting caused by abrupt change of the resistance of the signal wiring in the bending area of the display substrate can be avoided.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, display substrates suffer from a technical problem where large resistance differences between signal traces lead to screen splitting. Summary of the Invention

[0004] The problem to be solved by the embodiments of this disclosure is to provide a display substrate and a display device to solve the technical problem of large resistance differences between signal traces in existing display substrates leading to screen splitting.

[0005] To address the aforementioned technical problems, in a first aspect, embodiments of this disclosure provide a display substrate, including a display area and a first border area located on one side of the display area, wherein the first border area is provided with a bending region;

[0006] Multiple sub-pixels are located in the display area;

[0007] Multiple data signal lines are located in the display area and the first border area, and are electrically connected to the multiple sub-pixels. The multiple data signal lines are configured to provide data signals to the multiple sub-pixels. The data signal lines include data lines and data connection lines. The data lines are located in the display area, and the data connection lines are located in the first border area and are electrically connected to the corresponding data lines. In the same data signal line, at least a portion of the data connection line is located in the bending area.

[0008] Multiple first power connection structures are located in the bending area. The multiple first power connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide a first power signal to the multiple sub-pixels. The first direction intersects the second direction.

[0009] In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals with the plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures.

[0010] In an exemplary embodiment, the plurality of first power connection structures are arranged at equal intervals along the first direction in the bending region.

[0011] In an exemplary embodiment, in the bending area, along the first direction, a plurality of first distances between a plurality of data connection lines are consistent, wherein the first distance is the distance between two adjacent data connection lines.

[0012] In an exemplary embodiment, in the bending region, along the first direction, the plurality of data connection lines between two adjacent first power connection structures are arranged at equal intervals.

[0013] In an exemplary embodiment, in the bending region, along the first direction, the first distance is greater than or equal to a second distance, where the second distance is the distance between the first power connection structure and the adjacent data connection line.

[0014] In an exemplary embodiment, in the bending region, along the first direction, the ratio of the first distance to the second distance is greater than or equal to 1.5.

[0015] In an exemplary embodiment, in the bending region, along the first direction, the dimensions of the first power connection structure are consistent with the dimensions of the data connection line.

[0016] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the display substrate includes a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer disposed sequentially on the substrate. At least a portion of the data connection line and the plurality of first power connection structures are located on the fourth conductive layer.

[0017] In an exemplary embodiment, within a plane parallel to the display substrate, the first border region further includes a first fan-out area, which is located between the display area and the bending area in the second direction; the display substrate further includes a first power connection line, and the data connection line includes a first data connection line and a second data connection line. In the same data signal line, the data line is electrically connected to the second data connection line through the first data connection line, wherein:

[0018] The first power connection line is located in the first fan-out area. The first power connection line extends along the first direction and is electrically connected to the plurality of first power connection structures. The plurality of first power connection structures provide a first power signal to the plurality of sub-pixels through the first power connection line.

[0019] The first data connection line is located in the first fan-out area. Among the plurality of first data connection lines, at least a portion is located in the first conductive layer and at least a portion is located in the second conductive layer. The first data connection lines located in the first conductive layer and the first data connection lines located in the second conductive layer are arranged alternately.

[0020] The second data connection line is located in the bending area. In a direction perpendicular to the plane of the display substrate, the second data connection line is located in the fourth conductive layer, and at least a portion of the data connection line includes the second data connection line.

[0021] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the first power connection line is located in the fourth conductive layer, and the first power connection line is directly connected to the plurality of first power connection structures; in the same data signal line, the first data connection line and the second data connection line are electrically connected through vias, and the first data connection line and the data line are electrically connected through vias.

[0022] In an exemplary embodiment, within a plane parallel to the display substrate, the first border region further includes a second fan-out region. In the second direction, the second fan-out region is located on the side of the bending region away from the display region. The display substrate also includes a first power line, and the data connection line further includes a third data connection line. Within the same data connection line, the first data connection line is electrically connected to the third data connection line via the second data connection line; wherein:

[0023] The first power line is located in the second fan-out area and is connected to the plurality of first power connection structures;

[0024] The third data connection line is located in the second fan-out area. Among the plurality of third data connection lines, at least a portion is located in the first conductive layer and at least a portion is located in the second conductive layer. The third data connection lines located in the first conductive layer and the third data connection lines located in the second conductive layer are arranged alternately.

[0025] In an exemplary embodiment, the first power line is located in the fourth conductive layer in a direction perpendicular to the plane of the display substrate, and the first power line is directly connected to the plurality of first power connection structures; in the same data signal line, the second data connection line and the third data connection line are electrically connected through vias.

[0026] In an exemplary embodiment, in a plane parallel to the display substrate, the first border area further includes a bonding area. In the second direction, the bonding area is located on the side of the second fan-out area away from the display area. The bonding area is provided with a first power pad and a driving circuit. The third data connection line is electrically connected to the driving circuit. The first power line extends to the bonding area and is electrically connected to the first power pad.

[0027] Secondly, this disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0028] The display substrate and display device provided in this disclosure include a display area and a first border area located on one side of the display area. The display area includes multiple sub-pixels and data lines among multiple data signal lines. The first border area includes a bending area. In the bending area, along a first direction, data connection lines of multiple data signal lines and multiple first power connection structures are arranged at intervals, and at least one data connection line is provided between two adjacent first power connection structures. The display substrate provided in this disclosure can avoid the technical problem of display screen splitting caused by sudden changes in resistance (large resistance step difference) of signal traces in the bending area of ​​the display substrate.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0031] Figure 1 The diagram shown is a structural schematic of a display device;

[0032] Figure 2 The diagram shown is a schematic diagram of the structure of a display substrate;

[0033] Figure 3 The diagram shown is an enlarged view of the first border area.

[0034] Figure 4 The above is a schematic diagram of the structure of a display substrate;

[0035] Figure 5 The diagram shown is a schematic diagram of the structure of a display substrate;

[0036] Figure 6 The figure shown is a schematic diagram of the resistance curve of a data signal line;

[0037] Figure 7 The diagram shown is a structural schematic of a display substrate provided in an embodiment of this disclosure;

[0038] Figure 8a As shown Figure 7 A magnified structural diagram of position M1 in the middle;

[0039] Figure 8b As shown Figure 7 A magnified structural diagram of the M2 position in the middle;

[0040] Figure 8c As shown Figure 7 A magnified structural diagram of position M1 in the middle;

[0041] Figure 9 The diagram shown is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0042] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The embodiments of this disclosure can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0043] In the accompanying drawings, the size of constituent elements, the thickness of layers, or areas may sometimes be exaggerated for clarity. Therefore, any implementation of this disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and any implementation of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, rather than to limit the quantity.

[0045] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships when describing the positional relationships of constituent elements with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of embodiments and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described herein can be appropriately replaced as appropriate.

[0046] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0047] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0048] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged. In this disclosure, the control electrode can be the gate electrode.

[0049] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0050] Figure 1The diagram shows a schematic of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0051] Figure 2The diagram shown is a structural schematic of a display panel. Figure 2 As shown, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (bottom border) B1 and a second border area (top border) B2 arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a first edge (bottom edge) and a second edge (top edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixels may include pixel driving circuits and light-emitting devices. The first border area B1 may include a bonding circuit that connects signal lines to an external driving device. The third border area B3 and the fourth border area B4 may include gate driving circuits and a second power supply line VSS that transmits voltage signals to the plurality of sub-pixels.

[0052] Figure 3 The diagram shows a planar structural schematic of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along a direction away from the display area AA. The bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along a direction away from the bending area 12 along the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines configured to connect to the display area AA in a fan-out routing manner. The first power line is configured to connect to the display area AA as a high-voltage power line (VDD), and the second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA (e.g., Figure 4(As shown). The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may be provided with an integrated circuit (IC) 20, configured to be connected to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to be bonded to the flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with pads including multiple pins, and the flexible printed circuit 30 may be bonded to the pads.

[0053] In an exemplary implementation, such as Figure 4 As shown, the bending area 12 can reverse the surface of the bonding area 14, that is, the upward-facing surface of the bonding area 14 can be transformed to face downwards by bending the bending area 12. In an exemplary embodiment, when the bending area 12 is bent, the bonding area 14 can overlap with the display area AA in the thickness direction of the display panel.

[0054] In exemplary embodiments, for large-size display substrates, multiple data driver ICs (also known as driver ICs or driver integrated circuits) and multiple FPCs can be provided. The multiple FPCs are respectively bound to and connected to the multiple data driver ICs. For example, four data driver ICs can be provided, each bound to one of the four FPCs. This disclosure is not limited to four ICs and four FPCs; for example, two data driver ICs and two FPCs can be provided. For small-size display substrates, one or two data driver ICs can be provided. In this disclosure, the number of data driver ICs and FPCs can be set according to the size and functional requirements of the display substrate, and this disclosure does not limit this number.

[0055] In an exemplary implementation, such as Figure 5The diagram shows a schematic of a display substrate. The display area AA can be provided with multiple scan signal lines SL and multiple data signal lines D, including data lines DL0 (the same data signal line D can include data line D0 located in the display area AA and data connection line DL located in the first border area B1). The multiple scan signal lines SL can extend along the first direction X and be arranged at intervals along the second direction Y. The multiple data lines DL0 can extend along the second direction Y and be arranged at intervals along the first direction X. Each scan signal line SL can be electrically connected to multiple sub-pixels Pxij in a row of sub-pixels. Each data line DL0 can be electrically connected to multiple sub-pixels in a column of sub-pixels. The second border area B2 and the third border area B3 can be provided with multiple gate driving circuits GOA (GOA is short for Gate Driver on Array) and gate driving circuit signal lines (GOA signal lines). The GOA signal lines can include clock signal lines (e.g., CK signal lines, CB signal lines, STV signal lines, etc.). The gate driving circuit GOA is configured to be electrically connected to the corresponding scan signal line SL and provide scan signals to the corresponding scan signal line SL.The data connection lines DL in the data signal line D may include a first data connection line DL1, a second data connection line DL2, and a third data connection line DL3. The first fan-out region 11 may include multiple first data connection lines DL1 and a first power connection line PL11. The multiple first data connection lines DL1 may be arranged at intervals along the first direction X. The first power connection line PL11 and the multiple first data connection lines DL1 are located in different conductive layers. The bending region 12 may include multiple second data connection lines DL2, a first power connection structure PL12, and a second power connection structure PL22. The multiple second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 are arranged at intervals along the first direction X. The second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 in the bending region 12 are usually located in the same conductive layer. Different signal lines need to be arranged at intervals to avoid signal short circuits. The second fan-out region 13 may include... The circuit includes multiple third data connection lines DL3, a first power line VDD, and a second power line VSS. The first power line VDD and the second power line VSS can be located on the same conductive layer, while the third data connection line DL3 and the first power line VDD are located on different conductive layers. The driver chip area 141 can be provided with a driver circuit 20, the third fan-out area 142 can be provided with multiple bonding leads 201, and the bonding electrode area 143 can be provided with multiple pads. The multiple pads can include a first power pad 51, a second power pad 52, a driver pad 53, a first gate driver circuit pad 541, and a second gate driver pad 542. The driver circuit 20 can be electrically connected to the driver pad 53 in the bonding electrode area 143 through the bonding leads 201. The multiple pads can be bonded to the flexible circuit board 30. The first power line VDD can be connected to the first power pad 51, the second power line VSS can be connected to the second power pad 52, and the driver pad 53 can be electrically connected to the corresponding bonding lead 201. In an exemplary embodiment, the data line DL0, the first data connection line DL1, the second data connection line DL2, and the third data connection line DL3 can be connected one-to-one, and the first power line VDD can be electrically connected to the first power connection line PL11 through the first power connection structure PL12.

[0056] In an exemplary implementation, such as Figure 5As shown, the gate drive circuit signal lines may include a first gate drive circuit signal line 41 and a second gate drive circuit signal line 42. The first gate drive circuit signal line 41 extends from the third frame region B3 to the first frame region B1 and is connected to the first gate drive pad 541 and the gate drive circuit GOA located in the third frame region B3. The second gate drive circuit signal line 42 extends from the fourth frame region B4 to the first frame region B1 and is connected to the second gate drive pad 542 and the gate drive circuit GOA located in the fourth frame region B4. The gate drive circuit GOA may include a first gate drive circuit GOA1 disposed in the third frame region B3 and a second gate drive circuit GOA2 disposed in the fourth frame region B4. The first gate drive circuit GOA1 is configured to be electrically connected to the first gate drive pad 541 through the first gate drive circuit signal line 41, and the second gate drive circuit GOA2 is configured to be electrically connected to the second gate drive pad 542 through the second gate drive circuit signal line 42.

[0057] In an exemplary implementation, such as Figure 5 As shown, the second data connection line DL2 in the bending region 12 and the first power connection structure PL12 are located in the same conductive layer. In the bending region 12, the size of the second data connection line DL2 is much smaller than that of the first power connection structure PL12. The first power connection structure PL12 is a block structure, which causes the lengths of the two first data connection lines DL1 located on both sides of the first power connection structure PL12 to be different in the first direction X. For example, in order to avoid the first power connection structure PL12 in the bending region 12, the routing path of the first data connection line DL12 changes, resulting in the length of the first data connection line DL12 being greater than the length of the first data connection line DL11. Therefore, the resistance of the first data connection line DL12 is greater than that of the first data connection line DL11. Figure 6 The figure shows the resistance variation curve of the data signal line D. Figure 6 It can be seen that there are two large resistance abrupt changes (the resistance has a large step difference) on multiple data signal lines D. The abrupt change locations are on both sides of the data lines corresponding to the first power connection line DL1 on the first power connection line PL12. Figure 6 The two adjacent data signal lines D at positions Z1 and Z2 in the middle section experience a sudden change in resistance. Z1 and Z2 correspond to the positions of the two first power supply connection structures PL12 in the bend area 12, respectively. The magnitude of the resistance change is about 200 ohms (Ω), which can easily cause screen splitting problems. Figure 6 The horizontal axis represents the position of the data line DL0 along the first direction X, and the vertical axis represents the resistance of the corresponding data line DL0.

[0058] This disclosure provides a display substrate that may include a display area and a first border area located on one side of the display area, wherein the first border area is provided with a bending area.

[0059] Multiple sub-pixels are located in the display area;

[0060] Multiple data signal lines are located in the display area and the first border area, and are electrically connected to the multiple sub-pixels. The multiple data signal lines are configured to provide data signals to the multiple sub-pixels. The data signal lines include data lines and data connection lines. The data lines are located in the display area, and the data connection lines are located in the first border area and are electrically connected to the corresponding data lines. In the same data signal line, at least a portion of the data connection line is located in the bending area.

[0061] Multiple first power connection structures are located in the bending area. The multiple first power connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide a first power signal to the multiple sub-pixels. The first direction intersects the second direction.

[0062] In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals with the plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures.

[0063] The display substrate provided in this embodiment includes a display area and a first border area located on one side of the display area. The display area includes multiple sub-pixels and data lines from multiple data signal lines. The first border area includes a bending area. In the bending area, along a first direction, data connection lines of multiple data signal lines and multiple first power connection structures are arranged at intervals, and at least one data connection line is provided between two adjacent first power connection structures. The display substrate provided in this embodiment can avoid the technical problem of display screen splitting caused by sudden changes in resistance (large resistance step difference) of signal traces in the bending area of ​​the display substrate.

[0064] like Figures 7 to 8c As shown, Figure 7 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. Figure 8a for Figure 7 An enlarged structural diagram of position M1 in the middle. Figure 8b for Figure 7 An enlarged structural diagram of the M2 position. Figure 8c for Figure 7 Another enlarged structural diagram of the position M1 in the middle shows that the display substrate may include a display area AA and a first frame area B1 located on one side of the display area AA. The first frame area B1 is provided with a bending area 12.

[0065] Multiple sub-pixels Pxij are located in the display area AA;

[0066] Multiple data signal lines D are located in the display area AA and the first border area B1, and are electrically connected to multiple sub-pixels Pxij. The multiple data signal lines D are configured to provide data signals to the multiple sub-pixels Pxij. The data signal lines D may include data lines DL0 and data connection lines DL. Data lines DL0 may be located in the display area AA, and data connection lines DL may be located in the first border area B1 and are electrically connected to the corresponding data lines DL0. In the same data signal line D, at least a portion of the data connection line DL is located in the bending area 12.

[0067] Multiple first power connection structures PL12 are located in the bending area 12. The multiple first power connection structures PL12 are arranged at intervals along the first direction X and extend along the second direction Y, and are configured to provide first power signals to multiple sub-pixels Pxij. The first direction X and the second direction Y intersect.

[0068] In the bending region 12, along the first direction X, multiple data signal lines D have data connection lines DL and multiple first power connection structures PL12 arranged at intervals, and at least one data connection line DL is provided between two adjacent first power connection structures PL12.

[0069] In an exemplary implementation, such as Figure 8a and Figure 8b As shown, two data connection lines DL can be provided between two adjacent first power connection structures PL12, or, as... Figure 8c As shown, four data connection lines DL are provided between two adjacent first power connection structures PL12. This disclosure is not limited to specific embodiments. Figures 8a to 8c As shown, for example, the number of data connection lines DL between two adjacent first power connection structures PL12 can be one, three, or more than three.

[0070] In an exemplary embodiment, in the bending region 12, the first power supply provided by the first electrical connection structure PL12 can be a VDD signal, a VSS signal, or an initialization signal, used to provide an initialization signal to the transistor in the driving circuit, or to provide voltage signals such as VGH and VGL to drive the GOA. In an exemplary embodiment, the first power supply provided by the first electrical connection structure PL12 can be two constant voltage signals among the VDD signal, VSS signal, and initialization signal. In the bending region 12, in the first direction X, the lines providing the initial signal, VGL, and VGH can be located on both sides of the data connection line DL, and the line providing the VDD signal can be located in the middle.

[0071] In an exemplary embodiment, in the bending region 12, along the first direction X, the multiple first distances R1 between the multiple data connection lines DL are consistent, and the first distance R1 is the distance between two adjacent data connection lines DL.

[0072] In an exemplary embodiment, the multiple first distances R1 between the multiple data connection lines DL are consistent, which can be that the multiple first distances R1 between the multiple data connection lines DL are approximately the same, and can have a certain difference within the allowable error range, for example, the error range is 0 micrometers to 5 micrometers.

[0073] In an exemplary embodiment, in the bending region 12, the data connection lines DL of multiple data signal lines D are arranged at intervals with multiple first power connection structures PL12. At least one data connection line DL is provided between two adjacent first power connection structures PL12. On the one hand, this can improve the consistency of the signals provided by the first power connection structure PL12. On the other hand, the first power connection structure PL12 and the data connection lines DL are arranged alternately. The first power connection structure PL2 is not a single piece, but is divided into multiple parts and set between two adjacent data connection lines DL, which can avoid the resistance change of two adjacent data signal lines D.

[0074] In an exemplary embodiment, in the bending region 12, along the first direction X, the multiple first distances R1 between the multiple data connection lines DL are consistent, which can avoid the problem of large resistance step difference caused by large length differences between two adjacent data signal lines DL.

[0075] In an exemplary embodiment, in the bending area 12, a plurality of first power connection structures PL12 are arranged at equal intervals along the first direction X, so that the first power signals acquired by the plurality of sub-pixels Pxij are as consistent as possible, which can improve the display uniformity of the display area.

[0076] In an exemplary embodiment, in the bending area 12, along the first direction X, multiple data connection lines DL between two adjacent first power connection structures PL12 are arranged at equal intervals, which can avoid the resistance change of two adjacent data signal lines D and effectively reduce the risk of display splitting.

[0077] In an exemplary embodiment, within the bending region 12, along the first direction X, a first distance R1 is greater than or equal to a second distance R2, where the second distance R2 is the distance between the first power connection structure PL12 and the adjacent data connection line. This ensures that the distance between the two data connection lines DL located on both sides of the first power connection structure PL12 is as consistent as possible with the distance between the two adjacent data connection lines DL, thereby minimizing the resistance difference of the data signal lines D corresponding to the two data connection lines DL located on both sides of the first power connection structure PL12 and avoiding sudden changes in resistance.

[0078] In an exemplary embodiment, in the bending region 12, along the first direction X, the ratio of the first distance R1 to the second distance R2 is greater than or equal to 1.5.

[0079] In an exemplary embodiment, within the bending region 12, along the first direction X, the dimension L1 of the first power connection structure PL12 is consistent with the dimension L2 of the data connection line DL. This ensures that the dimension of the first power connection structure PL12 along the first direction X is not too large, thus preventing sudden changes in resistance in the data signal lines D corresponding to the two data connection lines DL located on both sides of the first power connection structure PL12.

[0080] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the display substrate may include a substrate and a driving circuit 20 layer disposed on the substrate. The driving circuit 20 layer may include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer disposed sequentially on the substrate. At least a portion of the line segments of a plurality of data connection lines and a plurality of first power connection structures PL12 are located on the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source-drain metal layer SD2.

[0081] In an exemplary embodiment, the first frame region B1 may further include a first fan-out region 11 in a plane parallel to the display substrate. In the second direction Y, the first fan-out region 11 is located between the display region AA and the bending region 12. The display substrate may further include a first power connection line PL11, and data connection lines include a first data connection line DL1 and a second data connection line DL2. In the same data signal line, data line DL0 is electrically connected to the second data connection line DL2 via the first data connection line DL1, wherein:

[0082] The first power connection line PL11 is located in the first fan-out area 11. The first power connection line PL11 extends along the first direction X and is electrically connected to multiple first power connection structures PL12. The multiple first power connection structures PL12 provide first power signals to multiple sub-pixels Pxij through the first power connection line PL11.

[0083] The first data connection line DL1 is located in the first fan-out area 11. Among the multiple first data connection lines DL1, at least part of them are located in the first conductive layer and at least part of them are located in the second conductive layer. The first data connection lines DL1 located in the first conductive layer and the first data connection lines DL1 located in the second conductive layer are arranged alternately.

[0084] The second data connection line DL2 is located in the bending area 12. In the direction perpendicular to the plane of the display substrate, the second data connection line DL2 may be located in the fourth conductive layer, and at least a portion of the data connection line may include the second data connection line DL2.

[0085] In an exemplary embodiment, the orthographic projection of the first power connection line PL11 on the substrate at least partially overlaps with the orthographic projections of the plurality of first data connection lines DL1 on the substrate, which can save space in the first border area B1. For example, the orthographic projection of the first power connection line PL11 on the substrate can cover the orthographic projections of the plurality of first data connection lines DL1 on the substrate.

[0086] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the first power connection line PL11 is located in the fourth conductive layer, and the first power connection line PL11 is directly connected to a plurality of first power connection structures PL12; in the same data signal line, the first data connection line DL1 and the second data connection line DL2 are electrically connected through vias, and the first data connection line DL1 and the data line DL0 are electrically connected through vias.

[0087] In an exemplary embodiment, within the plane parallel to the display substrate, the first border region B1 further includes a second fan-out region 13. In the second direction Y, the second fan-out region 13 is located on the side of the bending region 12 away from the display region AA. The display substrate also includes a first power line VDD, and the data connection line further includes a third data connection line DL3. In the same data connection line, the first data connection line DL1 is electrically connected to the third data connection line DL3 via the second data connection line DL2; wherein:

[0088] The first power line VDD is located in the second fan-out area 13, and the first power line VDD is connected to multiple first power connection structures PL12.

[0089] The third data connection line DL3 is located in the second fan-out area 13. Among the multiple third data connection lines DL3, at least a portion is located in the first conductive layer and at least a portion is located in the second conductive layer. The third data connection lines DL3 located in the first conductive layer and the third data connection lines DL3 located in the second conductive layer are arranged alternately.

[0090] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the first power line VDD is located in the fourth conductive layer, and the first power line VDD is directly connected to a plurality of first power connection structures PL12; in the same data signal line, the second data connection line DL2 and the third data connection line DL3 are electrically connected through vias.

[0091] In an exemplary embodiment, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of the plurality of third data connection lines DL3 on the substrate, which can save space in the first border area B1.

[0092] In an exemplary embodiment, in the plane content parallel to the display substrate, the first border area B1 may further include a bonding area 14. In the second direction Y, the bonding area 14 is located on the side of the second fan-out area 13 away from the display area AA. The bonding area 14 may include a first power pad 51 and a driving circuit 20; a third data connection line DL3 is electrically connected to the driving circuit 20; and a first power line VDD extends to the bonding area 14 and is electrically connected to the first power pad 51.

[0093] In an exemplary embodiment, the display area AA may also be provided with multiple scan signal lines SL. The multiple scan signal lines SL may extend along the first direction X and be arranged at intervals along the second direction Y. Each scan signal line SL may be electrically connected to multiple sub-pixels Pxij in a row of sub-pixels.

[0094] In an exemplary embodiment, the second border area B2 and the third border area B3 may be provided with multiple gate drive circuits GOA (GOA is short for Gate Driver on Array) and gate drive circuit signal lines (GOA signal lines). The GOA signal lines may include clock signal lines (e.g., CK signal lines, CB signal lines, STV signal lines, etc.). The gate drive circuit GOA may be configured to be electrically connected to the corresponding scan signal line SL and provide scan signals to the corresponding scan signal line SL.

[0095] In an exemplary implementation, such as Figure 7 As shown, the first frame area B1 is also provided with a second power line VSS and a second power connection structure PL22. The second power connection structure PL22 is located in the bending area 12. In the first direction X, the second power connection structure PL22 is located on both sides of a plurality of first power connection structures PL12 and a plurality of second data connection lines DL2. The second power line VSS is located in the second fan-out area 13 and the binding area 14. In the first direction X, the second power line VSS is located on both sides of the first power line VDD.

[0096] In an exemplary embodiment, the bonding region 14 may include a driver chip region 141, a third fan-out region 142, and a bonding electrode region 143 arranged sequentially along the direction away from the bending region 12 in the second fan-out region 13. The driver chip region 141 may be provided with a driver circuit 20, the third fan-out region 142 may be provided with multiple bonding leads 201, and the bonding electrode region 143 may be provided with multiple pads. The multiple pads may include a first power pad 51, a second power pad 52, a driver pad 53, a first gate driver circuit pad 541, and a second gate driver pad 542. The driver circuit 20 may be electrically connected to the driver pad 53 in the bonding electrode region 143 through the bonding leads 201. The multiple pads may be bonded to the flexible circuit board 30. The first power line VDD may be connected to the first power pad connection 51, the second power line VSS may be connected to the second power pad 52, and the driver pad 53 may be electrically connected to the corresponding bonding lead 201.

[0097] In an exemplary embodiment, the gate drive circuit signal line may include a first gate drive circuit signal line 41 and a second gate drive circuit signal line 42. The first gate drive circuit signal line 41 extends from the third frame region B3 to the first frame region B1 and is connected to the first gate drive pad 541 and the gate drive circuit GOA located in the third frame region B3. The second gate drive circuit signal line 42 extends from the fourth frame region B4 to the first frame region B1 and is connected to the second gate drive pad 542 and the gate drive circuit GOA located in the fourth frame region B4. The gate drive circuit GOA may include a first gate drive circuit GOA1 disposed in the third frame region B3 and a second gate drive circuit GOA2 disposed in the fourth frame region B4. The first gate drive circuit GOA1 is configured to be electrically connected to the first gate drive pad 541 through the first gate drive circuit signal line 41, and the second gate drive circuit GOA2 is configured to be electrically connected to the second gate drive pad 542 through the second gate drive circuit signal line 42.

[0098] This disclosure also provides a display device, such as... Figure 9 As shown, the display device may include a display substrate.

[0099] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0100] In one exemplary embodiment, the display device can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), or a light-emitting diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0101] The display substrate and display device provided in this disclosure include a display area and a first border area located on one side of the display area. The display area includes multiple sub-pixels and data lines among multiple data signal lines. The first border area includes a bending area. In the bending area, along a first direction, data connection lines of multiple data signal lines and multiple first power connection structures are arranged at intervals, and at least one data connection line is provided between two adjacent first power connection structures. The display substrate provided in this disclosure can avoid the technical problem of display screen splitting caused by sudden changes in resistance (large resistance step difference) of signal traces in the bending area of ​​the display substrate.

[0102] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0103] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0104] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized by, The display substrate comprises a display area and a first frame area located at one side of the display area, and the first frame area is provided with a bending area; a plurality of sub-pixels located in the display area; a plurality of data signal lines located in the display area and the first frame area and electrically connected with the plurality of sub-pixels, the plurality of data signal lines are configured to provide data signals to the plurality of sub-pixels; the data signal lines comprise data lines and data connection lines, the data lines are located in the display area, the data connection lines are located in the first frame area and electrically connected with corresponding data lines, and at least part of the line segments of the data connection lines are located in the bending area in the same data signal line; a plurality of first power supply connection structures located in the bending area, the plurality of first power supply connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide first power supply signals to the plurality of sub-pixels, the first direction intersects the second direction; in the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals with the plurality of first power supply connection structures, and at least one data connection line is arranged between adjacent two first power supply connection structures.

2. The display substrate of claim 1, wherein, in the bending area, along the first direction, the plurality of first power supply connection structures are arranged at equal intervals.

3. The display substrate of claim 1, wherein, in the bending area, along the first direction, a plurality of first distances between a plurality of data connection lines are consistent, the first distance being a distance between adjacent two data connection lines.

4. The display substrate of claim 1, wherein, in the bending area, along the first direction, a plurality of data connection lines are arranged at equal intervals between adjacent two first power supply connection structures. 5.The display substrate of claim 3, wherein, in the bending area, along the first direction, the first distance is greater than or equal to a second distance, the second distance being a distance between the first power supply connection structure and the adjacent data connection line. 6.The display substrate of claim 5, wherein, in the bending area, along the first direction, a ratio of the first distance to the second distance is greater than or equal to 1.

5.

7. The display substrate according to any one of claims 1 to 6, characterized in that, in the bending area, along the first direction, a size of the first power supply connection structure is consistent with a size of the data connection line. 8.The display substrate according to any one of claims 1 to 6, characterized in that, in a direction perpendicular to a plane in which the display substrate is located, the display substrate comprises a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged on the substrate in sequence, and at least part of the line segments of the data connection lines and the plurality of first power supply connection structures are located in the fourth conductive layer. 9.The display substrate of claim 8, wherein, in a plane parallel to the plane in which the display substrate is located, the first frame area further comprises a first fan-out area, and in the second direction, the first fan-out area is located between the display area and the bending area; the display substrate further comprises a first power supply connection line, the data connection lines comprise first data connection lines and second data connection lines, and in the same data signal line, the data line is electrically connected with the second data connection line through the first data connection line, wherein: The first power connection line is located in the first fan-out area, extends along the first direction, and is electrically connected with the plurality of first power connection structures, which provide first power signals to the plurality of sub-pixels through the first power connection line. The first data connection line is located in the first fan-out area, at least part of the plurality of first data connection lines is located in the first conductive layer, and at least part of the plurality of first data connection lines is located in the second conductive layer. The first data connection lines located in the first conductive layer and the first data connection lines located in the second conductive layer are arranged alternately. The second data connection line is located in the bending area and located in the fourth conductive layer in the direction perpendicular to the plane of the display substrate. At least part of the line segment of the data connection line includes the second data connection line. 10.The display substrate of claim 9, wherein, In the direction perpendicular to the plane of the display substrate, the first power connection line is located in the fourth conductive layer and directly connected with the plurality of first power connection structures. In the same data signal line, the first data connection line and the second data connection line are electrically connected through a via, and the first data connection line and the data line are electrically connected through a via. 11.The display substrate of claim 9, wherein, In the direction parallel to the plane of the display substrate, the first frame area further includes a second fan-out area. In the second direction, the second fan-out area is located on the side of the bending area away from the display area. The display substrate further includes a first power line and a third data connection line. In the same data connection line, the first data connection line is electrically connected with the third data connection line through the second data connection line. The first power line is located in the second fan-out area and connected with the plurality of first power connection structures. The third data connection line is located in the second fan-out area. At least part of the plurality of third data connection lines is located in the first conductive layer, and at least part of the plurality of third data connection lines is located in the second conductive layer. The third data connection lines located in the first conductive layer and the third data connection lines located in the second conductive layer are arranged alternately. 12.The display substrate of claim 11, wherein, In the direction perpendicular to the plane of the display substrate, the first power line is located in the fourth conductive layer and directly connected with the plurality of first power connection structures. In the same data signal line, the second data connection line and the third data connection line are electrically connected through a via. 13.The display substrate of claim 11, wherein, In the direction parallel to the plane of the display substrate, the first frame area further includes a binding area. In the second direction, the binding area is located on the side of the second fan-out area away from the display area. The binding area is provided with a first power pad and a driving circuit. The third data connection line is electrically connected with the driving circuit. The first power line extends to the binding area and is electrically connected with the first power pad.

14. A display device comprising: The display substrate includes any one of the display substrates according to claims 1 to 13.

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