Display module, display device and display method

Abstract

The invention provides a display module, a display device and a monitoring method, and relates to the technical field of display. The display module comprises a display panel, a first controller, a level shifter, a first power manager for supplying power to the display panel and the level shifter, and a second power manager for supplying power to the first controller, the first output end of the first controller is electrically connected with the second input end of the level translator, the first output end of the level translator is electrically connected with the second input end of the display panel, and a display signal is output to the display panel through the level translator; the first controller determines the display state of the display panel according to the first indication signal, the second output end of the level shifter is electrically connected with the second input end of the first controller, and the first indication signal is output to the first controller; and / or the first controller determines the display state according to the second indication signal, the second output end of the first power manager is electrically connected with the third input end of the first controller, and the second indication signal is output to the first controller.

Description

Display module, display device and display method

[0001] The present application claims priority to Chinese Patent Application No. 202410544344.2, filed on April 30, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display module, a display device and a display method. BACKGROUND

[0003] The display state of some display products usually needs to be judged by human eyes or machine vision, which leads to the failure to obtain abnormal display information of the display products in time, thereby affecting the user experience. In addition, through observation by human eyes or judgment by machine vision, great human resources are wasted, and the use cost is increased.

[0004] SUMMARY

[0005] The present disclosure provides a display module, a display device and a display method.

[0006] According to a first aspect, the present disclosure provides a display module, comprising: a display panel, a first controller, a level converter, and a first power manager for providing working voltage for the display panel and the level converter, and a second power manager for providing working voltage for the first controller; a first output end of the first power manager is electrically connected to a first input end of the display panel and a first input end of the level converter, and an output end of the second power manager is electrically connected to a first input end of the first controller; a first output end of the first controller is electrically connected to a second input end of the level converter, for outputting a display signal to the display panel through the level converter, and a first output end of the level converter is electrically connected to a second input end of the display panel, for outputting the display signal to the display panel; wherein the first controller is further configured to determine a display state of the display panel according to a first indication signal; a second output end of the level converter is electrically connected to a second input end of the first controller, for outputting the first indication signal to the first controller; and / or the first controller is further configured to determine the display state of the display panel according to a second indication signal, and a second output end of the first power manager is electrically connected to a third input end of the first controller, for outputting the second indication signal to the first controller.

[0007] According to a second aspect, the present disclosure provides a display module, comprising: a display panel, a first controller, a second controller, a level converter, and a first power manager for providing working voltage for the display panel, the level converter and the first controller, and a second power manager for providing working voltage for the second controller,

[0008] The first output end of the first power manager is electrically connected to the first input end of the display panel, the first input end of the level converter, and the first input end of the first controller, the output end of the second power manager is electrically connected to the first input end of the first controller, the first output end of the first controller is electrically connected to the second input end of the level converter, so as to output the display signal to the display panel through the level converter; the second controller is configured to determine the display state of the display panel according to the display signal, wherein the first output end of the level converter is electrically connected to the second input end of the display panel and the second input end of the second controller, wherein the display module further comprises a power control circuit, the input end of the power control circuit is electrically connected to the output end of the second controller, so as to output a fifth control signal to the power control circuit; the first output end of the power control circuit is electrically connected to the input end of the first power manager, so as to control the first power manager to switch between power-on and power-off according to the fifth control signal.

[0009] According to a third aspect, the present disclosure provides a display device, comprising: a main controller; and a display module provided by an embodiment of the present disclosure, which is electrically connected to the main controller, and is configured to receive an instruction and a video signal from the main controller, convert the video signal into a display signal based on the instruction, and send a display state based on the display signal and a voltage signal to the main controller.

[0010] According to a fourth aspect, the present disclosure provides a display method, comprising: obtaining a first indication signal from a level converter and / or a second indication signal from a first power manager; and monitoring whether a display state of a display panel is abnormal according to the first indication signal and / or the second indication signal; wherein the first indication signal is determined based on a display signal output by the level converter, the second indication signal is determined based on a voltage signal output by the first power manager, and the display panel displays according to the display signal and the voltage signal. BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 shows a structural schematic diagram of a display module according to an embodiment of the present disclosure;

[0012] FIG. 2 shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0013] FIG. 3 shows a structural schematic diagram of a display module of an example embodiment;

[0014] FIG. 4A shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0015] FIG. 4B shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0016] FIG. 5A shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0017] FIG. 5B shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0018] FIG. 6A shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0019] FIG. 6B shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0020] FIG. 7A shows a structural schematic diagram of a first restart circuit according to an embodiment of the present disclosure;

[0021] FIG. 7B shows a layout schematic diagram of a first restart circuit according to an embodiment of the present disclosure;

[0022] FIGS. 8A to 8U show circuit architecture schematic diagrams of a display module according to an embodiment of the present disclosure;

[0023] FIG. 9 shows a layout schematic diagram of a display module according to an embodiment of the present disclosure;

[0024] FIG. 10A shows a circuit structure schematic diagram of a first controller according to an embodiment of the present disclosure;

[0025] FIG. 10B shows a partial layout schematic diagram of a first controller according to an embodiment of the present disclosure;

[0026] FIG. 10C shows a partial layout schematic diagram of a first controller according to another embodiment of the present disclosure;

[0027] FIG. 10D shows a circuit structure schematic diagram of a level shifter according to an embodiment of the present disclosure;

[0028] FIG. 11 shows a layout schematic diagram of a display module according to another embodiment of the present disclosure;

[0029] FIG. 12 shows a partial layout schematic diagram of a level shifter according to an embodiment of the present disclosure;

[0030] FIG. 13 shows a structural schematic diagram of a display module according to another embodiment of the present disclosure;

[0031] FIG. 14 shows a circuit structure schematic diagram of a detection circuit according to an embodiment of the present disclosure;

[0032] FIG. 15 shows a connection structure schematic diagram of an adjustment circuit, a first controller, and a first power manager according to an embodiment of the present disclosure;

[0033] FIG. 16 shows a circuit structure schematic diagram of an adjustment circuit and a first power manager according to an embodiment of the present disclosure;

[0034] FIG. 17 shows a structural schematic diagram of a signal processing circuit and a first controller according to an embodiment of the present disclosure;

[0035] FIG. 18 shows a structural schematic diagram of a signal processing circuit and a first controller according to another embodiment of the present disclosure;

[0036] FIG. 19 shows a flow schematic diagram of a monitoring method of a display module according to an embodiment of the present disclosure;

[0037] FIG. 20 shows a flow schematic diagram of a monitoring method according to another embodiment of the present disclosure

[0038] FIG. 21 shows a structural schematic diagram of a display device according to an embodiment of the present disclosure;

[0039] FIG. 22 shows a flow schematic diagram of a monitoring method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any creative effort fall within the protection scope of the present disclosure. In the following description, some specific embodiments are only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by a person of ordinary skill in the art. The terms “first”, “second” and the like used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0042] In addition, in the description of the embodiments of the present disclosure, the term “connected to” or “connected” can mean that two components are directly connected, or that two components are connected via one or more other components, and the connection mode is electrical connection or electrical coupling. In addition, the two components can also be connected or coupled by wired or wireless means.

[0043] FIG. 1 shows a structural schematic diagram of a display module according to an embodiment of the present disclosure.

[0044] As shown in FIG. 1, the display module 100 includes a display panel 101, a first power manager 102, a level shifter 103 and a first controller 104.

[0045] In the embodiments of the present disclosure, the display panel 101 includes a plurality of pixel units. For example, the display panel 101 can be an active matrix organic light emitting diode (AMOLED) display panel, and each pixel unit includes one light emitting element. After the light emitting element in the display panel 101 is lighted, the display module 100 displays a picture. For example, the display panel 101 can also be a liquid crystal display (LCD) display panel. The voltage applied to the pixel electrode in each pixel unit can drive the liquid crystal molecules in the corresponding area to deflect, so as to realize the gray scale display of the display module 100.

[0046] In the embodiments of the present disclosure, the first power manager 102 can be a power management integrated circuit (PMIC), and the first power manager 102 is electrically connected to the display panel 101. The first power manager 102 provides a power voltage to the display panel 101. For example, the power voltage provided by the first power manager 102 is a voltage signal required by the light emitting element, and a driving current formed by the voltage signal is provided to the light emitting element through a driving transistor in the pixel unit, so as to drive the light emitting element to emit light.

[0047] In the embodiments of the present disclosure, the level shifter 103 can be a level shift integrated circuit (LSIC). The level shifter 103 is electrically connected to the display panel 101.

[0048] In the embodiments of the present disclosure, the first output end of the first power manager 102 is electrically connected to the first input end of the display panel 101 and the first input end of the level shifter 103, and the first power manager 102 provides a working voltage to the display panel 101 and the level shifter 103. The output end of the second power manager is electrically connected to the first input of the first controller 104, and the second power manager provides a working voltage to the first controller 104.

[0049] The second output end of the first power manager 102 is electrically connected to the first input end of the first controller 104, so as to output a second indication signal to the first controller 104. The first output end of the level shifter 103 is electrically connected to the third input end of the first controller 104, so as to output a first indication signal to the first controller 104. The first output end of the first controller 104 is electrically connected to the input end of the level shifter 103, so as to output a display signal to the display panel 101 through the level shifter 103. The first output end of the level shifter is electrically connected to the second input end of the display panel 101, so as to output the display signal to the display panel 101.

[0050] In the embodiments of the present disclosure, the first power manager 102 is configured to output a voltage signal required by the display panel 101 and output a second indication signal to the first controller 104. The level shifter 103 is configured to output the second indication signal to the first controller 104. The first controller 104 is configured to output a display signal required by the display panel 101 through the level shifter 103, and determine a display state of the display panel 101 according to at least one of the first indication signal and the second indication signal.

[0051] For example, the first output end of the first controller 104 is electrically connected to the second input end of the level shifter 103 via the wire L2, and sends the display signal to the level shifter 103 via the wire L2. The first output end of the first power manager 102 is electrically connected to the second input end of the first controller 104 via the wire L1, and sends the second indication signal to the first controller 104 via the wire L1. The second output end of the level shifter 103 is electrically connected to the second input end of the first controller 104 via the wire L3, and sends the first indication signal to the first controller 104 via the wire L3.

[0052] In the embodiments of the present disclosure, the first controller 104 can be a timing controller (TCON). For example, the first controller 104 outputs the display signal to the gate driving circuit (GOA) via the level shifter 103, so that the gate driving circuit outputs a scan signal to the display panel 101 based on the display signal. For example, the first controller 104 converts a video signal from a main controller into a data signal format required by a data driving circuit, for example, the first controller 104 can convert a low voltage differential signaling (LVDS) into a mini low voltage differential signaling (Mini-LVDS) or a reduced swing differential signaling (RSDS), and deliver to the data driving circuit (SDIC).

[0053] The gate driving circuit provides the scan signal to the display panel 101 based on the display signal, so that a transistor in the display panel 101 is turned on, and the data driving circuit provides the data signal to the display panel 101 based on the display signal, so that the data signal is written through the turned-on transistor, thereby lighting up the pixel unit.

[0054] In the embodiments of the present disclosure, the level shifter 103 can boost or reduce the voltage of the display signal output by the first controller 104 to meet the working voltage required by the gate driving circuit.

[0055] In the embodiments of the present disclosure, according to at least one of the second indication signal output by the first power manager 102 via the wiring L1 and the first indication signal output by the level shifter 103 via the second wiring L2, the first controller 104 determines the display state of the display panel 101.

[0056] The display state of the display module 100 is related to the working state of the first power manager 102, the level shifter 103 and the first controller 104, and the first power manager 102 and the first controller 104 have greater influence. For example, if the working state of the first power manager 102 is abnormal, the power voltage provided by the first power manager 102 to the display panel 101 or other voltage will also be abnormal, thereby causing the display module to be black screen. For example, if the working voltage of the first controller 104 is abnormal, the voltage of the timing control signal provided by the first controller 104 to the display panel 101 will also be abnormal, thereby causing the display module to be black screen.

[0057] In the embodiments of the present disclosure, by monitoring the real-time working state of the first power manager 102 and the level shifter 103 by the first controller 104, it can be determined whether the display module 100 is in a normal working state, and whether the display state of the display module 100 is abnormal in time, so that the abnormal display problem of the display module 100 can be solved in time, and the user experience is improved.

[0058] The first indication signal can be a voltage signal representing the working state of the level shifter 103, for example, the first indication signal can be the working voltage of the level shifter 103. If the voltage of the first indication signal is within the normal working voltage range, the first controller 104 determines that the level shifter 103 is in a normal working state, and can correctly perform level conversion on the input voltage signal to provide a correct voltage signal to the related circuit.

[0059] The second indication signal can be a voltage signal representing the working state of the first power manager 102, for example, the second indication signal can be the working voltage of the first power manager 102. If the voltage of the second indication signal is within the normal working voltage range, the first controller 104 determines that the first power manager 102 is in a normal working state, and can provide a correct power voltage to the related circuit.

[0060] In the embodiments of the present disclosure, in a case where the first controller 104 detects that the first power manager 102 and the level shifter 103 are abnormal based on the first indication signal and the second indication signal, the first controller 104 can control the first power manager 102 and the level shifter 103 to reset, so that the first power manager 102 and the level shifter 103 re-enter the working state.

[0061] In the embodiments of the present disclosure, the first controller 104 can also monitor the working state of the first power manager 102 based on only the second indication signal. In a case where the first controller 104 detects that the first power manager 102 is abnormal, the first controller 104 can control the first power manager 102 to reset, so that the first power manager 102 re-enters the working state. The first controller 104 can also monitor the working state of the level shifter 103 based on only the first indication signal. In a case where the first controller 104 detects that the level shifter 103 is abnormal, the first controller 104 can control the level shifter 103 to reset, so that the level shifter 103 re-enters the working state.

[0062] In the embodiments of the present disclosure, the first controller 104 can determine the voltage of the first indication signal and the second indication signal at a certain period, or can determine the voltage of the first indication signal and the second indication signal at a certain time interval. For example, the first controller 104 can determine the voltage of the first indication signal and the second indication signal once every 5s, which can realize real-time monitoring of the electrical signals in the display module 100, thereby realizing real-time monitoring of the display state of the display module 100.

[0063] In the embodiments of the present disclosure, the first controller 104 monitors the display state of the display module 100 according to the first indication signal and the second indication signal, without the need for human eyes to observe whether the display module displays normally, avoiding waste of human resources, and without the need for machine vision to determine whether the display is normal, avoiding image processing, reducing technical difficulty and user cost. In addition, the first controller 104 is used to monitor the display state of the display module 100, without the need to add additional hardware structures in the display module 100, saving cost and saving area.

[0064] FIG. 2 shows a structural schematic diagram of a display module according to another embodiment of the present disclosure.

[0065] As shown in FIG. 2, the display module 200 includes a display panel 101, a first power manager 102, a level shifter 103, a first controller 104, and a backlight driving controller 105.

[0066] In the embodiments of the present disclosure, the first output end of the backlight drive controller 105 is electrically connected to the input end of the backlight module, and the second output end of the backlight drive controller 105 is electrically connected to the fourth input end of the first controller 104. The backlight drive controller 105 is configured to provide a backlight signal to the backlight module and output a third indication signal to the first controller 104. The first controller 104 determines the display state of the display panel according to the third indication signal.

[0067] For example, the backlight drive controller 105 is connected to the first controller 104 via the wiring L4, and sends the third indication signal to the first controller 104 via the wiring L4.

[0068] In the embodiments of the present disclosure, the first controller 104 determines the display state of the display panel according to the third indication signal. The third indication signal can be a voltage signal representing the working state of the backlight drive controller 105. For example, the third indication signal can be the working voltage of the backlight drive controller 105. If the voltage of the third indication signal is within the normal working voltage range, the first controller 104 determines that the backlight drive controller 105 is in a normal working state, and can provide a correct power voltage to the backlight source.

[0069] In the embodiments of the present disclosure, in the case that the first controller 104 monitors that the backlight drive controller 105 works abnormally based on the third indication signal, the first controller 104 can control the backlight drive controller 105 to reset, so that the backlight drive controller 105 reenters the working state.

[0070] In the embodiments of the present disclosure, the first controller 104 can determine the third indication signal at a certain period or for a certain time interval, so as to realize real-time monitoring of the electrical signal of the backlight drive controller 105 in the display module 200, and thus realize real-time monitoring of the display state of the display module 200.

[0071] In some embodiments, the backlight drive controller 105 can also be arranged on the main controller. For example, the backlight drive controller 105 can be integrated on the SoC, and the backlight drive controller 105 can be controlled by the main controller.

[0072] In the embodiments of the present disclosure, when the backlight drive controller 105 is integrated on the SoC mainboard, the first controller 104 can also be electrically connected to the backlight drive controller 105 integrated on the SoC mainboard via the wiring L4, and monitor the working state of the backlight drive controller 105 through the third indication signal, and restart the backlight drive controller 105 working abnormally. For example, the first controller 104 determines the display state of the display panel according to the third indication signal. For example, in response to the third indication signal being high, the first controller 104 monitors that the backlight drive controller 105 works abnormally, so as to determine that the display state of the display module is abnormal.

[0073] In some embodiments, in response to the high level of the third indication signal, the first controller 104 can send the abnormal working state of the backlight driving controller 105 to the main controller, so that the main controller resets the backlight driving controller 105.

[0074] The inventors have found through experiments and investigations that the main cause of the display module failure is that the first power manager, the logic board and the chip on film are directly related. Among them, the first power manager PMIC1 and the logic board have a high proportion, and the main display failure is the logic board input signal or the related black screen abnormality, the first power manager PMIC1 voltage abnormality related black screen abnormality, and the gate drive circuit related picture abnormality.

[0075] The example embodiments of the present disclosure provide a display module, which can include a display panel, a first controller TCON, a first power manager PMIC1 and a level converter LSIC. The first controller TCON monitors whether the first power manager PMIC1 and the level converter LSIC work abnormally, so as to detect whether the display panel displays abnormally.

[0076] The display module of the present disclosure, the first controller TCON can monitor the display state of the display panel according to at least one of the first indication signal and the second indication signal. The first controller TCON can also monitor the display state of the display panel according to at least one of the display signal and the voltage signal, without observing whether the display module displays normally by the human eye, avoiding the waste of human resources, and without judging whether the display is normal by machine vision, avoiding image processing, reducing the technical difficulty and user cost; and outputting the judgment result, so that the user can directly know the abnormal type of abnormal display, facilitating subsequent maintenance.

[0077] FIG. 3 shows a structural schematic diagram of a display module of an example embodiment.

[0078] As shown in FIG. 3, the display panel 101 can be a liquid crystal display panel, which can include an array substrate 32, a color film substrate 34 and a liquid crystal layer 33 disposed between the array substrate 32 and the color film substrate 34. The display module can also include a backlight module 31.

[0079] The backlight module 31 can include a plurality of backlight sources arranged in an array, which can be LEDs (Light-Emitting Diodes). The backlight module 31 can be provided as only one partition, that is, the plurality of backlight sources of the backlight module 31 are uniformly controlled, and the voltage input to the plurality of backlight sources is substantially the same, so that the luminous intensity of the plurality of backlight sources of the backlight module 31 is substantially the same.

[0080] For the backlight module 31 of the local dimming, the backlight source can be adjusted according to the brightness of the image, so that the brightness of the highlighted part of the display image can reach the maximum, while the dark part can reduce the brightness, or even be turned off to achieve the best contrast. In this way, the reduction of the dark area brightness reduces the power consumption of the backlight. Therefore, the backlight module 31 can also be provided as two partitions, three partitions or more partitions, and the multiple backlight sources in the same partition are controlled uniformly, that is, the voltage input to the multiple backlight sources in the same partition is basically the same, so that the luminous brightness of the multiple backlight sources in the same partition is basically the same.

[0081] The display panel 101 has a display area and a non-display area surrounding the periphery of the display area. In the display area, the array substrate 32 can include a plurality of pixel circuits arranged in an array. The pixel circuit can include a transistor and a pixel electrode. The transistor can include a gate, a source and a drain. The gate of the transistor is connected to a corresponding gate line, the source of the transistor is connected to a corresponding data line, and the drain of the transistor is connected to the pixel electrode. A common electrode is also provided in the display area. The common electrode can be located on the array substrate 32 or on the color film substrate 34.

[0082] The signal loaded by the gate line controls the conduction of the transistor, so as to write the data voltage provided by the data line to the corresponding pixel electrode. An electric field can be formed between the pixel electrode and the common electrode to drive the liquid crystal molecules in the corresponding area to deflect, thereby realizing gray scale control. In order to accurately control the gray scale displayed by the sub-pixel, the data voltage provided by the data line needs to be accurately written to the pixel electrode of the sub-pixel.

[0083] A gate drive circuit is provided in the non-display area of the array substrate 32. The gate drive circuit can include a plurality of cascaded shift registers. The signal output end of each stage of shift register is connected to a corresponding gate line to provide a display signal to the corresponding gate line. The display signal provided by the gate drive circuit controls the gate switching of different rows of transistors. The data signal provided by the source drive chip is sent to the source of different columns of transistors. When the scanning line signal turns on the transistor, the signal line charges the liquid crystal and the storage capacitor from the source, and saves the data. When the scanning line signal turns off the transistor, the high impedance ROFF cuts off the loop to prevent the data from being changed.

[0084] FIG. 4A shows a structural schematic diagram of a display module according to another embodiment of the present disclosure. For example, FIG. 4A can show a circuit board structural schematic diagram of the display module shown in FIG. 2.

[0085] As shown in FIG. 4A, the display module can be a 1920x1080 track transportation strip screen. The display module can further include a first printed circuit board 351, on which a first power manager PMIC1 102, a level shifter LSIC 103, a first controller TCON 104, a capacitor, a resistor element, and the like are arranged. The first power manager PMIC1 can supply power to the level shifter 103 and the like. The first printed circuit board 351 can be a logic board. For example, the first printed circuit board 351 can be a TCON board.

[0086] The first printed circuit board 351 can be connected to a left X-printed circuit board assembly XPCBA-L and a right X-printed circuit board assembly XPCBA-R through two flexible printed circuit boards FPCB. The left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are respectively coupled to the conductive connection terminals on the array substrate in the display panel 101 within the bonding area through two chip on film COF (a total of four chip on film COF).

[0087] An input end of the first printed circuit board 351 is electrically connected to a main controller, which can be a SoC (System on Chip) mainboard. An input end of the first controller TCON is electrically connected to an output end of the main controller. The first controller TCON is configured to convert a video signal LVDS into a display signal according to an instruction of the main controller, and output the display signal required by the display panel 101 through the level shifter LSIC. An output end of the first printed circuit board 351 is connected to a source driving chip SDIC and a gate driving circuit, to realize signal input to a pixel circuit. The source driving chip SDIC can be arranged on the chip on film COF, and a total of four source driving chips SDIC are arranged. An output end of the first controller TCON can also be electrically connected to an input end of the SoC mainboard. The first controller TCON sends a display state of the display panel 101 to the SoC mainboard based on an I2C communication mode. It should be noted that the display module can also have other structures, which are not described here.

[0088] In the embodiment of the present disclosure, the first printed circuit board 351 is further provided with a second power manager PMIC 2107. The main controller can provide a 12V power voltage (VDD) for the first power manager 102 and the second power manager 107. The first power manager 102 is electrically connected to the level shifter 103, and can supply power to the level shifter 103. The second power manager 107 is electrically connected to the first controller 104, and can supply power to the first controller 104. The second power manager 107 can be a Buck IC. The second power manager 107 reduces the power voltage from the main controller, periodically switches the input voltage to the output end by using a switch tube, filters the voltage by using an inductor and a diode, and thus outputs a lower stable voltage, so that the reduced power voltage meets the working requirement of the first controller 104.

[0089] In the embodiment of the present disclosure, the first controller 104 is powered by the second power manager 107 alone, and the first power manager 102 can supply power to the circuits on the first printed circuit board 351 except the first controller 104. In this case, the abnormal working state of the first power manager 102 does not affect the normal working of the first controller 104, so that the monitoring work of the first controller TCON on other circuits is not affected.

[0090] In the embodiment of the present disclosure, the first controller 104 converts the video signal LVDS from the main controller into a display signal in a data signal format required by the data driving circuit SDIC, for example, converts the LVDS into RSDS or Mini-LVDS, and then outputs the display signal to the data driving circuit SDIC via the two flexible printed circuit boards FPCB, the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R. The data driving circuit SDIC drives the display panel 101 based on the received display signal. The first controller 104 outputs the display signal, the level shifter 103 boosts the display signal, and the boosted display signal is output to the gate driving circuit via the two flexible printed circuit boards FPCB, the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R. The gate driving circuit drives the display panel 101 based on the received display signal.

[0091] In the embodiment of the present disclosure, the first controller 104 determines the display state of the display panel 101 based on the display signal and the voltage signal according to at least one of the second indication signal and the first indication signal. The first controller 104 is electrically connected to the main controller through an I2C communication line, and the first controller 104 sends the display state to the main controller.

[0092] In the embodiment of the present disclosure, the first printed circuit board 351 is further provided with a backlight driving controller LED-D 105, a second output end of the backlight driving controller 105 is electrically connected to a fourth input end of the first controller 104, and the first controller 104 outputs a third indication signal according to the backlight driving controller 105. The first controller 104 determines the display state of the display panel according to the third indication signal.

[0093] In the embodiment of the present disclosure, the first controller 104 detects the display state of the display panel based on at least one of the display signal and the voltage signal. For example, the eighth input end of the first controller 104 can be electrically connected to the first output end of the first power manager 102, and the seventh input end of the first controller 104 can be electrically connected to the first output end of the level shifter 103. The first controller 104 monitors the display state of the display panel 101 according to at least one of the display signal and the voltage signal. The first output end of the level shifter 103 is electrically connected to the second input end of the display panel 101, and the first output end of the first power manager 101 is also electrically connected to the first input end of the display panel 101. The first controller 104 can output the judgment result to the main controller (SOC mainboard).

[0094] In the embodiment of the present disclosure, the first controller 104 sends the monitored display state to the main controller, so that the main controller can obtain the display state of the display panel 101 in time. The front-end system can be installed on the main controller, and the main controller displays the display state to the user of the display panel 101 through the front-end system, so that the user can also obtain the display state of the display panel 101 in time. If the display state of the display panel 101 is abnormal and the display panel 101 itself cannot solve the problem, the user can be prompted to intervene in the display panel 101 to solve the display abnormal problem.

[0095] FIG. 4B shows a structural schematic diagram of a display module according to another embodiment of the present disclosure. For example, FIG. 4B can show another circuit board structure schematic diagram of the display module shown in FIG. 2.

[0096] As shown in FIG. 4B, the display module can further include a backlight driving circuit, for example, the display module can further include a second printed circuit board 352. The second printed circuit board 352 can be a cross-flow board, and the backlight driving circuit is arranged on the second printed circuit board 352. The backlight driving circuit is configured to provide a backlight signal for the backlight module 31, and an output end of the backlight driving circuit is electrically connected to an input end of the processor MCU and the backlight module 31. The backlight driving circuit can include a backlight converter BLU-Con. The second printed circuit board 352 can be electrically connected to the first printed circuit board 351 by a wire, so that the backlight driving circuit on the second printed circuit board 352 can be electrically connected to the processor MCU. Moreover, the backlight driving circuit is electrically connected to the backlight module 31, and the control of the backlight module 31 is realized through the backlight driving circuit. For example, the backlight driving circuit can be electrically connected to the backlight module 31 through the first printed circuit board 351.

[0097] The signal processing circuit 2, the processor MCU, and the second power manager PMIC2 are arranged on the first printed circuit board 351, that is, the signal processing circuit 2, the processor MCU, and the second power manager PMIC2 are arranged on the same first printed circuit board 351 as the first power manager PMIC1, the first controller TCON, and the level converter LSIC. Of course, in some other example embodiments of the present disclosure, the signal processing circuit 2, the processor MCU, and the second power manager PMIC2 can also be arranged on another printed circuit board separately, and can be electrically connected to the first printed circuit board 351 through binding, or through a chip on film or a flexible circuit board.

[0098] The processor MCU can serve as a second controller to detect the display state of the display panel. An input end of the processor MCU is electrically connected to an output end of the first power manager PMIC1, and is electrically connected to an output end of the first controller TCON through the level converter LSIC. The processor MCU is configured to monitor the display state of the display panel 101 according to at least one of the display signal and the voltage signal, wherein an output end of the level converter LSIC is electrically connected to an input end of the display panel 101 and an input end of the processor MCU. The processor MCU can output the judgment result to the main controller (SOC mainboard).

[0099] In the embodiment of the present disclosure, the signal processing circuit 2 is electrically connected between the display circuit of the display module and the processor MCU. The display circuit can at least include the first power manager PMIC1, the level shifter LSIC and the first controller TCON. The signal processing circuit 2 is configured to process the working signal. The signal processing circuit 2 can include an emitter follower unit and a voltage dividing unit. The emitter follower unit is electrically connected to the output end of the display circuit. The voltage dividing unit is electrically connected to the output end of the emitter follower unit. The emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current. The voltage dividing unit is configured to adjust the voltage of the working signal. The working signal at least includes any one of the voltage signal, the display signal and the backlight signal. Therefore, the signal processing circuit 2 is used to collect any one of the voltage signal, the display signal and the backlight signal of the display circuit 1.

[0100] The display module of the present disclosure can also realize that the display module does not need to be observed by the human eye to determine whether the display module is displayed normally, and does not need to be determined by machine vision whether the display module is displayed normally, by the processor MCU monitoring the display state of the display panel 100 according to at least one of the display signal and the voltage signal.

[0101] FIG. 5A shows a structural schematic diagram of a display module according to another embodiment of the present disclosure.

[0102] As shown in FIG. 5A, the display module 300 includes a display panel 101, a first power manager 102, a level shifter 103, a first controller 104 and a power control circuit. The power control circuit includes a first restart circuit 108.

[0103] In the embodiment of the present disclosure, the output end of the first restart circuit 108 is electrically connected to the input end of the first power manager 102. The input end of the first restart circuit 108 is electrically connected to the second output end of the first controller 104. For example, the first controller 104 is connected to the first restart circuit 108 via a wiring L5. Under the control of the first control signal output by the first controller 104 via the wiring L5, the first restart circuit 108 controls the first power manager 102 to switch between power-on and power-off. For example, the first restart circuit 108 controls the input end of the first power manager 102 to switch between the connected state and the disconnected state with the first working power supply.

[0104] In the embodiments of the present disclosure, the first control signal can be determined based on at least one of the first indication signal, the second indication signal, the display signal and the voltage signal, and the first control signal is related to the display state of the display panel 101. For example, in the case that the first controller 104 determines that the voltage of the second indication signal indicates that the working state of the first power manager 102 is normal, the first controller 104 outputs the first control signal to the first restart circuit 108, and the first control signal instructs the first restart circuit 108 to control the first working power source and the first power manager 102 to be in a connected state, so as to provide the working voltage to the first power manager 102, so that the first power manager 102 can be in a normally powered state. For example, in the case that the first controller 104 determines that the voltage of the second indication signal indicates that the working state of the first power manager 102 is abnormal, the first controller 104 outputs the first control signal to the first restart circuit 108, and the first control signal instructs the first restart circuit 108 to control the first working power source and the first power manager 102 to be in a disconnected state, so as to stop providing the working voltage to the first power manager 102, so that the first power manager 102 is powered off. Subsequently, the first controller 104 outputs the first control signal to the first restart circuit 108, and the first control signal instructs the first restart circuit 108 to provide the first power voltage to the first power manager 102, so that the first power manager 102 is restarted.

[0105] For example, referring to FIG. 4A, the first working power source can be arranged on an SoC mainboard where the main controller is located, and the main controller provides the first power manager 102 with a working voltage of 12V. The first power voltage is transmitted from the main controller to the first power manager 102 via the first restart circuit 108. The first restart circuit 108 can control whether to provide the first power voltage to the first power manager 102, thereby controlling the power-on and power-off of the first power manager 102, and realizing the restart of the first power manager 102.

[0106] In the embodiments of the present disclosure, in response to the first level of the second indication signal, the first controller 104 outputs the first control signal with the first level. Under the control of the first level of the first control signal, the first restart circuit 108 controls the first power manager 102 and the first working power source to be in a disconnected state.

[0107] For example, the first level can be a low level. When the first power manager 102 is working normally, the second indication signal monitored by the first controller 104 is a high level, and the first controller 104 controls the first control signal to be a high level. In response to the high level of the first control signal, the first restart circuit 108 controls the first power manager 102 to be in a connected state with the first working power supply, and the working voltage is continuously provided to the first power manager 102 to ensure the normal working of the first power manager 102. When the second indication signal is monitored to be a low level, the first controller 104 determines that the working state of the first power manager 102 is abnormal, and the first controller 104 controls the level of the first control signal to be switched from the high level to the low level. In response to the low level of the first control signal, the first restart circuit 108 controls the first power manager 102 to be in a disconnected state with the first working power supply, and the first power manager 102 is powered off, and no working voltage is provided to the first power manager 102. Then the first controller 104 controls the level of the first control signal to be switched from the low level to the high level, and in response to the high level of the first control signal, the first restart circuit 108 provides the working voltage to the first power manager 102, so that the first power manager 102 is powered on again, and the restart of the first power manager 102 is completed.

[0108] In the embodiment of the present disclosure, the level converter 103 is powered by the first power manager 102. When the first power manager 102 is powered off, the first power manager 102 also stops powering the level converter 103, so that the level converter 103 is powered off. When the first power manager 102 is powered on again, the first power manager 102 powers the level converter 103 again, so that the level converter 103 is powered on again.

[0109] For example, when the first power manager 102 is working abnormally, the second indication signal is a low level. When the level converter 103 is working abnormally, the first indication signal is a low level. According to the low level of any one of the first indication signal and the second indication signal, the first controller 104 outputs the first control signal with a low level. Under the control of the low level of the first control signal, the first restart circuit 108 controls the first power manager 102 to be in a disconnected state with the first working power supply.

[0110] In the embodiment of the present disclosure, the first controller 104 can also be electrically connected with the second output end of the level converter 103 and the second output end of the first power manager 101. In this case, the first controller 104 can output the first control signal to the first restart circuit 108 via the wiring L5 according to at least one of the display signal and the voltage signal, to instruct the first restart circuit 108 to control the first working power supply to be in a connected state or a disconnected state with the first power manager 102.

[0111] For example, in a case where the first controller 104 determines that the voltage of the voltage signal indicates that the working state of the first power manager 102 is abnormal, the first controller 104 outputs the first control signal to the first restart circuit 108, and the first control signal indicates that the first restart circuit 108 controls the first working power source to be in a disconnected state with the first power manager 102, so as to stop providing the working voltage to the first power manager 102, and thus the first power manager 102 is powered off. Subsequently, the first controller 104 outputs the first control signal to the first restart circuit 108, and the first control signal indicates that the first restart circuit 108 provides the working voltage to the first power manager 102, and thus the first power manager 102 is restarted.

[0112] In a case where the first controller 104 determines that the voltage of the display signal indicates that the working state of the level shifter 103 is abnormal, the first controller 104 outputs the first control signal to the first restart circuit 108, and the first control signal indicates that the first restart circuit 108 controls the first power manager 102 to restart, so as to restart the level shifter 103.

[0113] In the embodiment of the present disclosure, in a case where the voltage of any one of the display signal and the voltage signal is abnormal, the first controller 104 outputs the first control signal with a low level. Under the control of the low level of the first control signal, the first restart circuit 108 controls the first power manager 102 to be in a disconnected state with the first working power source, and then switches the communication state, so as to restart the level shifter 103 and the first power manager 102.

[0114] In a case where the first controller 104 needs to control the first power manager 102 to restart, the level shifter 103 and the first power manager 102 are restarted. In a case where the first controller 104 needs to control the level shifter 103 to restart, the first controller 104 controls the first power manager 102 to restart, so as to restart the level shifter 103. In a case where any one of the first power manager 102 and the level shifter 103 works abnormally, the first controller 104 controls the first restart circuit 108 to restart the first power manager 102, so as to restart the level shifter 103.

[0115] FIG. 5B shows a structural schematic diagram of a display module according to another embodiment of the present disclosure.

[0116] As shown in FIG. 5B, the display module 400 includes the display panel 101, the first power manager 102, the level shifter 103, the first controller 104, the backlight driving controller 105, and a power control circuit, wherein the power control circuit includes the second restart circuit 109.

[0117] In the embodiment of the present disclosure, the input end of the second restart circuit 109 is electrically connected to the third output end of the first controller 104, and the output end of the second restart circuit 109 is electrically connected to the input end of the backlight drive controller 105. For example, the backlight drive controller 105 is connected to the first controller 104 via the wire L4, and the second restart circuit 109 is connected to the first controller 104 via the wire L6.

[0118] Under the control of the second control signal output by the first controller 104, the second restart circuit 109 controls the backlight drive controller 105 to switch between power-on and power-off, for example, the second restart circuit 109 controls the input end of the backlight drive controller 105 to switch between the connected state and the disconnected state with the second working power supply, wherein the second control signal is determined based on at least one of the third indication signal and the backlight signal.

[0119] In the embodiment of the present disclosure, under the control of the second control signal output by the first controller 104 via the wire L6, the second restart circuit 109 provides the working voltage of the second working power supply to the backlight drive controller 105. For example, in the case where the first controller 104 determines that the voltage of the third indication signal indicates that the working state of the backlight drive controller 105 is normal, the second control signal output by the first controller 104 to the second restart circuit 109 indicates that the second restart circuit 109 controls the second working power supply to be in the connected state with the backlight drive controller 105, so that the backlight drive controller 105 can be in the state of being normally powered. For example, in the case where the first controller 104 determines that the voltage of the third indication signal indicates that the working state of the backlight drive controller 105 is abnormal, the second control signal output by the first controller 104 to the second restart circuit 109 indicates that the second restart circuit 109 controls the second working power supply to be in the disconnected state with the backlight drive controller 105, so as to stop providing the working voltage to the backlight drive controller 105, so that the backlight drive controller 105 is powered off. Subsequently, the second control signal output by the first controller 104 to the second restart circuit 109 indicates that the second restart circuit 109 controls the second working power supply to be in the connected state with the backlight drive controller 105, so that the backlight drive controller 105 is restarted.

[0120] For example, the second working power supply can be arranged on the main controller, and the working voltage can be transmitted from the main controller to the backlight drive controller 105 via the second restart circuit 109. The second restart circuit 109 can control whether to provide the working voltage of the second working power supply to the backlight drive controller 105, thereby controlling the power-on and power-off of the backlight drive controller 105, and realizing the restart of the backlight drive controller 105.

[0121] In the embodiments of the present disclosure, in response to the high level of the third indication signal output by the backlight driving controller 105 via the wire L4, the first controller 104 outputs the second control signal with a low level to the second restart circuit 109 via the wire L6. Under the control of the low level of the second control signal, the second restart circuit 109 controls the backlight driving controller 105 to be in the disconnected state with the power supply.

[0122] For example, when the backlight driving controller 105 works normally, the third indication signal monitored by the first controller 104 is low level, and the second control signal is controlled to be high level. When the backlight driving controller 105 works abnormally, the third indication signal monitored by the first controller 104 is high level, and the second control signal is controlled to be low level. The restart process of the second restart circuit 109 to the backlight driving controller 105 can refer to the restart process of the first restart circuit to the first power manager. For the sake of simplicity, it will not be described here.

[0123] In the embodiments of the present disclosure, the fourth input end of the first controller 104 is further connected to the second output end of the backlight driving controller 105. In this case, the first controller 104 can output the second control signal to the second restart circuit 109 via the wire L6 according to the backlight signal, to instruct the second restart circuit 109 to control the second working power supply to be in the connected state or the disconnected state with the backlight driving controller 105.

[0124] For example, in the case that the first controller 104 determines that the voltage of the backlight signal indicates that the working state of the backlight driving controller 105 is abnormal, the second control signal output by the first controller 104 to the second restart circuit 109 instructs the second restart circuit 109 to control the second working power supply to be in the disconnected state with the backlight driving controller 105, to stop providing the working voltage to the backlight driving controller 105, so that the backlight driving controller 105 is powered off. Subsequently, the second control signal output by the first controller 104 to the second restart circuit 109 instructs the second restart circuit 109 to provide the working voltage to the backlight driving controller 105, so that the backlight driving controller 105 is restarted.

[0125] In the embodiments of the present disclosure, in the case that the voltage of the backlight signal is abnormal, the first controller 104 outputs the second control signal with a low level. Under the control of the low level of the second control signal, the second restart circuit 109 controls the backlight driving controller 105 to be in the disconnected state with the second working power supply, and switches to the connected state, thereby realizing the restart of the backlight driving controller 105.

[0126] In some embodiments, the backlight driving controller 105 can also be arranged on the main controller. For example, the backlight driving controller 105 can be integrated on the SoC motherboard, and the backlight driving controller 105 can be controlled by the main controller.

[0127] In the embodiments of the present disclosure, when the backlight driving controller 105 is integrated on the SoC motherboard, the first controller 104 can also be electrically connected with the backlight driving controller 105 integrated on the SoC motherboard via the wiring L4, monitor the working state of the backlight driving controller 105 through the third indication signal, and restart the backlight driving controller 105 with working abnormality. For example, in response to the third indication signal output by the backlight driving controller 105 via the wiring L6, the first controller 104 determines the display state of the display panel. For example, in response to the third indication signal being at a high level, the first controller 104 monitors that the backlight driving controller 105 is working abnormally, and thus determines that the display state of the display module is abnormal.

[0128] In some embodiments, in response to the high level of the third indication signal, the first controller 104 can send a second control signal to the main controller, and the second control signal is used to control the backlight driving controller 105 to restart. The first controller 104 sends the second control signal to the main controller, and the second control signal is provided to the backlight driving controller 105 integrated on the SoC motherboard. The main controller can restart the backlight driving controller 105 based on the second control signal.

[0129] In the embodiments of the present disclosure, in response to the high level of the third indication signal, the first controller 104 can also send the working state of the backlight driving controller 105 to the main controller, and the main controller controls the backlight driving controller 105 to restart based on the working state. In the case that the first controller 104 monitors that the backlight driving controller 105 is working abnormally based on the third indication signal, the first controller 104 sends the abnormal working state of the backlight driving controller 105 to the main controller, so as to only inform the main controller of the information that the backlight driving controller 105 is working abnormally. The way in which the main controller controls the backlight driving controller 105 to restart based on the abnormal working state can be realized based on the control logic of the main controller itself.

[0130] FIG. 6A shows a structural schematic diagram of a display module according to another embodiment of the present disclosure.

[0131] As shown in FIG. 6A, the display module 500 includes the display panel 101, the first power manager 102, the level converter 103, the first controller 104, the first restart circuit 108, and the second controller 110. For example, referring to the display module 300 shown in FIG. 5A, the display module 500 can be the display module 300 further including the second controller 110.

[0132] In the embodiment of the present disclosure, the second input terminal of the second controller 110 can be electrically connected with the first output terminal of the first power manager 102, and the first input terminal of the second controller 110 can be electrically connected with the first output terminal of the level shifter 103. The third input terminal of the second controller 110 can be electrically connected with the output terminal of the second power manager. The input terminal of the first restart circuit 108 is electrically connected with the first output terminal of the second controller 110. For example, the second controller 110 is electrically connected with the first output terminal of the first power manager 102 via the wire L7, and the second controller 110 is electrically connected with the first output terminal of the level shifter 103 via the wire L8. The first restart circuit 108 is electrically connected with the second controller 110 via the wire L9.

[0133] In this case, the second controller 110 can acquire the voltage signal via the wire L7, acquire the display signal via the wire L8, and determine the display state of the display panel 101 according to at least one of the display signal and the voltage signal. The second controller 110 can output the third control signal to the first restart circuit 108 via the wire L9 to instruct the first restart circuit 108 to control the first working power source and the first power manager 102 to be in the connected state or the disconnected state.

[0134] For example, in the case where the second controller 110 determines that the voltage of the voltage signal indicates that the working state of the first power manager 102 is abnormal, the third control signal output by the second controller 110 to the first restart circuit 108 instructs the first restart circuit 108 to control the first working power source and the first power manager 102 to be in the disconnected state, so as to stop providing the working voltage to the first power manager 102, so that the first power manager 102 is powered off. Subsequently, the third control signal output by the second controller 110 to the first restart circuit 108 instructs the first restart circuit 108 to provide the working voltage to the first power manager 102, so that the first power manager 102 is restarted.

[0135] In the case where the second controller 110 determines that the voltage of the display signal indicates that the working state of the level shifter 103 is abnormal, the third control signal output by the second controller 110 to the first restart circuit 108 instructs the first restart circuit 108 to control the first power manager 102 to restart, so as to realize the restart of the level shifter 103.

[0136] In the embodiment of the present disclosure, in the case where the voltage of any one of the display signal and the voltage signal is abnormal, the second controller 110 outputs the third control signal with a low level. Under the control of the low level of the third control signal, the first restart circuit 108 controls the first power manager 102 and the first working power source to be in the disconnected state, and then switches to the connected state, so as to realize the restart of the level shifter 103 and the first power manager 102.

[0137] When the second controller 110 needs to control the first power manager 102 to restart, both the level converter 103 and the first power manager 102 restart. When the second controller 110 needs to control the level converter 103 to restart, the second controller 110 controls the first power manager 102 to restart, thereby realizing the restart of the level converter 103. In the case of any abnormal work of the first power manager 102 and the level converter 103, the second controller 110 controls the first restart circuit 108 to restart the first power manager 102, thereby realizing the restart of the level converter 103.

[0138] In the embodiment of the present disclosure, the second controller 110 can be integrated inside the first controller 104. In this case, the input end of the first controller 104 can be electrically connected with the second output end of the first power manager 102 and the second output end of the level converter 103. The input end of the first restart circuit 108 is electrically connected with the output end of the first controller 104.

[0139] In the embodiment of the present disclosure, the display signal output by the first output end of the level converter 103 includes a first branch display signal and a second branch display signal. The second controller 110 determines the display state of the display panel 101 according to the second branch display signal. The first output end of the level converter 103 is electrically connected to the second input end of the display panel 101, so as to output the first branch display signal to the display panel 101. The first output end of the level converter 103 is electrically connected to the second input end of the second controller 110, so as to output the second branch display signal to the second controller 110.

[0140] In the embodiment of the present disclosure, the second controller 110 can detect the second branch display signal output by the level converter 103. In the case of determining that the second branch display signal is abnormal, it is considered that the level converter 103 is abnormal. At this time, the first branch display signal output by the level converter 103 is also abnormal, so that the display state of the display panel 101 is abnormal due to the abnormality of the level converter 103.

[0141] In the embodiment of the present disclosure, the working voltage output by the first output end of the first power manager 102 includes a first branch voltage signal and a second branch voltage signal. The second controller 110 determines the display state of the display panel 101 according to the second branch voltage signal. The first output end of the first power manager 102 is electrically connected to the first input end of the display panel 101, so as to output the first branch voltage signal to the display panel 101. The first output end of the first power manager 102 is electrically connected to the third input end of the second controller 110, so as to output the second branch voltage signal to the second controller 110.

[0142] In the embodiments of the present disclosure, the second controller 110 can detect the second branch display signal output by the first power manager 102. In the case that the second branch voltage signal is determined to be abnormal, it is considered that the first power manager 102 is abnormal. At this time, the first branch voltage signal output by the first power manager 102 is also abnormal, and thus the display state of the display panel 101 is abnormal due to the abnormality of the first power manager 102.

[0143] FIG. 6B shows a structural schematic diagram of a display module according to another embodiment of the present disclosure.

[0144] As shown in FIG. 6B, the display module 600 includes the display panel 101, the first power manager 102, the level shifter 103, the first controller 104, the backlight driving controller 105, the second restart circuit 109, and the second controller 110. For example, with reference to the display module 400 shown in FIG. 5B, the display module 600 can be the display module 400 further including the second controller 110.

[0145] In the embodiments of the present disclosure, the fourth input end of the second controller 110 can be electrically connected with the first output end of the backlight driving controller 105. The input end of the second restart circuit 109 is electrically connected with the second output end of the second controller 110. For example, the second controller 110 is electrically connected with the backlight driving controller 105 via the wiring L10. The second restart circuit 109 is electrically connected with the second controller 110 via the wiring L11.

[0146] In this case, the second controller 110 can acquire the backlight signal via the wiring L10, and determine the display state of the display panel 101 according to the backlight signal. The second controller 110 can output the fourth control signal to the second restart circuit 109 via the wiring L11, to instruct the second restart circuit 109 to control the second working power source and the backlight driving controller 105 to be in the connected state or the disconnected state.

[0147] For example, in the case that the second controller 110 determines that the voltage of the backlight signal indicates that the working state of the backlight driving controller 105 is abnormal, the fourth control signal output by the second controller 110 to the second restart circuit 109 instructs the second restart circuit 109 to control the second working power source and the backlight driving controller 105 to be in the disconnected state, to stop providing the working voltage to the backlight driving controller 105, so that the backlight driving controller 105 is powered off. Subsequently, the fourth control signal output by the second controller 110 to the second restart circuit 109 instructs the second restart circuit 109 to provide the working voltage to the backlight driving controller 105, so that the backlight driving controller 105 is restarted.

[0148] In the embodiment of the present disclosure, the second controller 110 outputs the fourth control signal with a low level in the case that the voltage of the backlight signal is abnormal. Under the control of the low level of the fourth control signal, the second restart circuit 109 controls the backlight driving controller 105 to be in the off state with the second working power supply, and switches the communication state again, so as to realize the restart of the backlight driving controller 105.

[0149] In the embodiment of the present disclosure, the second controller 110 can be integrated in the inside of the first controller 104. In this case, the input end of the first controller 104 can be electrically connected with the second output end of the backlight driving controller 105.

[0150] In the embodiment of the present disclosure, the backlight signal output by the first output end of the backlight driving controller 105 includes a first branch backlight signal and a second branch backlight signal. The second controller 110 determines the display state of the display panel 101 according to the second branch backlight signal. The first output end of the backlight driving controller 105 is electrically connected to the backlight module, so as to output the first branch backlight signal to the backlight module, and the first output end of the backlight driving controller 105 is electrically connected to the fourth input end of the second controller 110, so as to output the second branch backlight signal to the second controller 110.

[0151] In the embodiment of the present disclosure, the second controller 110 can detect the second branch backlight signal output by the backlight driving controller 105. In the case that it is determined that the second branch backlight signal is abnormal, it is considered that the backlight driving controller 105 is abnormal. At this time, the first branch backlight signal output by the backlight driving controller 105 is also abnormal, so that the display state of the display panel 101 is abnormal due to the abnormality of the backlight driving controller 105.

[0152] The control process of the first restart circuit is schematically described in combination with FIG. 7A. FIG. 7A shows a structural schematic diagram of the first restart circuit according to the embodiment of the present disclosure. For example, FIG. 7A shows the first restart circuit 108 in FIG. 5A.

[0153] As shown in FIG. 7A, the first restart circuit 108 includes a transistor VT, a transistor T1, a resistor R19 and a resistor R20.

[0154] In the embodiment of the present disclosure, the control electrode of the triode VT is connected to the second output terminal of the first controller TCON via the wire L5, the first electrode of the triode VT is electrically connected to the second end of the resistor R19, the second electrode of the triode VT is grounded GND to provide a voltage of 0 V. The control electrode of the transistor T1 is electrically connected to the second end of the resistor R20, the first electrode of the transistor T1 is electrically connected to the first working power supply VDD1, and the second electrode of the transistor T1 is electrically connected to the input terminal of the first power manager PMIC1. The first end of the resistor R19 is electrically connected to the first working power supply VDD1, and the first end of the resistor R20 is electrically connected to the first electrode of the triode VT.

[0155] In the embodiment of the present disclosure, the triode VT can be an NPN triode, and the transistor T1 can be a PMOS. The first controller TCON provides a first control signal. When the first control signal is at a high level, the triode VT is turned on, the control electrode of the transistor T1 is grounded, and the transistor T1 is turned on. At this time, the working voltage VDD1 provided by the first working power supply VDD1 is provided to the first power manager PMIC via the transistor T1. When the first control signal is at a low level, the triode VT is turned off, the control electrode of the transistor T1 is turned off between the power supply GND, and the transistor T1 is turned off. At this time, the working voltage VDD1 provided by the first working power supply VDD1 cannot be provided to the first power manager PMIC1 via the transistor T1.

[0156] It should be noted that the triode VT can also be a PNP triode, and the transistor T1 can also be an NMOS. The person skilled in the art can change the level of the first control signal accordingly to realize the control process of the first restart circuit 108 shown in FIG. 7A.

[0157] In the embodiment of the present disclosure, the resistor R19 and the resistor R20 are used to divide the voltage in the first restart circuit 108, so as to avoid the direct connection of the high voltage and the low level, which causes the short circuit. The first restart circuit 108 can further include a first capacitor and a second capacitor. The first end of the first capacitor is electrically connected to the first electrode of the transistor T1, and the second end of the first capacitor is electrically connected to the control electrode of the transistor. The first end of the second capacitor is electrically connected to the second electrode of the transistor T, and the second end of the first capacitor is electrically connected to the control electrode of the transistor. The first capacitor and the second capacitor can stabilize the voltage of the first electrode, the second electrode and the control electrode of the transistor T1 in the first restart circuit 108. According to the actual design requirement, the circuit structure of the first restart circuit 108 can be expanded and modified based on the first capacitor and the second capacitor to meet the corresponding restart requirement.

[0158] In some embodiments, the control electrode of the triode VT can also be connected to the second controller 110 via the wire L11. The second controller 110 provides a first control signal.

[0159] In some embodiments, the circuit structure of the second restart circuit 109 can refer to the circuit structure of the first restart circuit 108. The working process of the second restart circuit 109 can refer to the restart process of the first restart circuit 108. For the sake of simplicity, similar parts are not described again.

[0160] FIG. 7B shows a layout schematic diagram of the first restart circuit according to an embodiment of the present disclosure. FIG. 7B shows a layout diagram of the first restart circuit 108 in FIG. 7A.

[0161] As shown in FIG. 7B, the emitter E, the collector C and the base B of the transistor VT are electrically connected through the conductive element CE1. The emitter E of the transistor VT is electrically connected to the ground wire GND. The base B of the transistor VT is connected to the via H5 through the conductive element CE9. The via H5 is connected to the via H6 through the conductive element CE4. The via H6 is connected to the via H7 through the wire L5. The via H7 is connected to the first controller 104. The collector C of the transistor VT is electrically connected to the via H1 through the conductive element CE7. The collector C of the transistor VT is electrically connected to the via H1 and the via H3 through the conductive element CE7.

[0162] The gate G, the drain D and the source S of the transistor T1 are electrically connected through the conductive element CE2. The gate G of the transistor T1 is electrically connected to the via H2 through the conductive element CE8, so as to be electrically connected to the second end of the resistor R20. The source S of the transistor T1 is electrically connected to the power supply wire VDD1. The power supply wire VDD1 is electrically connected to the via H4, so that the source S of the transistor T1 is electrically connected to the first end of the resistor R19. The drain D of the transistor T1 is electrically connected to the first power manager PMIC1 through the conductive element CE3.

[0163] The via H1 is electrically connected to the first end of the resistor R20. The via H3 is electrically connected to the second end of the resistor R19. The via H1 is connected to the via H2 through the conductive element CE5. The via H3 is electrically connected to the via H4 through the conductive element CE6.

[0164] The via 1 and the via 2 can be arranged along the first direction x. The via 3 and the via 4 are also arranged along the first direction. The via 1 and the via 3 are arranged along the second direction y. The via 2 and the via 4 are arranged along the second direction y. The gate G, the drain D and the source S of the transistor T1 are arranged along the second direction y. The via H5 and the via H6 are arranged along the first direction x.

[0165] The first restart circuit 108 can be disposed on a three-layer circuit board, and the conductive element CE7, the conductive element CE4, the conductive element CE8, the conductive element CE3 and the conductive element CE9 can be located on the same layer of the circuit board. The power supply wire VDD1 can be located on a different layer of the circuit board from the conductive element CE3, the ground wire GND can be located on a different layer of the circuit board from the conductive element CE3, and the ground wire GND can also be located on a different layer of the circuit board from the power supply wire VDD1.

[0166] FIGS. 8A to 8R show schematic diagrams of circuit architectures of a display module according to embodiments of the present disclosure.

[0167] As shown in FIG. 8A, in the display module 700, the output end of the main controller is electrically connected to the sixth input end of the first controller 104, so as to output a video signal to the first controller 104. The first controller 104 converts the video signal transmitted by the main controller into a data signal format required by the data driving circuit. For example, a low-voltage differential signal connector LVDS Con sends the video signal from the main controller to the first controller 104 in the form of LVDS. The first controller 104 converts the video signal in the form of LVDS into a display signal in the form of Mini-LVDS required by the data driving circuit. The display signal in the form of Mini-LVDS is sent to the data driving circuit via the micro low-voltage differential signal connectors Mini-LVDS Con1 and Mini-LVDS Con2 of the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R, for data driving of the display module, and also provides display signals for the gate and the source. The main controller provides a working voltage (VDD) of 12V for the first power manager 101 and the second power manager 107. Moreover, the first controller 104 can output a judgment result to the main controller (SOC mainboard).

[0168] In embodiments of the present disclosure, the fourth output end of the first controller 104 is electrically connected to the input end of the main controller. The first controller 104 monitors the video signal from the main controller, obtains a monitoring result, and sends the monitoring result to the main controller. The monitoring result indicates whether the video signal is abnormal, and the display state indicates whether the display panel displays abnormally based on the display signal and / or indicates whether the display panel displays abnormally based on the voltage signal output by the first output end of the first power manager. For example, whether the video content of the video signal is correct, whether the resolution of the video picture described by the video signal is correct, and the like.

[0169] In the case of detecting the abnormal video signal, the display module 700 cannot display the correct picture. At this time, the first controller 104 can enter a built-in self-test (BIST) mode. In the BIST mode, the first controller 104 automatically detects the running state of the large-area screen and controls the display module to display a black picture or a picture of black, white, red, and green that is displayed in a cycle.

[0170] In this case, the first controller 104 also sends information about the abnormal video signal to the main controller, and the main controller shows the abnormal information to the user of the display module 700 to remind the user to provide the video signal again and avoid the user mistaking the display picture in the BIST mode as a normal display picture.

[0171] In the embodiment of the present disclosure, the second power manager 107 provides the working voltage DVDD to the first controller 104. For example, according to the working requirement of the first controller 104, the second power manager 107 can provide the working voltage of 3.3 V, 1.8 V, and 1.1 V to the first controller 104.

[0172] In the embodiment of the present disclosure, the first power manager 102 provides the supply voltage VGH and VGL to the level shifter 103. The first power manager 102 provides the analog power voltage signal AVDD, the reference voltage VCOM, and the correction voltage Gamma to the display panel via the micro-low voltage differential signal connector Mini-LVDS Con1 and Mini-LVDS Con2.

[0173] In the embodiment of the present disclosure, the first controller 104 provides the display signal to the level shifter 103, and the display signal includes the column clock signal CPV and the column start signal STV. The level shifter 103 performs level conversion on the column clock signal CPV and the column start signal STV, and provides the converted column clock signal CPV (clock signal CLK) and column start signal STV to the gate drive circuit via the micro-low voltage differential signal connector Mini-LVDS Con1 and Mini-LVDS Con2.

[0174] In the embodiment of the present disclosure, the first controller 104 monitors at least one of the first indication signal fault1 from the level shifter 103 and the second indication signal fault2 from the first power manager 102. The first controller 104 determines the working state of the level shifter 103 and the first power manager 102 based on the level of the first indication signal fault1 and the second indication signal fault2, respectively.

[0175] For example, if the voltage of the analog power voltage signal AVDD, the reference voltage VCOM, the correction voltage Gamma outputted by the first power manager 102 to the display panel is abnormal, or the supply voltage VGH, VGL outputted by the first power manager 102 to the level shifter 103 is abnormal, the second indication signal fault2 outputted by the first power manager 102 to the first controller TCON changes from high level to low level.

[0176] For example, if the voltage of the clock signal CLK and the column start signal STV outputted by the level shifter 103 to the display panel is abnormal, the first indication signal fault1 outputted by the level shifter 103 to the first controller 104 changes from high level to low level.

[0177] After determining the abnormality based on at least one of the first indication signal fault1 and the second indication signal fault2, the first controller 104 sends information of the display panel abnormality to the host controller via the low voltage differential signal connector LVDS Con through the I2C wire, so as to inform the user of the display panel. When the display state returns to normal, the first controller 104 also sends information of the display panel returning to normal to the host controller via the low voltage differential signal connector LVDS Con through the I2C wire.

[0178] The memory circuit Flash IC can be electrically connected to the serial peripheral interface (SPI) of the first controller 104. The memory circuit Flash IC can store the working parameters required by the first controller 104 to output the display signal. The first controller 104 obtains the working parameters stored in the memory circuit Flash IC through the SPI interface, and outputs the display signal to the level shifter 103 based on the working parameters. The memory circuit Flash IC is electrically connected to the first power manager PMIC1, and is powered by the first power manager PMIC1.

[0179] As shown in FIG. 8B, in the display module 700, the first controller 104 can also only monitor the second indication signal fault2 from the first power manager 102. The first controller 104 judges the working state of the first power manager 102 based on the level of the second indication signal fault2.

[0180] For example, if the voltage of the analog power voltage signal AVDD, the reference voltage VCOM, the correction voltage Gamma output by the first power manager 102 to the display panel or the supply voltage VGH, VGL output by the first power manager 102 to the level shifter 103 is abnormal, the second indication signal fault2 output by the first power manager 102 to the first controller TCON changes from high level to low level.

[0181] After determining the voltage abnormality of the signal output by the first power manager 102 based on the low level of the second indication signal fault2, the first controller 104 sends the information of the display state abnormality of the display panel to the host controller via the low-voltage differential signal connector LVDS Con through the I2C wire to inform the user of the display panel. When the display state returns to normal, the first controller 104 also sends the information of the display panel returning to the normal display state abnormality to the host controller via the low-voltage differential signal connector LVDS Con through the I2C wire.

[0182] As shown in FIG. 8C, in the display module 700, the first controller 104 can also receive the first indication signal fault1 from the level shifter 103. The first controller 104 judges the working state of the level shifter 103 based on the level of the first indication signal fault1.

[0183] For example, if the voltage of the column clock signal CPV and the column start signal STV output by the level shifter 103 to the display panel is abnormal, the first indication signal fault1 output by the level shifter 103 to the first controller 104 changes from high level to low level.

[0184] After determining the voltage abnormality of the signal output by the level shifter 103 based on the low level of the first indication signal fault1, the first controller 104 sends the information of the display state abnormality of the display panel to the host controller via the low-voltage differential signal connector LVDS Con through the I2C wire to inform the user of the display panel. When the display state returns to normal, the first controller 104 also sends the information of the display panel returning to the normal display state abnormality to the host controller via the low-voltage differential signal connector LVDS Con through the I2C wire.

[0185] As shown in FIG. 8D, based on the display module 700 shown in FIG. 8B, the display module 700 further comprises a first restart circuit CTRL1 108. The first controller 104 outputs a control signal POW_CTRL1 to the first restart circuit 108. The first restart circuit 108 can control the first power manager 102 to restart based on the working state of the first power manager 102.

[0186] When the voltage of at least one of the analog power voltage signal AVDD, the reference voltage VCOM, the correction voltage Gamma outputted by the first power manager 102 to the display panel and the supply voltage VGH, VGL outputted by the first power manager 102 to the level shifter 103 is abnormal, the second indication signal fault2 outputted by the first power manager 102 to the first controller 104 is low. When the voltages of the analog power voltage signal AVDD, the reference voltage VCOM, the correction voltage Gamma outputted by the first power manager 102 to the display panel and the supply voltage VGH, VGL outputted by the first power manager 102 to the level shifter 103 are all normal, the second indication signal fault2 outputted by the first power manager 102 to the first controller 104 is high.

[0187] According to the low level of the second indication signal fault2, the first controller 104 monitors that the signal voltage outputted by the first power manager 102 is abnormal. At this time, the control signal POW_CTRL1 outputted by the first controller 104 to the first restart circuit 108 is low. Under the control of the low level of the control signal POW_CTRL1, the first restart circuit 108 controls the first power manager 102 to be powered off.

[0188] According to the high level of the second indication signal fault2, the first controller 104 controls the control signal POW_CTRL1 to be high. Under the control of the high level of the control signal POW_CTRL1, the first restart circuit 108 provides the working voltage from the main controller to the first power manager 102.

[0189] As shown in FIG. 8E, the first restart circuit 108 can control the level shifter 103 to restart based on the working state of the level shifter 103.

[0190] When the voltage of the column clock signal CPV and the column start signal STV outputted by the level shifter 103 to the display panel is abnormal, the first indication signal fault1 outputted by the level shifter 103 to the first controller 104 is low. When the voltages of the column clock signal CPV and the column start signal STV outputted by the level shifter 103 to the display panel are all normal, the first indication signal fault1 outputted by the level shifter 103 to the first controller 104 is high.

[0191] According to a low level of the first indication signal fault1, the first controller 104 monitors that the signal voltage output from the first power manager 102 is abnormal. At this time, the first controller 104 outputs a low level of the control signal POW_CTRL1 to the first restart circuit 108. Under the control of the low level of the control signal POW_CTRL1, the first restart circuit 108 controls the first power manager 102 to be powered off, so that the first power manager 102 suspends the power supply to the level shifter 103.

[0192] According to a high level of the second indication signal fault2, the first controller 104 controls the control signal POW_CTRL1 to be a high level. Under the control of the high level of the control signal POW_CTRL1, the first restart circuit 108 provides the working voltage from the main controller to the first power manager 102, at this time, the first power manager 102 resumes the power supply to the level shifter 103, so that the level shifter 103 restarts.

[0193] As shown in FIG. 8F, the first restart circuit 108 can control the first power manager 102 and the level shifter 103 to restart based on the working state of the first power manager 102 and the level shifter 103.

[0194] If the voltage of any one of the clock signal CLK and the column start signal STV output from the level shifter 103 to the display panel, the analog power voltage signal AVDD output from the first power manager 102 to the display panel, the reference voltage VCOM, the correction voltage Gamma, and the supply voltage VGH, VGL output from the first power manager 102 to the level shifter 103 is abnormal, there is an indication signal from a high level to a low level in the first indication signal fault1 and the second indication signal fault2 received by the first controller 104.

[0195] At this time, the first controller 104 outputs a low level of the control signal POW_CTRL1 to the first restart circuit 108. Under the control of the low level of the control signal POW_CTRL1, the first restart circuit 108 controls the first power manager 102 to be powered off, so that the first power manager 102 suspends the power supply to the level shifter 103.

[0196] According to a high level of the second indication signal fault2, the first controller 104 controls the control signal POW_CTRL1 to be a high level. Under the control of the high level of the control signal POW_CTRL1, the first restart circuit 108 provides the working voltage from the main controller to the first power manager 102, at this time, the first power manager 102 resumes the power supply to the level shifter 103, so that the first power manager 102 and the level shifter 103 are restarted.

[0197] As shown in FIG. 8G, the display module 700 shown in FIG. 8B further includes a backlight driving controller 105. The backlight driving controller 105 sends the LED setting signal LEDA / LEAK and the cathode voltage signal LED- in the backlight signal to the backlight source via the backlight converter BLU Con.

[0198] In the embodiments of the present disclosure, the first controller 104 monitors the third indication signal fault3 from the backlight driving controller 105. The first controller 104 determines the working state of the backlight driving controller 105 based on the level of the third indication signal fault3. For example, if the voltage of at least one of the LED setting signal LEDA / LEAK and the cathode voltage signal LED- output by the backlight driving controller 105 to the backlight converter BLU Con is abnormal, the third indication signal fault3 output by the backlight driving controller 105 to the first controller 104 changes from low level to high level.

[0199] After determining that the voltage of the signal output by the backlight driving controller 105 is abnormal based on the third indication signal fault3, the first controller 104 sends the information that the display state of the display panel is abnormal to the host controller via the low-voltage differential signal connector LVDS Con through the I2C wire, so as to inform the user of the display panel. When the display state returns to normal, the first controller 104 also sends the information that the display panel returns to the normal display state to the host controller via the low-voltage differential signal connector LVDS Con through the I2C wire.

[0200] In the display module 700 shown in FIG. 8G, the first controller 104 can monitor the working states of the first power manager 102, the level converter 103 and the backlight driving controller 105 according to the first indication signal fault1, the second indication signal fault2 and the third indication signal fault3, respectively.

[0201] In the display module 700 shown in FIG. 8H, the first controller 104 can monitor the working state of the backlight driving controller 105 only according to the third indication signal fault3. At this time, the first power manager 102 can provide the working power DVDD for the first controller 104.

[0202] In some embodiments, the backlight driving controller 105 is integrated on the SoC motherboard.

[0203] The first controller 104 monitors the third indication signal fault3 from the backlight driving controller 105. The first controller 104 determines the working state of the backlight driving controller 550 based on the level of the third indication signal fault3. After determining that the backlight driving controller 105 is abnormal based on the third indication signal fault3, the first controller 104 sends information that the display state of the display module is abnormal to the main controller (SoC motherboard) via the low-voltage differential signal connector LVDS Con, so as to inform the user of the display module. When the display state returns to normal, the first controller 104 also sends information that the display module returns to the normal display state to the main controller via the low-voltage differential signal connector LVDS Con.

[0204] According to the high level of the third indication signal fault3, the first controller 104 sends the abnormal working state of the backlight driving controller 105 to the main controller (SoC motherboard) through the I2C communication mode. The main controller controls the backlight driving controller 105 to restart based on the abnormal working state of the backlight driving controller 105.

[0205] In some embodiments, the backlight driving controller 105 and the second restart circuit 109 are integrated on the SoC motherboard.

[0206] The first controller 104 sends the control signal POW_CTRL2 to the second restart circuit 109 integrated on the SoC motherboard. In response to the high level of the third indication signal fault3, the first controller 104 controls the control signal POW_CTRL2 to be at a low level. Under the control of the low level of the control signal POW_CTRL2, the SoC motherboard controls the second restart circuit 109 to power off and restart the control of the backlight driving controller 105. In response to the low level of the third indication signal fault3, the first controller 104 controls the control signal POW_CTRL2 to be at a high level. Under the control of the high level of the control signal POW_CTRL2, the SoC motherboard controls the second restart circuit 109 to provide the working voltage from the main controller to the backlight driving controller 105.

[0207] As shown in FIG. 81, the display module 700 further includes the second restart circuit CTRL2 109 on the basis of the display module 700 shown in FIG. 8H.

[0208] The first controller 104 outputs a control signal POW_CTRL2 to the second restart circuit 109. The second restart circuit 109 can control the backlight driving controller 105 to restart based on the working state of the backlight driving controller 105. When the voltage of at least one of the LED setting signal LEDA / LEAK and the cathode voltage signal LED- outputted by the backlight driving controller 105 to the backlight converter BLU Con is abnormal, the third indication signal fault3 outputted by the backlight driving controller 105 to the first controller 104 is high. When the voltage of both the LED setting signal LEDA / LEAK and the cathode voltage signal LED- outputted by the backlight driving controller 105 to the backlight converter BLU Con is normal, the third indication signal fault3 outputted by the backlight driving controller 105 to the first controller 104 is low.

[0209] According to the high level of the third indication signal fault3, the first controller 104 monitors that the signal voltage outputted by the backlight driving controller 105 is abnormal. At this time, the control signal POW_CTRL2 outputted by the first controller 104 to the second restart circuit 109 is low. Under the control of the low level of the control signal POW_CTRL2, the second restart circuit 109 controls the backlight driving controller 105 to be powered off.

[0210] According to the low level of the third indication signal fault3, the first controller 104 controls the control signal POW_CTRL2 to be high. Under the control of the low level of the control signal POW_CTRL2, the second restart circuit 109 provides the working voltage from the main controller to the backlight driving controller 105.

[0211] As shown in FIG. 8J, on the basis of the display module 700 shown in FIG. 8G, the display module 700 further includes a first restart circuit 108 and a second restart circuit CTRL2 109.

[0212] The restart process performed by the first restart circuit 108 can refer to FIG. 8F, and the restart process performed by the second restart circuit 109 can refer to FIG. 81. For the sake of simplicity, similar parts will not be described again.

[0213] As shown in FIG. 8K, the display module 700 can further include a signal processing circuit 2 electrically connected between the display circuit of the display module and the second controller MCU 110, the signal processing circuit 2 is configured to process the working signals, the signal processing circuit 2 can include an emitter follower unit and a voltage dividing unit, the emitter follower unit is electrically connected to the output end of the display circuit, the voltage dividing unit is electrically connected to the output end of the emitter follower unit, the emitter follower unit is configured to collect the working signals and prevent the backflow of the working signal current, and the voltage dividing unit is configured to adjust the voltage of the working signals; the working signals at least include any one of the voltage signals, the display signals and the backlight signals; so that the signal processing circuit 2 is used for collecting any one of the voltage signals, the display signals and the backlight signals of the display circuit 1.

[0214] The working signals at least include any one of the direct current digital voltage signal DVDD and the direct current analog voltage signal AVDD in the voltage signals, the frame start signal STV1 and the reset signal STV2 in the display signals, and the cathode voltage signal LED- in the backlight signals.

[0215] In the example embodiment, the voltage signals can include the direct current analog voltage signal and the direct current digital voltage signal. For example, generally, the voltage signals can be direct current voltage signals, and the voltage signals can include the direct current analog voltage signal AVDD, the direct current digital voltage signal DVDD, the gate drive high level VGH, the gate drive low level VGL, the analog working half voltage HAVDD, the reference voltage VCOM, the correction voltage Gamma, etc.; if all the voltage signals are detected, seven signal processing circuits need to be set, and the processor MCU also needs to select a chip with more interfaces, which will cause a substantial increase in hardware cost and a large increase in the area occupied by the first printed circuit board 351. Since the direct current analog voltage signal AVDD and the direct current digital voltage signal DVDD are the basic voltages for generating the gate drive high level VGH, the gate drive low level VGL, the analog working half voltage HAVDD, the reference voltage VCOM, and the correction voltage Gamma, i.e., the direct current analog voltage signal AVDD and the direct current digital voltage signal DVDD are the sources of other voltages, if the direct current analog voltage signal AVDD and the direct current digital voltage signal DVDD are abnormal, other voltages are also abnormal, and if the direct current analog voltage signal AVDD and the direct current digital voltage signal DVDD are normal, other voltages are also normal under no special circumstances. Therefore, monitoring the direct current analog voltage signal AVDD and the direct current digital voltage signal DVDD can achieve the monitoring of the first power manager PMIC1 of the display module, and the processor MCU does not need to select a chip with more interfaces, the hardware cost will not substantially increase, and the area occupied by the first printed circuit board 351 will not substantially increase.

[0216] The signal processing circuit 2 can have multiple outputs for outputting different signals to the second controller 110.

[0217] The first input of the signal processing circuit 2 is electrically connected to the first output of the level shifter 103, and the first output of the signal processing circuit is electrically connected to the second input of the second controller 110. The second input of the signal processing circuit 2 is electrically connected to the first output of the first power manager 102, and the second output of the signal processing circuit 2 is electrically connected to the third input of the second controller 110. The third input of the signal processing circuit 2 is electrically connected to the first output of the backlight driving controller 105, and the third output of the signal processing circuit 2 is electrically connected to the fourth input of the second controller 110. The first input of the second controller 110 is electrically connected to the output of the second power manager 107 for providing operating voltage to the second controller 110.

[0218] As shown in FIG. 8L, the display module 700 further includes a first restart circuit 108 based on the display module 700 shown in FIG. 8K. The second controller 110 outputs a control signal POW_CTRL1 to the first restart circuit 108. The first restart circuit 108 can control the first power manager 102 to restart based on the operating state of the first power manager 102. The first restart circuit 108 can control the level shifter 103 to restart based on the operating state of the level shifter 103.

[0219] When the voltage of at least one of the direct-current digital voltage signal DVDD and the direct-current analog voltage signal AVDD is abnormal, the second controller 110 outputs a low-level control signal POW_CTRL1 to the first restart circuit 108. When the voltages of the direct-current digital voltage signal DVDD and the direct-current analog voltage signal AVDD are normal, the second controller 110 controls the control signal POW_CTRL1 to be high level.

[0220] When the voltage of at least one of the frame start signal STV1, the reset signal STV2, and the clock signal CLK in the display signal is abnormal, the second controller 110 outputs a low-level control signal POW_CTRL1 to the first restart circuit 108. When the voltages of the frame start signal STV1, the reset signal STV2, and the clock signal CLK in the display signal are normal, the second controller 110 controls the control signal POW_CTRL1 to be high level.

[0221] Under the control of the low level of the control signal POW_CTRL1, the first restart circuit 108 controls the first power manager 102 to be powered off. Under the control of the high level of the control signal POW_CTRL1, the first restart circuit 108 provides operating voltage from the main controller to the first power manager 102.

[0222] Under the control of the low level of the control signal POW_CTRL1, the first restart circuit 108 controls the first power manager 102 to power off, thereby controlling the level shifter 103 to power off. Under the control of the high level of the control signal POW_CTRL1, the first restart circuit 108 provides the working voltage from the main controller to the first power manager 102, thereby controlling the level shifter 103 to restart.

[0223] As shown in FIG. 8M, the display module 700 further comprises the second restart circuit 109 and the backlight driving controller 105 on the basis of the display module 700 shown in FIG. 8K.

[0224] The second controller 110 outputs the control signal POW_CTRL2 to the second restart circuit 109. The second restart circuit 109 can control the backlight driving controller 105 to restart based on the working state of the backlight driving controller 105. When the voltage of the cathode voltage signal LED- in the backlight signal output by the backlight driving controller 105 to the backlight converter BLU Con is abnormal, the control signal POW_CTRL2 output by the second controller 110 to the second restart circuit 109 is at the high level. When the voltage of the cathode voltage signal LED- in the backlight signal output by the backlight driving controller 105 to the backlight converter BLU Con is normal, the control signal POW_CTRL2 output by the second controller 110 to the second restart circuit 109 is at the low level.

[0225] Under the control of the high level of the control signal POW_CTRL2, the second restart circuit 109 controls the backlight driving controller 105 to power off. Under the control of the low level of the control signal POW_CTRL2, the second restart circuit 109 provides the working voltage from the main controller to the backlight driving controller 105.

[0226] As shown in FIG. 8N, the display module 700 further comprises the first restart circuit 108, the second restart circuit 109 and the backlight driving controller 105 on the basis of the display module 700 shown in FIG. 8K.

[0227] The restart process performed by the first restart circuit 108 can refer to FIG. 8L, and the restart process performed by the second restart circuit 109 can refer to FIG. 8M. For the sake of simplicity, similar parts will not be described again.

[0228] As shown in FIG. 8O, the signal processing circuit 2 can be configured to process the first error identification signal LS-F. The signal processing circuit 2 is electrically connected to the output end of the level shifter LSIC, and instead of monitoring a plurality of clock signals CLK, the signal processing circuit 2 monitors only one first error identification signal LS-F, so that the number of signal processing circuits used is reduced, the interface of the second processor 110 is also reduced, the hardware cost is reduced, and the area of the first printed circuit board 351 can also be set smaller.

[0229] In this case, since the first error identification signal LS-F changes from a high level of normal operation to a low level, it is not necessary to accurately obtain the voltage of the first error identification signal LS-F, and a timing unit is not needed to accurately collect the frequency of the clock signal CLK.

[0230] The second processor 110 determines the display state of the display panel according to whether the first error identification signal LS-F is received, that is, the second processor 110 is configured to determine whether the first error identification signal LS-F is received, and if so, the display state of the display panel is determined to be abnormal display caused by the abnormality of the level shifter LSIC. The specific process is described in the monitoring method, which will not be described here.

[0231] In some other example embodiments of the present disclosure, the backlight module 31 of the highlight display module has a large number of partitions, for example, the number of partitions of the backlight module 31 of Local Dimming (Local Dimming) is usually several tens of partitions. If the cathode voltage signal LED- of each partition is monitored, the number of signal processing circuits used will increase, the interface of the processor MCU will also need to increase, thereby increasing the hardware cost, and increasing the area of the first printed circuit board 351.

[0232] In this case, the output end of the backlight driving controller 105 is electrically connected to the input end of the second controller 110 and the input end of the backlight driving circuit, and the output end of the backlight driving controller 105 is electrically connected to the backlight converter BLU-Con. The backlight driving controller 105 is configured to output the second error identification signal LED-DF or the backlight signal according to the working state of the backlight driving controller 105.

[0233] The input end of the second controller 110 is electrically connected to the output end of the backlight driving controller 105, and is electrically connected to the output end of the first controller 104 through the level shifter 103. The second controller 110 is configured to determine the display state of the display panel by determining whether the second error identification signal LED-DF is received.

[0234] The monitoring circuit further comprises a signal processing circuit 2 electrically connected between the backlight driving controller LED-D and the second controller 110, for processing the second error identification signal LED-DF.

[0235] In the case of over temperature protection (OTP) of the backlight driving controller LED-D, open circuit or short circuit of the backlight, the second error identification signal LED-DF changes from high level in normal working state to low level.

[0236] By monitoring one second error identification signal LED-DF instead of multiple cathode voltage signals LED-, no matter how many partitions the backlight module 31 has and how many backlight driving controllers 105 are used, the error signals of the backlight driving controllers 105 can be connected together to form one second error identification signal LED-DF. Therefore, only one second error identification signal LED-DF needs to be monitored, which reduces the number of signal processing circuits and the interface of the second controller 110, lowers the hardware cost, and makes the first printed circuit board 351 smaller.

[0237] In this case, since the second error identification signal LED-DF changes from high level in normal working state to low level, it is not necessary to accurately obtain the voltage of the second error identification signal LED-DF, and an analog-digital conversion unit is not needed to accurately collect the voltage of the second error identification signal LED-DF.

[0238] The second controller 110 is configured to determine the display state of the display panel by judging whether the second error identification signal LED-DF is received. The second controller 110 determines whether the backlight is normal or abnormal to cause abnormal display according to whether the second error identification signal is received. The specific process is described in the monitoring method, which will not be repeated here.

[0239] It should be noted that in the example embodiment of monitoring the second error identification signal LED-DF, the clock signal CLK can be monitored. Of course, in the example embodiment of monitoring the first error identification signal LS-F, the cathode voltage signals LED- of each partition of the backlight module 31 can be monitored.

[0240] As shown in FIG. 8P, the display module 700 further includes the first restart circuit 108 on the basis of the display module 700 shown in FIG. 8O. The second controller 110 outputs the control signal POW_CTRL1 to the first restart circuit 108. The first restart circuit 108 can control the first power manager 102 to restart based on the working state of the first power manager 102. The first restart circuit 108 can control the level shifter 103 to restart based on the working state of the level shifter 103.

[0241] The control signal POW_CTRL1 outputted by the second controller 110 to the first restart circuit 108 is low when the second controller 110 receives the first error identification signal LS-F. The second controller 110 controls the control signal POW_CTRL1 to be high when the second controller 110 does not receive the first error identification signal LS-F.

[0242] The first restart circuit 108 controls the level shifter 103 to restart by controlling the first power manager 102 to restart based on the control signal POW_CTRL1.

[0243] As shown in FIG. 8Q, the display module 700 further includes the second restart circuit 109 and the backlight driving controller 105 on the basis of the display module 700 shown in FIG. 8O.

[0244] The second controller 110 outputs the control signal POW_CTRL2 to the second restart circuit 109. The second restart circuit 109 can control the backlight driving controller 105 to restart based on the working state of the backlight driving controller 105.

[0245] The control signal POW_CTRL2 outputted by the second controller 110 to the second restart circuit 109 is high when the second controller 110 receives the second error identification signal LED-DF. The second controller 110 controls the control signal POW_CTRL2 to be low when the second controller 110 does not receive the second error identification signal LED-DF. The second restart circuit 109 controls the backlight driving controller 105 to restart based on the control signal POW_CTRL3.

[0246] As shown in FIG. 8R, the display module 700 further includes the first restart circuit 108, the second restart circuit 109 and the backlight driving controller 105 on the basis of the display module 700 shown in FIG. 8O.

[0247] The restart process performed by the first restart circuit 108 can refer to FIG. 8P, and the restart process performed by the second restart circuit 109 can refer to FIG. 8Q. For simplicity, similar parts are not described again.

[0248] As shown in FIG. 8S, the display module 700 further includes the second controller 110 based on the display module 700 shown in FIG. 8G.

[0249] The second controller 100 is electrically connected with the second power manager 107, and is configured to provide a working voltage to the second controller 110. The detection process performed by the second controller 110 can refer to the execution process of the second controller 110 in FIG. 8K. For the sake of brevity, similar parts are not described again.

[0250] The first controller 104 can monitor the display state of the display panel according to the first indication signal fault1, the second indication signal fault2 and the third indication signal fault3. The second controller 110 can monitor the display state of the display panel based on at least one of the direct-current analog voltage signal AVDD, the clock signal CLK, the column start signal STV and the cathode voltage signal LED-.

[0251] As shown in FIG. 8T, the display module 700 can further include a signal processing circuit 2, which is electrically connected between the display circuit of the display module and the first controller 104, and is configured to process the working signal. The signal processing circuit 2 acquires at least one of the direct-current analog voltage signal AVDD, the clock signal CLK, the column start signal STV and the cathode voltage signal LED-. The signal processing process performed by the signal processing circuit 2 can refer to FIG. 8K. For the sake of brevity, similar parts are not described again.

[0252] In the embodiments of the present disclosure, the first controller 104 outputs the display signal to the level shifter 103, and the first output end of the level shifter 103 is electrically connected to the second input end of the display panel 101, so as to output the first branch display signal to the display panel 101. The first output end of the level shifter 103 is electrically connected to the second input end of the first controller 104, so as to output the second branch display signal to the first controller 104.

[0253] In the embodiments of the present disclosure, the first controller 104 can detect the display signal output by itself via the first output end, so as to determine whether the voltage of the display signal output by itself is abnormal. In the case that it is determined that the display signal output by the first output end of the first controller 104 is abnormal, it is considered that both the first branch display signal and the second branch display signal are abnormal. At this time, the display state of the display panel 101 is abnormal due to the abnormal display signal output by the first controller 104.

[0254] In the embodiment of the present disclosure, the first controller 104 can also detect the display signal output by itself via the first output end and the second branch display signal output by the level converter 103. In the case that the first controller 104 determines that the display signal output by the first output end is normal, but the second branch display signal is abnormal, it is considered that the level converter 103 is abnormal. At this time, the first branch display signal output by the level converter 103 is also abnormal, so that the display state of the display panel 101 is abnormal due to the abnormality of the level converter.

[0255] In the embodiment of the present disclosure, the working voltage output by the first output end of the first power manager 102 includes a first branch voltage signal and a second branch voltage signal. The first controller 104 determines the display state of the display panel 101 according to the second branch voltage signal. The first output end of the first power manager 102 is electrically connected to the first input end of the display panel 101 to output the first branch voltage signal to the display panel 101, and the first output end of the first power manager 102 is electrically connected to the eighth input end of the first controller 104 to output the second branch voltage signal to the first controller 104.

[0256] In the embodiment of the present disclosure, the first controller 104 can detect the second branch voltage signal output by the first power manager 102. In the case that the second branch voltage signal is determined to be abnormal, it is considered that the first power manager 102 is abnormal. At this time, the first branch voltage signal output by the first power manager 102 is also abnormal, so that the display state of the display panel 101 is abnormal due to the abnormality of the first power manager 102.

[0257] In the embodiment of the present disclosure, the backlight signal output by the first output end of the backlight drive controller 105 includes a first branch backlight signal and a second branch backlight signal. The first controller 104 determines the display state of the display panel 101 according to the second branch backlight signal. The first output end of the backlight drive controller 105 is electrically connected to the backlight module to output the first branch backlight signal to the backlight module, and the first output end of the backlight drive controller 105 is electrically connected to the ninth input end of the first controller 104 to output the second branch backlight signal to the first controller 104.

[0258] In the embodiment of the present disclosure, the first controller 104 can detect the second branch backlight signal output by the backlight drive controller 105. In the case that the second branch backlight signal is determined to be abnormal, it is considered that the backlight drive controller 105 is abnormal. At this time, the first branch backlight signal output by the backlight drive controller 105 is also abnormal, so that the display state of the display panel 101 is abnormal due to the abnormality of the backlight drive controller 105.

[0259] In the embodiments of the present disclosure, the signal processing circuit 2 can have multiple output terminals for outputting different signals to the first controller 104. The multiple output terminals of the signal processing circuit 2 can refer to the following FIG. 17 and FIG. 18.

[0260] The first input terminal of the signal processing circuit 2 is electrically connected to the first output terminal of the level shifter 103, and the first output terminal of the signal processing circuit is electrically connected to the seventh input terminal of the first controller 104. The second input terminal of the signal processing circuit 2 is electrically connected to the first output terminal of the first power manager 102, and the second output terminal of the signal processing circuit 2 is electrically connected to the eighth input terminal of the first controller 104. The third input terminal of the signal processing circuit 2 is electrically connected to the first output terminal of the backlight driving controller 105, and the third output terminal of the signal processing circuit 2 is electrically connected to the ninth input terminal of the first controller 104.

[0261] As shown in FIG. 8U, the display module 700 can further include a signal processing circuit 2 electrically connected between the display circuit of the display module and the first controller 104, and the signal processing circuit 2 is configured to process working signals. The signal processing circuit 2 collects at least one of the direct-current analog voltage signal AVDD, the clock signal CLK, the column start signal STV, and the cathode voltage signal LED-, the first indication signal fault1, the second indication signal fault2, and the third indication signal fault3. The signal processing process performed by the signal processing circuit 2 can refer to FIG. 8K. For the sake of simplicity, similar parts will not be described again.

[0262] Of course, in some other example embodiments of the present disclosure, for example, in the case of high monitoring requirements, the voltage signals can not only include the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD, but also include one, two or more of the gate drive high level VGH, the gate drive low level VGL, the analog working half voltage HAVDD, the reference voltage VCOM, and the correction voltage Gamma, which are not described one by one here.

[0263] In this case, referring to FIGS. 8A to 8T, since the connection lines in the figures are crossed, the black dots at the crossing positions are cross connections, and the black dots at the crossing positions are only crossed without connections. The signal processing circuit 2 is electrically connected to the output terminal of the first power manager 102 for collecting the direct-current analog voltage signal AVDD. The signal processing circuit 2 is also electrically connected to the output terminal of the first power manager 102 for collecting the direct-current digital voltage signal DVDD.

[0264] FIG. 9 shows a layout schematic diagram of a display module according to an embodiment of the present disclosure. FIG. 9 shows a circuit board layout diagram of the display module of FIG. 4A.

[0265] As shown in FIG. 9, in a layout diagram of the display module, the first power manager PMIC1, the first controller TCON and the level shifter LSIC are arranged along a first direction x. The first power manager PMIC1 and the level shifter LSIC are respectively located on two sides of the first controller TCON.

[0266] The connector BTB can be arranged along a second direction y of the first controller TCON. The first controller TCON can be connected with the SoC mainboard via the connector BTB.

[0267] The left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are arranged along the first direction x, and the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are arranged on two sides of the first controller TCON along the second direction y via the connector BTB. The micro low voltage differential signal Mini-LVDS output by the first controller TCON is output to the display panel via the connector arranged on the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R.

[0268] The connection relationship among the first power manager PMIC1, the first controller TCON and the level shifter LSIC is schematically explained in combination with FIGS. 10A-10D.

[0269] FIG. 10A shows a schematic diagram of a circuit structure of the first controller according to an embodiment of the present disclosure. FIG. 10A shows the circuit structure of the first controller in FIG. 9.

[0270] As shown in FIG. 10A, the pins PIN1-PIN8 of the first controller TCON can be input / output (I / O) pins, the pin PIN9 can be an Inter-Integrated Circuit (I2C) communication pin, the pin PIN10 can be a power supply pin, the pin PIN11 can be a ground pin, the pin PIN12 can be a BIST pin, the pin PIN13 can be a reset pin, the pin PIN14 can be a start signal pin, the pin PIN15 can be a clock signal pin, and the pin PIN16 can be a video signal input / output pin. It should be noted that the number of pins shown in FIG. 10A is only schematically explained.

[0271] In the embodiments of the present disclosure, the three I / O pins of the first controller TCON can be electrically connected with the first power manager PMIC1, the level shifter LSIC and the backlight driving controller respectively, and are used for receiving the first indication signal fault1, the second indication signal fault2 and the third indication signal fault3 respectively. For example, the pin PIN1 is electrically connected with the backlight driving controller, the pin PIN2 is electrically connected with the first power manager PMIC1, and the pin PIN3 is electrically connected with the level shifter LSIC. The first controller TCON is electrically connected with the main controller through the pin PIN9, and is used for sending the display state to the main controller. The first controller TCON is also electrically connected with the main controller through the pin PIN16, and is used for receiving the video signal from the main controller.

[0272] For example, the base of the triode VT shown in FIG. 7A can be electrically connected to the pin PIN4 of the first controller TCON. The first controller TCON can send the first control signal to the first restart circuit 108 through the pin PIN4.

[0273] For example, the level shifter is also electrically connected to the pin PIN10 and the pin PIN11 of the first controller TCON. The level shifter receives the frame start signal through the pin PIN10 and receives the clock signal through the pin PIN11.

[0274] For example, the pin PIN1 of the first controller TCON is the fourth input terminal, the pin PIN2 of the first controller TCON is the third input terminal, the pin PIN3 of the first controller TCON is the second input terminal, the pin PIN4 of the first controller TCON is the second output terminal, the pin PIN5 of the first controller TCON is the third output terminal, the pin PIN6 of the first controller TCON is the seventh input terminal, the pin PIN7 of the first controller TCON is the eighth input terminal, the pin PIN8 of the first controller TCON is the ninth input terminal, the pin PIN9 of the first controller TCON is the fourth output terminal, the pin PIN10 of the first controller TCON is the first input terminal, the pin PIN14 and the pin PIN15 of the first controller TCON are the first output terminal, and the pin PIN16 of the first controller TCON is the sixth input terminal.

[0275] FIG. 10B shows a partial layout schematic diagram of a first controller according to an embodiment of the present disclosure. FIG. 10B shows the connection relationship of part of the pins of the first controller TCON in FIG. 9.

[0276] As shown in FIG. 10B, the pin PIN1 of the first controller TCON is connected with the via H8 via the wire L4, the via H8 is connected with the via H9 via the conductive element CE10. The via H9 is used for electrical connection with the backlight driving controller. The pin PIN2 of the first controller TCON is connected with the via H10 via the wire L1, the via H10 is connected with the via H11 via the conductive element CE11. The via H11 is used for electrical connection with the first power manager PMIC1. The pin PIN3 of the first controller TCON is connected with the via H12 via the wire L2, the via H12 is connected with the via H13 via the conductive element CE14. The via H13 is used for electrical connection with the level shifter LSIC. The pin PIN5 of the first controller TCON is connected with the via H14 via the wire L5, the via H14 is used for electrical connection with the first restart circuit 108.

[0277] The first controller TCON can be arranged on a multi-layer circuit board, the wire L1, the wire L2 and the wire L4 can be located on the same layer of the circuit board. The via H8, the via H10 and the via H12 can be located on the same layer of the circuit board as the wire L2. The via H9, the via H11 and the via H12 can be located on the same layer of the circuit board and different from the wire L1. The wire L5 and the via H14 can be located on the same layer of the circuit board. The wire L5 can be located on different layers of the circuit board from the wire L1 or the via H11.

[0278] The via H8, the via H9, the via H10 and the via H12 can be arranged along the first direction x, the via H13 and the via H12 can be arranged along the first direction x. The via H8 and the via H12 can be arranged along the second direction y, the via H9 and the via H13 can also be arranged along the second direction y.

[0279] FIG. 10C shows a partial layout diagram of the first controller according to another embodiment of the present disclosure. FIG. 10C shows the connection relationship between the first controller TCON and the connector BTB in FIG. 9.

[0280] As shown in FIG. 10C, the pin PIN9 of the first controller TCON is connected with the wire L13, the wire L13 is electrically connected with the wire L12. The first power manager PMIC1 can be connected with the pin of the connector BTB via the wire L12, so as to be electrically connected with the main controller. For example, the first power manager PMIC1 is connected with the wire L12, the wire L12 is electrically connected with the pin of the connector BTB, the connector BTB is electrically connected with the main controller.

[0281] In the embodiment of the present disclosure, the connector BTB lead-out wire L12 is connected to the via H15, the pin PIN9 lead-out wire L13 of the first controller TCON is electrically connected to the via H17, and the via H17 is connected to the via H16 through the conductive element CE13. The via H16 can be connected to the via H15 through the conductive element.

[0282] In the embodiment of the present disclosure, the wire L13 and the wire L12 are both used for transmitting data in the I2C communication mode. For example, in the production process of the display module, the wire L12 can be used for adjusting the display flicker and code burning. For example, the main controller sends a voltage signal and an instruction to the first power manager in the I2C communication mode through the wire L12, so as to adjust the brightness of the display panel and code burning. After the production is completed, the wire L12 is in an idle state, the I2C communication pin lead-out wire L13 of the first controller TCON is connected to the wire L12. In this case, the wire L12 can be multiplexed, so that the first controller TCON can send relevant information to the main controller in the I2C communication mode through the wire L13 and the wire L12.

[0283] In the embodiment of the present disclosure, in the production stage, the main controller sends an instruction to the power controller through the wire L12. After the product production is completed, the main controller no longer sends an instruction to the power controller through the wire L12, and the first controller TCON sends information to the main controller through the wire L13 and the wire L12. Therefore, the process of the first controller TCON sending information to the main controller will not be disturbed.

[0284] In the production stage, the main controller is the master device, and the power controller is the slave device. The power controller passively receives data. In the product production completion stage, the main controller is the slave device, and the first controller TCON is the master device. The first controller TCON actively sends data. The data transmission mode between the main controller and the first power controller PMIC1 is different from the data transmission mode between the main controller and the first controller TCON. Therefore, the use of the wire L12 will not cause data transmission conflict.

[0285] For the I2C data transmission process, the master device and the slave device follow a specified protocol format when transmitting data. The data is transmitted between the master device and the slave device through the data line SDA in the wire L13, and the serial data sequence composed of 0 and 1. The structure of the serial data sequence can include a start condition, an address bit, a read-write bit, a response bit, a data bit, and a stop condition.

[0286] For example, each device on the I2C bus can act as a master or a slave, and each device corresponds to a unique device address. The master and the slave on the I2C bus perform bidirectional data transmission in units of 8 bytes, and each unit is followed by an ACK bit (used to confirm correct reception of data). For example, when the clock line SCL in the wiring L13 is low, data is placed on the data line SDA in the wiring L13. When the clock line SCL is high, the master controller samples the voltage on the data line SDA to obtain the data transmitted by the wiring L13.

[0287] In the embodiments of the present disclosure, since the communication addresses of the power supply controller and the master controller are different, the first controller TCON can send the display state to the master controller via the wiring L13 and the wiring L12 based on the address of the master controller, so that the display state sent by the sequence controller TCON will not be transmitted to the power supply controller. In this case, it can be ensured that the wiring L13 and the wiring L12 will not mis-transmit the display state to the first power manager in the process of transmitting data, and the multiplexing of the wiring L12 is realized.

[0288] In some embodiments, the first controller TCON can also be electrically connected to the master controller through a serial port. For example, the first controller TCON can also be electrically connected to the master controller through a universal asynchronous receiver / transmitter (UART). For example, the IO pin of the first controller TCON is electrically connected to the master controller in a serial port manner.

[0289] FIG. 10D shows a circuit structure schematic diagram of a level shifter according to an embodiment of the present disclosure. FIG. 10D shows the circuit structure of the level shifter LSIC in FIG. 9.

[0290] As shown in FIG. 10D, the pin PIN1 of the level shifter LSIC can be an indication signal pin, the pin PIN2 can be a ground pin, the pin PIN3 and the pin PIN4 can be power supply pins, the pin PIN5 can be a frame start signal input pin, the pin PIN6 can be a clock signal input pin, the pin PIN7 can be a frame start signal output pin, and the pin PIN8 can be a clock signal output pin. It should be noted that the number of pins shown in FIG. 10D is only illustrative.

[0291] In the embodiment of the present disclosure, the pin PIN1 of the level shifter LSIC can be electrically connected to the first controller TCON, for sending a first indication signal fault1 to the first controller TCON. For example, the pin PIN3 and the pin PIN4 are electrically connected to the first power manager PMIC1, and the pin PIN5 and the pin PIN6 are electrically connected to the first controller TCON, for receiving a frame start signal and a clock signal sent by the first controller TCON, respectively. The pin PIN7 and the pin PIN8 are electrically connected to the display panel, for sending a frame start signal and a clock signal to the display panel, respectively.

[0292] For example, the pin PIN1 of the level shifter LSIC can be a second output terminal, the pin PIN3 and the pin PIN4 of the level shifter LSIC can be first input terminals, the pin PIN5 and the pin PIN6 of the level shifter LSIC can be second input terminals, and the pin PIN7 and the pin PIN8 of the level shifter LSIC can be first output terminals.

[0293] FIG. 11 shows a layout schematic diagram of a display module according to another embodiment of the present disclosure. FIG. 11 shows a layout diagram of the display module of FIG. 4B.

[0294] As shown in FIG. 11, in the layout diagram of the display module, the connector BTB, the first controller TCON, and the level shifter LSIC are arranged along the second direction y. The first power manager PMIC1 and the second power manager PMIC2 are located on the same side of the first controller TCON. The signal processing circuit 2 and the processor MCU are located on the same side of the first controller TCON, on the other side opposite to the first power manager PMIC1 and the second power manager PMIC2.

[0295] The left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are arranged along the first direction x, and the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are arranged on the two sides of the first controller TCON along the second direction y. The micro-low voltage differential signal Mini-LVDS output by the first controller TCON is output to the display panel via the connector arranged on the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R.

[0296] The connection relationship of the level shifter LSIC is schematically illustrated in combination with FIG. 12. FIG. 12 shows a partial layout schematic diagram of a level shifter according to an embodiment of the present disclosure.

[0297] The pin lead-out wire L14 of the level shifter LSIC, for example, the pin PIN7 lead-out wire L14 of the level shifter LSIC shown in FIG. 10D, is connected with the wire L16 and the wire L18 through the via H18. The wire L16 can be electrically connected with the display panel, for example, the wire L16 is connected to the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R, for outputting the frame start signal to the display panel. The wire L18 can be electrically connected with the signal processing circuit 2, so that the signal processing circuit 2 can collect the frame start signal output by the level shifter LSIC.

[0298] The pin lead-out wire L15 of the level shifter LSIC, for example, the pin PIN8 lead-out wire L15 of the level shifter LSIC shown in FIG. 10D, is connected with the wire L17 and the wire L19 through the via H19. The wire L17 can be electrically connected with the display panel, for example, the wire L17 is connected to the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R, for outputting the clock signal to the display panel. The wire L19 can be electrically connected with the signal processing circuit 2, so that the signal processing circuit 2 can collect the clock signal output by the level shifter LSIC.

[0299] The level shifter LSIC can be arranged on a multi-layer circuit board, the wire L14 and the wire L15 can be located on the same layer of the circuit board, and the wire L16, the wire L17, the wire L18 and the wire L19 can be located on the same layer of the circuit board. The wire L14 and the wire L16 can be located on different layers of the circuit board.

[0300] The wire L14 and the wire L15 can extend along the second direction y, and the wire L16, the wire L17, the wire L18 and the wire L19 can extend along the first direction x. The extending direction of the wire L16 and the wire L17 can be opposite to the extending direction of the wire L18 and the wire L19.

[0301] FIG. 13 shows a structural schematic diagram of a display module according to another embodiment of the present disclosure.

[0302] As shown in FIG. 13, the display module 800 includes a display panel 101, a first power manager 102, a level shifter 103, a first controller 104, a sensor 112 and a detection circuit 111.

[0303] In the embodiments of the present disclosure, the sensor 112 can be at least one of a temperature sensor and a brightness sensor. The sensor 112 is configured to acquire at least one of a temperature and a display brightness value of the display panel 101. For example, the sensor 112 can be disposed close to the display panel 101. An input end of the detection circuit 111 is electrically connected to an output end of the sensor 112, and an output end of the detection circuit 111 is connected to a fifth input end of the first controller 104.

[0304] The sensor 112 acquires at least one of a temperature and a display brightness value, and transmits the acquired at least one of the temperature information and the display brightness value to the detection circuit 111 in the form of an analog signal. The detection circuit 111 converts the analog signal into a digital signal, for example, generates a digital signal based on at least one of the temperature and the display brightness value, and outputs a detection signal to the first controller 104. The first controller 104 determines the display state of the display panel 101 based on the detection signal.

[0305] For example, the sensor 112 can include a temperature sensor and a brightness sensor, and the temperature sensor and the brightness sensor are respectively disposed on the printed circuit board FPCB shown in FIG. 4A. The detection circuit 111 can also include two detection units, and the two detection units are also respectively disposed on the printed circuit board FPCB, and the two detection units are respectively electrically connected to the temperature sensor and the brightness sensor.

[0306] For example, the pin PIN9 of the first controller 104 shown in FIG. 10A can be electrically connected to the detection circuit 111 to perform gray scale detection through the first controller 104. For example, when the first controller 104 detects that the temperature is too high or the brightness attenuation, the first controller 104 sends an instruction to inform the main controller, so that the main controller obtains the information of the display abnormality.

[0307] In the embodiments of the present disclosure, in the case that the display state is normal, the temperature detected by the temperature sensor is within a specified temperature range, and the display brightness value detected by the brightness sensor is also within a specified brightness range. For example, when the temperature exceeds the specified temperature range, the digital signal output by the detection circuit 111 will also be inconsistent with the expectation, and therefore the first controller 104 can determine that the display state is abnormal based on the digital signal.

[0308] In some embodiments, the detection circuit 111 can also include a photosensitive resistor, and the display brightness value of the display module is sensed by using the photosensitive resistor. When the display brightness value changes, the resistance value of the photosensitive resistor will change accordingly, and the voltage value across the photosensitive resistor in the detection circuit 111 will also change accordingly. Based on the change of the voltage value across the photosensitive resistor, whether the display brightness value of the display module is abnormal is determined by the first controller 104.

[0309] FIG. 14 shows a circuit structure schematic diagram of a detection circuit according to an embodiment of the present disclosure. For example, FIG. 14 shows the circuit structure of the detection circuit in FIG. 13.

[0310] The pin PIN1 of the detection circuit 111 can be a power supply pin, the pin PIN4 can be a ground pin, the pins PIN2 and PIN3 can be input pins, and the pins PIN5 and PIN6 can be output pins. It should be noted that the number of pins shown in FIG. 14 is only illustrative.

[0311] In the embodiment of the present disclosure, the pin PIN2 of the detection circuit 111 can be connected with a temperature sensor. The detection circuit 111 obtains the temperature of the display panel through the pin PIN2, and converts the temperature into a digital signal. The pin PIN5 of the detection circuit 111 can be electrically connected with the first controller TCON, and the digital signal converted from the temperature is output to the first controller TCON through the pin PIN5.

[0312] The pin PIN4 of the detection circuit 111 can be connected with a brightness sensor. The detection circuit 111 obtains the display brightness value of the display panel through the pin PIN4, and converts the display brightness value into a digital signal. The pin PIN6 of the detection circuit 111 can be electrically connected with the first controller TCON, and the digital signal converted from the display brightness value is output to the first controller TCON through the pin PIN6.

[0313] The pins PIN5 and PIN6 of the detection circuit 111 can be I2C pins, and the detection circuit 111 can be connected with the pin PIN1 of the first controller TCON shown in FIG. 10A, and the digital signal is transmitted in an I2C mode.

[0314] FIG. 15 shows a connection structure schematic diagram of an adjustment circuit, a first controller and a first power manager according to an embodiment of the present disclosure.

[0315] As shown in FIG. 15, the first end of the adjustment circuit 113 is grounded, the second end of the adjustment circuit 113 is electrically connected to a pull-down node Node, the second output end of the first power manager 102 is electrically connected to the pull-down node Node, the third input end of the first controller 104 is electrically connected to the pull-down node Node, and the adjustment circuit 113 is configured to adjust the voltage of the second indication signal.

[0316] The first power manager 102, the adjustment circuit 113 and the first controller 104 are all electrically connected to the pull-down node Node. For example, the pin PIN2 of the first controller TCON shown in FIG. 10A is electrically connected to the pull-down node Node. It should be noted that the pull-down node Node does not actually exist in the circuit, and the pull-down node Node only represents the convergence point of the circuit lines.

[0317] In the embodiment of the present disclosure, the first power manager 102 writes the second indication signal to the pull-down node Node, and the adjusting circuit 113 adjusts the voltage of the pull-down node Node, so that the voltage of the second indication signal received by the first controller 104 is within the bearing range of the first controller 104.

[0318] For example, the first power manager 102 writes the second indication signal to the pull-down node Node, and at this time, the voltage of the second indication signal is greater than the bearing capacity of the first controller 104. The adjusting circuit 113 pulls down the voltage of the pull-down node Node, so that the voltage of the adjusted second indication signal is within the bearing range of the first controller 104.

[0319] FIG. 16 shows a circuit structure schematic diagram of the adjusting circuit and the first power manager according to the embodiment of the present disclosure. FIG. 16 schematically illustrates the circuit structure of the adjusting circuit 113 and the first power manager 102 of FIG. 15.

[0320] As shown in FIG. 16, the first power manager 102 includes a resistor R21, a transistor T2, and a control unit, a first end of the resistor R21 is electrically connected to a pin PIN of the first power manager 102, and a second end of the resistor R21 is electrically connected to an output signal end VL. The output signal VL output by the output signal end VL is a working voltage signal of the first power manager 102. The control electrode of the transistor T2 is electrically connected to the control unit, the first electrode of the transistor T2 is electrically connected to the first end of the resistor R21, and the second electrode of the transistor T2 is grounded.

[0321] The adjusting circuit 113 includes a resistor R22, a first end of the resistor R22 is electrically connected to the node Node, and a second end of the resistor R22 is grounded. A first end of a resistor R23 is electrically connected to the node Node, and a second end of the resistor R23 is electrically connected to the pin PIN. The resistance value of the resistor R23 is 0Ω.

[0322] When the transistor T2 is in an off state, the output signal VL passes through the resistor R21 and is written to the node Node through the pin PIN. The adjusting circuit 113 performs voltage division processing on the output signal VL from the first power manager 102 to obtain the second indication signal fault2.

[0323] For example, the voltage of the output signal VL output by the first power manager 102 is 0-5V, and the voltage of the output signal VL exceeds the bearing range 0-3.3V of the first controller 104, so the adjusting circuit 113 performs voltage division on the output signal VL and pulls down the voltage of the node Node, so that the voltage of the second indication signal fault2 received by the first controller 104 is within the bearing range of the first controller 104.

[0324] For example, the resistance of resistor R21 is 100KΩ, and the resistance of resistor R22 is 400KΩ. When the first power manager 102 is in the normal working state, the voltage of the output signal VL is 5V. At this time, the control unit controls the transistor T2 to be in the off state, and the 5V voltage of the output signal VL is written to the node Node. The resistors R21 and R22 divide the voltage of the output signal VL, and at this time, the voltage of the node Node is 5×(200 / 300) = 3.33V, and the voltage of the second indication signal fault2 is 3.3V, and the second indication signal fault2 received by the first controller 104 is high.

[0325] When the first power manager 102 is in the abnormal working state, the control unit controls the transistor T2 to be in the on state, and the ground power GND pulls down the voltage of the node Node to 0V. At this time, the voltage of the second indication signal fault2 is 0V, and the second indication signal fault2 received by the first controller 104 is low.

[0326] In some embodiments, the working voltage of the level shifter is 0-3.3V, and the voltage of the first indication signal is within the bearing range of the first controller 104, so the adjustment circuit 113 does not need to process the working voltage signal of the level shifter.

[0327] FIG. 17 shows a structural schematic diagram of a signal processing circuit and a first controller according to an embodiment of the present disclosure.

[0328] Referring to FIG. 17, the signal processing circuit 2 can include a first signal processing circuit 21 and a second signal processing circuit 22. The first signal processing circuit 21 is configured to process a direct-current digital voltage signal DVDD in a voltage signal. The second signal processing circuit 22 is configured to process a direct-current analog voltage signal AVDD in a voltage signal.

[0329] The first signal processing circuit 21 can include a first emitter follower unit 211 electrically connected to an output end of the first power manager PMIC1, and the first emitter follower unit 211 is used to collect the direct-current digital voltage signal DVDD output by the first power manager PMIC1, that is, the first emitter follower unit 211 is configured to collect the direct-current digital voltage signal DVDD and prevent the direct-current digital voltage signal DVDD from flowing back to the display circuit 1. Since the processor MCU can only bear a voltage of 0-3.3V, and the direct-current digital voltage signal DVDD is about 3.3V, the direct-current digital voltage signal DVDD can be directly connected to the first controller TCON, that is, the output end of the first signal processing circuit 21 is directly electrically connected to the input end of the first controller TCON, for example, the output end of the first signal processing circuit 21 can be the second output end of the signal processing circuit 2 described above.

[0330] The second signal processing circuit 22 can include a second emitter follower unit 221 and a second voltage dividing unit 222. The second emitter follower unit 221 is electrically connected to the output end of the first power manager PMIC1, and is configured to collect the direct current analog voltage signal AVDD, and prevent the direct current analog voltage signal AVDD from flowing back to the display circuit 1. Since the first controller TCON can only withstand a voltage of 0-3.3V, and the direct current analog voltage signal AVDD is about 16V, the direct current analog voltage signal AVDD cannot be directly connected to the first controller TCON, and needs to be divided by the second voltage dividing unit 222 before being connected to the eighth input end of the first controller TCON. For example, the output end of the second voltage dividing unit 222 can also be the second output end of the signal processing circuit 2 described above. Therefore, the second voltage dividing unit 222 is electrically connected to the output end of the second emitter follower unit 221, and is configured to adjust the voltage value of the direct current analog voltage signal AVDD to be within a first required range, i.e., to be a fixed voltage.

[0331] It should be noted that the adjustment of the second voltage dividing unit 222 to the direct current analog voltage signal AVDD can be proportional adjustment. Generally, the maximum value is less than 3.3V. In the case of a certain voltage value of the direct current analog voltage signal AVDD, the adjusted value is a fixed voltage. Of course, the voltage value of the direct current analog voltage signal AVDD is different, and the adjusted voltage value will also change. In the present disclosure, the fixed voltage is a voltage that the first controller TCON can accept, for example, the fixed voltage is greater than or equal to 0 and less than or equal to 3.3V.

[0332] In the present example embodiment, the display signals can include a frame start signal STV1, a reset signal STV2, and a plurality of clock signals CLK. Since the gate driving circuit is arranged in the array substrate 32, if the output signals from the output end of the gate driving circuit are led out to the first printed circuit board 351 for detection, the difficulty of arranging the display panel 3 and the manufacturing cost will be increased, and the output signals of the gate driving circuit are generated by the input control signals, and the input control signals of the gate driving circuit are generated on the first printed circuit board 351. Therefore, the input control signals of the gate driving circuit, i.e. the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6 of the gate driving circuit can be monitored. The frame start signal STV1 and the reset signal STV2 are fixed frequency pulse signals, and the clock signals CLK1-6 are fixed frequency square wave signals, and the monitoring of the frequencies thereof can realize the monitoring of the display signals of the display module, and further realize the monitoring of the display state of the display panel 3.

[0333] Of course, in some other example embodiments of the present disclosure, the output signals of the gate driving circuit can also be detected.

[0334] In this case, referring to FIG. 8K, the first controller TCON generates the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6 and transmits them to the level shifter LSIC, which inputs them to the gate driving circuit. Therefore, referring to FIG. 17, the signal processing circuit 2 is electrically connected to the output end of the level shifter LSIC for collecting the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6; and the processor CPU is electrically connected to the first controller TCON through the level shifter LSIC to receive the electrical signals (the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6) of the first controller TCON.

[0335] Specifically, the signal processing circuit 2 can include a third signal processing circuit 23, a fourth signal processing circuit 24, and a plurality of fifth signal processing circuits 25. The third signal processing circuit 23 is configured to process the frame start signal STV1 in the display signals, the fourth signal processing circuit 24 is configured to process the reset signal STV2 in the display signals, and the fifth signal processing circuit 25 is configured to process the clock signals CLK in the display signals.

[0336] The third signal processing circuit 23 can include a third emitter follower unit 231 and a third voltage dividing unit 232. The third emitter follower unit 231 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the frame start signal STV1 in the display signal and prevent the frame start signal STV1 from flowing back to the display circuit 1. Since the first controller TCON can only withstand a voltage of 0-3.3V, although the frame start signal STV1 is a fixed frequency pulse signal, it is realized by voltage jump. Therefore, in the case that the high level of the frame start signal STV1 is high, the processor MCU cannot be directly connected, and the third voltage dividing unit 232 is needed to divide the voltage before connecting to the seventh input end of the first controller TCON. Therefore, the third voltage dividing unit 232 is electrically connected to the output end of the third emitter follower unit 231, and is configured to adjust the voltage value of the frame start signal STV1 to be within a second required range, i.e., to be a fixed voltage. Moreover, the third voltage dividing unit 232 does not affect the frequency of the frame start signal STV1 during the adjustment of the voltage value of the frame start signal STV1.

[0337] It should be noted that the adjustment of the voltage value of the frame start signal STV1 by the third voltage dividing unit 232 can be proportional adjustment. Generally, the maximum value is less than 3.3V. In the case that the voltage value of the frame start signal STV1 is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the frame start signal STV1 is different, and the adjusted voltage value will also change.

[0338] The fourth signal processing circuit 24 can include a fourth emitter follower unit 241 and a fourth voltage dividing unit 242. The fourth emitter follower unit 241 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the reset signal STV2 in the display signal and prevent the reset signal STV2 from flowing back to the display circuit 1. Since the first controller TCON can only withstand a voltage of 0-3.3V, although the reset signal STV2 is a fixed-frequency pulse signal, it is realized by voltage jump. Therefore, in the case that the high level of the reset signal STV2 is high, the reset signal STV2 cannot be directly connected to the seventh input end of the first controller TCON, and needs to be connected to the seventh input end of the first controller TCON after being divided by the fourth voltage dividing unit 242. Therefore, the fourth voltage dividing unit 242 is electrically connected to the output end of the fourth emitter follower unit 241, and is configured to adjust the voltage value of the reset signal STV2 to be within a third required range, i.e., to be a fixed voltage. Moreover, the fourth voltage dividing unit 242 does not affect the frequency of the reset signal STV2 during the adjustment of the voltage value of the reset signal STV2.

[0339] It should be noted that the adjustment of the voltage value of the reset signal STV2 by the fourth voltage dividing unit 242 can be proportional adjustment. Generally, the maximum value is less than 3.3V. In the case that the voltage value of the reset signal STV2 is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the reset signal STV2 is different, and the adjusted voltage value will also change.

[0340] The fifth signal processing circuit 25 includes a fifth emitter follower unit 251 and a fifth voltage dividing unit 252. The fifth emitter follower unit 251 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the clock signal CLK in the display signal and prevent the clock signal CLK from flowing back to the display circuit 1. Since the first controller TCON can only withstand a voltage of 0-3.3V, and the clock signal CLK is about -4V-32V, the clock signal CLK cannot be directly connected to the first controller TCON, and needs to be connected to the first controller TCON after being divided by the fifth voltage dividing unit 252. Therefore, the fifth voltage dividing unit 252 is electrically connected to the output end of the fifth emitter follower unit 251, and is configured to adjust the voltage value of the clock signal CLK to be within a fourth required range, i.e., to be a fixed voltage. Moreover, the fifth voltage dividing unit 252 does not affect the frequency of the clock signal CLK during the adjustment of the voltage value of the clock signal CLK.

[0341] It should be noted that the voltage value adjustment of the fifth voltage dividing unit 252 to the clock signal CLK can be proportional adjustment, and generally the minimum value is greater than 0V and the maximum value is less than 33V.

[0342] The number of the fifth signal processing circuit 25 can be set according to the number of the clock signal CLK, and the number of the fifth signal processing circuit 25 is equal to the number of the clock signal CLK, one fifth signal processing circuit 25 collects one clock signal CLK, for example, in the case of setting six clock signals CLK, six fifth signal processing circuits 25 can be set; in the case of setting ten clock signals CLK, ten fifth signal processing circuits 25 can be set. Only two fifth signal processing circuits 25 are shown in FIG. 17, and the middle part is replaced by an ellipsis.

[0343] For example, the output terminals of the third voltage dividing unit 232, the fourth voltage dividing unit 242 and the fifth voltage dividing unit 252 can be the first output terminals of the signal processing circuit 2 described above.

[0344] In the present example embodiment, the backlight signal can include the cathode voltage signal LED- of each sub-region of the backlight module 31. Since the cathode voltage signals LED- in the same sub-region are the same, for example, in the case of setting the backlight module 31 as only one sub-region, the backlight signal can be one cathode voltage signal LED-. In the case of setting the backlight module 31 as only two sub-regions, the backlight signal can be two cathode voltage signals LED-. Similarly, in the case of setting the backlight module 31 as three or more sub-regions, the backlight signal can be three or more cathode voltage signals LED-.

[0345] In this case, the signal processing circuit 2 is electrically connected to the backlight driving circuit of the backlight module 31, and is used to collect the cathode voltage signal LED- of each sub-region.

[0346] Specifically, referring to FIG. 17, the signal processing circuit 2 can include a sixth signal processing circuit 26, and the sixth signal processing circuit 26 is configured to process the cathode voltage signal LED- in the backlight signal.

[0347] The sixth signal processing circuit 26 can include a sixth emitter follower unit 261 electrically connected to the backlight driving circuit of the backlight module 31, specifically, the sixth emitter follower unit 261 is electrically connected to the backlight converter BLU-Con of the backlight driving circuit of the backlight module 31. The sixth emitter follower unit 261 is configured to collect the cathode voltage signal LED- of each sub-zone of the backlight module 31, i.e., the sixth emitter follower unit 261 is configured to collect the cathode voltage signal LED- in the backlight signal and prevent the cathode voltage signal LED- from flowing back to the display circuit 1. Since the cathode voltage signal LED- is usually less than 1V, the cathode voltage signal can be directly connected to the first controller TCON, i.e., the output end of the sixth signal processing circuit 26 is directly electrically connected to the ninth input end of the first controller TCON. For example, the output end of the sixth signal processing circuit 26 can be the third output end of the signal processing circuit 2 described above.

[0348] The number of the sixth signal processing circuits 26 can be set according to the number of the cathode voltage signals, i.e., the number of the sixth signal processing circuits 26 can be equal to the number of the sub-zones of the backlight module 31. For example, when the backlight module 31 is provided with two sub-zones, two sixth signal processing circuits 26 are needed to correspondingly collect the cathode voltage signals of the two sub-zones; when the backlight module 31 is provided with three or more sub-zones, three or more sixth signal processing circuits 26 are needed to correspondingly collect the cathode voltage signals of the three or more sub-zones.

[0349] The monitoring circuit can further include a first analog-to-digital conversion unit ADC1, a second analog-to-digital conversion unit ADC2, a third analog-to-digital conversion unit ADC3, a first timing unit Timer1, a second timing unit Timer2, a processor CPU, and a plurality of third timing units Timer3. In the example embodiment, referring to FIG. 17, the first analog-to-digital conversion unit ADC1, the second analog-to-digital conversion unit ADC2, the third analog-to-digital conversion unit ADC3, the first timing unit Timer1, the second timing unit Timer2, the processor CPU, and the plurality of third timing units Timer3 can be included in the first controller TCON. Of course, in some other example embodiments of the present disclosure, the first analog-to-digital conversion unit ADC1, the second analog-to-digital conversion unit ADC2, the third analog-to-digital conversion unit ADC3, the first timing unit Timer1, the second timing unit Timer2, the processor CPU, and the plurality of third timing units Timer3 can also be separately provided as one component respectively; and according to different signals to be monitored, one, two or more of them can be selected.

[0350] The first analog-to-digital conversion unit ADC1 is electrically connected to the output end of the first emitter follower unit 211, and is configured to convert the direct-current digital voltage signal DVDD into a digital signal. The processor CPU is electrically connected to the output end of the first analog-to-digital conversion unit ADC1, and is configured to output the display state of the display panel as a first abnormal display state, in which the direct-current digital voltage signal DVDD has a first set value. That is, the processor CPU is configured to determine whether the voltage of the direct-current digital voltage signal DVDD meets the first set value, and if so, determine that the display state of the display panel 101 is the first abnormal display state. The first set value is less than 3.0 V or greater than 3.6 V.

[0351] The second analog-to-digital conversion unit ADC2 is electrically connected to the output end of the second voltage dividing unit 222, and is configured to convert the direct-current analog voltage signal AVDD into a digital signal. The processor CPU is electrically connected to the output end of the second analog-to-digital conversion unit ADC2, and is configured to output the display state of the display panel as a second abnormal display state, in which the direct-current analog voltage signal AVDD has a second set value. That is, the processor CPU is configured to determine whether the voltage of the direct-current analog voltage signal AVDD meets the second set value, and if so, determine that the display state of the display panel 101 is the second abnormal display state. The second set value is less than 15 V or greater than 17 V.

[0352] The third analog-to-digital conversion unit ADC3 is electrically connected to the output end of the sixth emitter follower unit 261, and is configured to convert the cathode voltage signal LED- into a digital signal. The processor CPU is electrically connected to the output end of the third analog-to-digital conversion unit ADC3, and is configured to output the display state of the display panel as a sixth abnormal display state, in which the cathode voltage signal LED- has a sixth preset value. That is, the processor CPU is configured to determine whether the cathode voltage signal LED- meets the sixth preset value, and if so, determine that the display state of the display panel 101 is the sixth abnormal display state. The sixth preset value is less than 0.25 V or greater than 0.5 V.

[0353] The first timing unit Timer1 is electrically connected to the output end of the third voltage dividing unit 232; the first timing unit Timer1 is used to identify the frequency of the frame start signal STV1. The processor CPU is electrically connected to the output end of the first timing unit Timer1, and the processor CPU is configured to output the display state of the display panel as a third abnormal display state, in which the frequency of the frame start signal STV1 has a third set value; that is, the processor CPU is configured to determine whether the frequency of the frame start signal STV1 meets the third set value, and if so, it is determined that the display state of the display panel 3 is the third abnormal display state. The third set value is less than 58 Hz or greater than 62 Hz.

[0354] The second timing unit Timer2 is electrically connected to the output end of the fourth voltage dividing unit 242; the second timing unit Timer2 is used to identify the frequency of the reset signal STV2. The processor CPU is electrically connected to the output end of the second timing unit Timer2, and the processor CPU is configured to output the display state of the display panel as a fourth abnormal display state, in which the frequency of the reset signal STV2 has a fourth set value; that is, the processor CPU is configured to determine whether the frequency of the reset signal STV2 meets the fourth set value, and if so, it is determined that the display state of the display panel 3 is the fourth abnormal display state. The fourth set value is less than 56 Hz or greater than 60 Hz, or the fourth set value is less than 1.5 kHz or greater than 1.9 kHz.

[0355] The plurality of third timing units Timer3 are electrically connected to the output ends of the plurality of fifth voltage dividing units 252 one by one; the third timing unit Timer3 is used to identify the frequency of the clock signal CLK. The processor CPU is electrically connected to the output ends of the plurality of third timing units Timer3, and the processor CPU is configured to output the display state of the display panel as a fifth abnormal display state, in which the frequency of the clock signal CLK has a fifth set value; that is, the processor CPU is configured to determine whether the frequency of the clock signal CLK meets the fifth set value, and if not, it is determined that the display state of the display panel 101 is the fifth abnormal display state. The fifth set value is less than 22.5 kHz or greater than 22.9 kHz.

[0356] The processor CPU is configured to determine whether the voltage signal, the display signal, and the backlight signal in the working signal are all normal, and if so, it is determined that the display state of the display panel 101 is a normal display state; if not, the display state of the display panel 101 is an abnormal display state, which can include a plurality of types, as described above.

[0357] Further, the processor CPU is configured to judge whether all of the working signals satisfy the following conditions: the DC digital voltage signal DVDD is greater than or equal to 3.0 V and less than or equal to 3.6 V; the DC analog voltage signal AVDD is greater than or equal to 15 V and less than or equal to 17 V; the frame start signal STV1 is greater than or equal to 58 Hz and less than or equal to 62 Hz; the reset signal STV2 is greater than or equal to 56 Hz and less than or equal to 60 Hz, or the reset signal STV2 is greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz; the clock signal CLK is greater than or equal to 22.5 kHz and less than or equal to 22.9 kHz; and the cathode voltage signal LED- is greater than or equal to 0.25 V and less than or equal to 0.5 V, and if so, determine that the display state of the display panel 101 is a normal display state.

[0358] The specific judgment process of the processor CPU is described in the monitoring method, which will not be repeated here.

[0359] The emitter follower units (the first emitter follower unit 211, the second emitter follower unit 221, the third emitter follower unit 231, the fourth emitter follower unit 241, the fifth emitter follower unit 251, and the sixth emitter follower unit 261) have an isolation effect, i.e., prevent signal backflow to the display circuit 1, and ensure that the signal does not affect the normal operation of the original display circuit after being connected to the monitoring circuit. The isolation of the two circuits is achieved by using the high input impedance characteristic of the emitter follower unit. In addition, the output voltage of the emitter follower unit is equal to the size of its input voltage, and the signal parameter acquisition can be accurately achieved.

[0360] Of course, in some other example embodiments of the present disclosure, the signal processing circuit 2 can not be provided, so that the processor MCU is directly electrically connected with the display circuit.

[0361] FIG. 18 shows a structural schematic diagram of a signal processing circuit and a first controller according to another embodiment of the present disclosure.

[0362] Specifically, referring to FIGS. 8O and 18, the signal processing circuit 2 can include a seventh signal processing circuit 27 configured to process the first error identification signal LS-F. The seventh signal processing circuit 27 can include a seventh emitter follower unit 271 and a seventh voltage dividing unit 272; the seventh emitter follower unit 271 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the first error identification signal LS-F and prevent the first error identification signal LS-F from backflowing to the display circuit; and the seventh voltage dividing unit 272 is electrically connected to the output end of the seventh emitter follower unit 271, and is configured to adjust the voltage value of the first error identification signal LS-F to a fixed voltage, i.e., the seventh voltage dividing unit 272 is configured to adjust the voltage value of the first error identification signal LS-F to a required range.

[0363] By monitoring one first error identification signal LS-F instead of monitoring how many clock signals CLK, that is, no matter how many clock signals CLK are set, only one first error identification signal LS-F is monitored, so that the number of signal processing circuits used is reduced, the interface of the first controller TCON is also reduced, the hardware cost is reduced, and the area of the first printed circuit board 351 can also be set smaller.

[0364] In this case, since the first error identification signal LS-F changes from a normal high level to a low level, it is not necessary to accurately obtain the voltage of the first error identification signal LS-F, and a timing unit is not needed to accurately collect the frequency of the clock signal CLK. Therefore, the first controller TCON can include a first input port GPIO1. The first input port GPIO1 is electrically connected to the output end of the seventh voltage dividing unit 272.

[0365] The processor CPU is electrically connected to the output end of the seventh voltage dividing unit 272, specifically, the processor CPU is electrically connected to the first input port GPIO1; the processor CPU judges the display state of the display panel 101 according to whether the first error identification signal LS-F is received, that is, the processor CPU is configured to judge whether the first error identification signal LS-F is received, and if so, the display state of the display panel 101 is judged to be abnormal display caused by the level shifter LSIC being abnormal. The specific process is described in the monitoring method, which will not be repeated here.

[0366] In some other example embodiments of the present disclosure, the backlight module 31 of the highlight display module has more partitions, for example, the number of partitions of the backlight module 31 of Local Dimming (area dimming) is usually several tens of partitions. If the cathode voltage signal LED- of each partition is monitored, the number of signal processing circuits used will increase, the interface of the first controller TCON also needs to be increased, thereby increasing the hardware cost, and increasing the area of the first printed circuit board 351.

[0367] In this case, the specific conditions of the voltage signal and the first signal processing circuit 21 and the second signal processing circuit 22 included in the signal processing circuit 2 are the same as those in the above example embodiments, and thus will not be repeated here.

[0368] In this case, the display circuit can further include a backlight driving controller LED-D, an output terminal of the backlight driving controller LED-D being electrically connected to an input terminal of the processor CPU and an input terminal of the backlight driving circuit, and the output terminal of the backlight driving controller LED-D being electrically connected to the backlight converter BLU-Con; the backlight driving controller LED-D being configured to output the second error identification signal LED-DF or the backlight signal according to a working state of the backlight driving controller LED-D.

[0369] The input terminal of the processor CPU is electrically connected to the output terminal of the backlight driving controller LED-D and to the output terminal of the first controller TCON through the level converter LSIC, and the processor CPU is configured to determine the display state of the display panel by judging whether the second error identification signal LED-DF is received.

[0370] The monitoring circuit further includes a signal processing circuit 2 electrically connected between the backlight driving controller LED-D and the processor CPU, for processing the second error identification signal LED-DF.

[0371] Specifically, referring to FIGS. 8O and 18, the signal processing circuit 2 can include a sixth signal processing circuit 26, which can include a sixth emitter follower unit 261 electrically connected to the output terminal of the backlight driving controller LED-D, specifically, to the backlight converter BLU-Con of the backlight driving circuit of the backlight module 31. The sixth emitter follower unit 261 is configured to collect the second error identification signal LED-DF.

[0372] In the case of over temperature protection (OTP) of the backlight driving controller LED-D, open circuit or short circuit of the backlight source, the second error identification signal LED-DF can be triggered, and the second error identification signal LED-DF changes from a high level in normal working state to a low level.

[0373] By monitoring one second error identification signal LED-DF instead of multiple cathode voltage signals LED-, no matter how many partitions the backlight module 31 has or how many backlight driving controllers LED-D are used, the error signals of the respective backlight driving controllers LED-D can be connected together to form one second error identification signal LED-DF, so that only one second error identification signal LED-DF needs to be monitored, the number of signal processing circuits used is reduced, the interface of the first controller TCON is also reduced, the hardware cost is reduced, and the area of the first printed circuit board 351 can also be set smaller.

[0374] In this case, since the second error identification signal LED-DF changes from the high level of normal operation to the low level, the voltage of the second error identification signal LED-DF does not need to be accurately obtained, and an analog-digital conversion unit is not needed to accurately collect the voltage of the second error identification signal LED-DF. Therefore, the first controller TCON can include a second input port GPIO2, which is electrically connected to the output end of the sixth emitter follower unit 261.

[0375] The processor CPU is configured to determine the display state of the display panel 3 by judging whether the second error identification signal LED-DF is received; the processor CPU is electrically connected to the second input port GPIO2, and the processor CPU determines whether the backlight is normal or abnormal to cause abnormal display according to the judgment of whether the second error identification signal is received. The specific process is described in the monitoring method, which will not be described here.

[0376] It should be noted that in the example embodiment of monitoring the second error identification signal LED-DF, the clock signal CLK can be monitored; of course, in the example embodiment of monitoring the first error identification signal LS-F, the cathode voltage signal LED- of each sub-area of the backlight module 31 can be monitored.

[0377] In addition, the output end UART of the first controller TCON can be connected to the SoC mainboard, and the monitoring result can be transmitted to the SoC mainboard, so that the SoC mainboard knows the display state in the first time, and the technical effect of automatically monitoring the display state of the display module in real time is achieved. Moreover, the SoC mainboard can also be connected to the control center, which can be a customer after-sales platform, a railway central control platform, etc. For example, the SoC mainboard can upload the monitoring result to the cloud platform and issue abnormal information to the after-sales personnel, so that the display can be repaired and replaced in the first time after the display is abnormal, avoiding the bad use influence on consumers.

[0378] In some example embodiments of the present disclosure, referring to FIG. 4B and FIG. 8K, the monitoring circuit can further include a second power manager PMIC2, which is electrically connected to the monitoring circuit and is configured to supply power to the monitoring circuit; for example, the second power manager PMIC2 is electrically connected to the signal processing circuit 2 and the first controller TCON, and is configured to supply power to the signal processing circuit 2 and the first controller TCON, so that the signal processing circuit 2 and the first controller TCON are not powered by the same power supply as the level shifter LSIC. In the case of abnormality of the first power manager PMIC1, the normal operation of the signal processing circuit 2 and the first controller TCON will not be affected.

[0379] A jumper cap is also arranged on the first printed circuit board 351. The on-off of the analog signal can be simulated by plugging and unplugging the jumper cap. The first controller TCON can be used to monitor the state of each analog signal in real time.

[0380] Based on the same inventive concept, the example embodiments of the present disclosure provide a monitoring circuit of a display module. The display module can include a backlight module 31, a display panel 101, and a display circuit. The display circuit can include a main controller, a first controller TCON, a backlight driving controller LED-D, and a level shifter LSIC. The input end of the first controller TCON is electrically connected to the output end of the main controller. The output end of the first controller TCON is electrically connected to the input end of the level shifter LSIC. The output end of the backlight driving controller LED-D is electrically connected to the input end of the backlight module 31. The first controller TCON is configured to output a display signal required by the display panel or a first error identification signal LS-F according to the working state of the level shifter LSIC. The backlight driving controller LED-D is configured to output a second error identification signal LED-DF or a backlight signal according to the working state of the backlight driving controller LED-D.

[0381] In this case, the monitoring circuit can include a processor CPU. The input end of the processor CPU is electrically connected to the output end of the backlight driving controller LED-D and electrically connected to the output end of the first controller TCON through the level shifter LSIC. The processor CPU is configured to determine the display state of the display panel 101 by judging whether the first error identification signal LS-F and / or the second error identification signal LED-DF are received. That is, the display state of the display panel 101 can be determined by the first error identification signal LS-F and the second error identification signal LED-DF together or by any one of the first error identification signal LS-F and the second error identification signal LED-DF. The generation principle and judgment standard of the first error identification signal LS-F and the second error identification signal LED-DF are described in detail above, and will not be repeated here.

[0382] Based on the same inventive concept, the example embodiments of the present disclosure provide a monitoring method of a display module. The monitoring method can be used in any one of the monitoring circuits described above. The monitoring method can include the following steps: collecting a display signal and / or a voltage signal of a display circuit, judging whether a display panel displays normally and the abnormal type of abnormal display according to the display signal and / or the voltage signal, and outputting the judgment result.

[0383] The steps of the monitoring method are described below. FIG. 19 shows a flowchart of a monitoring method of a display module according to an embodiment of the present disclosure.

[0384] Referring to FIG. 19, when the system (i.e., the display device) is powered on stably, the voltage signals of the display circuit are collected. Specifically, the voltage signals can include a direct-current analog voltage signal AVDD and a direct-current digital voltage signal DVDD. Therefore, the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD of the display circuit are collected.

[0385] If the voltage signals are within the set ranges, it is determined that the voltage is normal; that is, if the voltage of the direct-current analog voltage signal AVDD meets the first preset value, and the voltage of the direct-current analog voltage signal AVDD meets the second preset value, it is determined that the voltage is normal and output.

[0386] Specifically, the first preset value of the direct-current analog voltage signal AVDD can be greater than or equal to 15V and less than or equal to 17V. The second preset value of the direct-current digital voltage signal DVDD can be greater than or equal to 3V and less than or equal to 3.6V. That is, the voltage of the collected direct-current analog voltage signal AVDD is greater than or equal to 15V and less than or equal to 17V, and the voltage of the collected direct-current digital voltage signal DVDD is greater than or equal to 3V and less than or equal to 3.6V, it is determined that the voltage is normal. That is, the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD are within the respective set ranges, and it is determined that the voltage is normal.

[0387] If the voltage signals are not within the set ranges, it is determined that the voltage is abnormal and output; that is, if the voltage of the direct-current digital voltage signal DVDD does not meet the first preset value, and / or the voltage of the direct-current analog voltage signal AVDD does not meet the second preset value, it is determined that the voltage is abnormal and output.

[0388] Specifically, the voltage of the collected direct-current analog voltage signal AVDD is less than 15V or greater than 17V, or the value of the collected direct-current digital voltage signal DVDD is less than 3V or greater than 3.6V, it is determined that the voltage is abnormal and output. That is, as long as one of the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD is not within the respective set ranges, it is determined that the voltage is abnormal and output; of course, if the voltage of the direct-current digital voltage signal DVDD does not meet the first preset value, and the voltage of the direct-current analog voltage signal AVDD does not meet the second preset value, it is also determined that the voltage is abnormal and output; for example, the code 0x01 in hexadecimal can be output as the code of voltage abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0389] In addition, in some other example embodiments of the present disclosure, only one of the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD can be monitored.

[0390] It should be noted that, since the voltage value of the direct-current analog voltage signal AVDD is adjusted to a fixed voltage by the second voltage dividing unit 222, the fixed voltage is greater than or equal to 0 and less than or equal to 3.3V, and the second preset value can be greater than or equal to 3V and less than or equal to 3.6V, therefore, a mapping table between the adjusted value and the actual value of the direct-current analog voltage signal AVDD can be established, and the adjusted value of the direct-current analog voltage signal AVDD can be mapped to the actual value before the comparison between the direct-current analog voltage signal AVDD and the second preset value is performed.

[0391] Referring to FIG. 19, after determining that the voltage is normal, the display signal of the display circuit is collected; since the voltage is abnormal, the display signal is also abnormal, therefore, it is unnecessary to collect the display signal in the case of determining that the voltage is abnormal, and the collection of the display signal is needed only in the case of determining that the voltage is normal. The display signal can include a frame start signal STV1, a reset signal STV2 and a plurality of clock signals CLK, therefore, the frame start signal STV1, the reset signal STV2 and the plurality of clock signals CLK of the display circuit are collected.

[0392] If the display signal is within the set range, it is determined that the driving is normal; that is, if the frequency of the frame start signal STV1 meets the third preset value, the frequency of the reset signal STV2 meets the fourth preset value, and the frequency of the plurality of clock signals CLK meets the fifth preset value, it is determined that the driving is normal and output.

[0393] Specifically, the third preset value of the frame start signal STV1 can be greater than or equal to 58Hz and less than or equal to 62Hz. The fourth preset value of the reset signal STV2 can be greater than or equal to 56Hz and less than or equal to 60Hz, or the fourth preset value of the reset signal STV2 can be greater than or equal to 1.5kHz and less than or equal to 1.9kHz. The fifth preset value of the clock signal CLK can be greater than or equal to 22.5kHz and less than or equal to 22.9kHz. That is, the value of the collected frame start signal STV1 is greater than or equal to 58Hz and less than or equal to 62Hz, the value of the collected reset signal STV2 is greater than or equal to 56Hz and less than or equal to 60Hz, or greater than or equal to 1.5kHz and less than or equal to 1.9kHz, and the value of the collected clock signal CLK is greater than or equal to 22.5kHz and less than or equal to 22.9kHz, then it is determined that the driving is normal. That is, the frame start signal STV1, the reset signal STV2 and the plurality of clock signals CLK are all within the respective set ranges, so that it is determined that the driving is normal.

[0394] If the display signal is not within the set range, it is determined that the driving is abnormal and output; that is, if the frequency of the frame start signal STV1 does not meet the third preset value, and / or the frequency of the reset signal STV2 does not meet the fourth preset value, and / or the frequency of the plurality of clock signals CLK does not meet the fifth preset value, it is determined that the driving is abnormal and output.

[0395] Specifically, if the value of the collected frame start signal STV1 is less than 58 Hz or greater than 62 Hz, or the value of the collected reset signal STV2 is less than 56 Hz or greater than 60 Hz, or less than 1.5 kHz or greater than 1.9 kHz, or the value of the collected clock signal CLK is less than 22.5 kHz or greater than 22.9 kHz, it is determined that the driving is abnormal and output. That is, as long as one of the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK is not within the respective corresponding set range, it is determined that the driving is abnormal and output; of course, it can also be that two or more of the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK are not within the respective corresponding set range, it is determined that the driving is abnormal and output; for example, the hexadecimal code 0x02 can be output as the code of the driving abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0396] In addition, in some other example embodiments of the present disclosure, only one, two or more of the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK can be monitored.

[0397] In some other example embodiments of the present disclosure, the monitoring method can further include: after determining that the voltage is normal, collecting a first error identification signal LS-F of the display circuit; if the first error identification signal LS-F is collected, it is determined that the driving is abnormal and output.

[0398] In this case, the display signal can include the frame start signal STV1 and the reset signal STV2, and the set range and judgment standard of the frame start signal STV1 and the reset signal STV2 have been described in detail above, so they will not be repeated here. The principle of generating the first error identification signal LS-F has also been described in detail above, so it will not be repeated here.

[0399] Specifically, if the frequency of the collected frame start signal STV1 is greater than or equal to 58 Hz and less than or equal to 62 Hz, and the frequency of the collected reset signal STV2 is greater than or equal to 56 Hz and less than or equal to 60 Hz, or greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz, and the first error identification signal LS-F is not collected, it is determined that the driving is normal. That is, only when the frame start signal STV1, the reset signal STV2, and the first error identification signal LS-F all satisfy the above conditions, it is determined that the driving is normal.

[0400] If the frequency of the collected frame start signal STV1 is less than 58 Hz or greater than 62 Hz, and / or, the frequency of the collected reset signal STV2 is less than 56 Hz or greater than 60 Hz, or less than 1.5 kHz or greater than 1.9 kHz, and / or, the first error identification signal LS-F is collected, it is determined that the driving is abnormal and output. That is, as long as one of the frame start signal STV1, the reset signal STV2, and the first error identification signal LS-F does not satisfy the above conditions, it is determined that the driving is abnormal and output, for example, the hexadecimal code 0x02 can be output as the code of the driving abnormality; of course, it can also be output by binary code, and can also be directly output by Chinese or English, which is not limited here.

[0401] In addition, in some other example embodiments of the present disclosure, when the first error identification signal LS-F of the display circuit is collected, the display signal can include one of the frame start signal STV1 and the reset signal STV2.

[0402] Referring to FIG. 19, the monitoring method can further include collecting a backlight signal of the display circuit, and determining whether the display panel 101 normally displays and an abnormal type of abnormal display according to the backlight signal, and outputting the determination result.

[0403] Specifically, the voltage signal is collected, and at the same time, the backlight signal of the display circuit 1 is collected; the backlight signal can include the cathode voltage signal LED- of each sub-zone of the backlight module 31, and therefore, the cathode voltage signal LED- of each sub-zone of the backlight module 31 of the display circuit is collected.

[0404] If the cathode voltage signal LED- satisfies the sixth preset value, it is determined that the backlight is normal; the sixth preset value of the backlight signal can be greater than or equal to 0.25 V and less than or equal to 0.5 V. That is, if the values of the collected cathode voltage signals LED- of each sub-zone of the backlight module 31 are all greater than or equal to 0.25 V and less than or equal to 0.5 V, it is determined that the backlight is normal.

[0405] If the cathode voltage signal LED- does not meet the sixth preset value, it is determined that the backlight is abnormal and output; that is, as long as the value of the cathode voltage signal LED- of each sub-area of the backlight module 31 collected is less than 0.25V or greater than 0.5V, it is determined that the backlight is abnormal and output, for example, in the case where the backlight module 31 is provided with three sub-areas, as long as the value of the cathode voltage signal LED- of one sub-area is less than 0.25V or greater than 0.5V, it is determined that the backlight is abnormal and output, for example, the code 0x04 in hexadecimal can be output as the code of the backlight abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0406] It should be noted that in the case where the backlight module 31 has only one sub-area, the cathode voltage signal LED- of one sub-area can be determined; in the case where the backlight module 31 has two or more sub-areas, the cathode voltage signals LED- of all sub-areas need to be determined, and as long as the cathode voltage signal LED- of one sub-area does not meet the set range, it is determined that the backlight is abnormal and output.

[0407] In some other example embodiments of the present disclosure, the monitoring method can further include collecting a second error identification signal LED-DF of the display circuit, and determining whether the display panel 3 is normally displayed and the abnormal type of the abnormal display according to the second error identification signal LED-DF, and outputting the determination result.

[0408] Specifically, the second error identification signal LED-DF is collected at the same time as the voltage signal; if the second error identification signal LED-DF is not collected, it is determined that the backlight is normal; if the second error identification signal LED-DF is collected, it is determined that the backlight is abnormal and output, for example, the code 0x04 in hexadecimal can be output as the code of the backlight abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0409] In the case where the backlight module 31 is provided with two or more sub-areas, only one second error identification signal LED-DF needs to be collected.

[0410] When the voltage is determined to be normal, the driving is determined to be normal, and the backlight is determined to be normal, the display is output to be normal, for example, the code 0xFF in hexadecimal can be output as the code of the normal display; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0411] Of course, in some other example embodiments of the present disclosure, in the case where only one or two of the voltage signal, the display signal, and the backlight signal is monitored, as long as the monitored one or two is normal, the display is output to be normal.

[0412] Referring to FIG. 19, in some example embodiments of the present disclosure, the monitoring method can further include setting the refresh rate of the built-in self-test display mode to a set value different from the refresh rate of normal display, for example, setting the refresh rate (STV1 special frequency) of the built-in self-test display mode to 70 Hz, 65 Hz, 50 Hz, or 48 Hz, etc. when the refresh rate of normal display is 60 Hz.

[0413] The built-in self-test (BIST) display mode can be used for abnormality detection in the use stage of the display module, and automatically detects the running state of a large-area screen. The built-in self-test display mode is generally a black picture or a black-and-white red-green-blue cycle picture.

[0414] After determining that the voltage is normal, the frame start signal STV1 is collected, that is, the refresh rate of the built-in self-test display mode is identified through the frame start signal STV1.

[0415] If the frame start signal (STV1 special frequency) is equal to the set value, it is determined that the built-in self-test is abnormal due to signal abnormality provided by the SoC mainboard and is output; if the frame start signal (STV1 special frequency) is not equal to the set value, it is determined that the built-in self-test is normal.

[0416] Referring to FIG. 19, in the case of built-in self-test determination, when it is determined that the voltage is normal, the built-in self-test is normal, the driving is normal, and the backlight is normal, the display is normal is output, for example, the code 0xFF in hexadecimal can be output as the code of the normal display; of course, it can also be output through a binary code, and can also be directly output through Chinese or English, which is not limited here.

[0417] The monitoring method can further include adjusting the voltage value of the above-mentioned signals to the required range after collecting the above-mentioned signals of the display circuit. Since the first controller TCON can only withstand a voltage of 0-3.3V, the voltage value of the collected signals needs to be adjusted to the required range to avoid damage to the first controller TCON.

[0418] It should be noted that the continuous collection time of various signals in the above-mentioned signals is about 5 seconds, and the collection and determination are performed simultaneously; after completing a round of collection and determination, the next round of collection and determination is performed, that is, after completing the collection and determination of the voltage signal, the display signal (voltage signal and constant time do not need to be collected and determined), and the backlight signal, the next round of collection and determination of the voltage signal, the display signal, and the backlight signal is performed. Moreover, the above-mentioned data is only an example for illustrating and explaining the logic, different data can be set according to different display modules, and the specific values are also different after being divided by the voltage dividing unit, which will not be described one by one here.

[0419] FIG. 20 shows a flowchart of a monitoring method according to an embodiment of the present disclosure.

[0420] As shown in FIG. 20, the monitoring method includes operation S201 to operation S213.

[0421] In operation S201, the system is powered on.

[0422] In operation S202, it is determined whether the second indication signal is abnormal. If yes, operation S206 is performed.

[0423] In operation S203, it is determined whether the first indication signal is abnormal. If yes, operation S210 is performed.

[0424] In operation S204, it is determined whether the third indication signal is abnormal. If yes, operation S211 is performed.

[0425] In operation S205, it is determined whether the video signal is abnormal. If yes, operation S212 is performed. If no, operation S213 is performed.

[0426] In operation S206, the first power manager is restarted.

[0427] In operation S207, the number of restarts is counted plus 1.

[0428] In operation S208, it is determined whether the number of restarts is greater than 5. If yes, operation S209 is performed; if no, operation S202 is performed.

[0429] In operation S209, the first controller feeds back 0x01 instruction to the main controller.

[0430] In operation S22, the first controller feeds back 0x02 instruction to the main controller.

[0431] In operation S211, the first controller feeds back 0x03 instruction to the main controller.

[0432] In operation S212, the first controller feeds back 0x04 instruction to the main controller.

[0433] In operation S213, the first controller feeds back 0xFF instruction to the main controller.

[0434] In the embodiment of the present disclosure, after the display module is powered on, operation S202 to operation S205 can be performed simultaneously. If the first indication signal, the second indication signal, the third indication signal and the video signal are all normal, the first controller feeds back 0xFF instruction to the main controller to inform the front-end system that the display module is displayed normally, and enters the next round of monitoring. For example, the monitoring result is fed back once every 5s, so as to realize automatic monitoring.

[0435] When the first indication signal is monitored to be abnormal, the first controller feeds back a 0x02 instruction to the main controller to inform the front-end system level converter is abnormal. When the third indication signal is monitored to be abnormal, the first controller feeds back a 0x03 instruction to the main controller to inform the front-end system backlight driver is abnormal. When the video signal is monitored to be abnormal, the first controller feeds back a 0x04 instruction to the main controller to inform the front-end system level converter is abnormal and enters the BIST mode.

[0436] When the second indication signal is monitored to be abnormal, the first controller restarts the first power manager and counts the number of restarts. If the number of restarts exceeds 5 times and the abnormality still exists, the first controller feeds back a 0x01 instruction to the main controller to inform the front-end system first power manager is abnormal.

[0437] FIG. 21 shows a structural diagram of a display device according to an embodiment of the present disclosure.

[0438] As shown in FIG. 21, the display device 10 includes a main controller 11 and a display module 800.

[0439] In the embodiment of the present disclosure, the display module 800 is electrically connected to the main controller 11. The display module 800 receives instructions and a video signal from the main controller 11, converts the video signal into a display signal based on the instructions, and sends a display state based on the display signal and a voltage signal to the main controller 11.

[0440] In the embodiment of the present disclosure, the display module 800 can be any of the display modules described above. For the sake of brevity, no further description is given.

[0441] The specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a rail transit display screen, an outdoor advertising machine, a refrigerator display screen, a vehicle-mounted display screen, a mobile device, a wearable device, a VR device, etc. A person skilled in the art can select a corresponding display device according to the specific use of the display device, and no further description is given here.

[0442] For example, the display device of rail transit, the display device at subway station / station / parking lot, etc. The display device is used to provide vehicle arrival and station guide information to pedestrians. If the display fails cannot be found and repaired in the first time, it will bring long-term inconvenience to the traveling personnel.

[0443] For example, the outdoor advertising machine has many applications in sparsely populated scenes, and the consumer and the operator cannot timely find the display failure. The above monitoring method and display module are more suitable.

[0444] It should be noted that the display device can further include other necessary components and compositions, for example, a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements according to the specific use requirements of the display device, which will not be described here.

[0445] Compared with the prior art, the display device provided by the example embodiments of the present application has the same beneficial effects as the display module provided by the above example embodiments, which will not be described here.

[0446] FIG. 22 is a flow diagram of a monitoring method according to another embodiment of the present disclosure.

[0447] As shown in FIG. 22, the monitoring method can include operation S110 and operation S120.

[0448] In the embodiments of the present disclosure, the monitoring method can be applied to any of the display modules described above.

[0449] In operation S110, a first indication signal from the level converter and / or a second indication signal from the first power manager are acquired.

[0450] In operation S120, according to the first indication signal and / or the second indication signal, it is monitored whether the display state of the display panel is abnormal.

[0451] In the embodiments of the present disclosure, the first indication signal is determined based on the display signal output by the level converter, and the second indication signal is determined based on the voltage signal output by the first power manager, and the display panel displays according to the display signal and the voltage signal.

[0452] In the embodiments of the present disclosure, operation S110 and operation S120 are similar to the operations performed by any of the display modules described above, which will not be described here.

[0453] In the embodiments of the present disclosure, operation S120 monitors whether the display state of the display panel is abnormal according to the first indication signal and / or the second indication signal, including: in a case where it is determined that the first indication signal is a first level, it is determined that the display signal is abnormal; in a case where it is determined that the second indication signal is the first level, it is determined that the voltage signal is abnormal; wherein in a case where it is determined that the display signal and / or the voltage signal is abnormal, it is determined that the display state is abnormal.

[0454] In the embodiments of the present disclosure, the monitoring method further comprises: in response to the first level of the first indication signal and / or the first level of the second indication signal, outputting a first control signal having a first level, the first level of the first control signal indicating that the display panel displays abnormally based on the display signal and / or the voltage signal; and controlling the first power manager to be powered off under the control of the first level of the first control signal, wherein the level shifter is powered off in the case that the first power manager is powered off.

[0455] In the embodiments of the present disclosure, the monitoring method further comprises: in the case that the first power manager is powered off, outputting a first control signal having a second level; and controlling the first power manager to be powered on under the control of the second level of the first control signal, wherein the level shifter is powered on in the case that the first power manager is powered on.

[0456] In the embodiments of the present disclosure, the monitoring method further comprises: obtaining a third indication signal from the backlight driving controller; and monitoring whether the display state of the display panel is abnormal according to the third indication signal; wherein the third indication signal is determined based on a backlight signal output by the backlight driving controller, and the display panel displays according to the backlight signal.

[0457] In the embodiments of the present disclosure, monitoring whether the display state of the display panel is abnormal according to the third indication signal comprises: in the case that the third indication signal is determined to be a second level, determining that the backlight signal is abnormal; and wherein, in the case that the backlight signal is determined to be abnormal, it is determined that the display state is abnormal.

[0458] In the embodiments of the present disclosure, the monitoring method further comprises: in response to the second level of the third indication signal, outputting a second control signal having a first level, the first level of the second control signal indicating that the display panel displays abnormally based on the backlight; and controlling the backlight driving controller to be powered off under the control of the first level of the second control signal.

[0459] In the embodiments of the present disclosure, the monitoring method further comprises: in the case that the backlight driving controller is powered off, outputting a second control signal having a second level; and controlling the backlight driving controller to be powered on under the control of the second level of the second control signal.

[0460] In the embodiments of the present disclosure, the monitoring method further comprises: obtaining a temperature of the display panel and / or a display brightness value of the display panel; and converting the temperature and / or the display brightness value into a detection signal; and determining that the display state of the display panel is abnormal based on the detection signal in the case that the temperature is determined to be outside a specified stable range and / or the display brightness is determined to be outside a specified brightness range, wherein the specified temperature range and the specified brightness range are determined based on a normally displayed display panel.

[0461] The computer program product of the first aspect can include one or more non-transitory computer-readable media storing instructions that, when executed, cause one or more processors to perform the operations of the first aspect. The one or more non-transitory computer-readable media can include, for example, magnetic media such as one or more magnetic disks, magnetic tapes or cassettes; optical media such as one or more compact discs (CD), optical discs or discs (for example, DVD, Blu-ray Disc®, digital video disc, ultra density disc, ultra-compact disc, any optical media, etc.); semiconductor media such as solid state hard drives (for example, flash memory, solid state USB drives, etc.); any other suitable medium; or any suitable combination of media.

[0462] Those skilled in the art will understand that features recited in various embodiments and / or claims of the present disclosure can be combined and / or interchanged, even if this is not explicitly stated in the present disclosure. In particular, features recited in various embodiments and / or claims of the present disclosure can be combined and / or interchanged, without departing from the spirit and teachings of the present disclosure. All such combinations and / or interchanges are within the scope of the present disclosure.

[0463] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A display module, comprising: a display panel, a first controller, a level shifter, and a first power manager configured to provide operating voltages for the display panel and the level shifter, and a second power manager configured to provide operating voltages for the first controller; a first output terminal of the first power manager is electrically connected to a first input terminal of the display panel and a first input terminal of the level shifter, and an output terminal of the second power manager is electrically connected to a first input terminal of the first controller; a first output terminal of the first controller is electrically connected to a second input terminal of the level shifter, so as to output a display signal to the display panel through the level shifter, a first output terminal of the level shifter is electrically connected to a second input terminal of the display panel, so as to output the display signal to the display panel; wherein the first controller is further configured to determine a display state of the display panel according to a first indication signal, and a second output terminal of the level shifter is electrically connected to a second input terminal of the first controller, so as to output the first indication signal to the first controller; and / or the first controller is further configured to determine the display state of the display panel according to a second indication signal, and a second output terminal of the first power manager is electrically connected to a third input terminal of the first controller, so as to output the second indication signal to the first controller.

2. The display module of claim 1, further comprising: a power control circuit, the power control circuit comprising a first restart circuit; an input terminal of the first restart circuit is electrically connected to a second output terminal of the first controller, so as to output a first control signal to the first restart circuit; an output terminal of the first restart circuit is electrically connected to an input terminal of the first power manager, so as to control the first power manager to switch between power-on and power-off according to the first control signal.

3. The display module of claim 1, wherein, the first controller is further configured to determine the display state of the display panel according to a third indication signal; the display module further comprises a backlight module and a backlight drive controller; a first output terminal of the backlight drive controller is electrically connected to an input terminal of the backlight module, so as to output a backlight signal to the backlight module; a second output terminal of the backlight drive controller is electrically connected to a fourth input terminal of the first controller, so as to output the third indication signal to the first controller.

4. The display module of claim 3, further comprising: a power control circuit, the power control circuit comprising a second restart circuit; an input terminal of the second restart circuit is electrically connected to a third output terminal of the first controller, so as to output a second control signal to the second restart circuit; an output terminal of the second restart circuit is electrically connected to an input terminal of the backlight drive controller, so as to control the backlight drive controller to switch between power-on and power-off according to the second control signal.

5. The display module of claim 2 or 4, wherein, the power control circuit comprises a triode, a transistor, a first resistor and a second resistor; wherein a control electrode of the triode is electrically connected to the first controller, a first electrode of the triode is electrically connected to a second terminal of the first resistor, and a second electrode of the triode is grounded. a control electrode of the transistor is electrically connected to a second end of the second resistor, a first electrode of the transistor is electrically connected to a working power supply, and a second electrode of the transistor is electrically connected to the first power manager or the backlight driving controller; and a first end of the first resistor is electrically connected to the working power supply, and a first end of the second resistor is electrically connected to the first electrode of the triode.

6. The display module of claim 1, wherein, The display module further comprises a backlight driving controller, a first input end of the backlight driving controller is electrically connected to a first output end of the main controller, so as to provide a working voltage to the backlight driving controller; a second output end of the backlight driving controller is electrically connected to a fourth input end of the first controller, so as to output a third indication signal to the first controller; a fourth output end of the first controller is electrically connected to an input end of the main controller, so as to output a working state or a second control signal of the backlight driving controller to the main controller according to the third indication signal, wherein the main controller controls the backlight driving controller to be powered on or powered off based on the working state or the second control signal. a sensor and a detection circuit; 7. The display module of claim 1, further comprising: the sensor is arranged on the display panel, and an output end of the sensor is electrically connected to an input end of the detection circuit, so as to acquire a temperature and / or a display brightness value of the display panel and output the temperature and / or the display brightness value to the detection circuit; the first controller is configured to determine a display state of the display panel according to a detection signal, wherein an output end of the detection circuit is connected to a fifth input end of the first controller, so as to output the detection signal to the first controller, and the detection signal is determined based on the temperature and / or the display brightness value. an adjusting circuit; 8. The display module of claim 1, further comprising: a first end of the adjusting circuit is grounded, a second end of the adjusting circuit is electrically connected to a pull-down node, a second output end of the first power manager is electrically connected to the pull-down node, a third input end of the first controller is electrically connected to the pull-down node, and the adjusting circuit is used for adjusting a voltage of the second indication signal.

9. The display module of claim 1, wherein a first output end of the main controller is electrically connected to a sixth input end of the first controller, so as to output a video signal to the first controller, and the first controller is configured to output the display signal to the level shifter according to the video signal; a fourth output end of the first controller is electrically connected to an input end of the main controller, so as to output a monitoring result to the main controller, so as to confirm whether the display state is abnormal, and the monitoring result comprises whether the video signal is abnormal, whether the level shifter is abnormal, whether the first power manager is abnormal, and whether the display state is abnormal.

10. The display module of claim 1, wherein the display signal comprises a first branch display signal and a second branch display signal, the first controller is further configured to determine the display state of the display panel according to the second branch display signal. ​ The first output end of the level shifter is electrically connected to the second input end of the display panel, so as to output the first branch display signal to the display panel, and the first output end of the level shifter is electrically connected to the seventh input end of the first controller, so as to output the second branch display signal to the first controller. And / or, The working voltage output by the first output end of the first power manager includes a first branch voltage signal and a second branch voltage signal, The first controller is further configured to determine the display state of the display panel according to the second branch voltage signal; The first output end of the first power manager is electrically connected to the first input end of the display panel, so as to output the first branch voltage signal to the display panel, and the first output end of the first power manager is electrically connected to the eighth input end of the first controller, so as to output the second branch voltage signal to the first controller.

11. The display module of claim 1, further comprising a backlight driving controller and a backlight module, the first output end of the backlight driving controller outputs a backlight signal including a first branch backlight signal and a second branch backlight signal, The first controller is further configured to determine the display state of the display panel according to the second branch backlight signal; The first output end of the backlight driving controller is electrically connected to the backlight module, so as to output the first branch backlight signal to the backlight module, and the first output end of the backlight driving controller is electrically connected to the ninth input end of the first controller, so as to output the second branch backlight signal to the first controller.

12. The display module of claim 11, further comprising a signal processing circuit, The first input end of the signal processing circuit is electrically connected to the first output end of the level shifter, and the first output end of the signal processing circuit is electrically connected to the seventh input end of the first controller; wherein The second input end of the signal processing circuit is electrically connected to the first output end of the first power manager, and the second output end of the signal processing circuit is electrically connected to the eighth input end of the first controller; The third input end of the signal processing circuit is electrically connected to the first output end of the backlight driving controller, and the third output end of the signal processing circuit is electrically connected to the ninth input end of the first controller.

13. The display module of claim 1, further comprising a second controller, the first input end of the second controller is electrically connected to the output end of the second power manager, so as to provide working voltage to the second controller; The display signal includes a first branch display signal and a second branch display signal, wherein, The second controller is further configured to determine the display state of the display panel according to the second branch display signal; The first output end of the level shifter is electrically connected to the second input end of the display panel, so as to output the first branch display signal to the display panel, and the first output end of the level shifter is electrically connected to the second input end of the second controller, so as to output the second branch display signal to the second controller; And / or, ​ ​ a working voltage outputted by a first output terminal of the first power manager comprises a first branch voltage signal and a second branch voltage signal, the second controller is further configured to determine a display state of the display panel according to the second branch voltage signal; a first output terminal of the first power manager is electrically connected to a first input terminal of the display panel, so as to output the first branch voltage signal to the display panel, and the first output terminal of the first power manager is electrically connected to a third input terminal of the second controller, so as to output the second branch voltage signal to the second controller.

14. The display module of claim 13, further comprising a backlight driving controller and a backlight module, a backlight signal outputted by a first output terminal of the backlight driving controller comprises a first branch backlight signal and a second branch backlight signal, the second controller is further configured to determine a display state of the display panel according to the second branch backlight signal; a first output terminal of the backlight driving controller is electrically connected to the backlight module, so as to output the first branch backlight signal to the backlight module, and the first output terminal of the backlight driving controller is electrically connected to a fourth input terminal of the second controller, so as to output the second branch backlight signal to the second controller.

15. The display module of claim 14, further comprising a signal processing circuit, wherein a first input terminal of the signal processing circuit is electrically connected to a first output terminal of the level converter, and a first output terminal of the signal processing circuit is electrically connected to a second input terminal of the second controller; a second input terminal of the signal processing circuit is electrically connected to a first output terminal of the first power manager, and a second output terminal of the signal processing circuit is electrically connected to a third input terminal of the second controller; a third input terminal of the signal processing circuit is electrically connected to a first output terminal of the backlight driving controller, and a third output terminal of the signal processing circuit is electrically connected to a fourth input terminal of the second controller.

16. The display module of claim 14, further comprising a first restart circuit; an input terminal of the first restart circuit is electrically connected to an output terminal of the second controller, so as to output a third control signal to the first restart circuit; an output terminal of the first restart circuit is electrically connected to an input terminal of the first power manager, so as to control the first power manager to switch between power-on and power-off according to the third control signal; and / or, a second restart circuit; an input terminal of the second restart circuit is electrically connected to an output terminal of the second controller, so as to output a fourth control signal to the second restart circuit; an output terminal of the second restart circuit is electrically connected to an input terminal of the backlight driving controller, so as to control the backlight driving controller to switch between power-on and power-off according to the fourth control signal.

17. The display module of claim 1, wherein, the first controller, the first power manager and the level converter are arranged on a same circuit board.

18. A display module, comprising: a display panel, a first controller, a second controller, a level converter, and a first power manager providing operating voltage for the display panel, the level shifter and the first controller, and a second power manager providing operating voltage for the second controller, a first output of the first power manager is electrically connected to a first input of the display panel, a first input of the level shifter and a first input of the first controller, and an output of the second power manager is electrically connected to the first input of the first controller, a first output of the first controller is electrically connected to a second input of the level shifter, for outputting display signal to the display panel through the level shifter; the second controller is configured to determine display state of the display panel according to the display signal, wherein a first output of the level shifter is electrically connected to a second input of the display panel and a second input of the second controller, wherein the display module further comprises a power control circuit, an input of the power control circuit is electrically connected to an output of the second controller, for outputting a fifth control signal to the power control circuit; a first output of the power control circuit is electrically connected to an input of the first power manager, for controlling the first power manager to switch between power on and power off according to the fifth control signal.

19. The display module of claim 18, further comprising: a backlight driving control circuit and a backlight module, an output of the backlight driving circuit is electrically connected to the backlight module, for outputting backlight signal to the backlight module, wherein the second controller is further configured to determine display state of the display panel according to the backlight signal; an output of the backlight driving circuit is electrically connected to a fourth input of the second controller, for outputting the backlight signal to the second controller; and / or the second controller is further configured to determine display state of the display panel according to the voltage signal; a first output of the first power manager is electrically connected to a third input of the second controller, for outputting voltage signal to the second controller.

20. The display module of claim 19, wherein a second output of the power control circuit is electrically connected to an input of the backlight control driver, for controlling the backlight control driver to switch between power on and power off according to a sixth control signal output by the second controller.

21. A display device, comprising: a main controller; and the display module of any one of claims 1-20, electrically connected to the main controller, the display module being configured to receive video signal from the main controller, convert the video signal into the display signal, and send display state based on the display signal and the voltage signal to the main controller.

22. A monitoring method of a display module, comprising: obtaining first indication signal from a level shifter and / or second indication signal from a first power manager; and monitoring whether display state of a display panel is abnormal according to the first indication signal and / or the second indication signal. The first indication signal is determined based on a display signal output by the level shifter, and the second indication signal is determined based on a voltage signal output by the first power manager, and the display panel displays according to the display signal and the voltage signal.

23. The monitoring method of claim 22, wherein, The monitoring of whether the display state of the display panel is abnormal according to the first indication signal and / or the second indication signal comprises: In a case where it is determined that the first indication signal is at a first level, it is determined that the display signal is abnormal. In a case where it is determined that the second indication signal is at a first level, it is determined that the voltage signal is abnormal. In a case where it is determined that the display signal and / or the voltage signal is abnormal, it is determined that the display state is abnormal.

24. The monitoring method of claim 22, further comprising: in response to the first level of the first indication signal and / or the first level of the second indication signal, outputting a first control signal having the first level, the first level of the first control signal indicating that the display panel displays abnormally based on the display signal and / or the voltage signal; controlling the first power manager to be powered off under the control of the first level of the first control signal, wherein in a case where the first power manager is powered off, the level shifter is powered off.

25. The monitoring method of claim 24, further comprising: in a case where the first power manager is powered off, outputting the first control signal having a second level; controlling the first power manager to be powered on under the control of the second level of the first control signal, wherein in a case where the first power manager is powered on, the level shifter is powered on.

26. The monitoring method of claim 22, further comprising: obtaining a third indication signal from a backlight driving controller; and monitoring whether the display state of the display panel is abnormal according to the third indication signal; The third indication signal is determined based on a backlight signal output by the backlight driving controller, and the display panel displays according to the backlight signal. The monitoring of whether the display state of the display panel is abnormal according to the third indication signal comprises:

27. The monitoring method of claim 26, wherein, In a case where it is determined that the third indication signal is at a second level, it is determined that the backlight signal is abnormal; and in a case where it is determined that the backlight signal is abnormal, it is determined that the display state is abnormal.

28. The monitoring method of claim 27, further comprising: in response to the second level of the third indication signal, outputting a second control signal having the first level, the first level of the second control signal indicating that the display panel displays abnormally based on the backlight; controlling the backlight driving controller to be powered off under the control of the first level of the second control signal.

29. The monitoring method of claim 26, further comprising: in a case where the backlight driving controller is powered off, outputting the second control signal having a second level; controlling the backlight driving controller to be powered on under the control of the second level of the second control signal.

30. The monitoring method of claim 22, further comprising: ​ acquiring a temperature of the display panel and / or a display brightness value of the display panel; and converting the temperature and / or the display brightness value into a detection signal; and determining that a display state of the display panel is abnormal based on the detection signal in a case where it is determined that the temperature is located outside a specified stable range and / or the display brightness is located outside a specified brightness range, wherein the specified temperature range and the specified brightness range are determined based on a normally displaying display panel.

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