Chip mass production test environment recovery method and device and electronic equipment

Abstract

The invention is suitable for the technical field of semiconductor testing, and provides a chip mass production testing environment recovery method and device and electronic equipment, and the chip mass production testing environment recovery method is used for carrying out anomaly detection on a second module used for executing a chip testing task. After an exception is found, a first module used for user interaction and monitoring triggers recovery in an overtime tolerance interval, at least a second module is restarted, and a mass production test environment context stored by the first module is injected, so that the second module quickly returns to a runnable state with existing batch parameters and a process state; and then the second module is automatically reconnected with the ATE test equipment, marks the current tested chip as retestable and sends the retestable chip to the chip processing equipment, so that the chip processing equipment confirms the test process and switches to the next to-be-tested chip, and the second module continues to execute the test task. According to the scheme, the continuity and the stability of the chip mass production test in the abnormal scene are realized.

Description

Technical Field

[0001] This application belongs to the field of semiconductor testing technology, and in particular relates to a method, apparatus and electronic equipment for restoring a chip mass production testing environment. Background Technology

[0002] In the mass production testing of semiconductor chips, each chip is typically tested individually using probe stations, sorters, and ATE (Automatic Test Equipment) equipment. Existing testing systems generally use host computer software to manage the overall process, handling task scheduling, equipment control, and test data acquisition. With the continuous updates and iterations of chip testing plans, the relevant programs in the testing system require frequent modifications and loading, which can easily lead to application-layer program errors or test process interruptions.

[0003] In existing technologies, when a critical process in test software abnormally exits, the common approach is to rely on manual intervention, such as having an operator restart the test software, manually resume the task, or reconfigure device connections. This approach often has the following problems: First, manual recovery is slow and easily exceeds timeout thresholds between devices, causing errors in the probe station or ATE test equipment, thus halting the entire test production line; second, manual intervention is uncertain, and inconsistencies in test status and loss of task information can easily occur during recovery; third, for the chip currently being tested, there is a lack of effective exception handling strategies, and it may be directly judged as a defective product, thus affecting the statistical yield.

[0004] Therefore, how to implement an efficient and stable anomaly detection and recovery mechanism in a mass production testing environment, reduce manual intervention, and avoid equipment false alarms and test data loss has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method, apparatus, and electronic device for restoring a chip mass production test environment. By implementing a modular anomaly detection and rapid recovery mechanism in the ATE test software, the test process can automatically restart and resume operation within the timeout tolerance range after an abnormal exit, ensuring the continuity and stability of chip mass production testing.

[0006] The first aspect of this application provides a method for restoring a chip mass production testing environment, applied to ATE testing software. The ATE testing software includes a first module for user interaction and monitoring, and a second module for executing chip testing tasks. The ATE testing software is connected to a chip processing device and an ATE testing device respectively to perform tests on semiconductor chips. The method includes: Detect whether the second module is in an abnormal state during chip mass production testing; When the second module is detected to be in the abnormal state, the first module performs a recovery operation within the timeout tolerance interval. The recovery operation includes at least restarting the second module and transmitting the mass production test environment context saved by the first module as a recovery parameter to the second module so that the second module can resume its running state. After the second module resumes operation, the connection with the ATE test equipment is re-established, the chip under test is marked as retestable and sent to the chip processing equipment, so that the chip processing equipment determines that the current chip under test has completed the test and switches to the next chip under test, and continues to execute the chip test task through the second module, thereby realizing the restoration of the chip mass production test environment. In this embodiment, the second module, used for executing chip testing tasks, undergoes anomaly detection. Upon detection, the first module, used for user interaction and monitoring, triggers recovery within the timeout tolerance range, at least restarting the second module and injecting the mass production test environment context saved by the first module. This allows the second module to quickly return to a runnable state with existing batch parameters and process status. Subsequently, the second module automatically reconnects to the ATE test equipment and marks the currently tested chip as "retestable" to the chip processing equipment, enabling it to confirm the current test process and switch to the next chip under test. The second module then continues executing the test task. Through the above-mentioned coordinated steps, this application achieves continuity and stability in chip mass production testing under abnormal scenarios.

[0007] In one possible implementation, detecting whether the second module is in an abnormal state during chip mass production testing includes: The first module sends heartbeat messages to the second module at a preset period; When the first module fails to receive a heartbeat response from the second module continuously within a preset confirmation period, and the number of times it fails to receive a heartbeat response reaches a preset number, the second module is confirmed to be in the abnormal state; and / or, When the termination of the second module process is detected, it is confirmed that the second module is in the abnormal state.

[0008] In one possible implementation, the timeout tolerance interval is determined based on the alarm timeout threshold of the chip processing device, the alarm timeout threshold of the ATE test device, and the historical time consumption of the second module restarting and reconnecting with the ATE device; the method further includes: The first module reads the first alarm timeout threshold of the chip processing device and the second alarm timeout threshold of the ATE test device, and collects the historical time taken for the second module to restart and reconnect with the ATE device. Determine the minimum alarm timeout threshold between the first alarm timeout threshold and the second alarm timeout threshold; The timeout tolerance range is determined based on the difference between the minimum alarm timeout threshold and the historical maximum recovery time, combined with a preset safety margin.

[0009] In one possible implementation, the method further includes: Before each chip under test begins testing, the current batch information and the chip identifier under test are recorded. After the test is completed, the device status snapshot and error status information are recorded to generate and update the mass production test environment context. The device status snapshot includes a panoramic record of the ATE test equipment operating status and the chip processing equipment operating status. The mass production test environment context is stored in the first module.

[0010] In one possible implementation, re-establishing the connection with the ATE test equipment includes: The second module sends a reconnection request to the ATE test equipment. Receive the handshake connection response from the ATE test device to complete the handshake confirmation and synchronize the status information of both parties.

[0011] In one possible implementation, the second module stores a chip test plan, which is used to provide test programs for chip mass production testing; the step of continuing to execute chip testing tasks through the second module includes: Reload the chip test plan and determine the test tasks to be performed; Upon re-establishing a connection with the ATE test equipment, a corresponding test instruction is sent to the ATE test equipment based on the test task to instruct the ATE test equipment to perform a test on the chip under test. Receive test results and status information returned from the ATE test equipment.

[0012] In one possible implementation, after marking the currently tested chip as retestable and sending it to the chip processing device, the method further includes: Add the currently tested chip to the retest task queue; During subsequent mass production testing, the chip is scheduled from the retest task queue and the test is re-executed to achieve automatic retesting of the chip that was interrupted.

[0013] In one possible implementation, the first module includes a UI interface and a processor. The first module is used to display test status information and test data, and to monitor the running status of the second module. The second module includes a chip test plan that provides a loader for chip mass production testing, and executes chip test tasks based on the chip test plan.

[0014] A second aspect of this application provides a recovery device for a chip mass production testing environment, configured in ATE testing software. The ATE testing software includes a first module for user interaction and monitoring, and a second module for performing chip testing tasks. The ATE testing software is connected to a chip processing device and an ATE testing device respectively to perform tests on semiconductor chips. The device includes: The detection module is used to detect whether the second module is in an abnormal state during the chip mass production test; A recovery module is used to enable the first module to perform a recovery operation within a timeout tolerance range when the second module is detected to be in the abnormal state. The recovery operation includes at least restarting the second module and transmitting the mass production test environment context saved by the first module as a recovery parameter to the second module so that the second module can resume its running state. The testing module is used to re-establish the connection with the ATE testing equipment after the second module resumes operation, mark the currently tested chip as retestable and send it to the chip processing equipment, so that the chip processing equipment determines that the currently tested chip has completed testing and switches to the next chip to be tested, and continues to execute the chip testing task through the second module, thereby realizing the restoration of the chip mass production testing environment.

[0015] A third aspect of this application provides an electronic device including a memory, a processor, ATE test software installed on the electronic device, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the first aspect above.

[0016] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0017] A fifth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to perform the method described in the first aspect.

[0018] The beneficial effects of the second to fifth aspects mentioned above can all be referred to the beneficial effects described in the first aspect, and will not be repeated here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the architecture of a chip mass production testing environment provided in an embodiment of this application; Figure 2 This is a schematic diagram of the architecture of another chip mass production testing environment provided in the embodiments of this application; Figure 3 This is an interactive timing diagram illustrating a chip mass production testing environment recovery method provided in an embodiment of this application; Figure 4 This is a flowchart illustrating a method for restoring a chip mass production testing environment provided in an embodiment of this application; Figure 5 This is a flowchart illustrating another method for restoring a chip mass production testing environment provided in an embodiment of this application; Figure 6 This is a schematic diagram of a device for restoring a chip mass production testing environment provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0027] In the mass production testing of semiconductor chips, each chip is typically tested individually using probe stations, sorters, and ATE (Automatic Test Equipment) equipment. Existing testing systems generally use host computer software to manage the overall process, handling task scheduling, equipment control, and test data acquisition. With the continuous updates and iterations of chip testing plans, the relevant programs in the testing system require frequent modifications and loading, which can easily lead to application-layer program errors or test process interruptions.

[0028] In existing technologies, when a critical process in test software abnormally exits, the common approach is to rely on manual intervention, such as having an operator restart the test software, manually resume the task, or reconfigure device connections. This approach often has the following problems: First, manual recovery is slow and easily exceeds timeout thresholds between devices, causing errors in the probe station or ATE test equipment, thus halting the entire test production line; second, manual intervention is uncertain, and inconsistencies in test status and loss of task information can easily occur during recovery; third, for the chip currently being tested, there is a lack of effective exception handling strategies, and it may be directly judged as a defective product, thus affecting the statistical yield.

[0029] Therefore, how to implement an efficient and stable anomaly detection and recovery mechanism in a mass production testing environment, reduce manual intervention, and avoid equipment false alarms and test data loss has become a technical problem that urgently needs to be solved in this field.

[0030] To address the aforementioned issues, this application provides a method, apparatus, and electronic device for restoring a chip mass production testing environment. First, anomaly detection is performed on the second module used to execute chip testing tasks. Upon detection, the first module, used for user interaction and monitoring, triggers recovery within the timeout tolerance range. This involves at least restarting the second module and injecting the mass production testing environment context saved by the first module, allowing the second module to quickly return to a runnable state with existing batch parameters and process status. Subsequently, the second module automatically reconnects to the ATE testing equipment and marks the currently tested chip as "retestable," sending this information to the chip processing equipment. This allows the equipment to confirm the current testing process and switch to the next chip under test, enabling the second module to continue executing the testing task. Through these interconnected steps, this application achieves continuity and stability in chip mass production testing under abnormal scenarios.

[0031] The following describes in detail, with reference to the accompanying drawings, the chip mass production testing environment recovery method, apparatus, electronic device, storage medium, and computer program provided in the embodiments of this application for chip mass production testing environment recovery method, apparatus, electronic device, storage medium, and computer program.

[0032] See Figure 1 This illustration shows a schematic diagram of the architecture of a chip mass production testing environment provided in an embodiment of this application. The chip mass production testing environment is built around ATE testing software, which includes two functional modules running on the same electronic device: a first module and a second module. The electronic device can be an industrial control computer or a host computer. The overall architecture of the chip mass production testing environment includes: the first module, the second module, ATE testing equipment, chip processing equipment, and the chip under test.

[0033] The first module is used for user (e.g., production line operator) interaction and monitoring. Specifically, it can be used to: provide parameter configuration and status visualization, maintain the mass production test environment context (such as batch number, machine / station configuration, test plan version, limit table, equipment connection parameters, current chip identification under test, and test progress, etc.), and monitor the second module online through a heartbeat connection; when the second module is detected to be in an abnormal state, a recovery command is sent within the timeout tolerance range to restart the second module and pass the saved mass production test environment context as a recovery parameter to the second module.

[0034] The second module is used to execute chip testing tasks. Specifically, it can be used to: load and run the internal chip test plan; call the electronic device driver and corresponding API interface to interact with the ATE test equipment with instructions or data; collect test data of the chip under test according to the test process obtained by loading the chip test plan; and send back the test results; at the same time, coordinate with the chip processing equipment, including sending the test results and retestable flags to the chip processing equipment so that the chip processing equipment can sort and switch to the next chip under test accordingly; at the same time, the test results and retestable flags are reported to the first module and archived for traceability and retest scheduling.

[0035] The ATE test equipment is used to perform tests on the chip under test under the control of the second module and to feed back the test results to the second module. The chip processing equipment is used to load, unload, and sort the chips under test. It receives test completion / retestable markers from the second module and switches to the next chip under test accordingly. It also sends back the chip location information / ID and other operating status to the second module. Specifically, the chip processing equipment can be implemented as a probe station (suitable for wafer-level testing, including alignment, lifting, contact establishment, and wafer map management) and / or a sorting machine (suitable for post-packaging testing, including pickup, sorting, and tray / ribbon / pallet switching), etc.

[0036] Specifically, such as Figure 1 As shown, the first module is located within the ATE test software and controls and interacts with the second module. The second module establishes communication links with both the ATE test equipment and the chip processing equipment. It issues test commands to the ATE test equipment and receives test results. It also synchronizes the workstation / chip status with the chip processing equipment and drives the sorting action, enabling the ATE test equipment to test the sorted chips under test, thus completing the test loop. This architecture, through the separation of monitoring and execution, achieves automatic detection, automatic recovery, automatic reconnection to the equipment, and automatic switching of chips under test in mass production testing scenarios. This significantly shortens the average recovery time after an anomaly and requires no manual intervention throughout the recovery and continuation of testing process.

[0037] As one possible implementation method, Figure 2 This illustration shows an architectural diagram of another chip mass production testing environment provided in an embodiment of this application. For example... Figure 2 As shown, the environment includes ATE test software deployed on an industrial control computer or host computer, as well as ATE test equipment and chip processing equipment connected to the ATE test software.

[0038] In this embodiment, the ATE testing software includes a first module and a second module. The first module includes at least a UI interface and a processor. The UI interface can display parameter configurations and the current testing progress or results of the chip under test. The processor is used to receive and issue configuration commands, monitor and schedule the status of the second module, maintain and save the context information of the mass production test environment, and trigger recovery when an anomaly is detected in the second module, sending the context information of the mass production test environment to the second module. The second module includes a chip test plan, which is a test procedure written by the test engineer to determine the quality of the semiconductor chip. It is a plan for evaluating a series of performance indicators such as the characteristics, functions, and power consumption of the chip, and is a test procedure used to determine whether the chip is a good product or a defective product. The second module can obtain a chip test program for mass production testing by loading the chip test plan.

[0039] It should be understood that production line operators can interact with the ATE testing software through the UI interface of the first module. For example, when the ATE testing software malfunctions, operators can view the automatically generated "retestable" list through the UI interface and add or remove items for retesting as needed. They can also choose whether to manually retest or isolate the software. When the ATE testing software malfunctions, the system performs automatic detection and recovery based on the context information of the test environment. During this process, production line operators only need to view the recovery results and do not need to manually restore the parameters.

[0040] In this embodiment, the ATE testing software employs process-level logical isolation, dividing it into a first module and a second module. The first module's internal program is implemented and provided by the ATE testing equipment manufacturer, exhibiting low change frequency and high stability. It interacts with production line operators, displays parameter configurations and the current testing status of the chip under test, and records critical information required for operation. The first module does not directly access the equipment; it only issues start / pause / stop and parameter setting control commands to the second module through a controlled interface and receives test results and alarms. The second module, however, does not provide an interface and executes test programs written by test engineers. It exhibits high change frequency and relatively low stability. Internally, it includes a chip test plan. The second module can obtain chip test programs for mass production testing by loading this plan and establish communication connections with the ATE testing equipment and chip processing equipment to complete the mass production testing and sorting linkage of the chip under test. The two modules run as independent processes in different address spaces and interact with each other through predefined command / status interfaces. When the second module malfunctions, it does not affect the display and interaction of the first module. The operator is unaware of the malfunction and the first module can trigger the recovery of the second module according to a preset strategy, thus allowing the test process to continue.

[0041] In this embodiment, the abnormality of the test program only affects the second module, preventing the fault from spreading to the first module and ensuring the continuous availability of the human-machine interface and production line collaboration. In abnormal scenarios, the first module can trigger the recovery of the second module, reducing downtime and manual intervention, improving mass production continuity and equipment utilization, and facilitating problem localization and subsequent maintenance and upgrades.

[0042] See Figure 3 This diagram illustrates the interactive timing of a chip mass production testing environment recovery method provided in an embodiment of this application; the following is based on... Figure 3 A detailed explanation of the interaction throughout the entire process is provided: During operation, the first module monitors the second module online based on heartbeat and timeout thresholds. When an anomaly is detected in the second module and it exits, the first module triggers a recovery operation within a preset timeout tolerance range, restarting the second module and transmitting the mass production test environment context (including batch information, test plan and limits, device connection parameters, currently tested chip identifier, and process progress) saved in the first module as recovery parameters to the second module, restoring it to a runnable state. Subsequently, the second module automatically re-establishes a connection with the ATE test equipment based on the recovery parameters and synchronizes the status information of both parties. At the same time, it marks the "currently tested chip" as retestable and sends it to the chip processing equipment, enabling the chip processing equipment to sort and switch to the next chip under test. After the status stabilizes, the first module issues an instruction to the second module to start testing. The second module then sends test instructions to the ATE test equipment according to the loaded chip test program and executes the test. After completing one chip, the same process is repeated to test subsequent chips under test sequentially. Through the above interactions, anomaly detection, recovery, device reconnection, retestable marking, and continued testing are all automatically completed in a closed loop within the system without manual intervention, thereby enabling rapid recovery and continuous operation of the testing process in mass production scenarios.

[0043] See Figure 4 The diagram illustrates a flowchart of a chip mass production test environment recovery method provided in an embodiment of this application. The method is applied to ATE test software, which includes a first module for user interaction and monitoring, and a second module for performing chip test tasks. The ATE test software is connected to both the chip processing device and the ATE test device to perform tests on the semiconductor chip.

[0044] like Figure 4 As shown, the method may include the following steps: Step 401: Detect whether the second module is in an abnormal state during the chip mass production test.

[0045] Abnormal states refer to the exit or unresponsiveness of the second module, as well as other states that prevent the continuation of the intended test program. Examples include process crashes, system termination, prolonged absence of heartbeats, and unresponsive commands.

[0046] In this embodiment of the application, the specific process of detecting whether the second module is in an abnormal state during the chip mass production test can be as follows: First, the first module can detect whether the second module is in an abnormal state through a heartbeat mechanism. That is, the first module sends a heartbeat message to the second module every preset interval. If no response is received from the second module within the preset time, the second module is determined to be in an abnormal state.

[0047] In one possible implementation, step 401 above may specifically include: The first module sends heartbeat messages to the second module at a preset cycle; If the first module fails to receive a continuous heartbeat response from the second module within a preset confirmation period, and the number of times it fails to receive a heartbeat response reaches a preset number, the second module is confirmed to be in an abnormal state; or, When the termination of the second module process is detected, it is confirmed that the second module is in an abnormal state.

[0048] The heartbeat message adopts a periodic sending mechanism, with the preset period set according to the response delay of the test equipment and the fault tolerance requirements of the system; the preset confirmation period can be defined as the maximum time window for receiving heartbeat responses, and its length is related to the communication delay of the test equipment; the preset number can be determined by the minimum value of the number of consecutive communication failures in the historical abnormal events, which is used to filter occasional communication interference; the process termination detection can obtain the running status of the second module in real time through the operating system-level process monitoring interface.

[0049] Specifically, the first module generates heartbeat messages at fixed time intervals and sends them to the second module. The second module immediately returns a heartbeat response upon receiving the message. If no response is received within a preset confirmation period (e.g., three consecutive no responses), the second module is determined to have experienced a communication anomaly or functional failure. Simultaneously, the process monitoring interface continuously polls the process identifier of the second module; if the process identifier disappears, an anomaly determination is directly triggered. This dual detection mechanism ensures timely fault identification in both communication link anomalies and process crashes, avoiding recovery delays due to the failure of a single detection method. Alternatively, detection can be performed using either of the two methods separately; this application does not limit this approach.

[0050] This application filters out transient communication interference by setting a preset threshold number of times, reducing the probability of misjudgment, thereby enabling the recovery process to be quickly started within the equipment timeout threshold range, maintaining continuous operation of the production line.

[0051] Step 402: When the second module is detected to be in an abnormal state, the first module performs a recovery operation within the timeout tolerance interval.

[0052] The timeout tolerance range refers to the maximum time window during which recovery operations are allowed to be performed, ensuring that the recovery operation is completed within the device's tolerance range and preventing the device from triggering a timeout error.

[0053] The recovery operation includes at least restarting the second module and transmitting the mass production test environment context saved by the first module as a recovery parameter to the second module so that the second module can resume its running state. The mass production test environment context includes at least the current batch information, the chip under test identifier, the device status snapshot, and error status information.

[0054] In this embodiment, when an anomaly is detected in the second module, the first module performs a recovery operation within the timeout tolerance interval. The timeout tolerance interval can be determined based on the alarm timeout thresholds of the chip processing device and the ATE test device, as well as the historical time taken for the second module to restart and reconnect with the ATE device.

[0055] In one possible implementation, the method further includes: The first module reads the first alarm timeout threshold of the chip processing device and the second alarm timeout threshold of the ATE test device, and collects the historical time taken for the second module to restart and reconnect with the ATE test device. Determine the minimum alarm timeout threshold between the first alarm timeout threshold and the second alarm timeout threshold; The timeout tolerance range is determined based on the difference between the minimum alarm timeout threshold and the historical maximum recovery time, combined with a preset safety margin.

[0056] In this embodiment, if the timeout tolerance range is set unreasonably, the recovery operation may not be completed before the equipment alarm timeout, thereby triggering false alarms or production line shutdowns. Therefore, this embodiment provides a scheme for determining the timeout tolerance range.

[0057] The first and second alarm timeout thresholds represent the maximum waiting time for the chip processing device and ATE test device before triggering an alarm, respectively. The historical maximum recovery time is obtained by statistically recording the longest time for restarting and reconnecting operations of the second module. The selection of the minimum alarm timeout threshold ensures that the upper limit of the recovery operation time does not exceed the tolerance limit of any device. The difference is calculated as a reserved time window for the recovery operation, and a preset safety margin is used to offset operational fluctuations or unexpected delays.

[0058] Specifically, the first module reads the alarm timeout parameters of the chip processing equipment and the ATE testing equipment through the device interface. For example, if the alarm timeout threshold for the chip processing equipment is 20 minutes and the alarm timeout threshold for the ATE testing equipment is 25 minutes, then the minimum alarm timeout threshold is 20 minutes. The historical maximum recovery time is recorded by recording the time of multiple restart and reconnection operations of the second module, for example, a maximum of 3 minutes. Subtracting the historical maximum recovery time of 3 minutes from the minimum alarm timeout threshold of 20 minutes yields a difference of 17 minutes. Combining this with a preset safety margin of 2 minutes, the final timeout tolerance range is determined to be 15 minutes. In this way, the recovery operation is limited to completion within 15 minutes, ensuring that it does not exceed the equipment's tolerance time, while providing a buffer for potential delays and avoiding equipment from falsely triggering alarms or production line interruptions.

[0059] Through the above technical solution, this application can dynamically determine the timeout tolerance range based on actual equipment parameters and historical data, improving the flexibility and adaptability of recovery operations. By considering equipment alarm timeout thresholds and historical recovery times, it can effectively avoid triggering equipment alarms during the recovery process, reducing the probability of test interruptions and manual intervention. Simultaneously, by introducing a safety margin, the system's stability is further enhanced, providing a reliable guarantee for rapid recovery under abnormal conditions. This method not only improves the automatic recovery capability of the chip mass production testing environment but also minimizes the impact of test interruptions on production efficiency.

[0060] In some of the solutions described above in this application, the state reconstruction during the abnormal recovery process of the second module relies on the mass production test environment context. However, the test system lacks a complete recording mechanism for batch information, chip identification, and device operating status, which may lead to inconsistent device status or loss of task information during recovery, thereby affecting the continuity of test tasks after recovery. Therefore, this application further proposes to record the current batch information and the chip identification under test before each chip under test starts testing, and to record a device status snapshot and error status information after the test is completed, so as to generate and update the mass production test environment context. The device status snapshot includes a panoramic record of the operating status of the ATE test equipment and the chip processing equipment; and the mass production test environment context is stored in the first module.

[0061] The batch information includes the test batch number, test program version, and process parameter configuration. Chips under test are identified using QR codes or serial numbers. Equipment status snapshots are structured records generated by real-time acquisition of voltage parameters from the ATE test equipment, test head status, and robotic arm coordinate data from the chip processing equipment. Error status information is generated by parsing exception codes and equipment alarm signals from the test logs and establishing a correlation index with the corresponding chip identifier.

[0062] Specifically, when the test program starts, the first module automatically obtains the process configuration file corresponding to the test batch, extracts the batch number and version information, and writes it to the context storage area. When the chip processing equipment (such as a probe station) picks up the chip under test, the camera reads the chip surface markings and records the timestamps. After the test task is completed, the register status of the ATE test equipment and the sensor data of the chip processing equipment are synchronously obtained through the device interface, forming a panoramic snapshot containing the equipment operating parameters. If an abnormal interruption occurs during the test, the error code and equipment alarm information are captured and bound to the current chip identifier for storage. All recorded data is version-managed through the database of the first module. When the second module resumes, it calls the context data of the latest version of the mass production test environment to reconstruct the state, ensuring the accurate restoration of the test equipment parameters and chip processing flow.

[0063] Step 403: After the second module resumes operation, the connection with the ATE test equipment is re-established, the chip under test is marked as retestable and sent to the chip processing equipment, so that the chip processing equipment can determine that the current chip under test has completed the test and switch to the next chip under test, and continue to execute the chip test task through the second module, thereby realizing the restoration of the chip mass production test environment.

[0064] Re-establishing the connection with the ATE test equipment refers to restoring the communication link and synchronizing status information. A handshake protocol and status synchronization mechanism are used to ensure the reliability of equipment command transmission and maintain the continuity of the test process.

[0065] Marking the chip currently under test as retestable means adding the chip being tested during an abnormal interruption to the queue to be retested, and automatically retesting it through the chip processing equipment scheduling mechanism, thus avoiding direct chip discarding and causing yield statistics errors.

[0066] In this embodiment, step 403 is implemented as follows: First, after the second module resumes operation, a reconnection request is sent to re-establish the connection with the ATE test equipment. After the handshake confirmation is completed, the status information of both parties is synchronized. Second, the chip currently under test is marked as retestable and sent to the chip processing equipment. The chip processing equipment determines that the current chip under test has completed the test and switches to the next chip under test. Finally, the second module reloads the chip test plan and determines the test tasks to be executed. Based on the test tasks, a test instruction is sent to the ATE test equipment, instructing the ATE test equipment to perform the test on the current chip under test. The test results and status information returned by the ATE test equipment are received, and the chip test task continues to be executed.

[0067] In one possible implementation, re-establishing the connection with the ATE test equipment includes: The second module sends a reconnection request to the ATE test equipment. Receive the handshake connection response from the ATE test equipment to complete the handshake confirmation and synchronize the status information of both parties.

[0068] Specifically, the second module first sends a reconnection request to the ATE test equipment. This reconnection request can use the TCP / IP protocol and includes information such as a reconnection identifier and timestamp. Second, it receives a handshake connection response from the ATE test equipment to complete the handshake confirmation. After receiving the reconnection request, the ATE test equipment returns a handshake response packet containing information such as the device ID and current status. Finally, the status information of both parties is synchronized. The second module exchanges status information such as the current test progress and device parameters with the ATE test equipment to ensure data consistency between the two parties.

[0069] For example, the reconnection process can be configured with a 3-retry mechanism, with each retry spaced 5 seconds apart. If the connection is still not successfully established after 3 retries, a connection failure is reported to the first module, which then decides whether to continue trying or take other recovery measures.

[0070] Through the above technical solution, this application can quickly and reliably re-establish the connection with the ATE test equipment, avoiding the uncertainty of manual intervention. Simultaneously, handshake confirmation and status synchronization ensure the consistency of the test environment and reduce the risk of data loss due to connection interruption.

[0071] In one possible implementation, the second module stores a chip test plan, which provides test programs for chip mass production testing; the second module continues to execute chip testing tasks, including: Reload the chip test plan and determine the test tasks to be performed; Once the connection with the ATE test equipment is re-established, corresponding test instructions are sent to the ATE test equipment based on the test task to instruct the ATE test equipment to perform tests on the current chip under test. Receive test results and status information returned from the ATE test equipment.

[0072] In this embodiment, the chip test plan includes a test process, parameter configuration, and task scheduling logic. After the second module restarts, it reads the stored chip test plan and combines it with the context information in the recovery parameters to determine the test task corresponding to the chip under test. During the test task loading process, based on the device status snapshot and error status information, completed test steps are skipped, and the execution node before the interruption is located. After receiving the test instruction, the ATE test equipment executes the test action based on the parameters in the instruction and returns the generated test results and real-time status to the second module. The test results and status information are recorded in the mass production test environment context for reference by subsequent test tasks. Thus, the execution process of the test task does not require manual intervention, avoiding test interruptions caused by test program loading errors or inconsistent task statuses, while ensuring the integrity and continuity of test data.

[0073] In the above method embodiments, the chip mass production test environment recovery method performs anomaly detection on the second module used to execute chip test tasks. Upon detection of an anomaly, the first module used for user interaction and monitoring triggers recovery within the timeout tolerance range, at least restarting the second module and injecting the mass production test environment context saved by the first module, enabling the second module to quickly return to the runnable state with existing batch parameters and process status. Subsequently, the second module automatically reconnects to the ATE test equipment and marks the currently tested chip as "retestable" and sends it to the chip processing equipment, allowing it to confirm the current test process and switch to the next chip under test. The second module then continues to execute the test task. Through the above-mentioned coordinated steps, this application achieves the continuity and stability of chip mass production testing under abnormal scenarios.

[0074] See Figure 5 This illustrates a flowchart of another chip mass production testing environment recovery method provided in an embodiment of this application; as shown... Figure 5 As shown, the method may include the following steps: Step 501: Detect whether the second module is in an abnormal state during the chip mass production test.

[0075] Step 502: When the second module is detected to be in an abnormal state, the first module performs a recovery operation within the timeout tolerance interval.

[0076] Step 503: After the second module resumes operation, the connection with the ATE test equipment is re-established, the chip under test is marked as retestable and sent to the chip processing equipment, so that the chip processing equipment can determine that the current chip under test has completed the test and switch to the next chip under test, and continue to execute the chip test task through the second module, thereby realizing the restoration of the chip mass production test environment.

[0077] The implementation of steps 501 to 503 in this embodiment is the same as that of steps 101 to 103 in the above embodiment, and they can be referred to each other. This application will not repeat them here.

[0078] Step 504: Add the chip currently under test to the retest task queue.

[0079] Step 505: During the subsequent mass production test task execution, the chip is scheduled from the retest task queue and the test is re-executed to achieve automatic retesting of the abnormal interrupt test chip.

[0080] In some of the above embodiments, when a critical process in the test software exits abnormally, although the second module can be restarted and the running state restored by performing a recovery operation within the timeout tolerance range by the first module, if the chip under test is not effectively managed after being marked as retestable and sent to the chip processing device, the chip may not be retested or may be mixed with other chips under test, resulting in test omissions or yield statistics errors.

[0081] Therefore, this application embodiment further proposes steps 504 and 505. The creation of the retest task queue is based on the tagging information returned by the chip processing device. The queue stores data including chip identifiers, abnormal interruption times, and original test progress. The scheduling mechanism can trigger test tasks according to the priority or interruption time order of the chips in the queue. The automatic retest process can be linked with the chip processing device through the second module to reposition the chips in the retest task queue to the test station.

[0082] Specifically, after the second module resumes operation and completes device reconnection, the chip processing device receives chip information marked as retestable and adds it to the retest task queue. This queue is independent of the regular test task queue and can use a first-in-first-out (FIFO) or sorting rule based on the time of abnormal interruption. During subsequent mass production testing, after completing the current batch of tests, the chip processing device automatically extracts the chip identifier from the retest task queue and then sends it back to the test station via a robotic arm or other gripper. The second module reloads and executes the test program from the breakpoint based on the original test progress recorded in the queue, while updating the chip's status in the queue to "scheduled". If an abnormality occurs again during the retest, the chip will be remarked and appended to the end of the queue. By synchronizing queue data to the monitoring interface of the first module in real time, operators can view the number of chips to be retested and the processing progress. The queue capacity threshold mechanism will pause the reception of newly marked chips when the storage capacity reaches the preset limit to avoid affecting regular test tasks. Thus, chips with abnormal interruptions can be automatically identified, tracked, and prioritized for retesting by the system, ensuring the integrity of test data and the accuracy of yield statistics.

[0083] Compared to the previous embodiment, this application embodiment achieves automatic retesting of chips subjected to abnormal interruptions, reducing the need for manual intervention and improving the automation level and stability of the testing system. Simultaneously, the retesting mechanism avoids directly classifying chips with abnormal interruptions as defective, improving the effective utilization rate of chips and the accuracy of testing.

[0084] See Figure 6 The diagram shows a schematic of a recovery device for a chip mass production testing environment provided in an embodiment of this application. The recovery device is configured in ATE testing software, which includes a first module for user interaction and monitoring, and a second module for performing chip testing tasks. The ATE testing software is connected to both the chip processing equipment and the ATE testing equipment to perform tests on the semiconductor chip. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0085] The chip mass production testing environment recovery device 600 includes: The detection module 601 is used to detect whether the second module is in an abnormal state during the chip mass production test; The recovery module 602 is used to perform a recovery operation by the first module within the timeout tolerance range when the second module is detected to be in an abnormal state. The recovery operation includes at least restarting the second module and transmitting the mass production test environment context saved by the first module as a recovery parameter to the second module so that the second module can resume its running state. The test module 603 is used to re-establish the connection with the ATE test equipment after the second module resumes operation, mark the chip under test as retestable and send it to the chip processing equipment, so that the chip processing equipment can determine that the chip under test has completed the test and switch to the next chip under test, and continue to execute the chip test task through the second module, thereby realizing the restoration of the chip mass production test environment.

[0086] In this embodiment of the application, the detection module 601 may specifically include: The message sending unit is used to send heartbeat messages to the second module through the first module at a preset period; The first anomaly determination unit is used to confirm that the second module is in an abnormal state when the first module fails to continuously receive a heartbeat response from the second module within a preset confirmation period, and the number of times it fails to receive a heartbeat response reaches a preset number; or, The second anomaly determination unit is used to confirm that the second module is in an abnormal state when the termination of the second module process is detected.

[0087] In this embodiment, the timeout tolerance range is determined based on the alarm timeout threshold of the chip processing device, the alarm timeout threshold of the ATE test device, and the historical time taken for the second module to restart and reconnect to the ATE device; the recovery device 600 for the chip mass production test environment may further include: The reading module is used to read the first alarm timeout threshold of the chip processing device and the second alarm timeout threshold of the ATE test device through the first module, and to collect the historical time taken for the second module to restart and reconnect with the ATE test device; The timeout threshold determination module is used to determine the minimum alarm timeout threshold between the first alarm timeout threshold and the second alarm timeout threshold; The interval determination module is used to determine the timeout tolerance interval based on the difference between the minimum alarm timeout threshold and the historical maximum recovery time, combined with a preset safety margin.

[0088] In this embodiment of the application, the chip mass production test environment recovery device 600 may further include: The information generation module is used to record the current batch information and the chip identifier under test before each chip under test starts testing, and to record the device status snapshot and error status information after the test is completed, so as to generate and update the mass production test environment context. The device status snapshot includes a panoramic record of the operating status of the ATE test equipment and the operating status of the chip processing equipment. The storage module is used to store the mass production test environment context into the first module.

[0089] In this embodiment of the application, the test module 603 may specifically include: The request unit is used to send a reconnection request to the ATE test equipment through the second module. The synchronization unit is used to receive the handshake connection response from the ATE test equipment to complete the handshake confirmation and synchronize the status information of both parties.

[0090] In this embodiment, the second module stores a chip test plan, which is used to provide test programs for chip mass production testing; the test module 603 may further include: The task determination unit is used to reload the chip test plan and determine the test tasks to be executed. The instruction unit is used to send corresponding test instructions to the ATE test equipment based on the test task when the connection with the ATE test equipment is re-established, so as to instruct the ATE test equipment to perform tests on the chip under test. The receiving unit is used to receive test results and status information returned from the ATE test equipment.

[0091] In this embodiment of the application, the chip mass production test environment recovery device 600 may further include: The add module is used to add the currently tested chip to the retest task queue; The retest module is used to schedule the chip from the retest task queue and re-execute the test during the subsequent mass production test task execution, so as to realize the automatic retesting of the chip with abnormal interruption test.

[0092] In this embodiment, the first module includes a UI interface and a processor. The first module is used to display test status information and test data, and to monitor the running status of the second module. The second module includes a chip test plan that provides a loading program for chip mass production testing, and executes chip test tasks based on the chip test plan.

[0093] The chip mass production test environment recovery device 600 provided in this application embodiment can be applied to the chip mass production test environment recovery method provided in the foregoing embodiment. For details, please refer to the description of the chip mass production test environment recovery method provided in the above embodiment, which will not be repeated here.

[0094] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Figure 7 As shown, the electronic device 700 of this embodiment includes: at least one processor 710 ( Figure 7 (Only one is shown in the image), memory 720, ATE test software 730 installed on the electronic device, and computer program 721 stored in the memory 720 and executable on the at least one processor 710, wherein the processor 710 executes the computer program 721 to implement the steps in the above-described chip mass production test environment recovery method embodiment.

[0095] The electronic device may be an industrial control computer, a host computer, a server (rack-mounted / tower-mounted / cloud-based), an edge computing gateway / embedded industrial control host (x86 / ARM architecture), a single-board computer (SBC), a laptop / tablet, a programmable logic controller (PLC), or an equivalent device. This electronic device may include, but is not limited to, a processor 710 and a memory 720. Those skilled in the art will understand that... Figure 7 This is merely an example of electronic device 700 and does not constitute a limitation on electronic device 700. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0096] The processor 710 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0097] In some embodiments, the memory 720 may be an internal storage unit of the electronic device 700, such as a hard disk or memory of the electronic device 700. In other embodiments, the memory 720 may be an external storage device of the electronic device 700, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 700. Furthermore, the memory 720 may include both internal and external storage units of the electronic device 700. The memory 720 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 720 can also be used to temporarily store data that has been output or will be output.

[0098] The ATE test software 730 can be stored in the memory 720 of the electronic device 700 and can run on the processor 710. The ATE test software 730 may include one or more program modules (executable files, dynamic link libraries, scripts, or combinations thereof), whose instructions, when executed by the processor 710, are used to implement all or part of the steps of the chip mass production test environment recovery method described in this application. Alternatively, the processor included within the ATE test software can be used to execute all or part of the steps of the chip mass production test environment recovery method described in this application. Typically, the ATE test software 730 includes, but is not limited to, the following functional units: a first module and a second module.

[0099] In specific implementations, the processor 710, memory 720, computer program 721, and ATE test software 730 described in the embodiments of this application can execute the embodiments of the method described in this application, and will not be repeated here.

[0100] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0102] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0106] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0107] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the above method embodiments.

[0108] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of restoring a chip production test environment, characterized by, The application is applied to ATE test software, which comprises a first module for user interaction and monitoring and a second module for executing chip test tasks; the ATE test software is connected with a chip processing device and an ATE test device respectively to execute test on semiconductor chips; The method comprises: detecting whether the second module is in an abnormal state during chip mass production test; when it is detected that the second module is in the abnormal state, performing a recovery operation by the first module within a timeout tolerance interval, the recovery operation at least comprising restarting the second module and transmitting a mass production test environment context saved by the first module to the second module as a recovery parameter to make the second module recover to a running state; after the second module recovers to the running state, re-establishing connection with the ATE test device, marking a current test chip as retestable and sending it to the chip processing device to make the chip processing device determine that the current test chip is tested and switch to a next test chip and continue to execute chip test tasks by the second module to realize recovery of a chip mass production test environment.

2. The method of claim 1, wherein, The detection of whether the second module is in an abnormal state during chip mass production test comprises: sending a heartbeat packet to the second module by the first module according to a preset period; when the first module does not continuously receive a heartbeat response from the second module within a preset confirmation deadline and the number of times of non-reception reaches a preset number, it is confirmed that the second module is in the abnormal state; and / or when it is detected that the second module process is terminated, it is confirmed that the second module is in the abnormal state.

3. The method of claim 1, wherein, The timeout tolerance interval is determined based on an alarm timeout threshold of the chip processing device, an alarm timeout threshold of the ATE test device and a historical time consumption of restarting the second module and reconnecting with the ATE device; the method further comprises: reading the first alarm timeout threshold of the chip processing device and the second alarm timeout threshold of the ATE test device by the first module and collecting the historical time consumption of restarting the second module and reconnecting with the ATE test device; determining a minimum alarm timeout threshold in the first alarm timeout threshold and the second alarm timeout threshold; determining the timeout tolerance interval according to a difference between the minimum alarm timeout threshold and a historical maximum recovery time consumption combined with a preset safety margin.

4. The method of claim 1, wherein, The method further comprises: recording current batch information and the test chip identification before each test chip starts test and recording device state snapshots and error state information after test ends to generate and update the mass production test environment context, the device state snapshots comprising panoramic records of ATE test device running state and chip processing device running state; storing the mass production test environment context into the first module.

5. The method of claim 1, wherein, The re-establishment of connection with the ATE test device comprises: sending a reconnection request to the ATE test device by the second module; receiving a handshake connection response of the ATE test device to complete handshake confirmation and synchronize state information of both sides.

6. The method of claim 1, wherein, The second module stores a chip test plan, which is used to provide a test program for mass production test of the chip; The second module continues to perform the chip test task, including: reloading the chip test plan and determining the test task to be performed; in the case of reestablishing connection with the ATE test device, sending corresponding test instructions to the ATE test device based on the test task to instruct the ATE test device to perform test on the current chip under test; receiving test results and state information returned from the ATE test device.

7. The method according to any one of claims 1 to 6, wherein, After marking the current chip under test as retestable and sending it to the chip processing device, the method further includes: adding the current chip under test to a retest task queue; in the subsequent mass production test task execution process, scheduling the chip from the retest task queue and re-executing the test to realize automatic retest of the abnormal interrupted test chip.

8. The method according to any one of claims 1 to 6, wherein, The first module includes a UI interface and a processor, which is used to display test state information and test data, and monitor the running state of the second module; the second module includes a chip test plan that provides a loading program for chip mass production test, and performs a chip test task based on the chip test plan.

9. A device for restoring a chip mass production testing environment, characterized in that, The ATE test software includes a first module for user interaction and monitoring, and a second module for executing a chip test task; the ATE test software is connected with a chip processing device and an ATE test device respectively to perform test on a semiconductor chip; The device includes: a detection module for detecting whether the second module is in an abnormal state during chip mass production test; a recovery module for performing a recovery operation by the first module within a timeout tolerance interval when it is detected that the second module is in the abnormal state, the recovery operation at least including restarting the second module, and transmitting a mass production test environment context saved by the first module as a recovery parameter to the second module to make the second module recover the running state; a test module for reestablishing connection with the ATE test device after the second module recovers the running state, marking the current chip under test as retestable and sending it to the chip processing device to make the chip processing device determine that the current chip under test is tested and switch to the next chip under test, and continue to perform the chip test task by the second module to realize recovery of the chip mass production test environment.

10. An electronic device comprising a memory, a processor, ATE test software installed on the electronic device, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to realize the method of any one of claims 1 to 8.

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