Code-free power management cluster design system and method

Abstract

The present invention relates to a system and method for designing a power management cluster in a code-free manner, the system comprising at least one processor for executing at least one instruction for generating a power instance based on power component information; instructions to generate a reset controller instance disposed at a front end of the power instance and delivering a reset output to a target including the power instance; instructions to set first connection point information between the target and the reset controller instance; an instruction to generate a reset test controller instance including a test mode test data register block corresponding to the reset controller instance and a test control test data register block; an instruction for setting information of a second connection point between the reset controller instance and the reset test controller instance; instructions to generate hardware code based on the power instance, the reset controller instance, the first connection point information, the reset test controller instance, the second connection point information, and hardware code logic.

Description

Technical Field

[0001] This invention relates to a system and method for designing a power management cluster for a system-on-a-chip, and more specifically, to a system and method for designing a power management cluster in a no-code manner, wherein a test reset is passed through the same path as the functional reset path in test mode. Background Technology

[0002] A system-on-chip (SoC) is a technology that integrates multiple function blocks, such as a central processing unit (CPU), memory, interface, digital signal processing circuits, and analog signal processing circuits, onto a single semiconductor integrated circuit, or an integrated circuit (IC) based on this technology, to realize a computer system or other electronic system. SoCs are evolving into more complex systems that include processors, multimedia, graphics, interfaces, and security functions.

[0003] The system-on-a-chip can be driven in test mode to detect defects and confirm whether the system-on-a-chip is working properly during the design and manufacturing process, and can be driven in functional mode when it passes the test and is running normally.

[0004] Typically, power supply and clock design are extremely important in on-chip systems. The power supply and clock design process for an on-chip system may include the following steps: power / clock diagram drawing, Verilog coding and scripting, initial documentation, generation of Unified Power Format / Standard Design Constraint (UPF / SDC) documents, implementation layout design, secondary documentation, Design for Testability (DFT) controller insertion, hardware system analysis, and software optimization.

[0005] The power / clock diagram drawing step visually represents the power and clock structure, creating a block diagram to represent the power and clock tree. In this step, clock components and their connections are shown graphically only. The Verilog coding and scripting step creates the Verilog code and scripts used to define and implement the functions of the on-chip system to execute the hardware's register transfer level (RTL) design. That is, based on the power / clock diagram artifacts, developers manually generate the register transfer level (RTL) code.

[0006] The first textualization step is to document the design intent and structure at the beginning of the project, creating various texts such as requirement details, architecture design, power / clock diagrams, etc., required by multiple stakeholders such as the validation team and software development team.

[0007] The Unified Power Format / Standard Design Constraint file generation step involves generating Unified Power Format (UPF) and Standard Design Constraint (SDC) files for controlling power management and timing constraints, thus generating the inputs required for hardware synthesis.

[0008] The implementation layout design step involves designing and configuring the actual system-on-chip (SoC) layout at the gate level. The second documentation step involves updating and refining various documents to reflect design and implementation changes. The design-testable controller insertion step involves designing and integrating the design-testable controller and logic circuits for testing and debugging into the SoC. The hardware system analysis step involves verifying and analyzing the software's operation through simulation and verification to confirm the design's accuracy and effectiveness. The software optimization step involves analyzing and optimizing the software code running on the SoC to optimize software performance.

[0009] Typically, the functional clock / data / reset path for operation in functional mode is designed in the power / clock diagram drawing step, while the test clock / reset path for operation in test mode is designed in the design-for-test (DFT) controller insertion step. That is, the functional clock / reset design steps and the test clock / reset design steps are separate and executed independently. Therefore, the power management unit is designed to provide a reset signal to the IP block via the functional reset path when driven in functional mode, and to transmit the test reset signal to the IP block via a different path when driven in test mode.

[0010] The power management unit designed in this way does not drive the power components of the power management unit in the on-chip system reset test mode. Therefore, it is impossible to test whether the power components are working properly. Furthermore, the functional reset path and the test reset path are different, so it is impossible to test all functional reset paths, resulting in a reduction in test coverage. Summary of the Invention

[0011] The purpose of this invention is to provide a system and method for designing a power management cluster in a no-code manner. In test mode, the test reset is transmitted through the same path as the functional reset path. When a reset test is performed, each power component and IP block constituting the system-on-a-chip can be tested to confirm whether the reset function is working properly.

[0012] The present invention can be implemented in a variety of ways, including apparatus (system), method, computer program stored in a computer-readable medium, or computer-readable medium storing a computer program.

[0013] An embodiment of the present invention provides a no-code power management cluster design system comprising: a memory for storing at least one instruction; a power component repository for storing information on power components constituting the power management cluster, information on reset controller components, and information on reset test controller components; a hardware code logic repository for storing hardware code logic for generating hardware code from the designed power management cluster; and at least one processor for executing at least one instruction stored in the memory, wherein the at least one instruction includes: an instruction for generating a power instance based on the power component information; an instruction for generating a reset controller instance disposed at the front end of the power instance and transmitting a reset output to a target including the power instance; an instruction for setting first connection point information between the target and the reset controller instance; an instruction for generating a reset test controller instance including a test mode test data register (TDR) block and a test control test data register block corresponding to the reset controller instance; an instruction for setting second connection point information between the reset controller instance and the reset test controller instance; and an instruction for generating hardware code based on the power instance, the reset controller instance, the first connection point information, the reset test controller instance, the second connection point information, and the hardware code logic.

[0014] Preferably, the reset controller instance is one of the pre-reset controller instance and the post-reset controller instance.

[0015] More preferably, the pre-reset controller example includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, with the scan reset control signal (ltest_reset) and reset input (RESET_IN) connected to each input terminal, and the scan test enable signal (ltest_en) connected to the selection terminal; a first logic OR unit block, with the output of the first test multiplexer block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminals, and the synchronization block connected to the output terminal; a second logic OR unit block, with the output of the synchronization block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminals; and a second test multiplexer block, with the output of the second logic OR unit block and reset test data (TEST_MODE_RESET) input to each input terminal, the reset test mode (TEST_MODE) signal connected to the selection terminal, and the reset output (RESET_OUT) connected to the target.

[0016] More preferably, the post-reset controller example includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, where a selection terminal and one input terminal are fixed to zero level, and the other input terminals are connected to a reset input; a first logic OR block, where the output of the first test multiplexer block and the scan reset inactive signal (ltest_rstdisable) are connected to the input terminals, and the synchronization block is connected to the output terminals; a second logic OR block, where the output of the synchronization block and the scan reset inactive signal (ltest_rstdisable) are connected to the input terminals; and a second test multiplexer block, where the output of the second logic OR block and the reset test data (TEST_MODE_RESET) are input to each input terminal, the reset test mode (TEST_MODE) signal is connected to the selection terminal, and the reset output (RESET_OUT) is connected to the target.

[0017] Preferably, the reset test controller instance is implemented based on the built-in IEEE1687 standard.

[0018] Preferably, the test mode test data register block is configured to output a reset test mode (TEST_MODE) signal to the reset controller instance to activate or deactivate the target's test mode, and the test control test data register block is configured to output reset test data (TEST_MODE_RESET) to the reset controller instance in the target's test mode.

[0019] More preferably, the test control test data register block is composed of a trigger block that resets the number of bits of the test data.

[0020] Preferably, the test mode test data register block and the test control test data register block are set through the Internal Joint Test Action Group interface.

[0021] Preferably, the power component is at least one of a reset component, a clock link component, a cold reset control component, a soft reset control component, and a domain power manager (PMD) connection component.

[0022] An embodiment of the present invention provides a no-code power management cluster design method executed by at least one processor in a computer system including a power component repository and a hardware code logic repository. The power component repository stores information about power components constituting the power management cluster, reset controller components, and reset test controller components. The hardware code logic repository stores hardware code logic for generating hardware code from the designed power management cluster. The method includes the following steps: generating a power instance based on the power component information; generating a reset controller instance that is positioned at the front end of the power instance and transmits a reset output to a target including the power instance; setting first connection point information between the target and the reset controller instance; generating a reset test controller instance including a test mode test data register block and a test control test data register block corresponding to the reset controller instance; setting second connection point information between the reset controller instance and the reset test controller instance; and generating hardware code based on the power instance, the reset controller instance, the first connection point information, the reset test controller instance, the second connection point information, and the hardware code logic.

[0023] Preferably, the reset controller instance is one of the pre-reset controller instance and the post-reset controller instance.

[0024] More preferably, the pre-reset controller example includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, with the scan reset control signal (ltest_reset) and reset input (RESET_IN) connected to each input terminal, and the scan test enable signal (ltest_en) connected to the selection terminal; a first logic OR unit block, with the output of the first test multiplexer block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminals, and the synchronization block connected to the output terminal; a second logic OR unit block, with the output of the synchronization block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminals; and a second test multiplexer block, with the output of the second logic OR unit block and reset test data (TEST_MODE_RESET) input to each input terminal, the reset test mode (TEST_MODE) signal connected to the selection terminal, and the reset output (RESET_OUT) connected to the target.

[0025] More preferably, the post-reset controller example includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, where a selection terminal and one input terminal are fixed to zero level, and the other input terminals are connected to a reset input; a first logic OR block, where the output of the first test multiplexer block and the scan reset inactive signal (ltest_rstdisable) are connected to the input terminals, and the synchronization block is connected to the output terminals; a second logic OR block, where the output of the synchronization block and the scan reset inactive signal (ltest_rstdisable) are connected to the input terminals; and a second test multiplexer block, where the output of the second logic OR block and the reset test data (TEST_MODE_RESET) are input to each input terminal, the reset test mode (TEST_MODE) signal is connected to the selection terminal, and the reset output (RESET_OUT) is connected to the target.

[0026] Preferably, the reset test controller instance is implemented based on the built-in IEEE1687 standard.

[0027] Preferably, the test mode test data register block is configured to output a reset test mode (TEST_MODE) signal to the reset controller instance to activate or deactivate the target's test mode, and the test control test data register block is configured to output reset test data (TEST_MODE_RESET) to the reset controller instance in the target's test mode.

[0028] More preferably, the test control test data register block is composed of a trigger block that resets the number of bits of the test data.

[0029] Preferably, the test mode test data register block and the test control test data register block are set through the internal joint test action group interface.

[0030] Preferably, the power component is at least one of a reset component, a clock link component, a cold reset control component, a soft reset control component, and a domain power manager connection component.

[0031] One embodiment of the present invention provides a computer program stored in a computer-readable medium for performing the method in a computer.

[0032] According to the present invention, the present invention has the following effects.

[0033] According to the present invention, when designing the functional reset path that operates in the functional mode during the power / clock diagram drawing step, the test reset path that operates in the test mode can be designed automatically at the same time.

[0034] According to the present invention, the separate testability design controller insertion step can be omitted, thereby reducing the resources required for the design of power management clusters and effectively improving the efficiency of the design process.

[0035] According to the present invention, even without coding knowledge or clock operation knowledge, staff can design a power management cluster that tests the reset path of power components in test mode in a no-code manner.

[0036] In the power management cluster designed according to the present invention, a test reset path is formed through the same path as the functional reset path. Therefore, it is possible to test whether multiple components constituting the functional reset path are working properly, thereby expanding the test coverage of the power management cluster.

[0037] In the power management cluster designed according to the present invention, a reset test can be performed on the synchronization part located on the functional reset path, thereby expanding the test coverage.

[0038] When the system-on-chip according to the present invention is driven in test mode, test resets are provided to IP blocks and components, thereby enabling smooth reset tests to be performed on the components and IP blocks of the system-on-chip.

[0039] The effects of this invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains (referred to as "skilled persons") can clearly understand other effects not mentioned from the description of the scope of protection of the invention. Attached Figure Description

[0040] Embodiments of the present invention will be described with reference to the accompanying drawings, wherein similar reference numerals denote similar structural elements, but are not limited thereto.

[0041] Figure 1 This is a block diagram illustrating a typical System-on-Chip (SoC).

[0042] Figure 2 for Figure 1 A detailed structural diagram of the power management cluster (PMC) included in the system-on-a-chip.

[0043] Figure 3 This is an embodiment of a reset domain that includes a root power manager and a domain power manager designed according to the present invention.

[0044] Figure 4 This is another embodiment that includes a reset domain for a root power manager and a domain power manager designed according to the present invention.

[0045] Figure 5 This is one embodiment that includes a reset domain for a second power management interface and an IP block designed according to the present invention.

[0046] Figure 6 for Figures 3 to 5 Detailed diagram of the pre-reset controller.

[0047] Figure 7 for Figure 4 Detailed diagram of the rear reset controller.

[0048] Figure 8 This is a structural diagram of the no-code power management cluster design system of the present invention.

[0049] Figure 9 This is an example diagram illustrating the display screen of the no-code power management cluster design system of the present invention.

[0050] Figure 10 This is a flowchart illustrating the no-code power management cluster design method of the present invention.

[0051] Figure 11 An exemplary computing device is shown for performing the methods and / or embodiments, etc.

[0052] Explanation of reference numerals in the attached figures

[0053] 810: Screen Window Processing Department

[0054] 811: Command Window Processing Department

[0055] 812: Content Window Processing Department

[0056] 813: Design Window Processing Department

[0057] 814: Setting up the window handling department

[0058] 820: Power Management Cluster Processing Department

[0059] 821: Power Instance Generation Department

[0060] 822: Reset Controller Instance Generation Department

[0061] 823: Reset Test Controller Instance Generation Department

[0062] 830: Data Repository

[0063] 831: Component Repository

[0064] 832: Content Repository

[0065] 833: Power Management Cluster Repository

[0066] 834: Hardware Code Logic Repository

[0067] 840: Hardware Code Processing Department

[0068] 841: Power Hardware Code Generation Department

[0069] 842: Reset Controller Hardware Code Generation Unit

[0070] 843: Reset Test Controller Hardware Code Generation Department Detailed Implementation

[0071] Hereinafter, with reference to the accompanying drawings, the specific contents for implementing the present invention will be described in detail. However, in the following description, specific descriptions of known functions or structures will be omitted where there is a concern that this may unnecessarily obscure the spirit of the invention.

[0072] In the accompanying drawings, the same or corresponding structural elements are given the same reference numerals. Furthermore, in describing the following embodiments, repeated descriptions of the same or corresponding structural elements may be omitted. However, even if descriptions related to structural elements are omitted, it does not mean that such structural elements are not included in any embodiment.

[0073] The advantages, features, and methods of implementing the embodiments described in this specification will be referenced in the appendix. Figure 1 The invention becomes clearer from the embodiments described below. However, the invention is not limited to the embodiments disclosed below, but can be embodied in many different forms. These embodiments are provided only to fully inform those skilled in the art of the scope of the invention.

[0074] The terminology used in this specification is briefly explained, and the disclosed embodiments are described in detail. The terminology used in this specification takes into account its function in the invention and, where possible, selects generally widely used terms. However, this may be changed according to the intentions of those skilled in the art, conventions, or the emergence of new technologies. Furthermore, in certain cases, there may be an intention by the applicant to arbitrarily choose terms; in such cases, their meanings are described in detail in the description of the corresponding invention. Therefore, the terminology used in this invention is not simply a name, but should be defined based on the meaning of the term and the overall content of the invention.

[0075] Unless explicitly specified in the context as singular, singular expressions in this specification include plural expressions. And unless explicitly specified in the context as plural, plural expressions include singular expressions. Throughout this specification, when a section includes a structural element, unless otherwise stated, it implies the inclusion of other structural elements, and not the exclusion of other structural elements.

[0076] In this invention, terms such as "comprising" and "including" can indicate the presence of features, steps, actions, elements and / or structural elements, and such terms do not exclude the addition of more than one other function, step, action, element, structural element and / or combination of these.

[0077] In this invention, when referring to a specific structural element being "combined," "combined," "connected," "related," or "reacting" with other structural elements, the specific structural element may be directly combined, combined, connected, and / or related or reacting with other structural elements, but is not limited thereto. For example, at least one intermediate structural element may exist between the specific structural element and other structural elements. Furthermore, in this invention, "and / or" may include a combination of each of the at least one listed item or at least a portion of at least one item.

[0078] In this invention, terms such as "first" and "second" are used to distinguish specific structural elements from other structural elements, and the structural elements are not limited to such terms. For example, a "first" structural element can be used to represent an element with the same or similar form as a "second" structural element.

[0079] In this invention, "power components" can refer to tools used for designing power managers, i.e., domain power managers and root power manager designs. Power components for designing domain power managers include reset components and clock link components. Power components for designing root power managers include cold reset control components, soft reset control components, and domain power manager (PMD) connection components.

[0080] In this invention, a "power instance" refers to a power component included in a power manager, which can be a power component added to the design window by user operation. Power instances can also be added automatically by the design system of this invention. The characteristics of a corresponding power manager can be determined by the multiple power instances included in each power manager. In the case of some power components, when the user drags and drops the corresponding power component icon from the power component window to the design window area, a power instance corresponding to the corresponding power component can be generated. When a power instance is generated, a register corresponding to the corresponding power instance can be automatically generated. In the case of some power components, when a new root power manager is generated, it will be automatically added, thereby automatically generating a corresponding power instance and its corresponding register.

[0081] The domain power manager and root power manager can include multiple power instances for each power component type. As a power component used to design the domain power manager, power instances generated based on the reset component are called reset instances, and power instances generated based on the clock link component are called clock link instances. As a power component used to design the root power manager, power instances generated based on the domain power manager connection component are called domain power manager connection instances, power instances generated based on the cold reset control component are called cold reset control instances, and power instances generated based on the soft reset control component are called soft reset control instances. Furthermore, individual power instances can be generated based on each power component. When a power instance is generated, register field values ​​corresponding to that power instance can be automatically assigned. Hardware code can also be generated based on the register field values ​​of the power instance.

[0082] In this invention, the power element is a module that implements hardware code based on a completed power instance design, which can form a power management cluster.

[0083] In summary, power components are materials used to design power management clusters, power instances are nodes included in the design of power management clusters, and power elements are modules implemented in hardware code based on the designed power instances and capable of operating within the power management cluster.

[0084] In this invention, the target can be the destination of a reset signal. The target can be at least one of multiple IP blocks, multiple power elements constituting a power management unit, multiple clock elements constituting a clock management unit, or internal logic circuits of each unit. The clock management unit provides a functional clock to the target. A reset controller for controlling the reset of the target can be configured at the front end of each target.

[0085] Figure 1 This is a block diagram illustrating a typical System-on-Chip (SoC) device.

[0086] The system-on-a-chip may include an input / output board 110, a clock management unit 120 (CMU), a power management unit 130 (PMU), a reset management unit 140 (RMU), and at least one IP block 150, 160 (intellectual property). When the system-on-a-chip operates in functional mode, the clock management unit 120 can generate a first functional clock CLK1 to a second functional clock CLK2, which are respectively provided to the first IP block 150 to the second IP block 160.

[0087] The first IP block 150 and the second IP block 160 can be connected to the system bus and communicate with each other through the system bus. The first IP block 150 and the second IP block 160 can be a processor, a graphics processor, a memory controller, an input and output interface block, etc.

[0088] The clock management unit 120 includes multiple clock elements. When the first IP block 150 is working, it provides a first functional clock CLK1 to the first IP block 150, and when the second IP block 160 is working, it provides a second functional clock CLK2 to the second IP block 160.

[0089] The power management unit 130 includes multiple power elements that control the power supplied to the system-on-a-chip (SoC). For example, when the SoC enters a standby mode, the power management unit 130 executes power sequences PWR1 and PWR2 to power down the first IP block 150 to the second IP block 160, thus disconnecting the power supply to the IP blocks. Conversely, when the SoC operates in drive mode, the power management unit 130 executes power sequences PWR1 and PWR2 to power up the first IP block 150 to the second IP block 160, thus supplying power to the IP blocks respectively.

[0090] The reset management unit 140 detects the reset mode of the on-chip system and transmits reset signals RST1 and RST2 to the first IP block 150 to the second IP block 160 through the power management unit 130, thereby initializing the hardware. The reset signal generated in the reset management unit 140 is also transmitted to the power management unit 130 and the clock management unit 120. When IP blocks 150 and 160 are reset, multiple power elements of the power management unit 130 and multiple clock elements of the clock management unit 120 are also reset.

[0091] Reset modes can initialize specific parts of the system or restore the system to a specific state. Reset modes include Power On Reset (POR_reset), Pin Activated Reset (PAD_reset), Software Reset, Watchdog Reset, Brown Out Reset (BOR_reset), Cold Reset, and Soft Reset.

[0092] A cold reset occurs when power is turned off and then on again, and all system states are initialized. Power-on reset and pin-activated reset can be considered cold resets. A soft reset occurs while power is maintained, and only a portion of the system is initialized. Only the central processing unit and some hardware modules are reset; memory and other components are retained.

[0093] That is, depending on the type of reset, all components and the entire IP block of the system-on-a-chip can be reset, or only a portion of the IP block and a portion of the components can be reset.

[0094] During the operation of the system-on-a-chip in functional mode, in order to maintain the reliability, stability and security of the system, such as system restart, system error recovery, firmware / software updates, power supply instability, clock and timer problem resolution, and external condition changes, it is necessary to initialize multiple components or multiple IP blocks that constitute the system-on-a-chip device.

[0095] The reset management unit 140 may include a functional reset generation unit that generates and distributes reset signals in functional mode. The functional reset generation unit can receive trigger signals from multiple reset sources (such as power-on, external reset pins, watchdog timers, software instructions, etc.) to generate reset signals and distribute the generated reset signals to various components within the system chip, thereby resetting those components. When the system chip operates in functional mode, the path used to transmit the reset signal can be called the functional reset path, and the destination of the reset signal can be called the target.

[0096] Figure 2 for Figure 1 A detailed structural diagram of the power management cluster (PMC) included in the system-on-a-chip.

[0097] The system-on-a-chip includes a power management cluster 200 (PMC). The power management cluster 200 is connected to at least one IP block 150. The system-on-a-chip may include at least one power management cluster 200. The IP block 150 can be... Figure 1 The first IP block is 150.

[0098] The power management cluster 200 may include: a domain power manager 220 (PMD, Power Management for Domain), which controls the power of IP block 150; a root power manager 210 (PMR, Power Management for Root), which manages the domain power manager 220; a first power management interface 230 (PMIF, Power Management Interface), located between the domain power manager 220 and the clock management unit 120; and a second power management interface 240 (PMIF, Power Management Interface), located between the domain power manager 220 and IP block 150. The clock management unit 120 can provide functional clocks to the root power manager 210, domain power manager 220, first power management interface 230, second power management interface 240, and IP block 150. The clock management unit 120 can provide... Figure 1 Clock management unit 120.

[0099] The root power manager 210 and the domain power manager 220 are set in the always-on (AON) domain area, the first power management interface 230 is set on the clock management unit 120 side, and the second power management interface 240 is set on the IP block 150 side.

[0100] The root power manager 210 may include: a cold reset control element 211, which receives a cold reset signal to reset all clock / power components and all IP blocks of the on-chip system device; a soft reset control element 212, which receives a soft reset signal to reset a subset of components and IP blocks of the on-chip system device; and a domain power manager connection element 213, which manages connections to the domain power managers (PMDs). Domain power managers 220 can be connected to the root power manager 210 via the domain power manager connection element 213. In the figure, one domain power manager 220 can be connected to the root power manager 210, and one domain power manager connection element can be connected to multiple domain power managers, thus connecting multiple domain power managers through multiple domain power manager connection elements.

[0101] Cold reset and soft reset signals can be received from the functional reset generation unit. Cold reset control element 211 and soft reset control element 212 can control the registers of the root power manager 210 and / or the registers of the domain power manager 220 to reset the clock / circuit elements of the logic circuits controlled by the corresponding registers. Furthermore, the internal logic circuits controlled by the root power manager 210 can also be reset.

[0102] Domain power manager 220 includes: a clock management unit link control element 221 for controlling the link with clock management unit 120; and a reset element 222 for sending a reset signal to IP block 150. Furthermore, domain power manager 220 also includes internal logic circuitry within the domain power manager itself.

[0103] The first power management interface 230 to the second power management interface 240 each include PMIF internal logic circuits as internal logic circuits, and physically transmit control signals output from the domain power manager 220 to the clock control unit 120 and IP block 150.

[0104] As described above, the root power manager 210 and the domain power manager 220 are physically located in the same always-on domain region, the first power management interface 230 and the clock management unit 120 are physically located in the same power domain region, and the second power management interface 240 and the IP block 150 are physically located in the same power domain region.

[0105] In this invention, reset domains can be distinguished based on physical power domain regions. That is, the root power manager 210 and the domain power manager 220 can constitute a reset domain, the first power management interface 230 and the clock management unit 120 can constitute a reset domain, and the second power management interface 240 and the IP block 150 can constitute a reset domain.

[0106] Figure 3 This is an embodiment that includes a reset domain of the root power manager and the domain power manager according to the present invention.

[0107] The reset domain includes multiple reset controllers 311, 312, 313, and 314. These controllers are positioned at the front end of the target and receive the functional reset and the target's functional clock. They selectively output a functional reset or test reset synchronized with the functional clock. These reset controllers can be placed in the target's functional reset path, and any target's functional reset path can include at least one reset controller. All reset controllers 311, 312, 313, and 314 can be front-end reset controllers 311, 312, 313, and 314.

[0108] The targets may include multiple elements 211, 212, 213 constituting the root power manager 210, internal logic circuits of the root power manager, multiple elements 221, 222 constituting the domain power manager 220, internal logic circuits of the domain power manager, etc.

[0109] The pre-reset controller 312, which targets the cold reset control element 211, can selectively output a functional reset or test reset synchronized with the functional clock of the cold reset control element 211. The pre-reset controller 313, which targets the soft reset control element 212, the root power manager's internal logic circuit, and the domain power manager connection element 213, can selectively output a functional reset or test reset synchronized with the target's functional clock. The pre-reset controller 314, which targets the domain power manager 220, can selectively output a functional reset or test reset synchronized with the domain power manager's functional clock.

[0110] When the function reset generation unit 340 sets the register, it can output a function reset to the pre-reset controller 311. The reset output of the pre-reset controller 311 is provided as the reset input to the back-end pre-reset controllers 312 and 313. The reset output of the pre-reset controller 312 is provided to the cold reset control element 211. The reset output of the pre-reset controller 313 is provided to the soft reset control element 212 and the domain power manager connection element 213, and is also provided as the reset input to the back-end pre-reset controller 314. The reset output of the pre-reset controller 314 is provided to the domain power manager 220.

[0111] The reset domain includes: a scan test controller 320, which outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is activated, a scan reset control signal (ltest_reset) controlling the reset in scan test mode, and a scan reset inactivation signal (ltest_rstdisable) controlling the inactivation of the reset in scan test mode to the pre-reset controllers 311, 312, 313, and 314; and a reset test controller 330, which outputs a reset test mode signal (TEST_MODE) indicating whether the target is in test mode and the target's reset test data (TEST_MODE_RESET) to each pre-reset controller 311, 312, 313, and 314.

[0112] Figure 4 This is another embodiment that includes a reset domain for a root power manager and a domain power manager designed according to the present invention.

[0113] The reset domain includes multiple reset controllers 411, 412, 413, and 414, which are positioned at the front end of the target. These controllers receive a functional reset and the target's functional clock, and selectively output a functional reset or test reset synchronized with the functional clock. Such reset controllers can be configured within the target's functional reset path. Any target's functional reset path may include at least one reset controller. The reset controllers include a front reset controller 411 positioned at the very front of the functional reset path within the reset domain, and rear reset controllers 412, 413, and 414 connected to the rear end of the front reset controller 411 within the reset domain.

[0114] The targets may include multiple elements 211, 212, 213 constituting the root power manager 210, internal logic circuits of the root power manager, multiple elements 221, 222 constituting the domain power manager 220, internal logic circuits of the domain power manager, etc.

[0115] When the function reset generation unit 440 sets the register, it can input a function reset to the pre-reset controller 411. The reset output of the pre-reset controller 411 is provided to the reset input of the rear-end reset controllers 412 and 413.

[0116] The post-reset controller 412 targets the cold reset control element 211 and can selectively output a functional reset or test reset synchronized with the functional clock of the cold reset control element 211. The post-reset controller 413 targets the soft reset control element 212, the root power manager's internal logic circuit, and the domain power manager connection element 213 and can selectively output a functional reset or test reset synchronized with the functional clock of each target. The post-reset controller 414 targets the domain power manager 220 and can selectively output a functional reset or test reset synchronized with the functional clock of the domain power manager.

[0117] The reset output of the pre-reset controller 411 is provided as the reset input of the subsequent post-reset controllers 412 and 413. The reset output of the post-reset controller 412 is provided to the cold reset control element 211. The reset output of the post-reset controller 413 is provided to the soft reset control element 212 and the domain power manager connection element 213, and is also provided as the reset input of the subsequent post-reset controller 414. The reset output of the post-reset controller 414 is provided to the domain power manager 220.

[0118] The reset domain includes: a scan test controller 420, which outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is activated, a scan reset control signal (ltest_reset) controlling the reset in the scan test mode, and a scan reset inactivation signal (ltest_rstdisable) controlling the inactivation of the reset in the scan test mode; and a reset test controller 430, which outputs a reset test mode signal (TEST_MODE) indicating whether the target is in test mode and the target's reset test data (TEST_MODE_RESET).

[0119] The scan test enable signal (ltest_en) and scan reset control signal (ltest_reset) are provided only to the pre-reset controller 411. The scan reset inactivation signal (ltest_rstdisable), reset test mode signal (TEST_MODE), and reset test data (TEST_MODE_RESET) are provided to the pre-reset controller 411, and the post-reset controllers 412, 413, and 414.

[0120] Figure 5 This is one embodiment that includes the reset domain of an IP block of a second power management interface according to the present invention.

[0121] The reset domain may include a pre-reset controller 511, which is positioned at the front of the target, receives the functional reset and the target's functional clock, and selectively outputs a functional reset or test reset synchronized with the functional clock. The pre-reset controller 511 is positioned at the very beginning of the functional reset path within the reset domain. Although described as... Figure 5 The reset domain of this embodiment includes only the pre-reset controller, but is not limited to this; a post-reset controller may also be added after the pre-reset controller. The target may include the internal logic circuitry of the power management interface of the second power management interface and IP block 150, etc.

[0122] The reset domain also includes: a scan test controller 520, which outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is activated, a scan reset control signal (ltest_reset) controlling the reset in the scan test mode, and a scan reset inactivation signal (ltest_rstdisable) controlling the inactivation of the reset in the scan test mode to the pre-reset controller 511; and a reset test controller 530, which outputs a target reset test mode signal (TEST_MODE) indicating whether the target is in the test mode and the target's reset test data (TEST_MODE_RESET) to the pre-reset controller 511.

[0123] Figure 3Scan test controller 320 and Figure 4 Scan test controller 420 and Figure 5 The scanning test controller 520 can use the same structural elements. Preferably, Figure 3 Reset test controller 330 and Figure 4 Reset test controller 430 and Figure 5 The reset test controller 530 performs the same function, and separate reset test controllers 330, 430, and 530 are set up for each reset domain.

[0124] Figure 6 for Figures 3 to 5 Detailed diagram of the pre-reset controller.

[0125] The scan test controller 610 outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is activated, a scan reset control signal (ltest_reset) controlling reset in scan test mode, and a scan reset inactivation signal (ltest_rstdisable) controlling reset deactivation in scan test mode. The reset test controller 620 outputs a reset test mode signal (TEST_MODE) indicating whether the target is in test mode, and reset test data (TEST_MODE_RESET).

[0126] The pre-reset controller 630 activates the reset function in scan test mode based on the scan test enable signal (ltest_en), scan reset control signal (ltest_reset), scan reset inactive signal (ltest_rstdisable), reset test mode signal (TEST_MODE), reset test data (TEST_MODE_RESET), and reset input (RESET_IN). During the period when the target's reset test mode is active, it outputs reset test data to the target.

[0127] The pre-reset controller 630 includes a synchronization unit 633 that synchronizes the function reset with the function clock of the target. In scan test mode, the synchronization unit 633 is reset during the period when the reset function is activated.

[0128] The reset test controller 620 may include: a test mode test data register 621, which outputs a reset test mode signal (TEST_MODE) indicating whether the target's reset test mode is activated or deactivated; and a test control test data register 622, which outputs reset test data (TEST_MODE_RESET) when the target is activated into reset test mode. The test mode test data register 621 and the test control test data register 622 can each be implemented as a flip-flop-based shift register structure.

[0129] The reset test controller 620 can be a controller based on the built-in IEEE 1687 standard. The reset test controller 620 can configure the test mode test data register 621 and the test control test data register 622 through the internal joint test action group (IJTAG) interface.

[0130] The test mode test data register 621 can be constructed from flip-flops, and can output a reset test mode signal indicating whether the target's reset test mode is active or inactive to the pre-reset controller 630. The reset test mode signal can be a 1-bit signal. The test control test data register 622 can be constructed from flip-flops, and can output reset test data (TEST_MODE_RESET) to the pre-reset controller 630. The reset test data determines whether to reset the target's value when the reset test mode is active. Therefore, the reset test data can be a 1-bit signal.

[0131] The pre-reset controller 630 may include: a first test multiplexer 631 (TMUX), which receives a scan reset control signal (ltest_reset) and a reset input (RESET_IN) at various input terminals, and a scan test enable signal (ltest_en) at a selection terminal, and outputs one of the scan reset control signal (ltest_reset) and the reset input (RESET_IN) according to the scan test enable signal (ltest_en); and a first logic OR unit 632, which performs a logical OR operation on the output of the first test multiplexer 631 and a scan reset inactive signal (ltest_rstdisable) and outputs it to a synchronization unit 633. The reset input (RESET_IN) is used to input a functional reset from a register.

[0132] When the scan test enable signal (ltest_en) is in scan test active mode, the first test multiplexer 631 selects and outputs the scan reset control signal. When the scan test enable signal (ltest_en) is not in scan test active mode, the first test multiplexer 631 selects and outputs the reset input (RESET_IN). When at least one of the output of the first test multiplexer 631 and the scan reset inactive signal (ltest_rstdisable) is "high", the first logic OR unit 632 will output "high". Thus, when the scan test is activated, the first test multiplexer 631 and the first logic OR unit 632 can control the scan reset control signal (ltest_reset) and reset the synchronization unit 633.

[0133] When the scan test is not activated, a reset input (RESET_IN) is input to the synchronization unit 633. The synchronization unit 633 synchronizes the reset input with the target's functional clock CLK and outputs it.

[0134] The pre-reset controller 630 includes: a second logic OR unit 634, which performs a logic OR operation on the output of the synchronization unit 633 and the scan reset inactive signal (ltest_rstdisable); and a second test multiplexer 635, which inputs the output of the second logic OR unit 634 and the reset test data (TEST_MODE_RESET) to each input terminal, inputs the reset test mode (TEST_MODE) signal to the selection terminal, and outputs one of the output of the second logic OR unit 634 and the reset test data (TEST_MODE_RESET) as a reset output (RESET_OUT) according to the reset test mode (TEST_MODE) signal.

[0135] Figure 7 for Figure 4 Detailed diagram of the rear reset controller.

[0136] The scan test controller 710 outputs a scan reset inactivation signal (ltest_rstdisable) to the rear reset controller 730 in scan test mode to control the inactivation of reset.

[0137] The rear reset controller 730 activates the reset function in scan test mode based on the scan reset inactive signal (ltest_rstdisable), the target reset test mode signal (TEST_MODE), the target reset test data (TEST_MODE_RESET), and the reset input (RESET_IN) from the front-end reset controller. During the activation of the reset test mode, it outputs reset test data to the target. The front-end reset controller can be either a front-end reset controller or a rear-end reset controller.

[0138] The post-reset controller 730 includes a synchronization unit 733 that synchronizes the function reset with the target function clock. In scan test mode, during the period when the reset function is activated, the synchronization unit 733 is reset via the reset input (RESET_IN).

[0139] The reset test controller 720 may include: a test mode test data register 721, which outputs a reset test mode signal (TEST_MODE) indicating whether the target's reset test mode is activated or deactivated; and a test control test data register 722, which outputs reset test data (TEST_MODE_RESET) when the target is activated into reset test mode. The test mode test data register 721 and the test control test data register 722 can each be implemented as a flip-flop-based shift register structure. Figure 7 The reset test controller 720, test mode test data register 721, and test control test data register 722 execute and Figure 6 The reset test controller 620, test mode test data register 621 and test control test data register 622 have the same functions.

[0140] The reset test controller 720 can be a controller based on the built-in IEEE 1687 standard. The reset test controller 720 can set the test mode test data register 721 and the test control test data register 722 through the internal joint test action group (IJTAG) interface.

[0141] The test mode test data register 721 can be constructed from flip-flops and can output a reset test mode signal indicating the activation / deactivation of the target's reset test mode to the rear reset controller 730. That is, the reset test mode signal can be a 1-bit signal. The test control test data register 722 can also be constructed from flip-flops and can output reset test data (TEST_MODE_RESET) to the rear reset controller 730. The reset test data can determine whether to reset the target value when the reset test mode is activated. Therefore, the reset test data can be a 1-bit signal.

[0142] The post-reset controller 730 may include: a first test multiplexer 731 (TMUX), whose select terminal and one input terminal are respectively fixed to zero level (0tie (0 connection)), and which inputs a reset input (RESET_IN) to other input terminals, thereby outputting a reset input (RESET_IN); and a first logic OR unit 732, which performs a logical OR operation on the reset input (RESET_IN) output from the first test multiplexer 731 and the scan reset inactive signal (ltest_rstdisable), and outputs it to the synchronization unit 733. The reset input (RESET_IN) can be input from either the front-end pre-reset controller or the post-reset controller. When at least one of the reset input (RESET_IN) and the scan reset inactive signal (ltest_rstdisable) is "high", the first test multiplexer 732 will output "high".

[0143] The reset input (RESET_IN) is passed from either the front-end pre-reset controller or the rear-end target reset controller. Therefore, when a scan test is activated, the reset input (RESET_IN) can be passed according to the functional reset path to perform a reset test, and the synchronization unit 733 can be reset. Furthermore, the synchronization unit 733 synchronizes the reset input (RESET_IN) with the target's functional clock CLK and outputs it.

[0144] The post-reset controller 730 includes: a second logic OR unit 734, which performs a logic OR operation on the output of the synchronization unit 733 and the scan reset inactive signal (ltest_rstdisable); and a second test multiplexer 735, wherein the output of the second logic OR unit 734 and the reset test data (TEST_MODE_RESET) are input to each input terminal, the reset test mode (TEST_MODE) signal is input to the selection terminal, and according to the reset test mode (TEST_MODE) signal, one of the output of the second logic OR unit 734 and the reset test data (TEST_MODE_RESET) is output as a reset output (RESET_OUT).

[0145] Right now, Figure 7 The post-reset controller 730 will Figure 6 The scan test enable signal (ltest_en) and scan reset control signal (ltest_reset) of the pre-reset controller 630 are fixed to zero level, causing the first test multiplexer 731 to output a reset input (RESET_IN) to the first logic OR unit 732.

[0146] thus, Figure 6The pre-reset controller 630 independently and selectively outputs the scan reset control signal (ltest_reset) and the scan input (RESET_IN) based on the scan test enable signal (ltest_en). However, Figure 7 The rear reset controller 730 receives the front-end scan output (RESET_OUT) as a scan input (RESET_IN) and performs a reset, thus it can be executed according to the functional reset path.

[0147] Figure 8 This is a structural diagram of the no-code power management cluster design system of the present invention. The no-code power management cluster design system of the present invention can be implemented through a computer system. The power management cluster design system of the present invention can be used for designing... Figures 3 to 7 A power management cluster system.

[0148] The no-code power management cluster design system of the present invention may include: a screen window processing unit 810, which detects user input and outputs the processing result of the user input to the display screen; a power management cluster processing unit 820, which generates at least one power instance based on power component information, and generates a reset controller instance and a reset test controller instance, and sets the connection points between the power instance and the reset controller instance and the reset test controller instance to design the power management cluster; a data storage unit 830, which stores hardware code logic for generating hardware code based on power component information and the designed power management cluster; and a hardware code processing unit 840, which uses the hardware code logic to generate hardware code corresponding to the designed power management cluster.

[0149] Figure 9 This is an example diagram illustrating the display screen of the no-code power management cluster design system of the present invention.

[0150] The display screen of the no-code power management cluster design system of the present invention may include: a command window 910 for inputting user commands; a power component window 920 for displaying multiple power component icons; a content window 930 for providing an environment for adding, deleting, and changing the list of power management clusters under design, and displaying a list of power instances constituting each power management cluster under design and functional information of each power instance layer by layer; a design window 940 for displaying the power diagram of the power management cluster under design, and providing an environment for adding, deleting, and changing the power instances constituting the power management cluster under design; and a setting window 950 for providing a setting environment for the functions of the power instances selected from the design window 940.

[0151] Command window 910 may include: a CHECK button, which receives error checking instructions such as the power diagram of the power management cluster under design and the setting values ​​of multiple power instances constituting the power management cluster under design; an UNCHECK button, which receives instructions to not activate the check results; a SAVE button, which receives instructions to save the power diagram displayed in design window 940; and a GENRTL button, which receives instructions to generate hardware code for the power diagram displayed in design window 940.

[0152] The Power Components window 920 can display multiple icons listing the power components that can be used to design a power management cluster. Power components may include the cold reset control component, soft reset control component, and domain power manager connection component required for designing the root power manager. The cold reset control component and soft reset control component are mandatory for the root power manager and are not displayed in the Power Components window 920; instead, they are automatically inserted into the newly created root power manager. Power components may also include the clock management unit link control component and reset component required for designing the domain power manager.

[0153] The cold reset control component, soft reset control component, domain power manager connection component, clock management unit link control component, and reset component are all implemented as hardware code, and are used as... Figures 2 to 4 The design elements for the operation of the cold reset control element 211, the soft reset control element 212, the domain power manager connection element 213, the clock management unit link control element 221, and the reset element 222.

[0154] Content window 930 displays a list of power management clusters under design and provides an environment for adding, deleting, and modifying these clusters. Below each power management cluster list, a list of power instances constituting that cluster is displayed. Design window 940 displays the power diagram of the power management clusters and provides an environment for adding, deleting, and modifying the power instances constituting those clusters. When a user drags and drops any power component from power component window 920 into design window 940, a corresponding power instance is generated within the corresponding power management cluster under design.

[0155] The settings window 950 provides a functional settings environment for the power instance selected from the design window 940.

[0156] Screen Window Processing Unit 810

[0157] The screen window processing unit 810 may include: a command window processing unit 811, which displays buttons for receiving user commands in the command window 910, detects input to each button in the command window 910, and executes the work corresponding to the input button; a content window processing unit 812, which displays a list of power management clusters and a list of power instances and register information included in each power management cluster under design in the content window 930, and detects user input in the content window 930 and executes the work corresponding to the user input; a design window processing unit 813, which displays the power diagram of the power management cluster under design selected by the user in the design window 940, detects user input in the design window 940, and executes the work corresponding to the user input; and a setting window processing unit 814, which displays setting information of the power management cluster and power instances under design selected by the user in the setting window 950, detects user input in the setting window 950, and executes the work corresponding to the user input.

[0158] When the CHECK button is selected, the command window processing unit 811 checks for errors in the power diagram of the power management cluster under design and the settings of the multiple power instances constituting the power management cluster under design, and displays the parts where errors occurred. When the UNCHECK button is selected, the command window processing unit 811 restores the erroneous parts of the power diagram of the power management cluster under design to their original state and displays them. When the SAVE button is selected, the command window processing unit 811 stores the job content of the power management cluster under design displayed in the design window 940 in the data repository 830. When the GENRTL button is selected, the command window processing unit 811 generates hardware code for the power diagram of the power management cluster under design displayed in the design window 940.

[0159] The content window processing unit 812 provides an environment for adding, deleting, and modifying the list of power management clusters under design and the list of power instances included in each power management cluster under design. The content window processing unit 812 can display the list of power instances and the register information of each power instance hierarchically below each power management cluster under design. Users can add, delete, and change the names of power management clusters under design in the content window 930. Corresponding to user input, the list of power management clusters under design can be added, deleted, and modified in the power management cluster repository 833. When a user changes the name of a power management cluster under design, the content window processing unit 812 can simultaneously change the name of the corresponding power management cluster under design, as well as the names of the power instances and registers below that corresponding power management cluster.

[0160] The design window processing unit 813 displays the power diagram of the power management cluster under design in the design window 940, providing an environment for adding, deleting, and changing power instances that constitute the power management cluster under design. When a user adds any power component from the power component window 920 to the design window 940, the design window processing unit 813 detects it and executes the power instance addition operation.

[0161] The setting window processing unit 814 displays the setting information of the power management cluster and power instance under design, detects user input in the setting window 950, and performs work corresponding to the user input.

[0162] Data repository 830

[0163] The data repository 830 may include: a component repository 831, storing information on power components, reset controller components, and reset test controller components; a content repository 832, storing a list of power instances included in the power management cluster under design and a list of registers corresponding to each power instance; a power management cluster repository 833, storing functional information of individual power instances included in the power management cluster under design, reset controller instance information, and reset test controller instance information; and a hardware code logic repository 834, storing hardware code logic for generating hardware code based on the designed power management cluster information. The reset controller instance is implemented as hardware code and is used as... Figures 3 to 7 The design elements for the operation of the pre-reset controller or post-reset controller, the reset test controller instance is implemented as hardware code, and is used as... Figures 3 to 7 The design elements for the operation of the reset test controller.

[0164] The power components stored in component repository 831 may include a cold reset control component, a soft reset control component, a domain power manager connection component, a clock management unit link control component, and a reset component. Furthermore, component repository 831 stores a reset controller component and a reset test controller component.

[0165] Content repository 832 stores the power management cluster under design, a list of power instances, and a list of registers corresponding to the power instances.

[0166] The power management cluster repository 833 stores information about each power instance, reset controller instance, reset test controller instance, connection point between the scan test controller and the reset controller instance, connection point between the power instance and the reset controller instance, and connection point between the reset controller instance and the reset test controller instance, all included in the power management cluster under design.

[0167] The hardware code logic repository 834 stores the hardware code logic generated based on the designed power management cluster information, power instance information, and register information. When a power instance is generated as hardware code, it can be implemented as a power element. When a reset controller instance is generated as hardware code, it can be implemented as a reset controller. When a reset test controller instance is generated as hardware code, it can be implemented as a reset test controller. Furthermore, when the connection point information is generated as hardware code, the scan test controller can connect to the reset controller, the reset controller can connect to the reset test controller, and the reset controller can connect to the power element.

[0168] Power Management Cluster Processing Unit 820

[0169] The power management cluster processing unit 820 includes: a power instance generation unit 821, which generates new power instances based on power component information; a reset controller instance generation unit 822, which generates reset controller instances connected to the power instances; and a reset test controller instance generation unit 823, which generates reset test controller instances connected to the reset controller instances.

[0170] When a user adds any power component from the power component window 920 to the design window 940, the power instance generation unit 821 can run and generate a new power instance. The name of the new power instance may include the name of the power management cluster under design that contains the new power instance and information about the type of power component in the new power instance. The power instance generation unit 821 can automatically generate the necessary power instances without user input. For example, cold reset control instances and soft reset control instances may be required to be included in the root power manager.

[0171] The reset controller instance generation unit 822 generates a reset controller instance that is positioned in front of a power instance and transmits a reset output to at least one target including the power instance. The present invention can be designed such that at least two reset controller instances are connected. The reset controller instances can be configured as a pre-set reset controller instance and a post-set reset controller instance. Without user input, when a power instance is generated, the reset controller instance generation unit 822 can automatically operate, generate a reset controller instance, and set the connection point information between the power instance and the reset controller instance.

[0172] An example of a pre-reset controller includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, with the scan reset control signal (ltest_reset) and reset input (RESET_IN) connected to their respective input terminals, and the scan test enable signal (ltest_en) connected to the selection terminal; a first logic OR unit block, with the output of the first test multiplexer block and the scan reset inactivation signal (ltest_rstdisable) connected to the input terminals, and the synchronization block connected to the output terminal; a second logic OR unit block, with the output of the synchronization block and the scan reset inactivation signal (ltest_rstdisable) connected to the input terminals; and a second test multiplexer block, with the output of the second logic OR unit block and reset test data (TEST_MODE_RESET) input to each input terminal, the reset test mode (TEST_MODE) signal connected to the selection terminal, and the reset output (RESET_OUT) connected to the target.

[0173] The synchronization block, first test multiplexer block, first logic OR unit block, second logic OR unit block, and second test multiplexer block of the pre-reset controller instance are respectively generated as hardware code, which can be implemented as follows: Figure 6 The system includes a synchronization unit 633, a first test multiplexer 631, a first logic OR unit 632, a second logic OR unit 634, and a second test multiplexer 635.

[0174] An example of a post-reset controller includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, where the selection terminal and one input terminal are fixed to zero level, and the other input terminals are connected to the reset input; a first logic OR block, where the scan reset inactivation signal (ltest_rstdisable) is connected to the input terminals, and the synchronization block is connected to the output terminals; a second logic OR block, where the output of the synchronization block and the scan reset inactivation signal (ltest_rstdisable) are connected to the input terminals; and a second test multiplexer block, where the output of the second logic OR block and the reset test data (TEST_MODE_RESET) are input to each input terminal, the reset test mode (TEST_MODE) signal is connected to the selection terminal, and the reset output (RESET_OUT) is connected to the target.

[0175] The synchronization block, first test multiplexer block, first logic OR unit block, second logic OR unit block, and second test multiplexer block of the post-reset controller instance are respectively generated as hardware code and can be implemented as follows: Figure 7 The synchronization unit 733, the first test multiplexer 731, the first logic OR unit 732, the second logic OR unit 734, and the second test multiplexer 735.

[0176] Without user input, when a reset controller instance is generated, the reset test controller instance generation unit 823 automatically operates and generates a reset test controller instance, and can generate connection point information between reset controller instances. The reset test controller instance may include a test mode test data register block and a test control test data register block. The test mode test data register block can be configured to provide a reset test mode (TEST_MODE) signal to the selection terminal of the second test multiplexer block of the reset controller instance, and the test control test data register block is configured to provide reset test data (TEST_MODE_RESET) to the second test multiplexer block of the reset controller instance. The reset test controller instance generation unit 823 can generate a test control test data register block consisting of a trigger chain of bits of reset test data.

[0177] The reset test controller example is a controller based on the built-in IEEE1687 standard. The test mode test data register block and the test control test data register block can be designed separately through the Internal Joint Test Action Group (IJTAG) interface.

[0178] Hardware Code Processing Unit 840

[0179] The hardware code processing unit 840 may include: a power hardware code generation unit 841, which generates hardware code corresponding to the functional modules of the power components based on the designed power instance information; a reset controller hardware code generation unit 842, which generates hardware code corresponding to the reset controller based on the designed reset controller instance information; and a reset test controller hardware code generation unit 843, which generates hardware code corresponding to the reset test controller based on the reset test controller instance information. Driven by the hardware code processing unit 840, the power instance, reset controller instance, and reset test controller instance can be implemented as follows: Figures 2 to 7 Power components, reset controllers, and reset test controllers.

[0180] The hardware code processing unit 840 can be executed when the GENRTL button in the command window 910 is pressed. The user selects the GENRTL button to run the program while the power diagram of the power management cluster under design is displayed in the design window 940. Before running the GENRTL button, a check button can be executed to pre-verify whether any errors have occurred in the power diagram.

[0181] Figure 10This diagram illustrates the workflow of the no-code power management cluster design method of the present invention. The no-code power management cluster design method of the present invention can be executed by the processor of a computer system.

[0182] The computer system includes: a component repository that stores information on power components, reset controller components, and reset test controller components; and a hardware code logic repository that stores the hardware code logic used to generate the designed power management cluster into hardware code.

[0183] The processor generates a root power manager based on the user's operation, and generates the power instance required for the root power manager (step S1010).

[0184] The processor generates a reset controller instance that is set at the front end of the power instance and transmits the reset output to the target, and sets the connection point information between the power instance and the reset controller instance (step S1020).

[0185] Based on user operations and power component information, the processor generates a new power instance, generates a reset controller instance in front of the new power instance, and sets the connection point information between the power instance and the reset controller instance (step S1030).

[0186] The reset controller instance can be either a pre-reset controller instance or a post-reset controller instance.

[0187] An example of a pre-reset controller includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, with the scan reset control signal (ltest_reset) and reset input (RESET_IN) connected to each input terminal, and the scan test enable signal (ltest_en) connected to the selection terminal; a first logic OR unit block, with the output scan reset inactive signal (ltest_rstdisable) of the first test multiplexer block connected to the input terminal, and the synchronization block connected to the output terminal; a second logic OR unit block, with the output of the synchronization block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminal; and a second test multiplexer block, with the output of the second logic OR unit block and the reset test data (TEST_MODE_RESET) input to each input terminal, the reset test mode (TEST_MODE) signal connected to the selection terminal, and the reset output (RESET_OUT) connected to the target.

[0188] An example of a post-reset controller includes: a synchronization block connected to the target's functional clock; a first test multiplexer block, with one selection terminal and one input terminal fixed at zero level, and a reset input connected to other input terminals; a first logic OR unit block, with the output of the first test multiplexer block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminals, and the synchronization block connected to the output terminals; a second logic OR unit block, with the output of the synchronization block and the scan reset inactive signal (ltest_rstdisable) connected to the input terminals; and a second test multiplexer block, with the output of the second logic OR unit block and the reset test data (TEST_MODE_RESET) input to each input terminal, the reset test mode (TEST_MODE) signal connected to the selection terminal, and the reset output (RESET_OUT) connected to the target.

[0189] The processor generates a reset test controller instance that generates a reset test mode (TEST_MODE) signal and reset test data (TEST_MODE_RESET) in test mode (step S1040). The reset test controller instance includes a test mode test data register block and a test control test data register block. The test mode test data register block is configured to output a reset test mode signal to the reset controller instance, and the test control test data register block is configured to output reset test data to the reset controller instance.

[0190] The processor sets the connection point information between the test mode test data register block and the test control test data register block and the reset controller instance (step S1050). That is, the test mode signal of the test mode test data register block is connected to the selection terminal of the second test multiplexer block, and the reset test data of the test control test data register block is connected to the input terminal of the second test multiplexer block.

[0191] The processor generates the hardware code for the designed power management cluster based on the power instance, reset controller instance, reset test controller instance, and the configuration information of each connection point and the hardware code logic (step S1060).

[0192] Figure 11An exemplary computing device 1100 is shown for performing the methods and / or embodiments, etc. According to one embodiment, the computing device 1100 may be implemented using hardware and / or software for user interaction. The computing device 1100 may include, but is not limited to, a laptop computer, a desktop computer, a workstation, a personal digital assistant, a server, a blade server, a mainframe, etc. The structural elements, connections, and functions of the computing device 1100 are illustrative, and the examples of the invention described herein and / or claimed within the scope of the invention are not limited thereto.

[0193] The computing device 1100 includes a processor 1110, a memory 1120, a storage device 1130, a communication device 1140, a high-speed interface 1150 connected to the memory 1120 and a high-speed expansion port, and a low-speed interface 1160 connected to a low-speed bus and the storage device. The structural elements 1110, 1120, 1130, 1140, 1150, and 1160 can be interconnected using various buses, and can be mounted on the same mainboard or connected through other suitable means. The processor 1110 can perform basic arithmetic, logic, and input / output operations, thereby processing computer program instructions. For example, the processor 1110 can process instructions stored in the memory 1120, storage device 1130, etc., and / or instructions running within the computing device 1100, thereby enabling the display of graphical information on an external input / output device 1170, such as a display device, in conjunction with the high-speed interface 1150.

[0194] The communication device 1140 can provide a structure or function that enables the input / output device 1170 and the computing device 1100 to communicate with each other via a network, and can also provide a structure or function that enables the input / output device 1170 and / or the computing device 1100 to communicate with other external devices. For example, requests or data generated by the processor of an external device according to arbitrary program code can be transmitted to the computing device 1100 via the network under the control of the communication device 1140. Conversely, control signals or instructions provided under the control of the processor 1110 of the computing device 1100 can be transmitted to other external devices via the communication device 1140 and the network.

[0195] Figure 11 The diagram shows a computing device 1100 including a processor 1110, a memory 1120, etc., but it is not limited to these. The computing device 1100 can be implemented using multiple memories, multiple processors, and / or multiple buses, etc. Furthermore, Figure 11 The diagram shows the presence of a computing device 1100, but is not limited to this; multiple computing devices can interact and perform the necessary work to execute the method.

[0196] The memory 1120 can store information within the computing device 1100. According to one embodiment, the memory 1120 can be composed of volatile memory cells or multiple memory cells. Alternatively or additionally, the memory 1120 can be composed of non-volatile memory cells or multiple memory cells. Furthermore, the memory 1120 can be composed of other forms of computer-readable media such as a magnetic disk or optical disk. The memory 1120 can also store an operating system and at least one program code and / or instructions.

[0197] Storage device 1130 may be at least one high-capacity storage device for storing data for computing device 1100. For example, storage device 1130 may be a computer-readable medium including, or may include, semiconductor storage devices such as hard disks, magnetic discs, optical discs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory devices, CD-ROMs, and DVD-ROMs. Furthermore, computer programs may be tangibly implemented on such computer-readable media.

[0198] The high-speed interface 1150 and the low-speed interface 1160 can be units for interacting with the input / output device 1170. For example, the input device may include a camera, keyboard, microphone, mouse, etc., with an audio sensor and / or image sensor, and the output device may include a display, speaker, haptic feedback device, etc. In other examples, the high-speed interface 1150 and the low-speed interface 1160 can be units for interfacing with a device that integrates input and output structures or functions, such as a touchscreen.

[0199] According to one embodiment, high-speed interface 1150 can manage bandwidth-intensive operations on computing device 1100, while low-speed interface 1160 can manage bandwidth-intensive operations that are less demanding than those of high-speed interface 1150; however, this functional allocation is merely illustrative. According to one embodiment, high-speed interface 1150 can be integrated into memory 1120, input / output device 1170, and a high-speed expansion port capable of accommodating various expansion cards (not shown). Furthermore, low-speed interface 1160 can be integrated into storage device 1130 and a low-speed expansion port. Additionally, a low-speed expansion card including various communication ports (e.g., USB, Bluetooth, IoT, wireless IoT) can be integrated into at least one input / output device 1170 such as a keyboard, pointing device, or scanner, or integrated into a network device such as a router or switch via a network adapter.

[0200] The computing device 1100 can be implemented in various different forms. For example, the computing device 1100 can be implemented as a standard server or as a group of multiple such standard servers. Additionally or alternatively, the computing device 1100 can be implemented as part of a rack server system, or as a personal computer such as a laptop computer. In this case, the structural elements of the computing device 1100 can be combined with other structural elements within any mobile device (not shown). Such a computing device 1100 may include at least one other computing device, or communicate with at least one other computing device.

[0201] Figure 11 The input / output device 1170 shown is not included in the computing device 1100, but is not limited thereto, and can be configured as a device with the computing device 1100. Furthermore, Figure 11 The high-speed interface 1150 and / or low-speed interface 1160 and processor 1110 are shown as separate components, but are not limited thereto. The high-speed interface 1150 and / or low-speed interface 1160 may be included in processor 1110.

[0202] The methods and / or various embodiments described herein can be implemented using digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the invention can be executed using a data processing apparatus, such as at least one programmable processor and / or at least one computer device, or can be implemented using a computer-readable medium and / or a computer program stored on that medium. The computer program can be written in any form of programming language, including compiled or interpreted languages, and can be distributed in any form, such as as standalone programs, modules, subroutines, etc. The computer program can be distributed using a single computing device, multiple computing devices connected via the same network, and / or multiple computing devices distributed across multiple different network connections.

[0203] The methods and / or various embodiments described herein can operate based on input data or generate output data, thereby enabling execution by at least one processor configured to run at least one computer program for processing, storing, and / or managing arbitrary functions, etc. For example, the methods and / or various embodiments of the present invention can be executed by special-purpose logic circuits such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and the apparatus and / or system for executing the methods and / or embodiments of the present invention can be implemented as special-purpose logic circuits such as field-programmable gate arrays or application-specific integrated circuits.

[0204] At least one processor running a computer program may include at least one processor of a general-purpose or special-purpose micro processor and / or any type of digital computing device. The processor may receive instructions and / or data from read-only memory and random access memory, respectively, or may receive instructions and / or data from both read-only memory and random access memory. In this invention, the structural elements of the computing device for executing methods and / or embodiments may include at least one processor for executing instructions and at least one memory for storing instructions and / or data.

[0205] According to one embodiment, the computing device can send and receive data with at least one mass storage device for storing data. For example, the computing device can receive data from and transfer data to a magnetic disc or optical disc. Computer-readable media suitable for storing instructions and / or data related to computer programs may include, but are not limited to, non-volatile memory of any form having a semiconductor storage device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory device. For example, computer-readable media may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.

[0206] To provide interaction with the user, a computing device may include, but is not limited to, display devices that provide or display information to the user (e.g., cathode ray tubes (CRTs), liquid crystal displays (LCDs), etc.) and pointing devices that allow the user to provide input and / or commands to the computing device (e.g., keyboards, mice, trackballs, etc.). That is, the computing device may also include any other type of device for providing interaction with the user. For example, to interact with the user, the computing device may provide sensory feedback of any form, including visual feedback, auditory feedback, and / or tactile feedback. In this regard, the user can provide input to the computing device through various gestures such as vision, voice, and movement.

[0207] In this invention, various embodiments can be implemented in a computer device including back-end structural elements (e.g., a data server), middleware structural elements (e.g., an application server), and / or front-end structural elements. In this case, the structural elements can be interconnected through any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network can consist of wired networks such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication; mobile communication networks; wireless local area networks (WLANs); Wi-Fi; Bluetooth; and wireless networks such as ZigBee, or combinations thereof. For example, the communication network may include local area networks (LANs), wide area networks (WANs), etc.

[0208] The computing device based on the exemplary embodiments described in this specification may be implemented using hardware and / or software that allows interaction with a user, including user equipment, user interface (UI) devices, user terminals, or client devices. For example, the computing device may include portable computing devices such as laptop computers. Additionally or alternatively, the computing device may include personal digital assistants (PDAs), tablet computers, game consoles, wearable devices, Internet of Things (IoT) devices, virtual reality (VR) devices, augmented reality (AR) devices, etc., but is not limited thereto. The computing device may also include other types of devices for interaction with the user. Furthermore, the computing device may include portable communication devices (e.g., mobile phones, smartphones, wireless cellular phones, etc.) suitable for wireless communication via networks such as mobile communication networks. The computing device may use wireless communication technologies and protocols such as radio frequency (RF), microwave frequency (MWF), and / or infrared ray frequency (IRF) to communicate wirelessly with a network server.

[0209] In this invention, various embodiments, including specific structural and functional details, are illustrative examples. Therefore, the embodiments of this invention are not limited to the described content, but can be embodied in many different forms. Furthermore, the terminology used in this invention is used to describe some embodiments, not to limit the embodiments. For example, unless explicitly stated in the context, singular words include plural forms.

[0210] In this invention, unless otherwise defined, all terms used in this specification, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, the meanings of commonly used terms, such as those defined in dictionaries, are the same as their meanings within the same technical context.

[0211] In this specification, the invention has been described in connection with some embodiments. It is to be understood that those skilled in the art can make various modifications and alterations without departing from the scope of this invention. Furthermore, such modifications and alterations should fall within the scope of protection of the appended claims.

[0212] This study was supported by the Ministry of Small and Medium-sized Enterprises. This research was funded by the Korea Technology and Information Promotion Agency for SMEs (TIPA) through the Korea Technology and Information Promotion Agency for SMEs. (Project No.: 1425182152; Project No.: RS-2023-00302523; Research Project Title: Startup Growth Technology Development (R&D); Research Topic Title: Low-Code-Based Semiconductor Low-Power Solution; Implementing Agency: ITDA Semiconductor; Research Period: July 1, 2023 to June 30, 2026). The Government of the Republic of Korea does not own any intellectual property rights in any aspect of this invention concept.

Claims

1. A no-code power management cluster design system for designing a power management cluster in a no-code manner, comprising: a memory for storing at least one instruction; a power component repository storing power component information, reset controller component information, and reset test controller component information constituting a power management cluster; a hardware code logic repository storing hardware code logic for generating a designed power management cluster into hardware code; and at least one processor for executing the at least one instruction stored in the memory, wherein the at least one instruction comprises: an instruction for generating a power instance based on the power component information; an instruction for generating a reset controller instance disposed at a front end of the power instance and delivering a reset output to a target including the power instance; an instruction for setting first connection point information between the target and the reset controller instance; an instruction for generating a reset test controller instance including a test mode test data register block corresponding to the reset controller instance and a test control test data register block; an instruction for setting second connection point information between the reset controller instance and the reset test controller instance; and an instruction for generating hardware code based on the power instance, the reset controller instance, the first connection point information, the reset test controller instance, the second connection point information, and the hardware code logic. The reset controller instance is one of a pre-reset controller instance and a post-reset controller instance. The pre-reset controller instance comprises: a synchronization block connected to a functional clock of the target; a first test multiplexer block having a scan reset control signal ltest_reset and a reset input RESET_IN connected to respective input terminals, and a scan test enable signal ltest_en connected to a selection terminal; a first logic OR operator block having an output of the first test multiplexer block and a scan reset disable signal ltest_rstdisable connected to input terminals, and the synchronization block connected to an output terminal; a second logic OR operator block having an output of the synchronization block and the scan reset disable signal ltest_rstdisable connected to input terminals; and a second test multiplexer block having an output of the second logic OR operator block and a reset test data TEST_MODE_RESET input to respective input terminals, a reset test mode TEST_MODE signal connected to a selection terminal, and a reset output RESET_OUT connected to the target. The post-reset controller instance comprises: a synchronization block connected to a functional clock of the target; a first test multiplexer block having a selection terminal and one input terminal fixed to zero level, and other input terminals connected to a reset input; a first logic OR operator block having an output of the first test multiplexer block and a scan reset disable signal ltest_rstdisable connected to input terminals, and the synchronization block connected to an output terminal. ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The no-code power management cluster design system of claim 1, wherein, ​ 3. The no-code power management cluster design system of claim 2, wherein, ​ ​ ​ ​ ​ ​ 4. The no-code power management cluster design system of claim 2, wherein, ​ ​ ​ ​ a second logic OR operator block, an output of the synchronization block and a scan reset disable signal ltest_rstdisable are connected to input terminals, and a second test multiplexer block, an output of the second logic OR operator block and a reset test data TEST_MODE_RESET are input to respective input terminals, a reset test mode TEST_MODE signal is connected to a selection terminal, and a reset output RESET_OUT is connected to the target.

5. The no-code power management cluster design system of claim 1, wherein, The reset test controller instance is implemented based on a built-in IEEE 1687 standard. 6.The codeless power management cluster design system of claim 1, wherein the test mode test data register block is configured to output a reset test mode TEST_MODE signal for activating or deactivating a test mode of the target to the reset controller instance, the test control test data register block is configured to output a reset test data TEST_MODE_RESET to the reset controller instance in the test mode of the target.

7. The no-code power management cluster design system of claim 6, wherein, The test control test data register block is composed of a flip-flop block of a bit number of the reset test data.

8. The no-code power management cluster design system of claim 1, wherein, The test mode test data register block and the test control test data register block are respectively configured through an internal joint test action group interface.

9. The no-code power management cluster design system of claim 1, wherein, The power components are at least one of a reset component, a clock link component, a cold reset control component, a soft reset control component, and a domain power manager connection component. 10.A codeless power management cluster design method, performed by at least one processor in a computer system including a power component repository and a hardware code logic repository, the power component repository storing power component information and reset controller component information and reset test controller component information constituting a power management cluster, and the hardware code logic repository storing hardware code logic for generating a designed power management cluster as hardware code, the codeless power management cluster design method comprising: generating a power instance based on the power component information; generating a reset controller instance disposed at a front end of the power instance and delivering a reset output to a target including the power instance; configuring first connection point information between the target and the reset controller instance; generating a reset test controller instance including a test mode test data register block and a test control test data register block corresponding to the reset controller instance; configuring second connection point information between the reset controller instance and the reset test controller instance; and generating hardware code based on the power instance, the reset controller instance, the first connection point information, the reset test controller instance, the second connection point information, and the hardware code logic.

11. The codeless power management cluster design method of claim 10, wherein, The reset controller instance is one of a pre-reset controller instance and a post-reset controller instance.

12. The codeless power management cluster design method of claim 11, wherein, The pre-reset controller instance includes: a synchronization block connected to a functional clock of the target, a first logic OR operator block connected to an output of the synchronization block and a scan reset disable signal ltest_rstdisable, a second logic OR operator block connected to an output of the first logic OR operator block and a scan reset disable signal ltest_rstdisable, a second test multiplexer block connected to an output of the second logic OR operator block and a reset test data TEST_MODE_RESET, and a reset output RESET_OUT connected to the target. a first test multiplexer block, whose selection terminal and one input terminal are fixed to zero level respectively, and whose other input terminals are connected with reset input; a first logic OR operator block, whose input terminals are connected with the output of the first test multiplexer block and scan reset disable signal ltest_rstdisable, and whose output terminal is connected with the synchronous block; a second logic OR operator block, whose input terminals are connected with the output of the synchronous block and scan reset disable signal ltest_rstdisable; and a second test multiplexer block, whose input terminals are connected with the output of the second logic OR operator block and reset test data TEST_MODE_RESET, and whose selection terminal is connected with reset test mode TEST_MODE signal, and whose output terminal is connected with the target.

13. The codeless power management cluster design method of claim 11, wherein, The post-reset controller instance comprises: a synchronous block, which is connected with the functional clock of the target; a first test multiplexer block, whose selection terminal and one input terminal are fixed to zero level respectively, and whose other input terminals are connected with reset input; a first logic OR operator block, whose input terminals are connected with the output of the first test multiplexer block and scan reset disable signal ltest_rstdisable, and whose output terminal is connected with the synchronous block; a second logic OR operator block, whose input terminals are connected with the output of the synchronous block and scan reset disable signal ltest_rstdisable; and a second test multiplexer block, whose input terminals are connected with the output of the second logic OR operator block and reset test data TEST_MODE_RESET, and whose selection terminal is connected with reset test mode TEST_MODE signal, and whose output terminal is connected with the target.

14. The codeless power management cluster design method of claim 10, wherein, The reset test controller instance is implemented based on the built-in IEEE1687 standard.

15. The codeless power management cluster design method of claim 10, wherein: the test mode test data register block is configured to output a reset test mode TEST_MODE signal to the reset controller instance to activate or deactivate the test mode of the target, the test control test data register block is configured to output reset test data TEST_MODE_RESET to the reset controller instance in the test mode of the target.

16. The codeless power management cluster design method of claim 15, wherein, the test control test data register block is composed of a flip-flop block with the number of bits of the reset test data.

17. The codeless power management cluster design method of claim 10, wherein, the test mode test data register block and the test control test data register block are configured through an internal joint test action group interface respectively.

18. The codeless power management cluster design method of claim 10, wherein, the power components are at least one of a reset component, a clock link component, a cold reset control component, a soft reset control component, and a domain power manager connection component.

19. A computer program, characterized in that, a computer readable storage medium storing the method according to any one of claims 10 to 18 for execution in a computer.

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