Power amplification chip and radio frequency front-end module

Abstract

The invention provides a power amplification chip and a radio frequency front end module, the power amplification chip comprises a substrate and at least two stages of power amplification arrays arranged on the substrate, each stage of power amplification array comprises a plurality of transistors and a plurality of ballast resistors, and each transistor corresponds to one ballast resistor; in the power amplification array located at the rear stage in the at least two stages of power amplification arrays, all the ballast resistors are sequentially connected with the input ends of the power amplification arrays, the resistance values of the ballast resistors are sequentially decreased from the first ballast resistor to the nth ballast resistor, and n is an integer. According to the power amplification chip, the problem of junction temperature difference of different transistors can be solved, so that the overall performance of the power amplification chip is improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a power amplifier chip and a radio frequency front-end module. Background Technology

[0002] In semiconductor devices, heterojunction bipolar transistors (HBTs) are widely used in high-frequency, high-power radio frequency and microwave circuits, such as mobile phone base stations, satellite communications, and radar systems, due to their excellent characteristics such as high current gain and high frequency response. In these applications, to meet higher power and performance requirements, multiple HBT dies are often integrated together to form an HBT array.

[0003] However, as the power of HBT arrays continues to increase, thermal effects are gradually becoming a key factor affecting their performance. In actual HBT array layout design, various factors can lead to differences in the junction temperature of each die in the array. For example, in power amplifier chips, the junction temperature difference of HBTs can severely degrade the overall performance of the power amplifier chip. Especially in high-power applications, thermal considerations are particularly important. Summary of the Invention

[0004] The main objective of this application is to provide a power amplifier chip and an RF front-end module that solves the problem of junction temperature differences between different transistors by setting the resistance value of the ballast resistor differently, thereby improving the overall performance of the power amplifier chip.

[0005] In a first aspect, this application provides a power amplifier chip, the power amplifier chip comprising: A substrate and at least two power amplifier arrays disposed on the substrate, each stage of the power amplifier array including a plurality of transistors and a plurality of ballast resistors, each transistor corresponding to one of the ballast resistors; The first terminal of each transistor is connected to the input terminal of the corresponding power amplifier array, the second terminal of each transistor is connected to the output terminal of the corresponding power amplifier array, and the third terminal of each transistor is grounded; the first terminal of each ballast resistor receives a bias signal, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor. In the at least two-stage power amplifier array, in the power amplifier array located in the later stage, each of the ballast resistors is sequentially connected to the input terminal of the power amplifier array, and the resistance value of the ballast resistor is sequentially decreased from the first ballast resistor to the nth ballast resistor, where n is an integer.

[0006] In one embodiment, this application also provides a power amplifier chip, the power amplifier chip comprising: a substrate and at least two stages of power amplifier array disposed on the substrate, each stage of the power amplifier array comprising a plurality of transistors and a plurality of ballast resistors, each transistor corresponding to one ballast resistor; The first terminal of each transistor is connected to the input terminal of the corresponding power amplifier array, the second terminal of each transistor is connected to the output terminal of the corresponding power amplifier array, and the third terminal of each transistor is grounded; the first terminal of each ballast resistor is used to receive a bias signal, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor. In each of the at least two power amplifier arrays, each transistor is disposed at a different position on the substrate and arranged in an array; the ballast resistor connected to the transistor in the middle position is configured with a first resistance value, and the ballast resistor connected to the transistor in the edge position is configured with a second resistance value. The first resistance value is greater than the second resistance value, and the maximum resistance difference between each ballast resistor is less than or equal to 50 ohms.

[0007] In one embodiment, this application also provides a power amplifier chip, the power amplifier chip comprising: a substrate and at least two stages of power amplifier array disposed on the substrate, each stage of the power amplifier array comprising a plurality of transistors and a plurality of ballast resistors, each transistor corresponding to one ballast resistor; The first terminal of each transistor is connected to the input terminal of the corresponding power amplifier array, the second terminal of each transistor is connected to the output terminal of the corresponding power amplifier array, and the third terminal of each transistor is grounded; the first terminal of each ballast resistor is used to receive a bias signal, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor. In each of the at least two power amplifier arrays, the transistors are disposed at different positions on the substrate and arranged in an array; the ballast resistor connected to the transistor in the middle position is taken as the starting point, and the ballast resistor connected to the transistor in the edge position is taken as the ending point, and the resistance difference between two adjacent ballast resistors is the same.

[0008] In one embodiment, this application also provides a power amplifier chip, the power amplifier chip comprising: a substrate and at least two stages of power amplifier array disposed on the substrate, each stage of the power amplifier array comprising a plurality of transistors and a plurality of current limiting resistors, each transistor corresponding to one current limiting resistor; The first terminal of each transistor is connected to the input terminal of the corresponding power amplifier array through a current-limiting resistor, the second terminal of each transistor is connected to the output terminal of the corresponding power amplifier array, and the third terminal of each transistor is grounded. In the at least two-stage power amplifier array, in the power amplifier array of the later stage, each of the current-limiting resistors is sequentially connected to the input terminal of the power amplifier array, and the resistance value of the current-limiting resistor is set to decrease sequentially from the first current-limiting resistor to the nth current-limiting resistor, where n is an integer.

[0009] Secondly, embodiments of this application also provide a radio frequency front-end module, including a power amplifier chip as described in any one of the embodiments of this application.

[0010] This application provides a power amplifier chip and an RF front-end module. The power amplifier chip includes a substrate and at least two power amplifier arrays disposed on the substrate. Each power amplifier array includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. In the power amplifier array of the later stages of the at least two-stage power amplifier array, each ballast resistor is sequentially connected to the input terminal of the power amplifier array, and the resistance value of the ballast resistors decreases sequentially from the first ballast resistor to the nth ballast resistor, where n is an integer. This application, for the power amplifier array in the later stages, achieves thermal balance among multiple transistors by setting the resistance values ​​of the ballast resistors differently, thereby reducing the junction temperature difference between different transistors in the power amplifier array. Compared to a uniform resistor configuration, this effectively reduces the thermal effect of the power amplifier array, expands the safe operating area of ​​each transistor, and thus improves the overall performance of the power amplifier chip. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 Infrared thermograms of multiple transistors in a power amplifier chip provided for related technologies; Figure 2 A schematic layout diagram of one embodiment of the power amplifier chip provided in this application; Figure 3 A schematic layout diagram of one embodiment of the power amplifier array provided in this application; Figure 4 A circuit diagram illustrating one embodiment of the power amplifier array provided in this application; Figure 5 An application scenario diagram illustrating the power amplifier chip provided in the embodiments of this application; Figure 6 Another application scenario diagram for implementing the power amplifier chip provided in the embodiments of this application; Figure 7 A schematic diagram of another embodiment of the power amplifier chip provided in this application; Figure 8 A circuit diagram illustrating another embodiment of the power amplifier array provided in this application; Figure 9 A layout schematic diagram of yet another embodiment of the power amplifier chip provided in this application; Figure 10 A circuit diagram illustrating yet another embodiment of the power amplifier array provided in this application. Figure 11 A schematic layout diagram of one embodiment of a power amplifier chip provided in this application; Figure 12 A circuit diagram illustrating another embodiment of the power amplifier array provided in this application. Figure 13 A circuit diagram illustrating another embodiment of a power amplifier array provided in this application. Figure 14 A schematic block diagram of a radio frequency front-end module provided in an embodiment of this application; Figure 15 Infrared thermograms of multiple transistors in a power amplifier chip provided in an embodiment of this application.

[0013] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] It should be noted that the terms "first" and "second" in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0015] It should also be noted that the methods disclosed in the embodiments of this application or the methods shown in the flowcharts include one or more steps for implementing the method. Without departing from the scope of the claims, the execution order of multiple steps can be interchanged, and some steps can also be deleted.

[0016] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0017] Figure 1 Infrared thermograms of multiple transistors in a power amplifier chip provided for related technologies. For example... Figure 1 As shown, due to the asymmetry of the heterojunction bipolar transistor (HBT) layout, the difference in the relative position of each die in the HBT, and the influence of the surrounding metal layer, the junction temperature difference of each die in the array HBT will lead to the deterioration of the overall array performance of the HBT.

[0018] Junction temperature refers to the temperature of the PN junction in a transistor, and the performance of an HBT is closely related to its junction temperature. When an HBT is operating, the current flowing through it generates heat, which accumulates inside the die, causing the junction temperature to rise. In an HBT array, due to the aforementioned layout asymmetry, differences in the relative positions of the dies, and the influence of surrounding metal layers, the heat generated by each die faces different challenges in dissipation. If the environment around a die is unfavorable for heat dissipation—for example, if it is surrounded by other heat-generating components or far from heat dissipation channels—then the heat will accumulate faster, resulting in a higher junction temperature.

[0019] Specifically, firstly, the uneven thermal distribution of the HBT array on both sides of the rear stage is caused by the positions of the preceding and following HBT arrays. Heat generated by the preceding HBTs during operation may be transferred to the following HBTs, and the different positions of the following HBT arrays result in varying heat absorption by the following HBTs, leading to uneven heat distribution on the left and right sides of the rear stage. Secondly, the imbalance caused by the relative positions of the HBT dies results in the middle die having a higher temperature than the outer dies. This is because the middle die is surrounded by other dies, making heat dissipation relatively difficult, while the outer dies have more space for heat exchange with the outside, thus resulting in a higher junction temperature for the middle die. Thirdly, the thermal effects of individual dies differ due to the influence of the positions of surrounding circuit metal layers and ground vias. The positions of metal layers and ground vias affect the heat conduction path. If the metal layer around a die obstructs heat dissipation, or the position of the ground via is unfavorable for heat diffusion, then the junction temperature of that die will differ from other dies. In the embodiments of this application, adjustments to the device effectively improve the aforementioned junction temperature problem and enhance device performance.

[0020] Next, combined Figures 2 to 4 This application introduces a power amplifier chip, which includes multiple transistors, including but not limited to heterojunction bipolar transistors (HBTs). The multiple transistors can form at least a two-stage HBT array. This power amplifier chip can address the junction temperature differences between different transistors by differentially setting the ballast resistor values, thereby improving the overall performance of the power amplifier chip.

[0021] Please see Figures 2 to 4 , Figure 2This is a layout schematic diagram of one embodiment of the power amplifier chip provided in this application. Figure 3 This is a schematic layout diagram of one embodiment of the power amplifier array provided in this application. Figure 4 A circuit diagram of one embodiment of the power amplifier array provided in this application.

[0022] like Figure 2 and Figure 3 As shown, the power amplifier chip 100 includes a substrate 110 and at least two power amplifier arrays 120 disposed on the substrate 110. The positions of the at least two power amplifier arrays 120 on the substrate 110 can be flexibly set according to actual conditions. For example, multiple power amplifier arrays 120 can be arranged along the horizontal or vertical axis of the substrate 110. The positions of the transistors and ballast resistors in each power amplifier array 120 on the substrate 110 can also be flexibly set according to actual conditions, and this application does not impose specific limitations on this.

[0023] like Figure 3 and Figure 4 As shown, each stage of the power amplifier array 120 includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. For example, the multiple transistors include Q1 to Qn, and the multiple ballast resistors include R1 to Rn, with transistor Q1 connected to R1 and transistor Qn connected to Rn. The first terminal of each transistor is connected to the input terminal Fin of the corresponding power amplifier array 120, the second terminal of each transistor is connected to the output terminal Fout of the corresponding power amplifier array 120, and the third terminal of each transistor is grounded. The first terminal of each ballast resistor receives a bias signal iref, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor.

[0024] In the power amplifier array 120 located in the latter stage of at least two power amplifier arrays 120, each ballast resistor is sequentially connected to the input terminal Fin of the power amplifier array 120, and the resistance value of the ballast resistor is set to decrease sequentially from the first ballast resistor to the nth ballast resistor, where n is an integer.

[0025] It should be noted that the substrate 110 can serve as a carrier providing physical support and electrical connection for the power amplifier chip 100. The power amplifier chip 100 may include at least two stages of power amplifier arrays 120, each of which can amplify the signal to a certain extent. During power amplification, the transistor is the core amplification element, capable of controlling the current flow according to changes in the input signal, thereby amplifying the signal. The first terminal of each transistor is connected to the input terminal Fin of the corresponding power amplifier array 120, allowing the input signal to be transmitted through the input terminal Fin to the first terminal of each transistor, thus controlling the transistor's operating state. The second terminal of each transistor is connected to the output terminal Fout of the corresponding power amplifier array 120, allowing the amplified signal to be output through the second terminal to the output terminal Fout of the power amplifier array 120, and then transmitted to the next stage circuit or load. The third terminal of each transistor is grounded, thus forming a complete current loop. When the transistor is operating, current can flow from the power supply VCC through the second and third terminals of the transistor to form a loop, thereby amplifying the signal.

[0026] It should be noted that the ballast resistor, also known as the ballasting resistor, serves to limit current and stabilize the transistor's operating state. The first terminal of each ballast resistor receives a bias signal iref. The iref signal provides a suitable static operating point for the transistor, allowing it to operate within its normal amplification region. The second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor, transmitting the iref signal to the transistor's first terminal. The transistor may include a heterojunction bipolar transistor (HBT) or other bipolar junction transistors, where the first terminal can be the base, the second terminal the collector, and the third terminal the emitter. The ballast resistor can be a series resistor on the HBT base bias. In some cases, the transistor may include a field-effect transistor (FET), where the first terminal can be the gate, the second terminal the drain, and the third terminal the source. For example, this embodiment uses non-uniform ballasting resistor values ​​for a specific HBT layout. Compared to a uniform resistor configuration, this reduces the HBT's thermal effect, lowers the HBT junction temperature, improves HBT performance, and expands the SOA (Safe Operating Area) of each HBT die.

[0027] It should be noted that in the power amplifier array 120 located in the subsequent stage, the resistance values ​​of the ballast resistors from the first to the nth ballast resistor are set to decrease sequentially. For ballast resistors with larger resistance values, the bias current provided is relatively small, and the operating current of the transistors is also small. According to Joule's law, the heat generated in the same amount of time is relatively less. In other words, the thermal balance of each transistor in the subsequent power amplifier array 120 is achieved through the differentiated setting of the ballast resistor values. Since each transistor corresponds to a ballast resistor, the sequential decrease in resistance value allows for a reasonable distribution of the bias current and power consumption of each transistor. When the power consumption of each transistor is similar, the heat generated is also similar, thus achieving thermal balance. In the thermal balance state, the junction temperature difference of each transistor will be significantly reduced.

[0028] The relevant technology employs a uniform resistance configuration, meaning all ballast resistors have the same resistance value. With a uniform resistance configuration, the bias current and power consumption of each transistor in the subsequent power amplifier array 120 may vary significantly. This can lead to some transistors generating excessive heat and experiencing a significant increase in junction temperature, while others generate less heat and have relatively lower junction temperatures. This junction temperature difference enhances the thermal effect of the power amplifier array 120, impacting transistor performance and the reliability of the power amplifier chip 100.

[0029] In this embodiment, by setting differentiated ballast resistor values, the junction temperature difference between different transistors in the power amplifier array 120 is reduced, effectively mitigating the thermal effect. When the junction temperature difference decreases, each transistor can operate in a more stable temperature environment, and its safe operating area can be expanded. The safe operating area refers to the parameter range within which a transistor can operate normally without damage, including parameters such as voltage, current, and power. After the junction temperature difference is reduced, the transistor can still maintain stable operation under higher voltage, current, and power, thereby improving the overall performance of the power amplifier chip 100. Specifically, the power amplifier chip 100 has stronger signal amplification capability, can amplify the input signal more accurately, and reduces signal distortion. The power gain is higher, enabling the input signal to be amplified to higher power. At the same time, the reliability and stability of the power amplifier chip 100 are also improved, reducing the risk of power amplifier chip 100 failure due to transistor overheating damage.

[0030] For example, in the power amplifier array 120 of the subsequent stage, the maximum resistance difference between each ballast resistor is less than or equal to 100 ohms. Specifically, the maximum resistance difference between each ballast resistor is less than or equal to 80 ohms, 70 ohms, and 50 ohms. It should be noted that controlling the maximum resistance difference between each ballast resistor to less than or equal to 100 ohms can improve the stability of the power amplifier array 120 in the subsequent stage. The bias current and junction temperature of each transistor are relatively balanced, enabling the transistors to operate under stable conditions, reducing the risk of transistor damage due to operating point offset and excessive junction temperature, thereby improving the reliability and stability of the entire power amplifier array 120.

[0031] For example, in the power amplifier array 120 at the later stage, the resistance value of each ballast resistor is set based on the preset average resistance value of each ballast resistor. The preset average resistance value can be set between 250 ohms and 350 ohms. For instance, the preset average resistance value can be set to 300 ohms.

[0032] It should be noted that the preset average resistance value can be determined by comprehensively considering factors such as the overall performance of the subsequent power amplifier array 120, the operating characteristics of the transistors, and circuit stability. Once the preset average resistance value is determined, each ballast resistor can be set around this preset average resistance value. By setting the resistance values ​​of each ballast resistor near the preset average resistance value, each transistor can obtain a relatively balanced bias current, thereby ensuring that the operating point of each transistor is relatively stable.

[0033] Taking a preset average resistance value of 300 ohms as an example, when the resistance values ​​of each ballast resistor are close to 300 ohms, the bias current provided to the corresponding transistors is approximately the same. A stable bias current allows the transistors to operate under appropriate amplification conditions, reducing signal distortion caused by operating point offset. Simultaneously, setting the ballast resistor values ​​based on the preset average resistance value helps achieve thermal management of the subsequent power amplifier array 120. The power consumption of each transistor is related to the sum of the square of the current and the resistance. When the resistance values ​​of each ballast resistor are relatively balanced, the operating current of each transistor is also relatively balanced, thus making the power consumption and junction temperature of each transistor relatively stable. This helps avoid localized overheating and improves the reliability and stability of the entire subsequent power amplifier array 120. Therefore, setting the preset average resistance value between 250 ohms and 350 ohms helps improve the heat dissipation efficiency of the power amplifier chip 100, extends the chip's lifespan, and also reduces the risk of performance degradation due to overheating.

[0034] For example, in the power amplifier array 120 at the later stage, the resistance value of each ballast resistor is set based on the sum of the preset average resistance value and the compensation value of each ballast resistor. The magnitude of the compensation value is positively correlated with the connection order of each ballast resistor. The compensation value can range from -50 ohms to 50 ohms. For instance, the compensation value of the ballast resistor connected in the middle position is zero, and its resistance value is the preset average resistance value.

[0035] It should be noted that the compensation value can be determined based on the connection order of the ballast resistors. The connection order can be understood as the order in which each ballast resistor is connected to the input terminal Fin of the subsequent power amplifier array 120. For example, the ballast resistors can be numbered according to their position in the layout design. Specifically, the ballast resistors can be numbered starting from the first ballast resistor connected to the input terminal Fin of the subsequent power amplifier array 120, based on their position on the substrate 110. The positive correlation between the compensation value and the connection order means that the closer the ballast resistor is to the input terminal Fin (the earlier in the connection order), the larger the compensation value. The farther the ballast resistor is from the input terminal Fin (the later in the connection order), the smaller the compensation value.

[0036] Specifically, when the compensation value is positive, the resistance of the ballast resistor will be greater than the preset average resistance value. When the compensation value is negative, the resistance of the ballast resistor can be less than the preset average resistance value. When the compensation value is zero, the resistance of the ballast resistor is equal to the preset average resistance value. This optimizes the thermal management of the subsequent power amplifier array 120. Furthermore, based on actual conditions, this application adjusts the power amplifier arrays of different stages to balance the bias current of each transistor, resulting in relatively stable power consumption and junction temperature. This avoids localized overheating, improves the heat dissipation efficiency of the power amplifier chip 100, extends its lifespan, and reduces the risk of performance degradation due to overheating.

[0037] Taking a power amplifier chip 100 used in a 5G communication base station as an example, the subsequent power amplifier array 120 of this chip contains five ballast resistors, with a preset average resistance value of 300 ohms. Assume that the ballast resistors are numbered 1-5 sequentially according to their connection order to the input terminal Fin. The ballast resistor in the middle connection position (numbered 3) has a compensation value of zero, so its resistance value is equal to the preset average resistance value, i.e., 300 ohms. For ballast resistors numbered 1 and 2 (closest to the input terminal), since they are connected earlier, their compensation values ​​are positive. Assume the compensation value of ballast resistor number 1 is +30 ohms and the compensation value of ballast resistor number 2 is +20 ohms. Then the resistance value of ballast resistor number 1 is 300 + 30 = 330 ohms, and the resistance value of ballast resistor number 2 is 300 + 20 = 320 ohms. For ballast resistors numbered 4 and 5 (farthest from the input), due to their later connection sequence, their compensation values ​​are negative. Assuming the compensation value for ballast resistor number 4 is -20 ohms and for ballast resistor number 5 is -30 ohms, then the resistance of ballast resistor number 4 is 300 - 20 = 280 ohms, and the resistance of ballast resistor number 5 is 300 - 30 = 270 ohms. This configuration allows each ballast resistor to provide a suitable bias current to its corresponding transistor, making the operating point of each transistor more stable. This reduces the junction temperature difference between different transistors in the power amplifier array 120, meeting the high performance and high reliability requirements of the power amplifier chip 100 for 5G communication base stations.

[0038] For example, in the power amplifier array 120 of the subsequent stage, the resistance difference between two adjacent ballast resistors is a fixed value. It should be noted that when the resistance difference between adjacent ballast resistors is fixed, it means that the bias current obtained by each transistor can vary uniformly. Because the bias current is related to the ballast resistor and the input signal, a uniform resistance difference makes the operating point variation of each transistor have a certain regularity. During signal amplification, the operating states of each transistor influence each other. If the resistance difference between adjacent ballast resistors is irregular, it will lead to large differences in the operating current and power consumption of each transistor, disrupting the circuit balance. A fixed difference allows the operating current and power consumption of each transistor to be relatively balanced, making the junction temperature of each transistor relatively stable, avoiding local overheating, improving the heat dissipation efficiency of the power amplifier chip 100, extending the chip's lifespan, and reducing the risk of performance degradation due to overheating.

[0039] The following section provides a detailed explanation of the junction temperature problem caused by the relative positional differences of multiple transistors within the power amplifier array 120. Unless otherwise specified, the following embodiments can be combined with the foregoing embodiments.

[0040] In one embodiment, such as Figure 2 and Figure 3 As shown, in each stage of the power amplifier array 120, transistors are disposed at different positions on the substrate 110 and arranged in an array. The resistance values ​​of the ballast resistors corresponding to the transistors in different regions are different. It should be noted that by setting different resistance values ​​for the ballast resistors in different regions, the operating point of each transistor can be precisely adjusted. For example, in regions with poor heat dissipation and high junction temperatures, appropriately increasing the resistance value of the ballast resistor can limit the current, reduce the heat generated by the transistor, and lower the junction temperature. In regions with good heat dissipation and low junction temperatures, appropriately decreasing the resistance value of the ballast resistor allows more current to pass through, thereby reducing the junction temperature difference between different transistors in the power amplifier array 120.

[0041] For example, each transistor includes an HBT die, and multiple HBT dies are arranged in an array on the substrate 110 to form a power amplifier array 120, with resistance values ​​set according to the region of the HBT dies relative to the power amplifier array 120. Figure 5 As shown, in a single-row array, multiple HBT dies, including HBT1 to HBT6, are used. HBT3 and HBT4, located near the center of the array, are set to mean value + positive compensation, while HBT1 and HBT6, located near the edge of the array, are set to mean value + negative compensation. Figure 6 As shown, in a multi-row array, multiple HBT dies, including HBT1 to HBT12, are used. For HBT dies near the array center, such as HBT3 and HBT4, and HBT9 and HBT10, a mean value plus positive compensation is applied. Because heat dissipation is difficult for dies at the center, the heat generated during operation is not easily dissipated, and the junction temperature easily rises. By increasing the positive compensation value and raising the ballast resistor value, the current through the HBT die can be limited, reducing heat generation and thus lowering the junction temperature, allowing the die to operate near a more stable operating point. For HBT dies near the array edge, such as HBT1 and HBT6, and HBT7 and HBT12, a mean value plus negative compensation is applied. While the heat dissipation conditions for edge HBT dies are relatively better, they may be affected by edge effects, resulting in a relatively smaller operating current. By increasing the negative compensation value and lowering the ballast resistor value, more current can be allowed to pass through the die, ensuring junction temperature balance.

[0042] Combination Figures 5-6As shown in the embodiments of this application, when describing the array, the plurality of HBT die arrays may include a first edge region 331, a middle region 332, and a second edge region 333. The first edge region 331 and the second edge region 333 may be located at the two side edges of the array, and the middle region 332 is located between the first edge region 331 and the second edge region 333. Furthermore, in the configuration, the HBT dies corresponding to the middle region 332 are configured with a mean value plus positive compensation, while the HBT dies corresponding to the first edge region 331 and the second edge region 333 are configured with a mean value plus negative compensation.

[0043] Furthermore, in this embodiment, the area of ​​the intermediate region 332 can account for 0.25-0.4% of the total area. In one embodiment, the area of ​​the intermediate region 332 is one-third of the total area. The total area is the sum of the areas of the first edge region 331, the second edge region 333, and the intermediate region 332. In this way, by differentiating the HBT dies in different regions and rationally allocating the areas of different regions, the heat dissipation of the HBT dies in each region is ensured to be optimal, avoiding uneven heat dissipation in a certain region or some dies. These poorly dissipated dies would then cause an imbalance in the thermal stability of the HBT dies in other regions, leading to uneven heat dissipation as well.

[0044] In one embodiment, in each stage of the power amplifier array 120, the ballast resistor connected to the transistors in the middle arrangement position is configured with a first resistance value, and the ballast resistor connected to the transistors in the edge arrangement position is configured with a second resistance value, wherein the first resistance value is greater than the second resistance value.

[0045] It should be noted that for transistors in the middle arrangement, due to their poor heat dissipation, heat easily accumulates, and the junction temperature easily rises. This elevated junction temperature further degrades the thermal stability of other transistors. By configuring the ballast resistor connected to it with a larger first resistance value, the current flowing through the transistor can be limited, reducing heat generation and thus lowering the junction temperature. This prevents impact on other normally operating transistors and reduces thermal imbalance. For transistors in the edge arrangement, due to their relatively better heat dissipation and potential edge effects, appropriately reducing the resistance value of the ballast resistor connected to it (i.e., the second resistance value is smaller than the first resistance value) allows more current to flow through the transistor, increasing its operating current and amplification capability. By reasonably adjusting the resistance values ​​of the ballast resistors connected at different positions, the junction temperature of each transistor becomes more balanced, reducing transistor performance fluctuations caused by junction temperature differences, avoiding localized overheating, improving the heat dissipation efficiency of the power amplifier chip 100, extending its lifespan, and also improving its performance.

[0046] The first and second resistance values ​​are set as the sum of the preset average resistance of each ballast resistor and its compensation value. The compensation value for the ballast resistor corresponding to the first resistance value is positive, and the compensation value for the ballast resistor corresponding to the second resistance value is negative. The compensation value can be a parameter adjusted based on the transistor's position in the array. By appropriately adjusting the ballast resistor values ​​for transistors at different positions, the operating current and junction temperature of each transistor are more balanced. Simultaneously, the risk of transistor damage due to junction temperature differences and performance mismatches is reduced, thereby improving the reliability and stability of the entire array.

[0047] For example, at least two-stage power amplifier array 120 includes a second power amplifier array in which a plurality of transistors are symmetrically arranged on substrate 110, and the ballast resistors connected to the transistors arranged in the central region of symmetry are configured with a first resistance value, and the ballast resistors connected to the transistors arranged in the edge region of symmetry are configured with a second resistance value.

[0048] Taking the second power amplifier array in a power amplifier chip 100 for a 5G communication base station as an example, assume that the array has 9 transistors arranged symmetrically in a 3×3 matrix, with the 5th transistor at the center and the 1st, 2nd, 3rd, 4th, 6th, 7th, 8th, and 9th transistors at the edges. Assume that, after design and testing, the ballast resistor connected to the 5th transistor in the symmetrical central region is configured with a first resistance value R1 = 350 ohms, and the ballast resistor connected to the transistors in the symmetrical edge region is configured with a second resistance value R2 = 250 ohms. When an input signal enters this power amplifier array 120, for the 5th transistor at the center, the larger first resistance value R1 limits the current flowing through it, reducing heat generation, lowering the junction temperature, and allowing it to operate near a stable operating point, thus ensuring the stability of signal amplification. For the edge transistors, the smaller second resistance value R2 allows more current to flow, improving their operating current and amplification capability, while also compensating for the edge effect. With this configuration, each transistor in the entire second power amplifier array can operate at a suitable operating point, improving the array's stability, signal amplification performance, and thermal management capabilities, ensuring that the 5G communication base station can operate stably and efficiently.

[0049] In one embodiment, in each stage of the power amplifier array 120, the ballast resistor connected to the transistor in the middle position is taken as the starting point, and the ballast resistor connected to the transistor in the edge position is taken as the ending point. From the starting point to the ending point, the resistance value of each ballast resistor is set to decrease sequentially.

[0050] It should be noted that transistors in the middle of the array face heat dissipation difficulties, leading to a higher junction temperature. By setting a larger resistance value at the starting point (the ballast resistor in the middle array), the current flowing through the transistors in this area can be limited, reducing heat generation and thus lowering the junction temperature. As the array moves from the middle towards the edges, heat dissipation gradually improves. Decreasing the ballast resistor value sequentially results in smaller resistance values ​​for the transistors at the edges, allowing for a reasonable increase in current and a more balanced junction temperature across the transistors. Therefore, this helps improve the heat dissipation efficiency of the power amplifier chip 100, extends its lifespan, and reduces the risk of performance degradation due to overheating. In practical applications, this is equivalent to improving the performance of the power amplifier chip 100.

[0051] Taking a power amplifier array 120 in a power amplifier chip 100 used in a 5G communication base station as an example, assuming the array has 7 transistors arranged linearly in one direction, the middle transistor is the 4th transistor, serving as the starting point, and its corresponding ballast resistor has the largest resistance value, set as R1 = 350 ohms. The edge transistors are the 1st and 7th transistors, serving as the ending points, and their corresponding ballast resistors have the smallest resistance value, set as R2 = 250 ohms. The 2nd and 3rd transistors and the 5th and 6th transistors in the middle have their ballast resistor values ​​decreasing sequentially according to their distance from the starting and ending points. For example, the ballast resistor corresponding to the 3rd transistor is R3 = 320 ohms, the ballast resistor corresponding to the 2nd transistor is R4 = 300 ohms, the ballast resistor corresponding to the 5th transistor is R5 = 280 ohms, and the ballast resistor corresponding to the 6th transistor is R6 = 260 ohms. When the input signal enters the power amplifier array 120, for the fourth transistor in the middle, the larger starting point ballast resistor R1 limits the current flow, reduces heat generation, lowers the junction temperature, and allows it to operate near its stable operating point, ensuring the stability of signal amplification. For the first and seventh transistors at the edges, the smaller ending point ballast resistor R2 allows more current to flow, thus making the junction temperature of each transistor more uniform.

[0052] In one embodiment, in each stage of the power amplifier array 120, the resistance value of each ballast resistor is set based on the sum of the preset average resistance value and the compensation value of each ballast resistor. The magnitude of the compensation value is positively correlated with the position of the corresponding connected transistor in the middle of the substrate 110. The preset average resistance value is set to 300 ohms, and the compensation value ranges from -50 ohms to 50 ohms.

[0053] It should be noted that the compensation value can be determined based on the position of the transistors on the substrate 110, and is positively correlated with the center position of the transistors on the substrate 110. That is, the closer the transistors are to the center position on the substrate 110, the larger the compensation value. The farther the transistors are from the center position (i.e., closer to the edge), the smaller the compensation value. When the compensation value is positive, the resistance value of the ballast resistor can be greater than the preset average resistance value; when the compensation value is zero, the resistance value of the ballast resistor can be equal to the preset average resistance value. When the compensation value is negative (a similar situation may occur when far from the center position), the resistance value of the ballast resistor can be less than the preset average resistance value.

[0054] Taking a power amplifier array 120 in a power amplifier chip 100 used in a 5G communication base station as an example, assume the array has 5 transistors arranged in a straight line, with the middle transistor being the 3rd transistor. Assume the preset average resistance Rmean is set to 300 ohms. For the 3rd transistor (located in the middle), due to its poor heat dissipation, a larger compensation value is given, assuming a compensation value ΔR1 = +30 ohms. Then, the resistance value of the ballast resistor connected to this transistor is R1 = Rmean + ΔR1 = 300 + 30 = 330 ohms. The larger resistance value can limit current, reduce heat generation, and lower the junction temperature. For the 2nd and 4th transistors (relatively far from the middle), a smaller compensation value is given, assuming a compensation value ΔR2 = +10 ohms. Then, the resistance value of the ballast resistor connected to them is R2 = R3 = Rmean + ΔR2 = 300 + 10 = 310 ohms. For the first and fifth transistors (located at the edge), a small compensation value or even close to zero compensation is given. Assuming the compensation value ΔR3 = 0 ohms, the corresponding ballast resistor value is R4 = R5 = Rmean + ΔR3 = 300 + 0 = 300 ohms.

[0055] For example, at least two-stage power amplifier array 120 includes a second power amplifier array, in which a plurality of transistors are arranged on substrate 110 along a first direction, with the transistor at the middle position of the first direction corresponding to a ballast resistor as the starting point, and the transistor at the end position of the first direction corresponding to a ballast resistor as the ending point.

[0056] It should be noted that the first direction can be flexibly defined based on actual design requirements, substrate shape, and overall chip layout. For example, in chip design, designers can choose a direction that facilitates description and analysis of transistor positional relationships, based on the actual transistor arrangement. If the transistors are arranged roughly in a straight line on substrate 110, the direction of this line can be defined as the first direction; if the transistors are arranged in a regular rectangular array, the first direction can be defined as the row or column direction of the rectangular array. Based on the first direction, transistors in the middle position (with the corresponding ballast resistor as the starting point) and transistors at the end positions (with the corresponding ballast resistor as the ending point) can be clearly defined. From the starting point to the ending point, the resistance values ​​of each ballast resistor can be set sequentially decreasing.

[0057] Taking the second power amplifier array in a power amplifier chip 100 for a 5G communication base station as an example, assume the array has 5 transistors arranged in a straight line along the first direction. The ballast resistor connected to the third transistor in the middle is taken as the starting point, and the ballast resistors connected to the first and fifth transistors are taken as the ending points. Assume the preset average resistance Rmean is set to 300 ohms. For the third transistor (the starting point), due to its relatively poor heat dissipation, a relatively large ballast resistor value may be given, such as R1 = 320 ohms, to limit current, reduce heat generation, and lower junction temperature. For the second transistor, its ballast resistor value R2 can be adjusted according to its position relative to the starting point and the heat dissipation situation; assume R2 = 310 ohms. For the fourth transistor, its ballast resistor value R4 can be appropriately reduced; assume R4 = 290 ohms. For the fifth transistor (the ending point), its ballast resistor value R5 can be further reduced; assume R5 = 280 ohms, to allow more current to pass through, thereby making the junction temperature of each transistor more uniform.

[0058] The following section provides a detailed explanation of the issue of varying thermal effects in individual chips due to the influence of surrounding circuit metal layers and the location of ground vias. Where there is no conflict, the following embodiments can be combined with the foregoing embodiments.

[0059] In one embodiment, the substrate 110 is provided with a heat sink; in each stage of the power amplifier array 120, transistors at different locations have different heat dissipation efficiencies relative to the heat sink, and the resistance values ​​of the ballast resistors corresponding to each transistor are set based on the heat dissipation efficiency of the transistors. The resistance value of each ballast resistor is negatively correlated with its corresponding heat dissipation efficiency.

[0060] It should be noted that, to improve heat dissipation, heat sinks, heat fins, or heat pipes are typically provided on the substrate 110. However, due to the different positions of the transistors on the substrate 110, the relative positions of each transistor to the heat sink and the heat conduction paths are also different, resulting in transistors at different positions having different heat dissipation efficiencies. The heat dissipation efficiency of a transistor determines whether it can dissipate the generated heat in a timely manner. When the heat dissipation efficiency of a transistor is low, its heat dissipation ability is poor, which leads to heat accumulation inside the transistor, causing the junction temperature to rise rapidly. The increased junction temperature not only degrades the performance of the transistor itself, but the higher temperature also affects other surrounding transistors, causing them to become unstable, ultimately affecting the transistor's electrical characteristics and lifespan.

[0061] Therefore, the corresponding ballast resistor needs to be set to a relatively high resistance value to limit the current through the transistor, reduce heat generation, and ensure that the transistor operates within a safe temperature range. By setting the resistance value of the ballast resistor according to the heat dissipation efficiency, the power consumption of each transistor is more balanced, avoiding local overheating, which helps improve the heat dissipation efficiency of the power amplifier chip 100, extends the chip's lifespan, and also reduces the risk of performance degradation due to overheating.

[0062] For example, the heat sink includes at least one through-hole. In each stage of the power amplifier array 120, each transistor has a first distance from each through-hole and / or each through-hole has a first number. The resistance value of the ballast resistor corresponding to each transistor is set based on the first distance and / or the first number. The resistance value of each ballast resistor is negatively correlated with the corresponding first distance, and positively correlated with the corresponding first number.

[0063] It's important to note that the heat dissipation efficiency of a transistor is closely related to its distance from the via and the number of vias. When the transistor is close to the via, air flows more easily between them, allowing heat to dissipate more quickly and resulting in higher heat dissipation efficiency; conversely, a greater distance leads to lower efficiency. The more vias there are, the more airflow channels there are, and the better the heat dissipation. The resistance value of each ballast resistor is negatively correlated with its corresponding first distance; that is, the closer the transistor is to the via, the lower the resistance value of the ballast resistor. The greater the first distance, the higher the resistance value of the ballast resistor. This is because closer proximity leads to better heat dissipation and allows for a larger current flow. The resistance value of each ballast resistor is positively correlated with its corresponding first number; that is, the more vias there are, the lower the resistance value of the ballast resistor. A larger number of vias means higher heat dissipation efficiency and also allows for a larger current to flow through the transistor, improving its performance. By rationally setting the ballast resistor value according to the distance between the transistor and the via and the number of vias, the power consumption of each transistor is more balanced, avoiding local overheating, which helps to improve the heat dissipation efficiency of the power amplifier chip 100, extend the chip's lifespan, and also reduce the risk of performance degradation due to overheating.

[0064] Taking a power amplifier chip 100 for a 5G communication base station as an example, a certain stage of the power amplifier array 120 of this chip contains multiple transistors, and the heat sink on the substrate 110 has three vias. Assume that transistor A is 1mm away from the nearest via, and there are two vias; transistor B is 3mm away from the nearest via, and there is one via. For transistor A, due to its proximity to the via and the large number of vias, its heat dissipation efficiency is high, so the corresponding ballast resistor value is set to a lower value, such as 200 ohms. Under the same bias voltage, the lower resistance value allows a larger current to pass through, enabling transistor A to fully utilize its amplification capability, while heat can be dissipated promptly through the vias. For transistor B, due to its distance from the via and the small number of vias, its heat dissipation efficiency is low, so the corresponding ballast resistor value is set to a higher value, such as 350 ohms. The higher resistance value limits the current passing through transistor B, reduces heat generation, avoids excessive junction temperature due to insufficient heat dissipation, and ensures that transistor B operates within a safe temperature range.

[0065] For example, the heat sink includes a heat-dissipating metal layer adjacent to each transistor. In each stage of the power amplifier array 120, the heat-dissipating metal layer adjacent to each transistor has a first area and / or a first thickness, and the resistance value of the ballast resistor corresponding to each transistor is set based on the first area and / or the first thickness. The resistance value of each ballast resistor is positively correlated with the corresponding first area, and the resistance value of each ballast resistor is positively correlated with the corresponding first thickness.

[0066] It's important to note that a larger heat dissipation metal layer area means more pathways for heat to dissipate into the surrounding environment, resulting in higher heat dissipation efficiency. Similarly, a thicker heat dissipation metal layer has stronger thermal conductivity, allowing for faster heat transfer from the transistor and further improving heat dissipation efficiency. The resistance value of each ballast resistor is positively correlated with its corresponding first area; that is, the larger the area of ​​the heat dissipation metal layer adjacent to the transistor, the higher the resistance value of the corresponding ballast resistor. This is because a larger heat dissipation area can better dissipate the heat generated by the transistor, allowing the transistor to withstand a larger current. Under the same bias voltage, a higher resistance value allows for a relatively larger current to pass through the transistor, thus fully utilizing the transistor's amplification capability. The resistance value of each ballast resistor is also positively correlated with its corresponding first thickness; that is, the thicker the heat dissipation metal layer, the higher the resistance value of the corresponding ballast resistor. A thicker heat dissipation metal layer has stronger thermal conductivity, enabling more efficient heat transfer from the transistor, thus allowing the transistor to carry a larger current and improving its operating performance. By rationally setting the ballast resistor value according to the area and thickness of the heat dissipation metal layer, the power consumption of each transistor is more balanced, avoiding local overheating, which helps to improve the heat dissipation efficiency of the power amplifier chip 100, extend the chip's lifespan, and also reduce the risk of performance degradation due to overheating.

[0067] Taking a power amplifier chip 100 for a 5G communication base station as an example, a certain stage of the power amplifier array 120 of this chip contains multiple transistors, each of which is in contact with an adjacent heat dissipation metal layer. Assume that the first area of ​​the heat dissipation metal layer adjacent to transistor A is 10 square millimeters and the first thickness is 0.5 millimeters; the first area of ​​the heat dissipation metal layer adjacent to transistor B is 5 square millimeters and the first thickness is 0.2 millimeters. For transistor A, due to the large area and thickness of its adjacent heat dissipation metal layer, the heat dissipation efficiency is high, and the corresponding ballast resistor value is set to a relatively high value, such as 350 ohms. Under the same bias voltage, the higher resistance value allows a relatively large current to pass through transistor A, enabling it to fully utilize its amplification capability, while heat can also be dissipated in a timely manner through the large area and thick heat dissipation metal layer. For transistor B, because its adjacent heat dissipation metal layer has a small area and thinness, the heat dissipation efficiency is low, and the corresponding ballast resistor value is set to a lower value, such as 200 ohms. The lower resistance value limits the current through transistor B, reduces heat generation, avoids excessive junction temperature due to insufficient heat dissipation, and ensures that transistor B operates within a safe temperature range.

[0068] The power amplifier chip 100 of the above embodiment includes a substrate 110 and at least two power amplifier arrays 120 disposed on the substrate 110. Each power amplifier array 120 includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. In the power amplifier array 120 located in the later stage of the at least two-stage power amplifier array 120, each ballast resistor is sequentially connected to the input terminal Fin of the power amplifier array 120, and the resistance value of the ballast resistors decreases sequentially from the first ballast resistor to the nth ballast resistor, where n is an integer. In this embodiment, for the power amplifier array 120 located in the later stage, by setting the resistance value of the ballast resistors differently, thermal balance of multiple transistors can be achieved, thereby reducing the junction temperature difference of different transistors in the power amplifier array 120. Compared with the configuration of uniform resistors, the thermal effect of the power amplifier array 120 can be effectively reduced, and the safe operating area of ​​each transistor can be expanded, thereby improving the overall performance of the power amplifier chip 100.

[0069] Taking a power amplifier chip 100 for a 5G communication base station as an example, this chip includes a multi-stage HBT power amplifier array 120. The front-stage HBT initially amplifies the weak 5G signal received from the base station, and the rear-stage HBT further amplifies the signal to meet transmission requirements. Near the rear-stage HBT die, which is close to the front-stage HBT, the heat and electric field generated during signal amplification by the front-stage HBT make the die susceptible to overcurrent. Assuming an average resistance of 300Ω, a positive compensation of +30Ω is applied based on its distance from the front-stage HBT, setting the ballasting resistor to 330Ω. This higher resistance value limits the current, preventing the die from overheating due to overcurrent and ensuring stable operation. For the rear-stage HBT die further away from the front-stage HBT, it is less directly affected by the front-stage HBT, resulting in a relatively smaller current. Assuming a negative compensation of -20Ω is applied based on its distance, the ballasting resistor is set to 280Ω. A lower resistance value allows more current to flow, enabling the die to fully perform its amplification function and work with the preamplifier and other dies to amplify the 5G signal. By setting the ballasting resistor value according to its location, the junction temperature difference of the dies in the entire HBT array is reduced, resulting in more accurate signal amplification. This improves the signal transmission quality of the 5G communication base station and the reliability of the power amplifier chip 100, ensuring that the 5G signal can be transmitted stably and efficiently to the mobile terminal.

[0070] Please see Figure 7 and Figure 8 , Figure 7 This is a layout schematic diagram of another embodiment of the power amplifier chip provided in this application. Figure 8 A circuit diagram of another embodiment of the power amplifier array provided in this application.

[0071] like Figure 7 and Figure 8 As shown, the power amplifier chip 200 includes a substrate 210 and at least two stages of power amplifier arrays 220 disposed on the substrate 210. Each stage of the power amplifier array 220 includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. For example, the multiple transistors include Q1 to Qn, and the multiple ballast resistors include R1 to Rn, with transistor Q1 connected to R1 and transistor Qn connected to Rn. The first terminal of each transistor is connected to the input terminal Fin of the corresponding power amplifier array 220, the second terminal of each transistor is connected to the output terminal FoutFout of the corresponding power amplifier array 220, and the third terminal of each transistor is grounded. The first terminal of each ballast resistor is used to receive a bias signal iref, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor.

[0072] In each of the at least two power amplifier arrays 220, transistors are disposed at different positions on the substrate 210 and arranged in an array. The ballast resistors connected to transistors in the middle positions are configured with a first resistance value, and the ballast resistors connected to transistors in the edge positions are configured with a second resistance value. The first resistance value is greater than the second resistance value, and the maximum resistance difference between all ballast resistors is less than or equal to 50 ohms. In one specific embodiment, the maximum resistance difference between all ballast resistors is less than or equal to 20 ohms. By limiting the resistance value in each region, the stability of transistors at different positions is ensured as much as possible.

[0073] It should be noted that for transistors in the middle arrangement, heat is easily accumulated due to poor heat dissipation, leading to a rise in junction temperature. By configuring the ballast resistor connected to it with a larger first resistance value, the current flowing through the transistor can be limited, reducing heat generation and thus lowering the junction temperature. For transistors in the edge arrangement, heat dissipation is relatively better, but they may be affected by edge effects. Appropriately reducing the resistance value of the ballast resistor connected to it (i.e., the second resistance value is smaller than the first resistance value) allows more current to flow through the transistor, increasing its operating current and amplification capability. By reasonably adjusting the resistance values ​​of the ballast resistors connected at different positions, the junction temperature of each transistor is made more uniform, reducing transistor performance fluctuations caused by junction temperature differences, avoiding local overheating, improving the heat dissipation efficiency of the power amplifier chip 200, extending the chip's lifespan, and also improving the performance of the power amplifier chip 200.

[0074] In one embodiment, the first resistance value and the second resistance value are set as the sum of the preset average resistance value and the compensation value of each ballast resistor. The compensation value of the ballast resistor corresponding to the first resistance value is positive, and the compensation value of the ballast resistor corresponding to the second resistance value is negative.

[0075] In one embodiment, the at least two-stage power amplifier array 220 includes a first power amplifier array 220 in which a plurality of transistors are symmetrically arranged on a substrate 210. The ballast resistors connected to the transistors arranged in the center region of the symmetry are configured with a first resistance value, and the ballast resistors connected to the transistors arranged in the edge region of the symmetry are configured with a second resistance value.

[0076] The power amplifier chip 200 of the above embodiment includes a substrate 210 and at least two power amplifier arrays 220 disposed on the substrate 210. Each power amplifier array 220 includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. In each power amplifier array 220 of the at least two power amplifier arrays 220, the transistors are disposed at different positions on the substrate 210 and arranged in an array. The ballast resistor connected to the transistor in the middle position is configured with a first resistance value, and the ballast resistor connected to the transistor in the edge position is configured with a second resistance value. The first resistance value is greater than the second resistance value, and the maximum resistance difference between the ballast resistors is less than or equal to 50 ohms. In this embodiment, by setting the resistance value of the ballast resistors differently for each power amplifier array 220, thermal balance of multiple transistors can be achieved, thereby reducing the junction temperature difference between different transistors in the power amplifier array 220. Compared to the configuration of uniform resistors, the thermal effect of the power amplifier array 220 can be effectively reduced, and the safe operating area of ​​each transistor can be expanded, thereby improving the overall performance of the power amplifier chip 200.

[0077] Taking a power amplifier array 220 in a power amplifier chip 200 used in a 5G communication base station as an example, assume the array has 9 transistors arranged in a 3×3 matrix, with the 5th transistor in the middle and the 1st, 2nd, 3rd, 4th, 6th, 7th, 8th, and 9th transistors at the edges. Assume that, after design and testing, the ballast resistor connected to the 5th transistor in the middle is configured with a first resistance value R1 = 320 ohms, and the ballast resistors connected to the transistors at the edges are configured with a second resistance value R2 = 270 ohms. The maximum resistance difference is then 320 - 270 = 50 ohms, satisfying the requirement of being less than or equal to 50 ohms. When an input signal enters the power amplifier array 220, for the 5th transistor in the middle, the larger first resistance value R1 limits the current flowing through it, reducing heat generation and lowering the junction temperature, allowing it to operate near its stable operating point and ensuring the stability of signal amplification. For the edge transistors, the smaller second resistance value R2 allows more current to flow, thus making the junction temperature of each transistor more uniform. With this configuration, each transistor in the entire power amplifier array 220 can operate at the appropriate operating point, ensuring that the 5G communication base station can operate stably and efficiently.

[0078] It is understood that the specific implementation of the power amplifier chip 200 provided in this application embodiment can be referred to the corresponding implementation of the aforementioned power amplifier chip 100, and the beneficial effects that the power amplifier chip 200 provided in this application embodiment can be referred to the beneficial effects of the power amplifier chip 100 in the corresponding embodiment provided above, which will not be repeated here.

[0079] Please see Figure 9 and Figure 10 , Figure 9 This is a layout schematic diagram of yet another embodiment of the power amplifier chip provided in this application. Figure 10 This is a circuit diagram of yet another embodiment of the power amplifier array provided in this application.

[0080] like Figure 9 and Figure 10As shown, the power amplifier chip 300 includes a substrate 310 and at least two stages of power amplifier arrays 320 disposed on the substrate 310. Each stage of the power amplifier array 320 includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. For example, the multiple transistors include Q1 to Qn, and the multiple ballast resistors include R1 to Rn, with transistor Q1 connected to R1 and transistor Qn connected to Rn. The first terminal of each transistor is connected to the input terminal Fin of the corresponding power amplifier array 320, the second terminal of each transistor is connected to the output terminal Fout of the corresponding power amplifier array 320, and the third terminal of each transistor is grounded. The first terminal of each ballast resistor is used to receive a bias signal iref, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor.

[0081] In each of the at least two power amplifier arrays 320, transistors are disposed at different positions on the substrate 310 and arranged in an array. The ballast resistor connected to the transistor in the middle position is taken as the starting point, and the ballast resistor connected to the transistor in the edge position is taken as the ending point. The resistance difference between two adjacent ballast resistors is the same.

[0082] like Figure 15 As shown, Figure 15 This is an infrared thermogram of multiple transistors in a power amplifier chip provided in this embodiment. The power amplifier chip includes at least two power amplifier arrays, with transistors arranged in rows and columns in each array. Region 51 represents multiple transistors in the middle area of ​​the array. Region 52 corresponds to either the first or second stage of the power amplifier array. A relatively large ballast resistor value is applied to the transistors in the middle area. After a period of operation, junction temperature testing reveals consistent die thermal effects within the same array in region 51, with no significant temperature anomalies or deviations, thus ensuring the stability of each stage. It should be noted that transistors in the middle arrangement have difficulty dissipating heat, and their junction temperature is prone to rise. By setting a larger resistance value at the starting point (the ballast resistor in the middle arrangement), the current flowing through the transistors in this area can be limited, reducing heat generation and lowering the junction temperature. As the transistors move from the middle to the edge, heat dissipation conditions gradually improve. The ballast resistor values ​​are progressively decreased, resulting in smaller ballast resistor values ​​for transistors at the edges, thereby increasing the current within a reasonable range and making the junction temperature of each transistor more uniform. Therefore, it helps improve the heat dissipation efficiency of the power amplifier chip 300, extends the chip's lifespan, and also reduces the risk of performance degradation due to overheating. In practical applications, this is equivalent to improving the performance of the power amplifier chip 300.

[0083] In one embodiment, in each stage of the power amplifier array 320, the resistance value of each ballast resistor is set based on the sum of the preset average resistance value and the compensation value of each ballast resistor. The magnitude of the compensation value is positively correlated with the position of the corresponding connected transistor in the middle of the substrate 310. The preset average resistance value is set to 300 ohms, and the compensation value ranges from -50 ohms to 50 ohms.

[0084] For example, at least two-stage power amplifier array 320 includes a second power amplifier array 320, in which a plurality of transistors are arranged on substrate 310 along a first direction, with the transistor at the middle position of the first direction corresponding to the ballast resistor as the starting point, and the transistor at the end position of the first direction corresponding to the ballast resistor as the ending point.

[0085] The power amplifier chip 300 of the above embodiment includes a substrate 310 and at least two power amplifier arrays 320 disposed on the substrate 310. Each power amplifier array 320 includes multiple transistors and multiple ballast resistors, with each transistor corresponding to one ballast resistor. In each of the at least two power amplifier arrays 320, the transistors are disposed at different positions on the substrate 310 and arranged in an array. The ballast resistor connected to the transistor in the middle position is taken as the starting point, and the ballast resistor connected to the transistor in the edge position is taken as the ending point. The resistance difference between two adjacent ballast resistors is the same. In this embodiment, for the power amplifier array 320 located in the later stage, by setting the resistance value of the ballast resistors differently, thermal balance of multiple transistors can be achieved, thereby reducing the junction temperature difference of different transistors in the power amplifier array 320. Compared with the configuration of uniform resistors, the thermal effect of the power amplifier array 320 can be effectively reduced, and the safe operating area of ​​each transistor can be expanded, thereby improving the overall performance of the power amplifier chip 300.

[0086] Taking a power amplifier array 320 in a power amplifier chip 300 used in a 5G communication base station as an example, assume the array has 5 transistors arranged in a straight line. The middle transistor is the 3rd transistor, serving as the starting point, and its corresponding ballast resistor value is set to R1 = 320 ohms. The edge transistors are the 1st and 5th transistors, serving as the ending points, and their corresponding ballast resistor values ​​are set to R5 = 300 ohms. Since the resistance difference between two adjacent ballast resistors is the same, and the interval from the 3rd transistor to the 1st or 5th transistor is 2 intervals, the resistance value changes by 320 - 300 = 20 ohms. Therefore, the resistance difference for each interval is 20 ÷ 2 = 10 ohms. Thus, the ballast resistor value connected to the 2nd transistor is R2 = 320 - 10 = 310 ohms, and the ballast resistor value connected to the 4th transistor is R4 = 300 + 10 = 310 ohms. When the input signal enters the power amplifier array 320, for the third transistor in the middle, the larger starting-point ballast resistor R1 limits the current flowing through it, reducing heat generation and lowering the junction temperature, allowing it to operate near its stable operating point and ensuring the stability of signal amplification. For the first and fifth transistors at the edges, the smaller ending-point ballast resistor R5 allows more current to flow, thus making the junction temperature of each transistor more uniform. Through this configuration, all transistors in the entire power amplifier array 320 can operate at their appropriate operating points, ensuring the stable and efficient operation of the 5G communication base station.

[0087] It is understood that the specific implementation of the power amplifier chip 300 provided in this application embodiment can be referred to the corresponding implementation of the aforementioned power amplifier chip 100, and the beneficial effects that the power amplifier chip 300 provided in this application embodiment can be referred to the beneficial effects of the power amplifier chip 300 in the corresponding embodiment provided above, which will not be repeated here.

[0088] Please see Figure 11 and Figure 12 , Figure 11 This is a layout schematic diagram of another embodiment of the power amplifier chip provided in this application. Figure 12 This is a circuit diagram of another embodiment of the power amplifier array provided in this application.

[0089] like Figure 11 and Figure 12As shown, the power amplifier chip 400 includes a substrate 410 and at least two power amplifier arrays 420 disposed on the substrate 410. Each power amplifier array 420 includes multiple transistors and multiple current-limiting resistors, with each transistor corresponding to a current-limiting resistor. For example, the multiple transistors include Q1 to Qn, and the multiple current-limiting resistors include Rbase1 to Rbasen. Transistor Q1 is connected to Rbase1, and transistor Qn is connected to Rbasen. The first terminal of each transistor is connected to the input terminal Fin of the corresponding power amplifier array 420 through a current-limiting resistor, the second terminal of each transistor is connected to the output terminal Fout of the corresponding power amplifier array 420, and the third terminal of each transistor is grounded.

[0090] In the power amplifier array 420 of at least two stages, each current-limiting resistor in the power amplifier array 420 in the later stage is connected to the input terminal Fin of the power amplifier array 420 in sequence, and the resistance value of the current-limiting resistor is set to decrease sequentially from the first current-limiting resistor to the nth current-limiting resistor, where n is an integer.

[0091] It should be noted that the transistors can include heterojunction bipolar transistors (HBTs) or field-effect transistors (FETs). The current-limiting resistors can be, for example, the base resistors of the transistors. The thermal effect is adjusted by controlling the power (dBm) of the input signal. The principle is that by setting different current-limiting resistor values, the compensation value is increased or decreased to increase or decrease the signal power input to the HBTs, thus adjusting the junction temperatures of the different HBTs to be consistent. By reasonably adjusting the resistance values ​​of the current-limiting resistors, the power consumption of each transistor is more balanced, avoiding localized overheating. This helps improve the heat dissipation efficiency of the power amplifier chip 400, extends the chip's lifespan, and also reduces the risk of performance degradation due to overheating.

[0092] In this embodiment, by setting differentiated current-limiting resistor values, the junction temperature difference between different transistors in the power amplifier array 420 is reduced, effectively mitigating the thermal effect. When the junction temperature difference decreases, each transistor can operate in a more stable temperature environment, and its safe operating area can be expanded. The safe operating area refers to the parameter range within which a transistor can operate normally without damage, including parameters such as voltage, current, and power. After the junction temperature difference is reduced, the transistor can still maintain stable operation under higher voltage, current, and power, thereby improving the overall performance of the power amplifier chip 400. Specifically, the power amplifier chip 400 has stronger signal amplification capability, can amplify the input signal more accurately, and reduces signal distortion. The power gain is higher, enabling the input signal to be amplified to higher power. At the same time, the reliability and stability of the power amplifier chip 400 are also improved, reducing the risk of the power amplifier chip 400 failing due to transistor overheating.

[0093] In one embodiment, such as Figure 13As shown, each stage of the power amplifier array 420 also includes multiple ballast resistors, with each transistor corresponding to one ballast resistor. These multiple ballast resistors include, for example, R1 to Rn, with transistor Q1 connected to R1 and transistor Qn connected to Rn. The first terminal of each ballast resistor receives a bias signal iref, and the second terminal of each ballast resistor is connected to the first terminal of the corresponding transistor. In at least two stages of the power amplifier array 420, in the later stage, each ballast resistor is sequentially connected to the input terminal Fin of the power amplifier array 420, and the resistance values ​​of the ballast resistors decrease sequentially from the first ballast resistor to the nth ballast resistor, where n is an integer.

[0094] In one embodiment, in each stage of the power amplifier array 420, each transistor is disposed at a different position on the substrate 410 and arranged in an array. The resistance value of the current-limiting resistor corresponding to each transistor in different regions is different.

[0095] In one embodiment, in each power amplifier array 420, the current-limiting resistor connected to the transistor in the middle arrangement position is configured as a first resistance value, and the current-limiting resistor connected to the transistor in the edge arrangement position is configured as a second resistance value, wherein the first resistance value is greater than the second resistance value.

[0096] The first and second resistance values ​​are set as the sum of the preset average resistance of each current-limiting resistor and its compensation value. The compensation value of the current-limiting resistor corresponding to the first resistance value is positive, and the compensation value of the current-limiting resistor corresponding to the second resistance value is negative.

[0097] For example, at least two-stage power amplifier array 420 includes a first power amplifier array 420, in which a plurality of transistors are symmetrically arranged on a substrate 410, and the current-limiting resistors connected to the transistors arranged in the central region of symmetry are configured with a first resistance value, and the current-limiting resistors connected to the transistors arranged in the edge region of symmetry are configured with a second resistance value.

[0098] In one embodiment, in each stage of the power amplifier array 420, the current-limiting resistor connected to the transistor in the middle position is taken as the starting point, and the current-limiting resistor connected to the transistor in the edge position is taken as the ending point. From the starting point to the ending point, the resistance value of each current-limiting resistor is set to decrease sequentially.

[0099] In one embodiment, in each stage of the power amplifier array 420, the resistance value of each current-limiting resistor is set based on the sum of the preset average resistance value and the compensation value of each current-limiting resistor. The magnitude of the compensation value is positively correlated with the position of the corresponding connected transistor in the middle of the substrate 410. The preset average resistance value is set to 300 ohms, and the compensation value ranges from -50 ohms to 50 ohms.

[0100] For example, at least two-stage power amplifier array 420 includes a second power amplifier array 420, in which a plurality of transistors are arranged on substrate 410 along a first direction, with the transistor at the middle position of the first direction corresponding to a current-limiting resistor as the starting point, and the transistor at the end position of the first direction corresponding to a current-limiting resistor as the ending point.

[0101] In one embodiment, the substrate 410 is provided with a heat sink; in each stage of the power amplifier array 420, transistors at different locations have different heat dissipation efficiencies relative to the heat sink, and the resistance values ​​of the current-limiting resistors corresponding to each transistor are set based on the heat dissipation efficiency of the transistors. The resistance value of each current-limiting resistor is negatively correlated with its corresponding heat dissipation efficiency.

[0102] For example, the heat sink includes at least one via. In each stage of the power amplifier array 420, each transistor has a first distance from each via and / or each via has a first number. The resistance value of the current-limiting resistor corresponding to each transistor is set based on the first distance and / or the first number. The resistance value of each current-limiting resistor is negatively correlated with the corresponding first distance, and positively correlated with the corresponding first number.

[0103] For example, the heat sink includes a heat-dissipating metal layer adjacent to each transistor. In each stage of the power amplifier array 420, the heat-dissipating metal layer adjacent to each transistor has a first area and / or a first thickness, and the resistance value of the current-limiting resistor corresponding to each transistor is set based on the first area and / or the first thickness. The resistance value of each current-limiting resistor is positively correlated with the corresponding first area, and the resistance value of each current-limiting resistor is positively correlated with the corresponding first thickness.

[0104] The power amplifier chip 400 of the above embodiment includes a substrate 410 and at least two stages of power amplifier arrays 420 disposed on the substrate 410. Each stage of the power amplifier array 420 includes multiple transistors and multiple current-limiting resistors, with each transistor corresponding to one current-limiting resistor. In the power amplifier array 420 at the later stage of the at least two-stage power amplifier arrays 420, each current-limiting resistor is sequentially connected to the input terminal Fin of the power amplifier array 420, and the resistance value of the current-limiting resistors decreases sequentially from the first current-limiting resistor to the nth current-limiting resistor, where n is an integer. In this embodiment, for the power amplifier array 420 located at the later stage, by setting the resistance value of the current-limiting resistors differently, thermal balance of multiple transistors can be achieved, thereby reducing the junction temperature difference of different transistors in the power amplifier array 420. Compared with the configuration of uniform resistors, the thermal effect of the power amplifier array 420 can be effectively reduced, and the safe operating area of ​​each transistor can be expanded, thereby improving the overall performance of the power amplifier chip 400.

[0105] It is understood that the specific implementation of the power amplifier chip 400 provided in this application embodiment can be referred to the corresponding implementation of the aforementioned power amplifier chip 100, power amplifier chip 200 or power amplifier chip 300. For example, the specific setting method of each current limiting resistor can be referred to the implementation of the ballast resistor provided in the aforementioned embodiment. This application embodiment will not be repeated here.

[0106] Please refer to Figure 14 , Figure 14 This is a schematic block diagram of a radio frequency front-end module provided in an embodiment of this application.

[0107] like Figure 14 As shown, the RF front-end module 500 includes the power amplifier chip 520 of the above embodiments. The power amplifier chip 520 can be the power amplifier chip 100, power amplifier chip 200, power amplifier chip 300, or power amplifier chip 400 of the above embodiments.

[0108] It is understood that the beneficial effects that the RF front-end module 500 provided in this application embodiment can achieve can be referred to the beneficial effects of the power amplifier chip 100, power amplifier chip 200, power amplifier chip 300 or power amplifier chip 400 in the corresponding embodiments provided above, and will not be repeated here.

[0109] This embodiment provides a radio frequency (RF) front-end module. An RF front-end module is a component that integrates two or more discrete devices, such as RF switches, low-noise amplifiers, filters, duplexers, power amplifiers, and transformers, into a single independent module. This improves the integration and hardware performance of the RF front-end module and reduces its size. Specifically, the RF front-end module can be applied to 4G and 5G communication devices such as smartphones, tablets, and smartwatches.

[0110] With the development of information technology, 5G technology and 5G equipment place higher demands on the performance of radio frequency (RF) front-end modules. The technical solution provided in this application offers a filter and RF front-end module that can effectively suppress nonlinear distortion generated by the filter, thereby better meeting the needs of 5G technology and thus applicable to 5G equipment.

[0111] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A power amplifier chip, characterized by, The power amplifier chip comprises: a substrate and at least two stages of power amplifier arrays arranged on the substrate, each stage of the power amplifier arrays comprising a plurality of transistors and a plurality of ballast resistors, each of the transistors corresponding to one of the ballast resistors; a first end of each of the transistors is connected to an input end of the corresponding power amplifier array, a second end of each of the transistors is connected to an output end of the corresponding power amplifier array, and a third end of each of the transistors is grounded; a first end of each of the ballast resistors receives a bias signal, and a second end of each of the ballast resistors is connected to the first end of the corresponding transistor; wherein in the power amplifier array at the rear stage of the at least two stages of power amplifier arrays, each of the ballast resistors is sequentially connected to the input end of the power amplifier array, and the resistance value of the ballast resistor decreases sequentially from the first ballast resistor to the nth ballast resistor, n being an integer.

2. The power amplifier chip of claim 1, wherein, In the power amplifier array at the rear stage, the maximum resistance difference between each of the ballast resistors is less than or equal to 100 ohms.

3. The power amplifier chip of claim 1, wherein, In the power amplifier array at the rear stage, the resistance value of each of the ballast resistors is set based on a preset resistance average of each of the ballast resistors.

4. The power amplifier chip of claim 3, wherein, The preset resistance average is set to be between 250 ohms and 350 ohms.

5. The power amplifier chip of claim 1, wherein, In the power amplifier array at the rear stage, the resistance value of each of the ballast resistors is set based on the sum of a preset resistance average and a compensation value of each of the ballast resistors, the value of the compensation value being positively correlated with the connection order of each of the ballast resistors.

6. The power amplifier chip of claim 5, wherein, The value of the compensation value ranges from -50 ohms to 50 ohms.

7. The power amplifier chip of claim 5, wherein, The compensation value of the ballast resistor at the intermediate connection position in each of the ballast resistors is zero, and the resistance value is the preset resistance average.

8. The power amplifier chip of claim 1, wherein, In the power amplifier array at the rear stage, the resistance difference between two adjacent ballast resistors is a fixed value.

9. The power amplifier chip of any of claims 1-8, wherein, In each stage of the power amplifier array, each of the transistors is arranged at different positions of the substrate and arranged in an array. Wherein the resistance values of the ballast resistors corresponding to the transistors at different regions are different.

10. The power amplifier chip of claim 9, wherein, In each of the power amplifier arrays, the ballast resistor corresponding to the transistor at the intermediate arrangement position is configured as a first resistance value, and the ballast resistor corresponding to the transistor at the edge arrangement position is configured as a second resistance value, the first resistance value being greater than the second resistance value.

11. The power amplifier chip of claim 10, wherein, The first resistance value and the second resistance value are set as the sum of a preset resistance average and a compensation value of each of the ballast resistors. Wherein the compensation value of the ballast resistor corresponding to the first resistance value is positive, and the compensation value of the ballast resistor corresponding to the second resistance value is negative.

12. The power amplifier chip of claim 10, wherein, The at least two stages of power amplifier arrays comprise a first power amplifier array, and the plurality of transistors in the first power amplifier array are arranged symmetrically on the substrate, the ballast resistor corresponding to the transistor arranged in the symmetric center region is configured as a first resistance value, and the ballast resistor corresponding to the transistor arranged in the symmetric edge region is configured as a second resistance value.

13. The power amplifier chip of claim 9, wherein, In each of the power amplification arrays, a transistor arranged in a middle position is connected to a ballast resistor as a starting point, and a transistor arranged in an edge position is connected to a ballast resistor as an ending point, and the resistance values of the ballast resistors decrease from the starting point to the ending point.

14. The power amplifier chip of claim 13, wherein, In each of the power amplification arrays, the resistance values of the ballast resistors are set based on a preset average resistance value and a compensation value, and the compensation value is positively correlated with the arrangement position of the transistor on the substrate.

15. The power amplifier chip of claim 14, wherein, The preset average resistance value is 300 ohms, and the compensation value ranges from -50 ohms to 50 ohms.

16. The power amplifier chip of claim 13, wherein, The at least two power amplification arrays include a second power amplification array, and the transistors in the second power amplification array are arranged in a first direction on the substrate, a transistor arranged in a middle position of the first direction is connected to a ballast resistor as the starting point, and a transistor arranged in an end position of the first direction is connected to a ballast resistor as the ending point.

17. The power amplifier chip of any of claims 1-8, wherein, The substrate is provided with a heat dissipation member, and the transistors arranged in different positions in each of the power amplification arrays have different heat dissipation efficiencies relative to the heat dissipation member, and the resistance values of the ballast resistors corresponding to the transistors are set based on the heat dissipation efficiencies of the transistors. The resistance values of the ballast resistors are negatively correlated with the corresponding heat dissipation efficiencies.

18. The power amplifier chip of claim 17, wherein, The heat dissipation member includes at least one through hole. In each of the power amplification arrays, each of the transistors has a first distance from each of the through holes and / or each of the through holes has a first number, and the resistance values of the ballast resistors corresponding to the transistors are set based on the first distance and / or the first number. The resistance values of the ballast resistors are negatively correlated with the corresponding first distances, and the resistance values of the ballast resistors are positively correlated with the corresponding first numbers.

19. The power amplifier chip of claim 17, wherein, The heat dissipation member includes a heat dissipation metal layer adjacent to each of the transistors. In each of the power amplification arrays, the heat dissipation metal layer adjacent to each of the transistors has a first area and / or a first thickness, and the resistance values of the ballast resistors corresponding to the transistors are set based on the first area and / or the first thickness. The resistance values of the ballast resistors are positively correlated with the corresponding first areas, and the resistance values of the ballast resistors are positively correlated with the corresponding first thicknesses.

20. The power amplifier chip of any of claims 1-8, wherein, The transistors include heterojunction bipolar transistors.

21. A power amplifier chip, comprising: The power amplification chip includes: a substrate and at least two power amplification arrays arranged on the substrate, each of the power amplification arrays including a plurality of transistors and a plurality of ballast resistors, and each of the transistors being connected to a corresponding ballast resistor; a first end of each of the transistors is connected to an input end of a corresponding power amplification array, a second end of each of the transistors is connected to an output end of the corresponding power amplification array, and a third end of each of the transistors is grounded; a first end of each of the ballast resistors is used to receive a bias signal, and a second end of each of the ballast resistors is connected to the first end of a corresponding transistor; Each of the transistors in each of the at least two power amplification arrays is arranged at different positions of the substrate in an array manner; a ballast resistor corresponding to a transistor arranged at a middle array position is configured as a first resistance value, and a ballast resistor corresponding to a transistor arranged at an edge array position is configured as a second resistance value, the first resistance value being greater than the second resistance value, and a maximum resistance difference between the ballast resistors being less than or equal to 50 ohms.

22. A power amplifier chip, comprising: The power amplification chip comprises: a substrate and at least two power amplification arrays arranged on the substrate, each of the power amplification arrays comprising a plurality of transistors and a plurality of ballast resistors, each of the transistors corresponding to one of the ballast resistors; a first end of each of the transistors is connected to an input end of the corresponding power amplification array, a second end of each of the transistors is connected to an output end of the corresponding power amplification array, and a third end of each of the transistors is grounded; a first end of each of the ballast resistors is configured to receive a bias signal, and a second end of each of the ballast resistors is connected to the first end of the corresponding transistor; each of the transistors in each of the at least two power amplification arrays is arranged at different positions of the substrate in an array manner; a ballast resistor corresponding to a transistor arranged at a middle array position is configured as a first resistance value, and a ballast resistor corresponding to a transistor arranged at an edge array position is configured as a second resistance value, the first resistance value being greater than the second resistance value, and a maximum resistance difference between the ballast resistors being less than or equal to 50 ohms.

23. A power amplifier chip, comprising: The power amplification chip comprises: a substrate and at least two power amplification arrays arranged on the substrate, each of the power amplification arrays comprising a plurality of transistors and a plurality of ballast resistors, each of the transistors corresponding to one of the ballast resistors; a first end of each of the transistors is connected to an input end of the corresponding power amplification array, a second end of each of the transistors is connected to an output end of the corresponding power amplification array, and a third end of each of the transistors is grounded; a first end of each of the ballast resistors is configured to receive a bias signal, and a second end of each of the ballast resistors is connected to the first end of the corresponding transistor; each of the transistors in each of the at least two power amplification arrays is arranged at different positions of the substrate in an array manner; a ballast resistor corresponding to a transistor arranged at a middle array position is configured as a first resistance value, and a ballast resistor corresponding to a transistor arranged at an edge array position is configured as a second resistance value, the first resistance value being greater than the second resistance value, and a maximum resistance difference between the ballast resistors being less than or equal to 50 ohms.

24. A radio frequency front end module, comprising: The power amplification chip comprises: a substrate and at least two power amplification arrays arranged on the substrate, each of the power amplification arrays comprising a plurality of transistors and a plurality of ballast resistors, each of the transistors corresponding to one of the ballast resistors; a first end of each of the transistors is connected to an input end of the corresponding power amplification array, a second end of each of the transistors is connected to an output end of the corresponding power amplification array, and a third end of each of the transistors is grounded; a first end of each of the ballast resistors is configured to receive a bias signal, and a second end of each of the ballast resistors is connected to the first end of the corresponding transistor; each of the transistors in each of the at least two power amplification arrays is arranged at different positions of the substrate in an array manner; a ballast resistor corresponding to a transistor arranged at a middle array position is configured as a first resistance value, and a ballast resistor corresponding to a transistor arranged at an edge array position is configured as a second resistance value, the first resistance value being greater than the second resistance value, and a maximum resistance difference between the ballast resistors being less than or equal to 50 ohms.

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