Clock frequency divider and control method thereof

Abstract

Disclosed are a clock divider and a control method thereof, which enable retention work to be smoothly performed by ensuring that an output clock of the clock divider is in a low-level state in a retention signal conversion section. A clock divider according to an embodiment of the present invention comprises: a counter that counts clocks of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a generated clock edge according to the counter output, thereby generating an output clock divided from an input clock; and the state machine controls the counter according to a clock low level request of the power management unit, so that the output clock is in a low level state in a retention signal conversion interval.

Description

Technical Field

[0001] This invention relates to a clock divider and its control method, and more specifically, to a clock divider and its control method that ensure the retention function can be executed smoothly by guaranteeing that the output clock of the clock divider is in a low-level state during the retention signal transition interval. Background Technology

[0002] A System-on-a-Chip (SoC) is a technology that integrates multiple function blocks, such as a central processing unit (CPU), memory, interface, digital signal processing circuitry, and analog signal processing circuitry, onto a single semiconductor integrated circuit to realize a computer system or other electronic system. SoCs are evolving into more complex systems that include processors, multimedia, graphics, interface, and security functions. Clock design is typically extremely important in SoCs.

[0003] Figure 1 This is an example diagram illustrating how a clock divider divides the clock input by 8 to generate the clock output. In clock design, the clock divider used in the clock tree typically operates an internal counter based on the number of divisions required for the clock, and divides the clock by generating a clock output edge whenever the counter expires.

[0004] Figure 2 This is an example diagram illustrating that when the input clock is gated, the output clock from the clock divider is in a low-level state. Figure 3 This diagram illustrates an example where the output clock from the clock divider is high when the input clock is gated. When it is necessary to retain any power domain within a semiconductor system, the clock input to the flip-flop is subject to a constraint that it is low during the retention signal transition.

[0005] Retention triggers retain stored data even during power outages, which is especially useful in power-saving applications. Retention triggers preserve data during power outages or when entering low-power modes, reducing overall system power consumption, and allow data recovery when power is restored, thus ensuring data integrity.

[0006] like Figure 2 As shown, during the 8-fold clock division process, when the input clock is gated at time GT, and the counter used for clock division has a count value of 4, 5, 6, or 7, the output clock is in a low-level state. If the condition is to simply stop the clock toggle, clock gating can be performed using integrated clock gating (ICG). However, if clock gating is performed using a clock divider with a counter, the output clock may stop at a high level instead of a low level depending on the counter's count state within the corresponding period.

[0007] like Figure 3 For example, when the input clock is gated, the counter used for clock division will stop at a high level when the output clock is in the high-level range, i.e., when the counter's count value is 0, 1, 2, or 3. As mentioned above, even if the input clock is gated, the output clock can stop at a high level instead of a low level depending on the counter's count state.

[0008] If the condition is that there are flip-flops that receive the output clock from the clock divider and need to be retained, then during the retention signal transition interval, the clock of the corresponding flip-flop must be in a low-level state. However, if it cannot be guaranteed that the output clock of the clock divider is in a low-level state, then these flip-flops cannot be retained normally. These issues may become factors that limit the freedom of clock design. Summary of the Invention

[0009] The purpose of this invention is to provide a clock divider and its control method that ensure the output clock of the clock divider is in a low-level state during the retention signal transition interval, so that the retention operation can be performed smoothly.

[0010] Furthermore, the purpose of this invention is to provide a clock divider and its control method that can keep the output clock duty cycle constant regardless of the timing of the frequency division value change.

[0011] Furthermore, the purpose of this invention is that the design of all flip-flops used to receive the output of the clock divider can be unrestricted by the duty cycle and can change the division value in a variety of ways without causing a degradation in clock duty cycle quality.

[0012] The technical problems to be solved by the embodiments of the present invention are not limited to the above-mentioned technical problems, and other technical problems can be derived from the following embodiments.

[0013] The clock divider of this invention includes: a counter that counts the clock of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a clock edge based on the counter output, thereby generating an output clock divided from the input clock; and a state machine that controls the counter according to a clock low-level request from a power management unit, such that the output clock is in a low-level state during the retention signal transition interval.

[0014] When the clock low-level request is received, the state machine can perform the following steps: wait until the counter's count value reaches the counter expiration value corresponding to the frequency division value; and when the counter's count value reaches the counter expiration value corresponding to the frequency division value, interrupt the operation of the counter, so that the output clock stops in the low-level state.

[0015] When the clock low-level request is received, the state machine can perform the following steps: determine whether the output clock generated by the output clock generator is in a low-level state; when the output clock is in the low-level state, interrupt the operation of the counter, so that the output clock stops in the low-level state; and when the output clock is in the high-level state, keep the counter operating until the output clock is in the low-level state.

[0016] When the clock low-level request is received, the state machine can perform the following steps: determine whether the counter value is within the low-level counting range that satisfies the output clock being in a low-level state; when the counter value is within the low-level counting range, interrupt the operation of the counter, causing the output clock to stop in the low-level state; and when the counter value has not reached the low-level counting range, keep the counter operating until it reaches the low-level counting range.

[0017] When the clock low-level request is received, the state machine can perform the following steps: compare the count set value, which is half of the counter expiration value corresponding to the frequency division value, with the count value of the counter; when the count value of the counter has not reached the count set value, keep the counter working until the count set value is reached; when the count value of the counter reaches the count set value and the output clock is in a low-level state, interrupt the operation of the counter.

[0018] The output clock is input to a flip-flop, and the flip-flop can be retained when the output clock is at a low level.

[0019] The state machine can perform the following steps: when the frequency division value changes, the counter is updated using the expiration value of the second counter corresponding to the changed frequency division value, based on whether the expiration value of the first counter corresponding to the frequency division value before the change has expired.

[0020] When the frequency division value changes, the state machine can execute the following steps: determine whether the count of the first counter has expired by comparing the expiration value of the first counter corresponding to the frequency division value before the change with the count value of the counter; when the count value of the counter has not reached the expiration value of the first counter, do not update the expiration value of the second counter corresponding to the changed frequency division value, but wait; and when the count value of the counter reaches the expiration value of the first counter, use the expiration value of the second counter to update the counter.

[0021] According to an embodiment of the present invention, a semiconductor system is provided, comprising: the clock divider; one or more flip-flops, in the power domain, receiving an output clock output by the clock divider after dividing an input clock, and operating according to the output clock; and a power management unit that outputs a low-level clock request to the state machine of the clock divider for retention.

[0022] When the power management unit requests that the output clock be kept low in accordance with the low clock level, it may output a hold signal to the flip-flop.

[0023] Furthermore, the clock divider control method of this embodiment of the invention is used to control the operation of a clock divider including a counter, an output clock generator, and a state machine, and includes the following steps: counting the clock of the input clock through the counter and generating a counter output for dividing the input clock; generating a clock edge according to the counter output through the output clock generator, thereby generating an output clock divided from the input clock; and controlling the counter through the state machine according to the clock low-level request of the power management unit, so that the output clock is in a low-level state during the retention signal transition interval.

[0024] The steps of controlling the counter may include the following steps: waiting until the counter count value reaches the counter expiration value corresponding to the frequency division value; and when the counter count value reaches the counter expiration value corresponding to the frequency division value, interrupting the operation of the counter, so that the output clock stops at a low level.

[0025] The steps of controlling the counter may include the following steps: determining whether the output clock output by the output clock generator is in a low-level state; when the output clock is in the low-level state, interrupting the operation of the counter so that the output clock stops in the low-level state; and when the output clock is in the high-level state, maintaining the operation of the counter until the output clock is in the low-level state.

[0026] The steps of controlling the counter may include the following steps: determining whether the counter's count value is within the low-level counting range that satisfies the output clock being in a low-level state; when the counter's count value is within the low-level counting range, interrupting the operation of the counter, causing the output clock to stop in the low-level state; and when the counter's count value has not reached the low-level counting range, maintaining the operation of the counter until the low-level counting range is reached.

[0027] The steps of controlling the counter may include the following steps: comparing a count set value, which is half of the counter expiration value corresponding to the frequency division value, with the count value of the counter; keeping the counter running until the count set value is reached when the count value of the counter has not reached the count set value; and interrupting the operation of the counter when the count value of the counter reaches the count set value and the output clock is in a low level state.

[0028] The clock divider control method of this invention may further include the following steps: when the state machine changes the frequency division value, the counter is updated using the expiration value of the second counter corresponding to the changed frequency division value, based on whether the expiration value of the first counter corresponding to the frequency division value before the change has expired.

[0029] The update step may include the following steps: determining whether the count of the first counter has expired by comparing the expiration value of the first counter corresponding to the frequency division value before the change with the count value of the counter; when the count value of the counter has not reached the expiration value of the first counter, not updating the expiration value of the second counter corresponding to the changed frequency division value, but waiting; and when the count value of the counter reaches the expiration value of the first counter, using the expiration value of the second counter to update the counter.

[0030] The clock divider control method of this invention may further include the following steps: one or more flip-flops in the power domain operate by receiving an output clock output by the clock divider after dividing the input clock; the power management unit outputs a clock low-level request to the state machine of the clock divider for retention; and when the output clock is kept low according to the clock low-level request, the power management unit outputs a retention signal to the flip-flops.

[0031] Furthermore, according to an embodiment of the present invention, a computer-readable recording medium is provided, wherein a computer program for performing the clock divider control method is recorded.

[0032] According to an embodiment of the present invention, a clock divider and its control method are provided, which ensure that the output clock of the clock divider is in a low-level state during the retention signal conversion interval, so that the retention operation can be performed smoothly.

[0033] Furthermore, according to embodiments of the present invention, a clock divider and its control method are provided that can keep the output clock duty cycle constant regardless of the change time of the frequency division value.

[0034] Furthermore, according to embodiments of the present invention, the design of all flip-flops used to receive the output of the clock divider can be unrestricted by the duty cycle and can change the division value in a variety of ways without causing a degradation in clock duty cycle quality. Attached Figure Description

[0035] Figure 1 This is an example diagram illustrating how a clock divider divides the clock input by 8 to generate the clock output.

[0036] Figure 2 This is an example diagram illustrating that when the input clock is gated, the output clock from the clock divider is in a low-level state.

[0037] Figure 3 This is an example diagram illustrating that when the input clock is gated, the output clock from the clock divider is in a high-level state.

[0038] Figure 4 This is a structural diagram of a clock divider according to an embodiment of the present invention.

[0039] Figure 5 The flowchart illustrates the operation of the state machine of the clock divider constituting an embodiment of the present invention and the clock divider control method.

[0040] Figure 6 This is a flowchart of a clock divider control method according to an embodiment of the present invention.

[0041] Figure 7 This is a flowchart of a clock divider control method according to another embodiment of the present invention.

[0042] Figure 8 For illustrative purposes Figure 7 An example diagram of the clock divider control method in the embodiment.

[0043] Figure 9 This is a conceptual diagram illustrating a computing device for performing a clock division method according to an embodiment of the present invention.

[0044] Explanation of reference numerals in the attached figures

[0045] 100: Clock divider

[0046] 110: Counter

[0047] 120: Output clock generator

[0048] 130: State Machine

[0049] 200: Power Management Unit

[0050] 300: Flip-flop

[0051] 900: Computing device

[0052] 910: Processor

[0053] 920: Memory

[0054] 930: Storage device

[0055] 940: Communication device

[0056] 950: High-speed interface

[0057] 960: Low-speed interface

[0058] 970: External Input / Output Device Detailed Implementation

[0059] The specific details for implementing the present invention will now be described in detail with reference to the accompanying drawings. However, in this description, specific descriptions related to known functions or structures will be omitted where there is a risk of unnecessarily obscuring the spirit of the invention. In the drawings, the same or corresponding structural elements are given the same reference numerals. Furthermore, repeated descriptions of the same or corresponding structural elements may be omitted in the description of the following embodiments. However, even if descriptions related to structural elements are omitted, it does not mean that such structural elements are not included in any embodiment.

[0060] The advantages, features, and methods of implementing the embodiments described in this specification will be referenced in the appendix. Figure 1 The invention becomes clearer from the embodiments described below. However, the invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and these embodiments are provided only to fully inform those skilled in the art of the invention of the scope of the invention.

[0061] The terminology used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terminology used in this specification has been selected as much as possible from currently widely used general terms in view of its function in this invention, but this may be changed according to the intentions of those skilled in the art, conventions, or the emergence of new technologies. Furthermore, in certain cases, there may be terms arbitrarily chosen by the applicant; in such cases, their meanings will be described in detail in the description of the corresponding invention. Therefore, the terminology used in this invention should be defined based on the meaning of the term and the overall content of the invention, rather than simply as term names.

[0062] Unless explicitly specified in the context as singular, the expression of singularity in this specification includes the expression of plurality. Furthermore, unless explicitly specified in the context as plural, the expression of plurality includes the expression of singularity. Throughout this specification, when a part is described as including a structural element, unless specifically stated otherwise, it means that other structural elements are also included, and not that other structural elements are excluded. In this invention, terms such as "comprising," "including," etc., can indicate the presence of features, steps, operations, factors, and / or structural elements, and these terms do not exclude the addition of more than one other function, step, operation, element, structural element, and / or combination thereof.

[0063] In this invention, when referring to a specific structural element as being "combined," "combined," "connected," "associated," or "reacting" with other structural elements, the specific structural element may be directly combined, combined, connected, and / or associated with or reacting with other structural elements, but is not limited thereto. For example, at least one intermediate structural element may exist between the specific structural element and other structural elements. Furthermore, in this invention, "and / or" may include a combination of at least one item listed or at least a portion of each item. In this invention, terms such as "first," "second," etc., are used to distinguish a specific structural element from other structural elements, and the structural elements are not limited to these terms. For example, a "first" structural element may be used to represent an element of the same or similar form as a "second" structural element.

[0064] The clock divider in this embodiment of the invention includes a state machine, which controls a counter such that the output clock of the clock divider 100 is in a low-level state during the retention signal transition interval according to the clock low-level request from the power management unit. Therefore, by ensuring that the output clock of the clock divider is in a low-level state during the retention signal transition interval, the retention operation can be performed smoothly.

[0065] The retention signal transition range can be either the range from normal mode to retention mode, or the range from retention mode to normal mode. Retention mode can be a mode that retains data stored in the trigger during power-off or low-power conditions. After entering retention mode, when transitioning to normal mode and power is restored, or when transitioning to a normal power mode (a power mode higher than low-power mode), the trigger retains the data stored at the time of transition to retention mode.

[0066] Figure 4 This is a structural diagram of a clock divider according to an embodiment of the present invention. (Refer to...) Figure 4 The clock divider 100 of this embodiment may include a counter 110, an output clock generator 120, and a state machine 130. The clock divider 100 of this embodiment includes a state machine 130, which controls the counter 110 so that, according to a low-level clock request from the power management unit 200 within the clock divider 100, the output clock of the clock divider 100 is in a low-level state during the reserved signal transition interval.

[0067] Counter 110 generates a counter output by counting the input clock, based on the counter expiration value corresponding to the clock's divide value. Counter 110 generates the counter output by comparing the counter expiration value corresponding to the divide value with the count value of counter 110 for the input clock. If the divide value is N (N is an integer greater than or equal to 2), then whenever the count reaches N / 2, counter 110 outputs the counter to the output clock generator 120.

[0068] For example, when the frequency division value is 8, the counter 110 can generate a first counter output and output it to the output clock generator 120 when counting the four input clocks from the first clock to the fourth clock. Then, it can generate a second counter output and output it to the output clock generator 120 when counting the four input clocks from the fifth clock to the eighth clock.

[0069] As another example, when the frequency division value is 4, the counter 110 can generate a first counter output and output it to the output clock generator 120 when counting the two input clocks from the first clock to the second clock. Then, when counting the two input clocks from the third clock to the fourth clock, it can generate a second counter output and output it to the output clock generator 120.

[0070] When the frequency division value is 8, the counter expiration value of counter 110 can be set to 8. When the frequency division value is 4, the counter expiration value of counter 110 can be set to 4. When the frequency division value is N, the counter expiration value of counter 110 can be set to N. That is, when the frequency division value is N, based on the counter expiration value set for counter 110, counting from 1, when the input clock counts to the Nth time, the counter expiration output can be input to the output clock generator 120.

[0071] When the frequency division value is N, counter 110 can count to N / 2 clock cycles out of N clock cycles of the input clock, generate a first counter output, and output it to output clock generator 120. Then, at the N / 2 clock cycle of the input clock, it generates a second counter output and outputs it to output clock generator 120. Output clock generator 120 can generate an output clock divided from the input clock based on the counter outputs of counter 110 (first counter output and second counter output).

[0072] The first counter output can be a signal that causes the output clock generator 120 to generate the falling edge (or rising edge) of the output clock, and the second counter output can be a signal that causes the output clock generator 120 to generate the rising edge (or falling edge) of the output clock. Whenever the count reaches a value corresponding to half of the division value, the output clock generator 120 can repeatedly generate rising and falling edges according to the counter output of the counter 110, thereby generating and outputting an output clock divided from the input clock.

[0073] When the frequency division value is 8, the output clock period can be 8 times the reference clock period of the input clock. In this case, the output clock frequency is 1 / 8 of the input clock. As another example, when the frequency division value is 4, the output clock period can be 4 times the reference clock period of the input clock. In this case, the output clock frequency is 1 / 4 of the input clock. When the frequency division value is N (N is an integer greater than 2), the output clock period is N times the reference clock period of the input clock, and the output clock frequency is 1 / N of the input clock.

[0074] When the frequency division value changes, before the change, counter 110 can generate a counter output based on the count of the first counter corresponding to the previous frequency division value. After the change, it can generate a counter output based on the count of the second counter corresponding to the new frequency division value. For example, when the frequency division value changes from 8 to 4, the previous frequency division value can be 8, and the new frequency division value can be 4. As another example, when the frequency division value changes from 4 to 8, the previous frequency division value can be 4, and the new frequency division value can be 8. The frequency division value is preferably a multiple of 2, but is not necessarily limited to this. Furthermore, in addition to the examples of 4 and 8, various frequency division values ​​can be applied.

[0075] To prevent unexpected duty cycle changes in the clock divider 100 due to changes in the divider value, the state machine 130 can control the updating of the counter expiration value based on the count value of the counter 110 and the counter expiration value corresponding to the previous divider value. When the divider value changes, the state machine 130 can update the counter using the second counter expiration value corresponding to the changed divider value, depending on whether the first counter expiration value has expired. The first counter expiration value can be the counter expiration value corresponding to the previous first divider value, and the second counter expiration value can be the counter expiration value corresponding to the changed second divider value. For example, when the divider value changes from 8 to 4, the first counter expiration value can be 8, and the second counter expiration value can be 4.

[0076] Figure 5 The following flowchart illustrates the operation of the state machine of the clock divider constituting an embodiment of the present invention and the clock divider control method. When the division value changes, state machine 130 can compare the first counter expiration value (the existing counter expiration value before the division value change) corresponding to the previous division value with the counter count value to determine whether the count of the first counter expiration value has expired (steps S10, S20). When the count value of counter 110 has not reached the first counter expiration value, state machine 130 may not update the second counter expiration value (the new counter expiration value) corresponding to the changed division value, but waits (step S30). State machine 130 may update the counter expiration value of counter 110 to the second counter expiration value when the count value of counter 110 reaches the first counter expiration value (step S40).

[0077] As described above, when the frequency division value changes, the state machine 130 may not update the counter expiration value corresponding to the changed frequency division value, but wait until it counts to the counter expiration value corresponding to the frequency division value before the change. Then, at the moment when the counting of the counter 110 corresponding to the frequency division value before the change is completed (the moment when the first counter expiration value expires), the counter expiration value (second counter expiration value) corresponding to the frequency division value changed for the counter 110 may be updated.

[0078] That is, state machine 130 can retain the counter expiration value corresponding to the updated and changed frequency division value until the clock duty cycle under the pre-change frequency division value is the same as the clock duty cycle under the changed frequency division value. In other words, state machine 130 can wait for the update of the counter expiration value, and the number of clock cycles waited corresponds to the difference between the first counter expiration value before the frequency division value change of counter 110 and the counter at the time of the frequency division value change.

[0079] For example, when counter 110 counts to the fifth clock cycle of the input clock, and the frequency division value changes from 8 to 4, the first counter's expiration value is 8, and the current count value of counter 110 is 5. Therefore, state machine 130 can hold onto updating the counter's expiration value and wait until counter 110 further counts to 3 clock cycles of the input clock (8 to 5 clock cycles). Then, when counter 110 counts to the remaining 3 clock cycles and is in the counter expiration state, the counter's expiration value can be updated from the existing 8 to 4. When the changed frequency division value is N (N is an integer greater than 2), state machine 130 can set the counter's expiration value of counter 110 to the count value N corresponding to the number of clock cycles.

[0080] The power management unit 200 can control the power supplied to network address (IP) blocks. For example, when the on-chip system enters a standby mode, the power management unit 200 cuts off the power supply to each IP block, thereby reducing the power consumption of the on-chip system. The power management unit 200 can output a clock low request to the state machine 130 of the clock divider 110 for retention.

[0081] State machine 130 can control counter 110 so that the output clock remains low during the retention signal transition period according to the clock low-level request from power management unit 200. When a clock low-level request is received from power management unit 200 ( Figure 5 In step S110), state machine 130 can determine whether the count value of counter 110 has reached the counter expiration value corresponding to the frequency division value (whether the counter has expired), and wait until the count value of counter 110 reaches the counter expiration value corresponding to the frequency division value (whether the counter has expired). Figure 5Steps S120 and S130). When the count value of counter 110 reaches the counter expiration value corresponding to the frequency division value, state machine 130 can interrupt the operation of counter 110, causing the output clock to stop at a low level. Figure 5 Steps S120 and S140).

[0082] Figure 6 A flowchart illustrating the clock divider control method according to an embodiment of the present invention is provided. (Refer to...) Figure 4 and Figure 6 When a low-level clock request is received from the power management unit 200 (step S61), the state machine 130 can determine whether the output clock output by the output clock generator 120 is in a low-level state (step S62). If the output clock output by the output clock generator 120 is in a low-level state, the operation of the counter 110 is immediately interrupted, causing the output clock to stop in a low-level state (step S63). If the output clock output by the output clock generator 120 is in a high-level state, the counter 110 can be kept running until the output clock is in a low-level state (step S64), and the operation of the counter 110 is interrupted when the output clock is in a low-level state, causing the output clock to stop in a low-level state.

[0083] Figure 7 This is a flowchart of a clock divider control method according to another embodiment of the present invention. Figure 8 For illustrative purposes Figure 7 An example diagram of the clock divider control method of the embodiment. (Refer to...) Figure 4 , Figure 7 and Figure 8 When a low-level clock request is received from the power management unit 200 (step S71), the state machine 130 can determine whether the count value of the counter 110 is within the low-level count range where the output clock satisfies the low level (step S72).

[0084] When the count value of counter 110 is within the low-level counting range, state machine 130 can interrupt the operation of counter 110, causing the output clock to stop at a low level (step S73). When the count value of counter 110 has not reached the low-level counting range, state machine 130 can keep counter 110 running until it reaches the low-level counting range (step S74). Through the above process, when the output clock of clock divider 100 is kept at a low level according to the low-level clock request, power management unit 200 can output a hold signal to the flip-flop.

[0085] For example, when the frequency division value is 8, if the count value of counter 110 is in the low-level counting range, that is, if the count value of counter 110 is 5 to 8 when the first count number is 1 (4 to 7 when the first count number is 0), then state machine 130 can immediately interrupt the operation of counter 110, so that the output clock stops in the low-level state.

[0086] Conversely, if the count value of counter 110 is not within the low-level counting range, that is, if the count value of counter 110 is 1 to 4 when the first count number is 1 (0 to 3 when the first count number is 0), then state machine 130 keeps counter 110 working. If the count value of counter 110 reaches the low-level counting range, then the operation of counter 110 is interrupted.

[0087] When the count value of counter 110 has not reached the low-level counting range, state machine 130 can keep counter 110 running until the count value of counter 110 reaches the counter expiration value. However, it can also interrupt the operation of counter 110 by outputting a low-level clock before reaching the counter expiration value. In this case, state machine 130 can keep counter 110 running and interrupt the operation of counter 110 when counter 110 counts to more than half of the counter expiration value.

[0088] exist Figure 8 In the example, during the process of generating an 8-division output clock from the input clock, if a clock low-level request CLR occurs before the count value of counter 110 reaches half of the counter's expiration value, then state machine 130 can keep counter 110 running until the count value of counter 110 reaches half of the counter's expiration value. At the moment when the count value of counter 110 reaches half of the counter's expiration value, or between the moment when the count value of counter 110 reaches half of the counter's expiration value and the moment when the counter's expiration value is reached (i.e., when the first count is 1), counter 110 continues to run until it reaches 4, 5, 6, 7, or 8 (when the first count is 0, until it reaches 3, 4, 5, 6, or 7), which is the low-level counting range of counter 110. Then, at the counter operation interruption time point CS, the operation of counter 110 is interrupted.

[0089] As described above, when a low-level clock request is received from the power management unit 200, the state machine 130 can compare the count set value, which is half of the counter expiration value corresponding to the frequency division value, with the count value of the counter 110. When the count value of the counter 110 has not reached the count set value, the counter 110 is kept running until the count set value is reached.

[0090] If the counter value of counter 110 reaches the count set value and the output clock is in a low-level state, state machine 130 can interrupt the operation of counter 110. The output clock generated by output clock generator 120 can be input to one or more flip-flops 300. According to an embodiment of the present invention, flip-flops 300 can be retained when the output clock is guaranteed to be in a low-level state.

[0091] According to the embodiments of the present invention described above, by ensuring that the output clock of the clock divider is in a low-level state during the hold signal transition interval, the hold operation of the flip-flop can be executed smoothly and correctly. Furthermore, during hold operation, the output clock of the clock divider can be guaranteed to be in a low-low level state, thereby allowing the output clock of the clock divider to be used as is in the hold logic. This improves the clock design freedom of the semiconductor system.

[0092] When the frequency division value changes, state machine 130 can update counter 110 using the expiration value of the second counter corresponding to the changed frequency division value, based on whether the expiration value of the first counter corresponding to the previous frequency division value has expired. When the frequency division value changes, state machine 130 can determine whether the count of the first counter has expired by comparing the expiration value of the first counter corresponding to the previous frequency division value with the count value of counter 110.

[0093] When the count value of counter 110 has not reached the first counter expiration value (the existing counter expiration value before the frequency division value is changed), state machine 130 may not update the second counter expiration value (the new counter expiration value) corresponding to the changed frequency division value, but waits, and when the count value of counter 110 reaches the first counter expiration value, it uses the second counter expiration value to update counter 110.

[0094] Figure 9 This is a conceptual diagram illustrating a computing device for performing a clock division method according to an embodiment of the present invention. An exemplary computing device 900 for performing the above-described methods and / or embodiments will be described. According to one embodiment, the computing device 900 can be implemented using hardware and / or software for user interaction. The computing device 900 may include, but is not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, etc. The structural elements of the computing device 900, their connections, and their functions are intended to be exemplary and are not intended to limit the embodiments of the present invention described and / or claimed herein.

[0095] The computing device 900 includes a processor 910, a memory 920, a storage device 930, a communication device 940, a high-speed interface 950 connected to the memory 920 and a high-speed expansion port, and a low-speed interface 960 connected to a low-speed bus and the storage device. The structural elements 910, 920, 930, 940, 950, and 960 can be interconnected using various buses and can be installed on the same mainboard or connected through other suitable methods. The processor 910 can perform basic arithmetic, logic, and input / output operations, thereby processing computer program instructions. For example, the processor 910 can process instructions stored in the memory 920, storage device 930, etc., and / or instructions running within the computing device 900, thereby displaying graphical information on an external input / output device 970, such as a display device, combined with the high-speed interface 950.

[0096] The communication device 940 can provide a structure or function that enables the input / output device 970 and the computing device 900 to communicate with each other via a network, and can also provide a structure or function that enables the input / output device 970 and / or the computing device 900 to communicate with other external devices. For example, requests or data generated by the processor of an external device according to arbitrary program code can be transmitted to the computing device 900 via the network under the control of the communication device 940. Conversely, control signals or instructions provided under the control of the processor 910 of the computing device 900 can be transmitted to other external devices via the communication device 940 and the network.

[0097] The accompanying drawings show a computing device 900 including a processor 910, a memory 920, etc., but it is not limited to these. The computing device 900 can be implemented using multiple memories, multiple processors, and / or multiple buses, etc. Furthermore, Figure 9 The diagram shows the presence of a computing device 900, but is not limited to this; multiple computing devices can interact and perform necessary tasks to execute the method.

[0098] The memory 920 can store information within the computing device 900. According to one embodiment, the memory 920 can be composed of volatile memory cells or multiple memory cells. Further or alternatively, the memory 920 can be composed of non-volatile memory cells or multiple memory cells. Furthermore, the memory 920 can be composed of other forms of computer-readable media such as a magnetic disk or optical disk. Additionally, the memory 920 can store an operating system and at least one program code and / or instructions.

[0099] Storage device 930 can be at least one high-capacity storage device for storing data for computing device 900. For example, storage device 930 can be a computer-readable medium including, or may include, semiconductor storage devices such as hard disks, magnetic discs, optical discs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory devices, CD-ROMs, and high-density optical discs (DVD-ROMs). Furthermore, computer programs can be tangibly implemented on such computer-readable media.

[0100] The high-speed interface 950 and the low-speed interface 960 can be units for interacting with the input / output device 970. For example, the input device may include a camera, keyboard, microphone, mouse, etc., with an audio sensor and / or image sensor, and the output device may include a display, speaker, haptic feedback device, etc. In other examples, the high-speed interface 950 and the low-speed interface 960 can be units for interfacing with devices that integrate input and output structures or functions, such as touchscreens.

[0101] According to one embodiment, the high-speed interface 950 can manage bandwidth-intensive tasks on the computing device 900, while the low-speed interface 960 can manage less bandwidth-intensive tasks than the high-speed interface 950; however, this functional allocation is merely illustrative. According to one embodiment, the high-speed interface 950 can be integrated into the memory 920, the input / output device 970, and a high-speed expansion port capable of accommodating various expansion cards (not shown). Furthermore, the low-speed interface 960 can be integrated into the storage device 930 and the low-speed expansion port. Further, a low-speed expansion card including various communication ports (e.g., USB, Bluetooth, IoT, wireless IoT) can be integrated into at least one input / output device 970 such as a keyboard, pointing device, or scanner, or integrated into a network device such as a router or switch via a network adapter.

[0102] The computing device 900 can be implemented in a variety of different forms. For example, the computing device 900 can be implemented as a standard server or as a group of multiple such standard servers. Further or alternatively, the computing device 900 can be implemented as part of a rack server system, or as a personal computer such as a laptop computer. In this case, the structural elements of the computing device 900 can be combined with other structural elements within any mobile device (not shown). Such a computing device 900 may include at least one other computing device, or communicate with at least one other computing device.

[0103] The input / output device 970 shown in the figure is not included in the computing device 900, but it is not limited thereto and can be configured as a single device with the computing device 900. Furthermore, Figure 9 The high-speed interface 950 and / or low-speed interface 960 and processor 910 are shown as separate components, but are not limited thereto. The high-speed interface 950 and / or low-speed interface 960 may be included in processor 910.

[0104] The methods and / or various embodiments described herein can be implemented using digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the invention can be executed by a data processing apparatus, such as at least one programmable processor and / or at least one computer device, or by a computer-readable medium and / or a computer program stored on that medium. The computer program can be written in any form of programming language, including compiled or interpreted languages, and can be distributed in any form, such as as a standalone program, module, subroutine, etc. The computer program can be distributed via a single computing device, multiple computing devices connected via the same network, and / or multiple computing devices distributed via multiple different network connections.

[0105] The methods and / or various embodiments described herein can operate based on input data or generate output data, thereby being executed by at least one processor of at least one computer program that runs processes, stores and / or manages arbitrary functions, etc. For example, the methods and / or various embodiments of the present invention can be executed by special purpose logic circuits such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and the apparatus and / or system for executing the methods and / or embodiments of the present invention can be implemented as special purpose logic circuits such as field-programmable gate arrays or application-specific integrated circuits.

[0106] At least one processor running a computer program may include at least one processor of a general-purpose or special-purpose micro processor and / or any type of digital computing device. The processor may receive instructions and / or data from read-only memory and random access memory, respectively, or may receive instructions and / or data from both read-only memory and random access memory. In this invention, the structural elements of the computing device for executing methods and / or embodiments may include at least one processor for running instructions and at least one memory for storing instructions and / or data.

[0107] According to one embodiment, the computing device can send and receive data with at least one mass storage device for storing data. For example, the computing device can receive data from and transfer data to a magnetic disc or optical disc. Computer-readable media suitable for storing instructions and / or data related to computer programs may include, but are not limited to, any form of non-volatile memory having semiconductor storage devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices. For example, computer-readable media may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.

[0108] To provide interaction with the user, a computing device may include, but is not limited to, display devices that provide or display information to the user (e.g., cathode ray tubes (CRTs), liquid crystal displays (LCDs), etc.) and pointing devices that enable the user to provide input and / or instructions to the computing device (e.g., keyboards, mice, trackballs, etc.). That is, the computing device may also include any other type of device for providing interaction with the user. For example, to interact with the user, the computing device may provide the user with any form of sensory feedback, including visual feedback, auditory feedback, and / or tactile feedback. In this regard, the user can provide input to the computing device through various gestures such as vision, voice, and movement.

[0109] In this invention, various embodiments can be implemented in a computer device including back-end structural elements (e.g., a data server), middleware structural elements (e.g., an application server), and / or front-end structural elements. In this case, the structural elements can be interconnected through any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network can consist of wired networks such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication; mobile communication networks; wireless local area networks (WLANs); mobile hotspots (Wi-Fi); Bluetooth; and wireless networks such as ZigBee, or combinations thereof. For example, the communication network may include local area networks (LANs), wide area networks (WANs), etc.

[0110] The computing device based on the exemplary embodiments described in this specification may be implemented using hardware and / or software that includes user equipment, user interface (UI) devices, user terminals, or client devices for interacting with a user. For example, the computing device may include portable computing devices such as laptop computers. Further or alternatively, the computing device may include personal digital assistants (PDAs), tablet computers, game consoles, wearable devices, Internet of Things (IoT) devices, virtual reality (VR) devices, augmented reality (AR) devices, etc., but is not limited thereto. The computing device may also include other types of devices for interacting with a user. Furthermore, the computing device may include portable communication devices (e.g., mobile phones, smartphones, wireless cellular phones, etc.) suitable for wireless communication via networks such as mobile communication networks. The computing device may use wireless communication technologies and protocols such as radio frequency (RF), microwave frequency (MWF), and / or infrared ray frequency (IRF) to communicate wirelessly with a network server.

[0111] In this invention, various embodiments, including specific structural and functional details, are exemplary embodiments. Therefore, the embodiments of this invention are not limited to the described content, but can be implemented in various different forms. Furthermore, the terminology used in this invention is used to describe some embodiments, and not to limit the embodiments. For example, unless explicitly stated in the context, singular words include plural forms.

[0112] In this invention, unless otherwise defined, all terms used in this specification, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, commonly used terms, such as those defined in dictionaries, have the same meaning as those in the same technical context.

[0113] Although this specification has described the invention in conjunction with some embodiments, it is to be understood that those skilled in the art can make various modifications and alterations without departing from the scope of the invention. Furthermore, such modifications and alterations should fall within the scope of protection of the appended claims.

[0114] This work was supported by a grant from the Ministry of Small and Medium Enterprises and Entrepreneurship funded by the Technology and Information Promotion Agency for Small and Medium Enterprises (SMEs) of Korea (TIPA). (Project No.: 1425182152, Project No.: RS-2023-00302523, Research Program Name: Entrepreneurial Growth Technology Development (R&D), Research Project Name: Low-Code-Based Low-Power Semiconductor Solutions, Implementing Agency: ITDA Semiconductor, Research Period: July 1, 2023 to June 30, 2026) Furthermore, the Government of the Republic of Korea has no property rights in any aspect of this invention concept.

Claims

1. A clock divider, characterized by comprises: a counter that counts a clock of an input clock and generates a counter output for frequency-dividing the input clock; an output clock generator that generates a clock edge from the counter output, thereby generating an output clock that is frequency-divided from the input clock; and a state machine that controls the counter so that the output clock is in a low level state at a reserved signal transition interval, in accordance with a clock low level request of a power management unit. When the clock low level request is received, the state machine performs the following steps:

2. The clock divider of claim 1, wherein, waits until a count value of the counter reaches a counter expiration value corresponding to a frequency division value; and interrupts the operation of the counter when the count value of the counter reaches the counter expiration value corresponding to the frequency division value, so that the output clock stops in a low level state. When the clock low level request is received, the state machine performs the following steps:

3. The clock divider of claim 1, wherein, determines whether the output clock output from the output clock generator is in a low level state; interrupts the operation of the counter when the output clock is in the low level state, so that the output clock stops in the low level state; and maintains the operation of the counter when the output clock is in a high level state, until the output clock is in the low level state. When the clock low level request is received, the state machine performs the following steps:

4. The clock divider of claim 1, wherein, determines whether a count value of the counter is within a low level count range that satisfies the output clock being in a low level state; interrupts the operation of the counter when the count value of the counter is within the low level count range, so that the output clock stops in the low level state; and maintains the operation of the counter when the count value of the counter does not reach the low level count range, until the low level count range is reached. When the clock low level request is received, the state machine performs the following steps:

5. The clock divider of claim 4, wherein, compares a count set value that is half of a counter expiration value corresponding to a frequency division value with a count value of the counter; maintains the operation of the counter when the count value of the counter does not reach the count set value, until the count set value is reached; and interrupts the operation of the counter when the count value of the counter reaches the count set value and the output clock is in a low level state. The output clock is input to a flip-flop, and the flip-flop is reserved when it is ensured that the output clock is in a low level state.

6. The clock frequency divider of claim 1, wherein, The state machine performs the following steps: when a frequency division value is changed, a second counter expiration value corresponding to the changed frequency division value is used to update the counter, in accordance with whether a first counter expiration value corresponding to the frequency division value before the change is expired.

7. The clock divider of claim 1, wherein, When the frequency division value is changed, the state machine performs the following steps:

8. The clock divider of claim 7, wherein, determines whether a count of a first counter expiration value corresponding to a frequency division value before a change is expired, by comparing the first counter expiration value with a count value of the counter; when the count value of the counter does not reach the first counter expiration value, a second counter expiration value corresponding to the changed frequency division value is not updated, but is waited for; and and ​ At a time when the count value of the counter reaches the first counter expiration value, the second counter expiration value is used to update the counter.

9. A semiconductor system, characterized by Comprising: The clock divider according to any one of claims 1 to 8; One or more flip-flops, in a power domain, receive an output clock outputted by the clock divider from an input clock after being divided, and operate according to the output clock; And A power management unit outputs a clock low level request to a state machine of the clock divider to reserve.

10. The semiconductor system of claim 9, wherein, When the output clock is guaranteed to be in a low level state according to the clock low level request, the power management unit outputs a reservation signal to the flip-flops.

11. A clock divider control method for controlling operation of a clock divider including a counter, an output clock generator, and a state machine, the method comprising: Comprising the steps of: Counting a clock of an input clock by the counter and generating a counter output used for dividing the input clock; Generating a clock edge from the counter output by the output clock generator, thereby generating an output clock divided from the input clock; And According to a clock low level request of a power management unit, controlling the counter by the state machine, so that the output clock is in a low level state at a reservation signal transition interval.

12. The clock divider control method of claim 11, wherein, The step of controlling the counter comprises the steps of: Waiting until the count value of the counter reaches a counter expiration value corresponding to a division value; and When the count value of the counter reaches the counter expiration value corresponding to the division value, interrupting the operation of the counter, so that the output clock stops in a low level state.

13. The clock divider control method of claim 11, wherein, The step of controlling the counter comprises the steps of: Judging whether the output clock outputted by the output clock generator is in a low level state; When the output clock is in the low level state, interrupting the operation of the counter, so that the output clock stops in the low level state; And When the output clock is in a high level state, keeping the operation of the counter until the output clock is in the low level state.

14. The clock divider control method of claim 11, wherein, The step of controlling the counter comprises the steps of: Judging whether the count value of the counter is in a low level counting range meeting the output clock being in a low level state; When the count value of the counter is in the low level counting range, interrupting the operation of the counter, so that the output clock stops in the low level state; And When the count value of the counter does not reach the low level counting range, keeping the operation of the counter until the low level counting range is reached.

15. The clock divider control method according to claim 14, wherein The step of controlling the counter comprises the steps of: Comparing a count setting value which is half of a counter expiration value corresponding to a division value with the count value of the counter; When the count value of the counter does not reach the count setting value, keeping the operation of the counter until the count setting value is reached; and When the count value of the counter reaches the count setting value and the output clock is in a low level state, interrupting the operation of the counter.

16. The clock divider control method of claim 11, wherein, The output clock is inputted to flip-flops, and when the output clock is guaranteed to be in a low level state, the flip-flops are reserved.

17. The clock divider control method of claim 11, wherein, Further comprising the step of updating the counter using a second counter expiration value corresponding to the changed frequency division value, when the state machine changes the frequency division value, depending on whether a first counter expiration value corresponding to the frequency division value before the change has expired.

18. The clock divider control method of claim 17, wherein, The updating step includes the steps of: determining whether the count of the first counter expiration value has expired by comparing the first counter expiration value corresponding to the frequency division value before the change with the count value of the counter; when the count value of the counter has not reached the first counter expiration value, not updating the second counter expiration value corresponding to the changed frequency division value, but waiting; and at the time when the count value of the counter reaches the first counter expiration value, updating the counter using the second counter expiration value.

19. The clock divider control method of claim 11, wherein, Further comprising the steps of: one or more flip-flops within a power domain operate by receiving an output clock output from the clock divider after the input clock is divided by the clock divider; the power management unit outputs the clock low level request to the state machine of the clock divider to make a reservation; and when the output clock is guaranteed to be in a low level state according to the clock low level request, the power management unit outputs a reservation signal to the flip-flops.

20. A computer-readable recording medium, characterized by A computer program for executing the clock divider control method according to any one of claims 11 to 19 is recorded.

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