Firmware management of least recently used memory for cache hint optimization

Abstract

The application is directed to memory management in an electronic device. The memory includes a plurality of super blocks and receives a plurality of access requests. The electronic device stores information of an ordered list of superblocks in a cache, and each of a first subset of superblocks has a hint value and is ordered based on the hint value. In response to the plurality of access requests, the electronic device accumulates respective cue values for a first subset of the super blocks, and dynamically determines a location of the first subset of the super blocks in the ordered list of super blocks based on the respective cue values for the first subset of the super blocks. The ordered list of superblocks is pruned to generate a pruned list of superblocks. Based on the pruned list of superblocks, the electronic device translates a second subset of superblocks from the first memory type to a second memory type.

Description

[0001] Related applications

[0002] This application is a continuation of and claims priority to U.S. Patent Application No. 18 / 207,570, filed June 8, 2023, entitled "Firmware Management of Least Recently Used Memory for CacheHint Optimization," which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to memory management, including but not limited to memory cells for managing memory systems (e.g., solid-state drives) and methods, systems, apparatuses, and non-transitory computer-readable media for enhancing memory operation efficiency at the firmware level. Background Technology

[0004] In computer systems, memory is used to store instructions and data, and the data is processed by one or more processors based on the instructions stored in the memory. Specifically, the one or more processors are coupled to non-volatile memory (e.g., hard disk drives (HDDs) or solid-state drives (SSDs)) that can store instructions and data even when the computer system is decoupled from power. The non-volatile memory contains a host-managed cache (HMC) that relies on hints sent by the host drive to select the coldest block for garbage collection. Firmware aggregates hints to access a particular memory block in the non-volatile memory until the aggregated hints reach a threshold level that causes the memory block to be classified as "hot" or "important." However, many computer systems do not provide a signaling mechanism for degrading "hot" memory blocks to "cold." A memory block storing data that is frequently accessed at a given point in time will continue to be considered "hot," even if the memory block has not been accessed for a long period and may have been degraded to "cold" by the host drive. This type of memory block can easily exhaust a limited number of logical block addresses (e.g., approximately 20GB), which should be reserved for important and frequently accessed data (also known as "hot" data). In the absence of a signal-switching mechanism to degrade memory blocks that are no longer frequently accessed, the limited memory space reserved for important data can be freed up and cleared to accommodate new important data. It would be beneficial to efficiently and effectively manage memory cells in a memory system (specifically, Least Recently Used (LRU) memory cells) to store important data that requires frequent access. Summary of the Invention

[0005] Various embodiments of this application pertain to methods, systems, apparatuses, and non-transitory computer-readable media for real-time monitoring of individual memory block activity based on incoming access requests and for correspondingly managing different types of memory blocks in a memory system (e.g., a NAND SSD). A host drive sends prompts to a host-managed cache (HMC) to access different memory cells (e.g., superblocks) in the memory system. For each individual superblock, prompt values ​​are tracked and aggregated to determine whether the corresponding superblock is currently "hot" (e.g., frequently and recently accessed). Based on the corresponding prompt values, multiple superblocks of the memory system are dynamically hierarchically classified in an ordered list of superblocks. In some embodiments, the memory system stores a limited amount of data classified as "hot," and firmware defines a constant maxLRUSize (e.g., in 4KB units) to correspondingly limit the amount of "hot" data. For example, based on the constant maxLRUSize, the ordered list of superblocks is pruned to generate a pruned list of superblocks. Superblocks on the pruned list of superblocks are maintained as or converted to a first memory type (e.g., single-level cell (SLC) memory). Furthermore, in some embodiments, superblocks outside the trimmed list of superblocks are maintained as or converted to a second memory type (e.g., quad-level cell (QLC) memory), which has a higher memory density but a slower access rate than the first memory type. In these ways, a limited amount of memory space with the first memory type is dynamically reallocated to store "hot" data that requires frequent access, especially when the memory space of the preferred memory type has been exhausted or nearly exhausted.

[0006] In one aspect, a method is implemented at an electronic device to manage a memory system comprising multiple superblocks. The method includes receiving multiple access requests to the memory system and storing information of an ordered list of superblocks in a cache. Each superblock in a first subset has a hint value and is ordered based on the hint values. The method further includes, in response to the multiple access requests, accumulating the corresponding hint values ​​of the first subset of superblocks and dynamically determining the position of the first subset of superblocks in the ordered list based on the corresponding hint values. The method further includes trimming the ordered list of superblocks to generate a trimmed list of superblocks and converting a second subset of superblocks from a first memory type to a second memory type based on the trimmed list of superblocks.

[0007] In some embodiments, dynamically determining the position of the first subset of superblocks in the ordered list of superblocks further includes: dynamically and in response to each corresponding access request, based on the prompt value of the corresponding superblock exceeding a threshold prompt value HV. TThe determination of the superblock classifies the corresponding superblock as a hot superblock, and sets the position of the corresponding superblock as the head of the ordered list of superblocks.

[0008] In some embodiments, pruning the ordered list of superblocks further includes removing one or more superblocks from the tail of the ordered list of superblocks until the superblocks in the pruned list of superblocks satisfy a predefined list requirement. Furthermore, in some embodiments, the total memory size of the superblocks in the pruned list of superblocks does not exceed a predefined hot superblock size, according to the predefined list requirement.

[0009] In some embodiments, the method further includes determining whether the memory meets a reorganization strategy (e.g., requiring a first portion of a memory system of a first memory type to be fully occupied or partially occupied by a predefined portion (e.g., 80%)). Based on the determination that the memory meets the reorganization strategy, the ordered list of superblocks is pruned, and a second subset of the superblocks is transformed.

[0010] In another aspect, some embodiments include an electronic device comprising one or more processors and a memory having instructions stored thereon, which, when executed by the one or more processors, cause the processors to perform any of the methods described above.

[0011] In another aspect, some embodiments include a non-transitory computer-readable storage medium storing one or more programs. The one or more programs contain instructions that, when executed by one or more processors, cause the processors to perform any of the methods described above.

[0012] These illustrative embodiments and implementations are mentioned not to limit or restrict this disclosure, but to provide examples to aid in understanding it. Additional embodiments are discussed in the detailed description, and further description is also provided. Attached Figure Description

[0013] To better understand the various implementations described, refer to the detailed embodiments below in conjunction with the following figures, wherein the same reference numerals refer to corresponding parts throughout the figures.

[0014] Figure 1 This is a block diagram of example system modules in a typical electronic device according to some embodiments.

[0015] Figure 2 This is a block diagram of a memory system of an example electronic device having one or more memory access queues according to some embodiments.

[0016] Figure 3 An example procedure for accessing a superblock of a memory system in response to a prompt received from a host, according to some embodiments, is shown.

[0017] Figure 4A and 4B This is a structural diagram of a superblock of a memory system associated with a threshold prompt value, according to some embodiments.

[0018] Figure 5 This is a structural diagram of an ordered list of superblocks in a memory system according to some embodiments.

[0019] Figures 6A-6C Three example orders of an ordered list of superblocks in a trimmed memory system according to some embodiments are shown.

[0020] Figure 7 This is a flowchart of an example process for dynamically managing an ordered list of superblocks in a memory system based on prompts received from the host, according to some embodiments.

[0021] Figure 8 This is a flowchart of an example process for managing the memory type of a memory system's superblocks based on an ordered list of superblocks, according to some embodiments.

[0022] Figure 9 This is a flowchart of another example memory management method implemented by an electronic device according to some embodiments.

[0023] In the various views of the accompanying drawings, the same reference numerals denote corresponding parts. Detailed Implementation

[0024] Specific embodiments will now be described in detail with reference to the accompanying drawings, examples of which are illustrated. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used without departing from the scope of the claims, and that the subject matter may be practiced without these specific details. For example, it will be apparent to those skilled in the art that the subject matter presented herein can be implemented in many types of electronic devices with digital video capabilities.

[0025] Figure 1This is a block diagram of an example system module 100 in a typical electronic device according to some embodiments. System module 100 in this electronic device includes at least a processor module 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces such as a network interface 108, and one or more communication buses 140 for interconnecting these components. In some embodiments, the I / O controller 106 allows the processor module 102 to communicate with I / O devices (e.g., a keyboard, mouse, or touchpad) via a universal serial bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each allowing the electronic device to exchange data with an external source (e.g., a server or another electronic device). In some embodiments, the communication bus 150 includes a circuitry (sometimes referred to as a chipset) that interconnects the various system components included in system module 100 and controls communication between them.

[0026] In some embodiments, memory module 104 includes high-speed random access memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), double data rate (DDR) random access memory (RAM), or other random access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state memory devices. In some embodiments, the non-volatile memory devices within memory module 104, or alternatively, memory module 104, include non-transitory computer-readable storage media. In some embodiments, system module 100 has a memory slot reserved for receiving memory module 104. Once inserted into the memory slot, memory module 104 is integrated into system module 100.

[0027] In some embodiments, system module 100 further includes one or more components selected from memory controller 110, solid-state drive (SSD) 112, hard disk drive (HDD) 114, power management integrated circuit (PMIC) 118, graphics module 120, and audio module 122. Memory controller 110 is configured to control communication between processor module 102 and memory components of the electronic device, including memory module 104. SSD 112 is configured to use integrated circuit assemblies to store data in the electronic device, and in several embodiments, they are based on NAND or NOR memory configurations. HDD 114 is a conventional data storage device used for storing and retrieving digital information based on electromechanical disks. Power connector 116 provides electrical coupling to receive external power. PMIC 118 is configured to modulate the received external power to other desired DC voltage levels, such as 5V, 3.3V, or 1.8V, as needed by various components or circuits within the electronic device, such as processor module 102. The graphics module 120 is configured to generate an output image for feeding to one or more display devices according to a desired image / video format. The audio module 122 is configured to facilitate the input and output of audio signals to and from the electronic device under the control of a computer program.

[0028] It should be noted that the communication bus 150 also includes interconnecting various system components, including components 110-122, and controlling communication between them.

[0029] Furthermore, those skilled in the art will recognize that other non-transitory computer-readable storage media can be used, as new data storage technologies have been developed for storing information in non-transitory computer-readable storage media within memory module 104, SSD 112, and / or hard disk drive 114. These new non-transitory computer-readable storage media include, but are not limited to, media made of biological materials, nanowires, carbon nanotubes, and individual molecules, although the corresponding data storage technologies are currently under development and have not yet been commercialized.

[0030] Some embodiments of this application are aimed at effectively and efficiently managing data protection and verification to reduce associated over-allocation space and virtual data operations in the memory system (e.g., SSD 112, memory module 104) of system module 100. User data and associated integrity data are stored in two disparate memory blocks of the memory system. After storing user data and integrity data, the user data is read back, and its validity is checked relative to the integrity data. Based on the verification of the user data, the corresponding integrity data is invalidated and discarded from the memory system. Conversely, based on the invalidation of the user data, the user data is corrected based on the integrity data, and subsequently, the corresponding integrity data is invalidated and discarded from the memory system. In these ways, the memory system can verify the user data before receiving any read request for the user data and discard the integrity data after verifying or correcting the user data. System module 100 does not need to reserve a large amount of dedicated memory space in SSD 112 or memory module 104 to store integrity data, nor does it need to perform additional data migration operations on integrity data when user data needs to be migrated (e.g., in internal write-back).

[0031] Figure 2 This is a block diagram of a memory system 200 of an example electronic device having one or more memory access queues according to some embodiments. The memory system 200 is coupled to a host device 220 (e.g., Figure 1 The processor module 102 is configured to store instructions and data for extended periods, such as when the electronic device is in sleep, hibernation, or off. The host device 220 is configured to access and process the instructions and data stored in the memory system 200 to run an operating system and execute user applications. The memory system 200 also includes a controller 202 and multiple memory channels 204. Each memory channel 204 contains multiple memory units. The controller 202 is configured to execute firmware-level software to bridge the multiple memory channels 204 to the host device 220. Specifically, the controller 202 is configured to communicate with the host device 220, manage a file system directory (FSD) 212 to track data locations in the memory channels 204, organize the multiple memory channels 204, and facilitate internal and external requests for access to the memory channels 204.

[0032] Each memory channel 204 includes one or more memory packages 206 (also referred to as flash chips). In one example, each memory package 206 includes eight memory dies. In another example, each memory package 206 corresponds to one memory die. Each memory package 206 includes a plurality of memory planes 208, and each memory plane 208 further includes memory blocks optionally organized into memory blocks. Figure 2Multiple memory pages 210 (not shown). Each memory page 210 contains a set of ordered memory cells, and each memory cell is identified by a corresponding physical address. In some embodiments, the memory system 200 includes multiple superblocks. Each superblock includes multiple memory blocks, and each memory block further includes multiple memory pages 210. For each superblock, the multiple memory blocks are configured to be written to and read from the memory system simultaneously via a memory input / output (I / O) interface. Optionally, each superblock groups memory cells distributed across multiple memory planes 208, multiple memory channels 204, and multiple memory chips 204. In one example, each superblock includes at least one set of memory pages, wherein each page is distributed across dissimilar memory chips 210, has the same die, plane, block, and page identifiers, and is accessed via dissimilar channels of the dissimilar memory chips 204. In another example, each superblock comprises at least one set of memory blocks, wherein each memory block is distributed across disparate memory chips 210, comprises multiple pages, has the same die, plane, and block identifier, and is accessed via disparate channels of the disparate memory chips 204. The memory system 200 stores information about the ordered list of superblocks (operation 904) in cache 232. In some embodiments, cache 232 is managed by a host driver of host device 220 and is referred to as a host-managed cache (HMC).

[0033] In some embodiments, memory system 200 includes a single-cell (SLC) memory system, with each memory cell storing a single data bit. In some embodiments, memory system 200 includes an MLC memory system, with each memory cell storing multiple data bits. In one example, each memory cell of a multi-cell (MLC) memory system stores two data bits. In another example, each memory cell of a three-cell (TLC) memory system stores three data bits. In another example, each memory cell of a four-cell (QLC) memory system stores four data bits. In yet another example, each memory cell of a five-cell (PLC) memory system stores five data bits. In some embodiments, each memory cell can store any suitable number of data bits through six or higher-level memory cells. Compared to MLC, TLC, QLC, or PLC memory systems, SLC memory systems offer higher operating speeds, higher reliability, and longer lifespans, but have lower device density and higher cost. In some embodiments, each of the SLC, MLC, TLC, QLC, PLC, or six- or higher-level memory systems includes one or more SSDs.

[0034] Each memory channel 204 is coupled to a corresponding channel controller 214, which is configured to control internal and external requests for access to memory cells in the corresponding memory channel 204. In some embodiments, each memory package 206 (e.g., each memory die) corresponds to a corresponding queue 216 of memory access requests. In some embodiments, each memory channel 204 corresponds to a corresponding queue 216 of memory access requests. Furthermore, in some embodiments, each memory channel 204 corresponds to a distinct and different queue 216 of memory access requests. In some embodiments, a subset (less than all) of the plurality of memory channels 204 corresponds to a distinct queue 216 of memory access requests. In some embodiments, all of the plurality of memory channels 204 of the memory system 200 correspond to a single queue 216 of memory access requests. Each memory access request is optionally received internally from the memory system 200 to manage the corresponding memory channel 204, or externally from a host device 220 to write or read data stored in the corresponding channel 204. Specifically, each memory access request includes one of the following: a system write request received from memory system 200 to write to the corresponding memory channel 204, a system read request received from memory system 200 to read from the corresponding memory channel 204, a host write request originating from host device 220 to write to the corresponding memory channel 204, and a host read request received from host device 220 to read from the corresponding memory channel 204.

[0035] In some embodiments, in addition to FSD 212 and channel controller 214, controller 202 also includes a local memory processor 218, a host interface controller 222, an SRAM buffer 224, and a home memory buffer (HMB) controller 226. The local memory processor 218 accesses the plurality of memory channels 204 based on the one or more memory access request queues 216. In some embodiments, the local memory processor 218 writes to and reads from the plurality of memory channels 204 on a memory block basis. Data in one or more memory blocks is written to or read from the plurality of channels together. Data in the same memory block is not written through more than one operation. Each memory block optionally corresponds to one or more memory pages 210. In one example, each memory block to be written to or read together in the plurality of memory channels 204 has a size of 16 KB (e.g., one memory page 210). In another example, each memory block to be written to or read together in the plurality of memory channels 204 has a size of 64 KB (e.g., four memory pages 210). In some embodiments, each memory page 210 has 16 KB of user data and 2 KB of metadata. Furthermore, the number of memory blocks to be accessed together and the size of each memory block can be configured for each of the system read, host read, system write, and host write operations. In other words, the number of memory blocks to be accessed together and the size of each memory block are not limited to the examples shown in this application and can have different sizes not detailed herein.

[0036] In some embodiments, the local memory processor 218 temporarily stores data to be written to or read from the memory channel 204 in the SRAM buffer 224 of the controller 202. Alternatively, in some embodiments, the local memory processor 218 is coupled to the HMB controller 226 and temporarily stores data to be written to or read from the memory channel 204 in the host memory buffer (HMB) 228 via the HMB controller 226 or the host interface controller 222. The HMB 228 is external to the controller 202 and is used by the processor module 102 ( Figure 1 The main memory used. In some embodiments, the HMB 228 is one of SRAM, DRAM, 3D XPOINT, and magnetoresistive RAM (MRAM), or other RAM devices. Additionally, in some embodiments, the memory system 200 includes an SSD coupled to the DRAM-based HMB 228. Alternatively, in some embodiments, the memory system 200 includes an SSD coupled to an HMB 228 that does not contain DRAM.

[0037] Figure 3 An example process 300 is illustrated, according to some embodiments, of accessing a superblock 302 of a memory system 200 in response to a prompt received from a host device 220. The host device 220 is coupled to a memory system 200 comprising a plurality of superblocks 302. Each superblock 302 has a plurality of memory blocks, and the memory blocks of each superblock 302 are configured to be simultaneously written to and read from the memory system via a memory I / O interface. The host device 220 is configured to send prompts to the memory system 200 to access different superblocks 302. Each prompt corresponds to a memory access request 304, which includes identification information (e.g., logical address) of one or more corresponding superblocks 302 to be accessed via the memory access request. In some embodiments, the prompts correspond to multiple memory access requests 304 (e.g., AR1, AR2, ..., AR...). M The plurality of memory access requests include identification information 306 (e.g., LA1, LA2, ..., LA1) of the corresponding one or more superblocks 302 to be accessed. M The memory system 200 includes a cache 232 that maps the identification information 306 (e.g., logical addresses) of the plurality of superblocks 302 to the plurality of superblocks 302 (e.g., SB1-SB) in the memory system 200. N The physical address of 308 (e.g., PA1, PA2, ..., PA...) M Each of the first subset 302-1 of superblocks has a hint value 310 indicating the access level of the corresponding superblock 302-1. The first subset 302-1 of superblocks is sorted in list 312 based on the hint values ​​310 of the corresponding superblocks, and cache 232 further stores information about the ordered list 312 of superblocks.

[0038] In response to the plurality of access requests 304, the memory system 200 (e.g., controller 2020) accumulates the corresponding hint values ​​310 for a first subset 302-1 of superblocks and dynamically determines the position of the first subset 302-1 of superblocks in the ordered list 312 of superblocks based on the corresponding hint values ​​310. In some cases, for example, the ordered list 312 of superblocks is pruned from the tail to generate a pruned list 314 of superblocks. Based on the pruned list 314 of superblocks, a second subset 302-2 of superblocks is selected from the set 302-4 of remaining superblocks in the ordered list 312 and converted from a first memory type (e.g., SCL) to a second memory type (e.g., QCL).

[0039] In some embodiments, a first memory type has a first memory access rate, and a second memory type has a second memory access rate that is slower than the first memory access rate. For example, the first memory type is a single-level cell (SLC), and the second memory type is a four-level cell (QLC), which has a higher storage density but a slower access rate than SLC. In some embodiments, the memory system 200 (e.g., a new SSD) is substantially empty. The first portion of the memory system 200 (e.g., Figure 8 The second part of the memory system 200 (e.g., 200A) is configured as the first memory type, while the second part of the memory system 200 (e.g., Figure 8 The second memory type (200B) differs from the first memory type and is configured as a second memory type. If there is space available in the first memory type, data is stored in the first memory type, and if the first memory type is fully occupied, data continues to be stored in the second memory type. The ordered list 312 of superblocks is pruned to identify less frequently accessed superblocks or LRU superblocks, also known as cold superblocks. A subset of the identified cold superblocks is converted from the first memory type to the second memory type. In other words, the storage space of the first memory type is dynamically, adaptively, and in real time organized based on the multiple access requests 304, and thus the storage space can be reserved to store the most frequently or recently accessed superblocks (i.e., hot superblocks).

[0040] Figure 4A and 4B It is based on some embodiments and the threshold prompt value HV T A structural diagram of a superblock 302 of the associated memory system 200. Superblock 302 includes multiple memory cells configured to be simultaneously written to and read from the memory system via a memory I / O interface, and these multiple memory cells are distributed across multiple memory planes 208, multiple memory channels 204, and multiple memory packages 206 (e.g., memory chips). In some embodiments not shown, superblock 302 stores only data corresponding to a program. In some embodiments, superblock 302 is divided into multiple portions (e.g., 402A-402F), and each portion 402 stores data for a corresponding dissimilar program, or is empty and awaiting storage. Each portion 402 has a corresponding portion size, and the sum of the corresponding portion sizes of these portions is the superblock size of superblock 302. Furthermore, in some embodiments, data corresponding to a program is stored in two superblocks 302, each superblock being completely or partially filled with the program data.

[0041] Host device 220 will send multiple access requests 304 ( Figure 3Access requests 304 are sent to memory system 200, and the plurality of access requests 304 include one or more access requests 304A to a superblock 302 comprising portions 402A-402F. In response to each corresponding access request 304A, memory system 200 accumulates a hint value 310 for the superblock 302. For example, the hint value 310 is initially equal to 0 and is increased based on the access size of one or more portions 402 of the superblock 302 accessed by each corresponding access request 304A. In some embodiments, a scaling factor (e.g., 1, 2, or 3) is equal to or greater than 1 and is applied to determine the hint value 310 based on the access size. The access size of each corresponding access request 304A is scaled by the scaling factor and added to the hint value 310. For example, the superblock size is 64 KB, and portion 402C is 4 KB. If the scaling factor is 3, then access request 304 for portion 402C will increase the hint value 310 by 12 KB. Therefore, the hint value 310A is stored in cache 232 along with the physical address of superblock 302, and is updated in response to each of the one or more access requests 304A.

[0042] In some embodiments, a threshold hint value HV is defined for superblock 302. T For example, the threshold indicator value HV T This is based on the superblock size of superblock 302, for example, equal to 80%, 150%, or 300% of the superblock size. Based on the determination that the prompt value 310 of superblock 302 exceeds a threshold prompt value, the memory system 200 classifies the corresponding superblock as a hot superblock and sets the position of superblock 302 as the head of the ordered list 312 of superblocks. In some embodiments, when the prompt value 310 reaches the threshold prompt value HV... T Previously, superblock 302 was not added to the ordered list 312. Instead, in some embodiments, a prompt value 310 is added when a threshold prompt value HV is reached. T Previously, superblock 302 was hierarchically ordered within ordered list 312 based on hint value 310. In one instance, the one or more access requests 304A all target a single portion 402C, and hint value 310 cumulatively reaches a threshold hint value HV. T In another instance, the one or more access requests 304 are for two or more dissimilar parts, and the prompt value 310 cumulatively reaches the threshold prompt value HV. T In some cases, when one or more access requests 304A are for a portion 402E that is a relatively small portion size, a larger number of access requests 304A are required to increase the prompt value 310 to the threshold prompt value HV, compared to when the one or more access requests 304A are for a portion having a relatively large size (e.g., 402C or 402F). T .

[0043] In some embodiments, for example, when portion 402F is empty and no data has been stored, superblock 302 is not yet fully filled. As data is written to each of portions 402A-402E, superblock 302 is stored in cache 232, and the hint value 310 gradually increases based on the size of the corresponding portion of the superblock, optionally scaled by a scaling factor. When the last portion (e.g., 402F) is written in response to a write request, memory system 200 determines that superblock 302 is closed after the write request and writes superblock 302 from cache 232 to the corresponding physical address 308 of memory system 200. In some cases, the hint value 310 of superblock 302 exceeds a threshold hint value HV after this write request. T The determination of this sets superblock 302 as the head of the ordered list 312 of superblocks. See below for reference. Figure 7 Further details regarding the closing of the open superblock 302.

[0044] Figure 5 This is a structural diagram of an ordered list 312 of superblocks in a memory system 200 according to some embodiments. The ordered list 312 of superblocks contains a first subset 302-1 of superblocks in the memory system 200, and each of the first subset 302-1 of superblocks has a hint value 310 and is dynamically ordered in the list 312 based on the hint value 310. Since multiple access requests 304 are received from the host device 220 and processed by the memory system 200, the hint values ​​310 of the first subset 302-1 of superblocks are accumulated and applied to dynamically determine the location of the first subset 302-1 of superblocks in the ordered list 312. The ordered list 312 is stored in a cache 232 and contains corresponding information (e.g., physical addresses) for the first subset of superblocks. The ordered list 312 does not contain superblocks 302 themselves. In some embodiments, the first subset of superblocks includes a collection of completed first superblocks stored in the memory system 200 at their corresponding physical addresses. In some embodiments, a first subset of superblocks includes at least one second superblock that is incomplete and temporarily stored in cache 232.

[0045] The ordered list 312 of superblocks is pruned to generate a pruned list 314 of superblocks. In some embodiments, the ordered list 312 of superblocks is pruned based on a determination that the memory system 200 satisfies a reorganization policy 502 (e.g., a portion of the memory system 200 having a first memory type is fully occupied or partially occupied by a predefined portion (e.g., 80%, 90%)). In some cases, the memory system 200 starts substantially empty, and a first portion of the memory system is configured to have a first memory type (e.g., SLC memory type), while the remaining portion of the memory system is configured to have a second memory type (e.g., QLC memory type). The superblock 302 of the first portion of the memory system 200 is populated before data is stored in the superblock 302 of the remaining portion of the memory system 200. In one instance, when the superblock 302 of the first portion of the memory system 200 is fully occupied, the reorganization policy 502 is satisfied, and a subset of superblocks needs to be pruned from the ordered list 312 of superblocks and converted to the second memory type. In another instance, when a superblock 302 of a first portion of a memory system of a first memory type is occupied by a predefined portion (e.g., 80%, 90%), the reorganization strategy 502 is satisfied, and a subset of the superblocks needs to be pruned from the ordered list of superblocks and converted to a second memory type.

[0046] The pruned list 314 of superblocks contains a third subset 302-3 of superblocks, and the ordered list 312 of superblocks is pruned such that the total size of the third subset of superblocks in the pruned list 314 is equal to or less than a predefined hot superblock size 504 (maxLRUSize). An example size of the predefined hot superblock size 504 is 20 GB. The pruned list 314 is shorter than the ordered list 312 and is stored in cache 232. The pruned list 314 contains information about the third subset 302-3 of superblocks (e.g., physical addresses) but does not contain the third subset 302-3 of superblocks themselves. In some embodiments, the third subset 302-3 of superblocks contains a set of completed first superblocks stored in the memory system 200 at their corresponding physical addresses. In some embodiments, the third subset 302-3 of superblocks contains at least one incomplete second superblock temporarily stored in cache 232.

[0047] In some embodiments, one or more superblocks are removed from the end of the ordered list 312 of superblocks until the superblocks in the pruned list 314 satisfy a predefined list requirement. For example, according to the predefined list requirement, the total memory size of superblocks 302-3 in the pruned list 314 does not exceed a predefined hot superblock size 504 (maxLRUSize). Reference Figure 5The ordered list of superblocks 312 contains superblocks SB3, SB1, SB5, SB8, SB4, and SB5. N And other superblocks, and pruned to remove superblock SB from ordered list 312. N and following the super block SB N Other superblocks. The trimmed list 314 of superblocks contains superblocks SB3, SB1, SB5, SB8, and SB4, and the total size of superblocks SB3, SB1, SB5, SB8, and SB4 is less than or equal to the predefined hot superblock size 504 (maxLRUSize), for example, 20 GB.

[0048] In other words, the predefined hot superblock size 504 (maxLRUSize) identifies the total size of hot superblocks that the host device 220 frequently or recently accesses. The pruned list 314 contains these hot superblocks, while the remaining superblocks 302-4 in the ordered list 312 are a list 506 of cold superblocks in the pruned list 314 that are less frequently or least recently used as hot superblocks. The remaining superblocks 302-4 are not selected or remain in the pruned list 314 corresponding to the hot superblocks. Additionally, in some embodiments, these remaining superblocks 302-4 pruned from the ordered list 312 have a first memory type (e.g., SLC) that has a faster access rate and a limited size than a second memory type. The remaining superblocks 302-4 are converted to a second memory type (e.g., QLC) such that the first memory type is partially cleared to store upcoming data, allowing the upcoming data to benefit from the faster access rate of the first memory type. It should be noted that in some embodiments, the first memory type is not limited to SLC, and may optionally be one of SLC, MLC, TLC, QLC or the like, while the second memory type is slower than the first memory type.

[0049] Figures 6A-6C Three example sequences 600, 620, and 640 are shown, respectively, of an ordered list 312 of superblocks of a trimmed memory system 200 according to some embodiments. The memory system 200 includes a series of superblocks SB1, SB2, SB3, ..., SB... N-1 and SB N The trimmed list 314 of superblocks contains a third subset (302-3) of superblocks SB3, SB1, SB5, SB8, and SB4. Based on the trimmed list 314, a second subset 302-2 of superblocks is converted from a first memory type (e.g., SLC) to a second memory type (e.g., QLC). In some embodiments, at least in part, the set 302-4 of the remaining superblocks not included in the trimmed list of superblocks 302-3 is converted. Figure 5 Select the second subset 302-2 of the superblock.

[0050] refer to Figure 6A In some embodiments, from the first superblock SB1 to the Nth superblock SB N Superblocks SB1, SB2, SB3, ..., SB N-1 and SB N The sequence is written sequentially into the memory system. Based on the pruned list 314 of the superblocks, the set 302-4 of the remaining superblocks contains SB2, Sb6, SB7, SB9-SB. N Furthermore, the second subset 302-2 of the superblocks is selected, either partially or entirely, from the set 302-4 of the remaining superblocks (SB2, Sb6, SB7, SB9-SB). N Additionally, based on the corresponding data creation time of the remaining superblock set 302-4, for example, according to a first-in-first-out scheme, the second subset 302-2 of superblocks is consecutively selected from the set 302-4 of remaining superblocks. For example, remaining superblocks SB2, Sb6, SB7, and SB9-SB... N They are sorted according to their data creation time and therefore successively selected for conversion to the second memory type based on a first-in, first-out (FIFO) scheme. Specifically, in some embodiments, the set 302-4 of remaining superblocks includes a first subset 302-4A of remaining superblocks (e.g., SB2, SB6, SB7) and a second subset 302-4B of remaining superblocks (e.g., SB9-SB8). N Each of the first subset 302-4A of the remaining superblocks (e.g., SB2, SB6, SB7) is in the second subset 302-4B of the remaining superblocks (e.g., SB9-SB). N The first subset of the remaining superblocks, 302-4A (e.g., SB2, SB6, SB7), is selected and transformed, and the second subset of the remaining superblocks, 302-4B (e.g., SB9-SB...), is... N ) Not selected or converted.

[0051] refer to Figure 6B In some embodiments, after partially selecting a second subset 302-2 of superblocks from the set 302-4 of remaining superblocks, the memory system 200 selects additional superblocks from the tail of the trimmed list 314 of superblocks from the second subset 302-2. For example, after selecting all remaining superblocks SB2, SB6, SB7, and SB9-SB... N After the transformation, additional superblocks are selected from the trimmed list 324 of superblocks in reverse order of superblocks SB4, SB8, SB5, SB1 and SB3, forming a second subset 302-2 of superblocks.

[0052] refer to Figure 6C In some embodiments, from the Nth superblock SB N Up to the first superblock SB1, superblocks SB1, SB2, SB3, ..., SB N-1 and SB N The sequence is written sequentially into the memory system in reverse order. Based on the pruned list 314 of the superblocks, the set 302-4 of the remaining superblocks contains SB2, Sb6, SB7, SB9-SB N Furthermore, the second subset 302-2 of the superblocks is selected, either partially or entirely, from the set 302-4 of the remaining superblocks (SB2, Sb6, SB7, SB9-SB). N Furthermore, in some embodiments, according to a first-in, first-out (FIFO) scheme, a second subset 302-2 of superblocks is consecutively selected from the set 302-4 of remaining superblocks based on the corresponding data creation time of the set 302-4. For example, one or more remaining superblocks SB2, SB6, SB7, and SB9-SB... N Sort in reverse order based on their data creation time, therefore the superblock SB N SB N-1 ...SB9, SB7, SB6, and SB2 are successively selected to be converted to the second memory type. Specifically, in some embodiments, the set 302-4 of remaining superblocks contains a first subset 302-4A of remaining superblocks (e.g., SB...). N SB N-1 The second subset of the remaining superblocks, 302-4B (e.g., SB7, SB6, SB2), and the first subset of the remaining superblocks, 302-4A (e.g., SB7, SB6, SB2). N SB N-1 SB7, SB6, SB2) are written before the second subset 302-4B of the remaining superblock (e.g., SB7, SB6, SB2). The first subset 302-4A of the remaining superblock (e.g., SB...) is written before SB9. N SB N-1 SB7, SB6, SB2) are selected and transformed, and the second subset of the remaining superblocks 302-4B (e.g., SB7, SB6, SB2) are not selected or transformed.

[0053] Figure 7This is a flowchart of an example process 700 for dynamically managing an ordered list 312 of superblocks of a memory system 200 based on prompts received from a host device 220, according to some embodiments. The memory system 200 includes a plurality of superblocks 302 and a controller 202 coupled to and configured to read from and write to the superblocks. The memory system 200 is coupled to the host device 220 and receives (operation 702) a plurality of prompts from (host driver of the host device 220). The firmware of the memory system 200 aggregates (operation 704) the plurality of prompts at the superblock level. Each prompt corresponds to a memory access request 304, which contains identification information (e.g., logical address) of one or more corresponding superblocks 302 to be accessed in response to the memory access request 304. The firmware of the memory system 200 determines (operation 706) the plurality of memory access requests 304 corresponding to the plurality of prompts at the superblock level. The plurality of memory access requests 304 include identification information 306 for the corresponding one or more superblocks 302 to be accessed in response to each memory access request 304. The memory system 200 includes a cache 232 (e.g., a host-managed cache (HMC)) for storing one or more of the following: address mappings, a corresponding hint value HV for each of the first subset 302-1 of superblocks, an ordered list 312 of superblocks, and a pruned list 314 of superblocks. The address mappings associate the identification information 306 (e.g., logical addresses) with the physical addresses 308 of the corresponding one or more superblocks 302 to be accessed in response to each access request 304.

[0054] For each of the plurality of memory access requests 304-i received from host device 220, memory system 200 determines (operation 708) whether the corresponding access request 304-i contains, for example, a read request or write request associated with a first superblock 302A or a second superblock 302B. In some embodiments, based on the determination that the corresponding access request 304-i contains a read request for the first superblock 302, memory system 200 identifies (operation 710) the first superblock 302A and cumulatively increments (operation 712) a first hint value 310A for the first superblock 302A. The first hint value 310A is then compared with a threshold hint value HV. T Compare (operation 714), for example, to determine whether the first prompt value 310A is greater than the threshold prompt value HT. T Determine whether the first prompt value 310A is equal to or greater than the threshold prompt value HT. T Based on the first prompt value 310A being equal to or greater than (i.e., ≥) the threshold prompt value HV. TUpon determination, the memory system 200 moves or adds (operation 716) the first superblock 302A to the head of the ordered list 312 of superblocks. Specifically, in some embodiments, the information identifying the first superblock 302A is associated with the head position of the ordered list 312 of superblocks in the cache 232, and the data written to the first superblock 302A is stored in the corresponding physical address 308 of the memory system 200. Conversely, based on the first hint value 310A being less than the threshold hint value HV... T In determining the position of the first superblock 302A in the ordered list 312, the memory system 200 may optionally not add the superblock 302A to the ordered list 312 at all, or determine the position of the first superblock 302A in the ordered list 312 based on the hint value (e.g., by arranging the first superblock 302A with the remaining superblocks of the first subset 302-1 of superblocks in descending order of their hint values).

[0055] In some embodiments, based on the determination that the corresponding access request 304-i includes a write request for the first superblock 302A, the memory system 200 further determines (operation 720) whether the write request will overwrite the first superblock 302A or invalidate the first superblock. Based on the determination that the write request will overwrite the first superblock 302A or invalidate the first superblock, the memory system 200 identifies (operation 722) the first superblock 302A and decrements (operation 724) the first hint value 310A of the first superblock 302A. The first superblock 302A is reopened (operation 725). Conversely, based on the determination that the write request will not overwrite the first superblock 302A or invalidate the first superblock, the write request will write to the first superblock 302A (which is an open superblock). The memory system 200 identifies (operation 726) the open first superblock 302A and increments (operation 728) the first hint value 310A of the open first superblock 302A. Furthermore, in some cases, based on the determination that the open first superblock 302A is filled and can be shut down, the memory system 200 shuts down (operation 730) the open first superblock 302A. Based on the determination that the first superblock 302A is shut down (operation 732), the memory system 200 sets the first prompt value 310A of the first superblock 302A against the threshold prompt value HV. T Compare (operation 734), for example, to determine whether the first prompt value 310A is greater than (>) the threshold prompt value HV. T Determine whether the first prompt value 310A is equal to or greater than (≥) the threshold prompt value HV. T .

[0056] Based on the first prompt value 310A being equal to or greater than the threshold prompt value HV TUpon determination, memory system 200 adds (operation 736) the first superblock 302A to the head of the ordered list 312 of superblocks. The information identifying superblock 302 is associated with the head position of the ordered list 312 of superblocks in cache 232, and the data written to superblock 302 is stored in the corresponding physical address 308 of memory system 200. Conversely, based on the first hint value 310A being less than the threshold hint value HV... T The memory system 200 does not add superblock 302 to the ordered list 312 at all, or determines the position of the first superblock 302A in the ordered list 312 based on the hint value (e.g., by arranging the first superblock 302A with the remaining superblocks of the first subset 302-1 of superblocks in descending order of their hint values).

[0057] In some embodiments, in response to a second memory access request 304B to access a portion of the second superblock 302B, the memory system 200 increments a second hint value 310B of the second superblock 302B based on the size of said portion of the second superblock 302B. In some cases, this increments the second hint value 310B of the second superblock 302B if the second memory access request 304B is a read request and the second hint value of the second superblock exceeds a threshold hint value HV. T Upon determination, memory system 200 moves the second superblock 302B to the head of the ordered list 312 of superblocks. Alternatively, in some cases, in response to the second memory access request 304B, based on (1) the second memory access request 304B is a write request, (2) the second superblock 302B is closed after the write request, and (3) the second hint value 310B of the second superblock 302B exceeds the threshold hint value HV. T Upon confirmation, the memory system 200 adds the second superblock 302B to the head of the ordered list 312 of superblocks.

[0058] Figure 8This is a flowchart of an example process 800 for managing the memory type of superblocks 302 of a memory system 200 according to an ordered list 312 of superblocks based on some embodiments. The memory system 200 includes multiple superblocks 302. Each superblock includes multiple memory pages 210 distributed across multiple memory planes 208, multiple memory channels 204, and multiple memory chips. For each superblock, the multiple memory pages 210 are configured to be simultaneously written to and read from the memory system 200 via a memory I / O interface. In some embodiments, the memory system 200 is configured such that a first portion 200A has a first memory type (e.g., SLC) and a second portion 200B has a second memory type (e.g., MLC, TLC, QLC). The first memory type has a first access rate that is faster than the second access rate. In some cases, both the first portion 200A and the second portion 200B of the memory system 200 have unfilled memory cells, and data is written to the first portion 200A with a higher priority than the second portion 200B. A first portion 200A of the memory system 200 is configured with a predefined first memory size. When the first portion 200A is filled, data begins to be written to the second portion 200B. In some embodiments, the first portion 200A is further associated with a predefined hot superblock size 504 (MaxLRUSize) smaller than the predefined first memory size. An example size of the predefined hot superblock size 504 is 20 GB.

[0059] In response to multiple access requests 304, a first subset 302-1 of the superblocks (e.g., having a first memory type) is sorted based on the corresponding hint value 310 to form an ordered list 312 of the superblocks. In cache 232 ( Figure 2 The memory system 200 stores (operation 802) information of the ordered list 312 of superblocks in the ordered list of superblocks. The memory system 200 determines (operation 804) whether the reorganization strategy 502 is satisfied. In some cases, the reorganization strategy 502 is satisfied based on the determination that the first portion 202A of the first memory type is fully occupied or partially occupied by a predefined portion (e.g., 80%, 90%). Based on the determination that the reorganization strategy 502 is satisfied, the memory system 200 trims (operation 806) the ordered list 312 of superblocks to generate a trimmed list 314 of superblocks. The superblocks in the trimmed list 314 of superblocks optionally have a total size equal to or less than the predefined hot superblock size 504 (MaxLRUSize). In addition, based on the trimmed list 314 of superblocks, the memory system 200 selects (operation 808) a second subset 302-2 of superblocks from at least part of the set 302-4 of remaining superblocks not included in the trimmed list 314 of superblocks. In some embodiments ( Figure 6BIn operation 810, memory system 200 continues to select a second subset 302-2 of superblocks from the tail of the trimmed list 314 of superblocks. The second subset 302-2 of superblocks is then converted from the first memory type to the second memory type (operation 812). In these ways, the set of cold superblocks outside the trimmed list 314 of superblocks is converted from the first memory type to the second memory size to clear some allocated space of the first memory type to store new data, especially when the first portion 200A of memory system 200 allocated to the first memory type is fully occupied.

[0060] Figure 9 This is a flowchart of another example memory management method 900 implemented by an electronic device according to some embodiments. Memory system 200 includes a plurality of superblocks 302. Memory system 200 receives (operation 902) a plurality of access requests to the plurality of superblocks 302, for example, from a host driver of host device 220. Memory system 200 stores (operation 904) information of an ordered list 312 of superblocks in cache 232 (e.g., a host-managed cache). Each of the first subset 302-1 of superblocks has a hint value and is ordered based on the hint value. In response to the plurality of access requests (operation 906), memory system 200 accumulates (operation 908) the corresponding hint values ​​310 of the first subset 302-1 of superblocks and dynamically determines (operation 910) the position of the first subset 302-1 of superblocks in the ordered list 312 of superblocks based on the corresponding hint values ​​310. The ordered list 312 of superblocks is pruned to generate a pruned list 314 of superblocks. Based on the pruned list 314 of superblocks, the memory system 200 converts a second subset 302-2 of superblocks from a first memory type (operation 912) to a second memory type. In some embodiments, the first memory type has a first memory access rate, and the second memory type has a second memory access rate that is slower than the first memory access rate.

[0061] In some embodiments, the memory system 200 includes an SSD having multiple NAND flash chips, and each superblock 302 includes multiple memory blocks, each memory block further including multiple memory pages. For each superblock, the multiple memory blocks are configured to be written to and read from the memory system 200 simultaneously via a memory input / output (I / O) interface. In some embodiments, each superblock 302 is a series of memory cells distributed across multiple memory planes 208, multiple memory channels 204, and multiple memory chips. It should be noted that in some embodiments, a “superblock” is broadly considered as a memory cell managed by the memory system 200 in response to a memory access request 304.

[0062] In some embodiments, dynamically and in response to each corresponding access request 304, the threshold threshold HV is exceeded based on the prompt value 310 of the corresponding superblock 302. T The position of the first subset 302-1 of the superblocks in the ordered list 312 of superblocks is determined dynamically by classifying the corresponding superblocks (operation 914) as hot superblocks and setting the position of the corresponding superblocks as the head of the ordered list 312 of superblocks.

[0063] In some embodiments, the ordered list 312 of superblocks is pruned by removing (operation 918) one or more superblocks from the tail of the ordered list 312 of superblocks until the superblocks in the pruned list 314 of superblocks satisfy a predefined list requirement. Furthermore, in some embodiments, the total memory size of the superblocks in the pruned list 314 of superblocks does not exceed (operation 920) a predefined hot superblock size (e.g., 20GB) according to the predefined list requirement.

[0064] In some embodiments, memory system 200 determines (operation 916) whether memory system 200 satisfies reorganization policy 502. Based on the determination that memory system 200 satisfies reorganization policy 502, memory system 200 prunes the ordered list 312 of superblocks and transforms a second subset 302-2 of superblocks. In some cases, memory system 200 is substantially empty, and a portion of the superblocks of memory system 200 is configured as SLC memory type, while the remaining superblocks of memory system 200 are configured as a different memory type (e.g., QLC memory type). When data begins to be stored in memory system 200, said portion of the superblocks of memory system 200 are populated. In one instance, when said portion of the superblocks of memory system 200 with SLC memory type is fully occupied, reorganization policy 502 is satisfied, and a subset of superblocks needs to be pruned from the ordered list 312 of superblocks and transformed into a different memory type. In another instance, when a portion of the superblocks of a memory system 200 with an SLC memory type is occupied by a predefined portion (e.g., 80%, 90%), a reorganization strategy 502 is satisfied, and a subset of the superblocks needs to be pruned from the ordered list 312 of the superblocks and converted to a different memory type. Therefore, in some embodiments, the first memory type is (operation 922) Single Level Cell (SLC), and the second memory type is Quad Level Cell (QLC). The second subset 302-2 of the superblocks is pruned to become outside the pruned list 314 of the superblocks, and thus converted from the SLC-based first memory type to the QLC-based second memory type.

[0065] In some embodiments, the memory system 200 selects (operation 924) a second subset 302-2 of superblocks from at least part of the set 302-4 of remaining superblocks not included in the pruned list 314 of superblocks. Furthermore, in some embodiments ( Figure 6B In this embodiment, after partially selecting a second subset 302-2 of superblocks from the remaining superblock set 302-4, the memory system 200 selects (operation 926) additional superblocks from the tail of the trimmed superblock list 314. Additionally, in some embodiments ( Figure 6A and 6C In the first-in, first-out (FIFO) scheme, based on the corresponding data creation time of the remaining superblock set 302-4, the second subset 302-2 of superblocks is continuously selected from the remaining superblock set 302-4 (operation 928). Specifically, refer to... Figure 6AAlternatively, in 6C, the set 302-4 of the remaining superblocks contains a first subset 302-4A of the remaining superblocks and a second subset 302-4B of the remaining superblocks. Each element in the first subset 302-4A of the remaining superblocks is written before the second subset 302-4B of the remaining superblocks. The first subset 302-4A of the remaining superblocks is selected and transformed, while the second subset 302-4B of the remaining superblocks is not selected and transformed.

[0066] In some embodiments, the memory system 200 obtains a first hint set from a host driver, and the first hint set includes a set of first memory access requests (e.g., access request 302-i) for the first superblock 302A. The memory system 200 accumulates a first hint value 310A for the first superblock 302A in response to each corresponding first memory access request. Specifically, the first hint value 310A decreases based on a determination that the first superblock 302A has been overwritten or invalidated in response to the corresponding first memory access request, and increases based on a determination that the corresponding first memory access request includes a read request. Upon a determination that the first superblock 302A is closed, the memory system 200 stores the first hint value 310A together with the first superblock 302A in the memory system 200.

[0067] In some embodiments ( Figure 7 In the memory system 200, in response to accessing a portion of the second superblock 302B (e.g., Figure 4A A second memory access request 304B (any one of 402A-402F in the second superblock) accumulates the corresponding hint value 310 of the first subset 302-1 of the superblock by increasing the second hint value 310B of the second superblock 302B based on the size of said portion of the second superblock 302B. Furthermore, in some embodiments, in response to the second memory access request 304B, the memory system 200 determines whether the second memory access request 304B is a read request and whether the second hint value 310B of the second superblock 302B exceeds a threshold hint value HV. T The determination (e.g., Figure 7 In operations 710-716), the second superblock 302B is moved to the head of the ordered list 312 of superblocks. Alternatively, in some embodiments, in response to the second memory access request 304B, based on (1) the second memory access request 304B is a write request, (2) the second superblock 302B is closed after the write request, and (3) the second prompt value 310B of the second superblock 302B exceeds the threshold prompt value HV. T In determining (e.g., in operations 708, 732, and 734), memory system 200 adds a second superblock 302B to the head of the ordered list 312 of superblocks.

[0068] It should be understood that Figure 7-9 The specific order of operations described herein is merely exemplary and is not intended to indicate that the described order is the only possible order in which operations can be performed. Those skilled in the art will recognize various ways to manage data stored in memory system 200 (e.g., SSD 112). Additionally, it should be noted that the above description regarding... Figure 1-6C The details of the other processes described also apply in a similar manner to the above regarding... Figure 7 , 8 Methods 700, 800, and 900 are described in section 9. For the sake of brevity, these details will not be repeated here.

[0069] The memory is also used to store instructions and data associated with methods 700, 800, and 900, and includes high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state memory devices; and optionally, includes non-volatile memory, such as one or more disk storage devices, one or more optical disk storage devices, one or more flash memory devices, or one or more other non-volatile solid-state memory devices. Optionally, the memory includes one or more storage devices located remotely from one or more processing units. The non-volatile memory within the memory, or alternatively the memory, includes a non-transitory computer-readable storage medium. In some embodiments, the memory or the non-transitory computer-readable storage medium of the memory stores programs, modules, and data structures, or subsets or supersets for implementing methods 700, 800, and 900.

[0070] The host-managed cache 232 relies on hints sent by the host driver to select the coldest blocks for garbage collection. The host software has a limited range (e.g., approximately 20GB) of logical block addresses that are classified as "hot" or "critical." Firmware aggregates hints at the superblock level, and its associated hints are also stored in NAND when the superblock is closed. The superblock's merged hints can increase if more reads exist and they are considered hot data. However, the superblock's hints can only decrease if part of the host fails (the host partially rewrites content or partially trims data). Because there is no signaling exchange for hint degradation (hot to cold), there is a risk that data that is hot at some point may have already been classified as cold by the host, but will continue to be considered hot. This consumes critical SLC space and leads to insufficient SLC for newer data. Therefore, it is necessary to limit the maximum amount of hot data to maintain consistency with host classification.

[0071] Since the host only has a limited amount of data classified as hot, the firmware should follow the same principle and limit the amount of hot data. The firmware defines a constant maxLRUSize (in 4K units) to control the maximum data LRU list. In some embodiments, a classifier is applied on the firmware side to track data in the SLC as two categories: hot data and normal data. The firmware should employ a bare-metal LRU algorithm to retail only the last 'maxLRUSize' of the host's hot data.

[0072] The firmware aggregates data hints from the host (on reads and writes) at the superblock level and classifies superblocks into hot and cold blocks using a threshold. The QLC memory is initially configured as SLC, with all hot and cold data residing in the SLC. The total amount of hot data in the SLC can exceed the maxLRUsize. The LRU size is pruned only when data needs to be moved from the SLC to the QLC (e.g., when reorganization policy 502 is satisfied). All reads from the host will have a hit associated with them, and the firmware adds this hint to the superblock to which the data is mapped (the superblock). If the superblock's hint exceeds the threshold, it is moved to the head of the LRU. All writes from the host will have a hit associated with them, and the firmware always writes this to open blocks and aggregates it. When a block is closed, if the superblock's hint exceeds the threshold, it is added to the head of the LRU. When data needs to be moved from the SLC to the QLC, the firmware LRU is pruned by removing superblocks from the tail of the LRU until the total data in the LRU is less than the maximum LRU size. Once the LRU list is pruned, source SLC blocks are picked up in FIFO order (outside the LRU). When a block is encountered, it represents the portion of the LRU that was skipped. If all blocks outside the LRU have been moved to the QLC and no more SLC blocks need to be moved, the source block is picked up from the tail of the LRU. When the total SLC space is less than maxLRUSize, the HMC is deactivated and the LRU is cleared. All future GCs are FIFO-based until more SLC memory space is reclaimed.

[0073] Each of the elements identified above may be stored in one or more of the previously mentioned memory devices and corresponds to an instruction set for performing the functions described above. The modules or programs (i.e., instruction sets) described above need not be implemented as separate software programs, procedures, modules, or data structures; therefore, various subsets of these modules may be combined or otherwise rearranged in various embodiments. In some embodiments, optionally, the memory stores a subset of the modules and data structures described above. Additionally, optionally, the memory stores additional modules and data structures not described above.

[0074] The terminology used in describing the various embodiments described herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the descriptions of the various described embodiments and the appended claims, the singular forms “a / an” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, it will be understood that although terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0075] As used herein, depending on the context, the term "if" may optionally be interpreted as meaning "when," "after," "in response to determining," "in response to detecting," or "according to determining." Similarly, depending on the context, the phrase "if determining," or "if [the stated condition or event] is optionally interpreted as meaning "after determining," "in response to determining," "after detecting [the stated condition or event]," "in response to detecting [the stated condition or event]," or "according to determining that [the stated condition or event] was detected."

[0076] For illustrative purposes, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussions are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the operating principles and practical applications, thereby enabling others skilled in the art to implement them.

[0077] In particular, any examples relating to specific figures or configurations are not intended to be exhaustive or to limit the scope of the claims to the precise instances disclosed. Many modifications and variations are possible in light of the foregoing teachings or common knowledge of those skilled in the art. The embodiments were chosen and described in order to best explain the principles of operation and practical application, thereby enabling others skilled in the art to implement them.

[0078] Although the accompanying figures show several logical stages in a specific order, stages that are not sequentially related can be reordered, and other stages can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art, and therefore the orderings and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that stages can be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. A method implemented at an electronic device, the method comprising: receiving a plurality of access requests to a memory system containing a plurality of superblocks; storing information of an ordered list of superblocks in a cache, wherein each of a first subset of superblocks has a hint value and is ordered based on the hint value; in response to the plurality of access requests: accumulating respective hint values of the first subset of superblocks; and determining, dynamically, positions of the first subset of superblocks in the ordered list of superblocks based on the respective hint values of the first subset of superblocks; and pruning the ordered list of superblocks to generate a pruned list of superblocks; and converting a second subset of superblocks from a first memory type to a second memory type based on the pruned list of superblocks.

2. The method of claim 1, the dynamically determining the positions of the first subset of superblocks in the ordered list of superblocks further comprising, dynamically and in response to each respective access request: in accordance with a determination that the hint value of a respective superblock exceeds a threshold hint value, classifying the respective superblock as a hot superblock and setting the position of the respective superblock as a head of the ordered list of superblocks.

3. The method of claim 1 or 2, the pruning the ordered list of superblocks further comprising: removing one or more superblocks from a tail of the ordered list of superblocks until superblocks of the pruned list of superblocks satisfy a predefined list requirement.

4. The method of claim 3, wherein in accordance with the predefined list requirement, a total memory size of the superblocks in the pruned list of superblocks does not exceed a predefined hot superblock size.

5. The method of any of claims 1-4, further comprising: determining whether the memory system satisfies a reorganization policy, wherein in accordance with a determination that the memory system satisfies the reorganization policy, pruning the ordered list of superblocks and converting the second subset of superblocks.

6. The method of any of claims 1-5, wherein the first memory type has a first memory access rate and the second memory type has a second memory access rate that is slower than the first memory access rate.

7. The method of any of claims 1-6, wherein the first memory type is single level cell (SLC) and the second memory type is quad level cell (QLC).

8. The method of any of claims 1-7, further comprising: selecting the second subset of superblocks at least in part from a set of remaining superblocks that are not included in the pruned list of superblocks.

9. The method of claim 8, further comprising: after selecting the second subset of superblocks in part from the set of remaining superblocks, selecting additional superblocks of the second subset of superblocks from a tail of the pruned list of superblocks from the pruned list of superblocks. ​ 10. The method of claim 8 or 9, wherein the second subset of superblocks is selected from the set of remaining superblocks consecutively based on respective data creation times of the set of remaining superblocks according to a first-in-first-out scheme.

11. The method of any one of claims 8-10, wherein: the set of remaining superblocks includes a first subset of remaining superblocks and a second subset of remaining superblocks; each of the first subset of remaining superblocks is written before the second subset of remaining superblocks; and the first subset of remaining superblocks is selected and converted, and the second subset of remaining superblocks is not selected or converted.

12. The method of any one of claims 1-11, further comprising: obtaining a first set of hints from a host driver, the first set of hints including a set of first memory access requests to a first superblock; accumulating a first hint value for the first superblock in response to each respective first memory access request, including: decreasing the first hint value according to a determination that the first superblock is overwritten or invalidated in response to the respective first memory access request; and increasing the first hint value according to a determination that the respective first memory access request includes a read request; and storing the first hint value in the memory system with the first superblock according to a determination that the first superblock is closed.

13. The method of any one of claims 1-12, accumulating respective hint values for the first subset of superblocks further comprising: increasing a second hint value for a second superblock based on a size of a portion of the second superblock accessed in response to a second memory access request.

14. The method of claim 13, accumulating respective hint values for the first subset of superblocks further comprising, in response to the second memory access request: moving the second superblock to a head of an ordered list of superblocks according to a determination that the second memory access request is a read request and the second hint value for the second superblock exceeds a threshold hint value.

15. The method of claim 13 or 14, accumulating respective hint values for the first subset of superblocks further comprising, in response to the second memory access request: adding the second superblock to a head of an ordered list of superblocks according to a determination that (1) the second memory access request is a write request, (2) the second superblock is closed after the write request, and (3) the second hint value for the second superblock exceeds a threshold hint value.

16. The method of any one of claims 1-15, wherein: the memory system includes an SSD having a plurality of NAND flash chips; each superblock includes a plurality of memory blocks, each memory block further including a plurality of memory pages; and for each superblock, the plurality of memory blocks are configured to be written to and read from the memory system simultaneously via a memory input / output interface.

17. An electronic device comprising: one or more processors; and a memory system including a plurality of superblocks and storing one or more programs configured for execution by the one or more processors, the one or more programs including instructions for performing the method of any of claims 1-16.

18. A non-transitory computer-readable medium storing one or more programs to be executed by one or more processors for managing data in a memory system including a plurality of superblocks, the one or more programs including instructions for performing the method of any of claims 1-16.

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