Heterojunction solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a heterojunction solar cell, a preparation method thereof and a photovoltaic module, and relates to the field of heterojunction solar cells. The heterojunction solar cell comprises a substrate; a front passivation layer and a front anti-reflection layer are sequentially arranged on the front surface of the substrate from inside to outside; the back surface of the substrate is provided with an N-type contact region and a P-type contact region; the N-type contact area is provided with a first passivation layer, a first conductive layer, a first mask layer, a seed layer, a copper gate electrode, insulation paste and a solder strip from inside to outside in sequence. The P-type contact area is provided with a second passivation layer, a second conductive layer, a third conductive layer, a seed layer, a copper gate electrode and a solder strip from inside to outside in sequence. Solder paste is arranged on the side wall of the copper gate electrode. The copper electroplating technology can accurately control the height and width, and is of a main-grid-free structure, so that the material cost is reduced, and the double-sided rate of the solar cell is improved; the conductivity of copper is superior to that of silver paste, so that the short-circuit current, the filling factor and the efficiency of the solar cell structure can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of heterojunction solar cells, and particularly relates to a heterojunction solar cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0002] Silicon-based heterojunction solar cells have been widely concerned due to their high efficiency, low attenuation and other excellent performances. Many preparation methods of silicon-based heterojunction solar cells have been disclosed in the prior art. However, the preparation methods in the prior art have some defects, for example, the production cost is high, and the double-sided rate of the solar cell is low.

[0003] The paper entitled "Improvement of the conversion efficiency of polycrystalline silicon thin film solar cell" by M Taguchi et al. performs double-sided etching on a silicon wafer at one time, then uses PECVD and PVD to deposit intrinsic amorphous silicon film, doped nanocrystalline silicon film and TCO film on the two sides respectively, and finally uses screen printing technology to print silver grid lines on the two sides respectively to obtain a conventional heterojunction solar cell HJT. However, the prior art has the following disadvantages: (1) The HJT solar cell uses amorphous silicon passivation. Although amorphous silicon has excellent passivation performance, its parasitic absorption is serious, resulting in low short-circuit current; (2) The HJT uses screen printing technology to prepare electrodes. The accuracy of this method is difficult to control, and it is not easy to make narrow grid lines, which results in high shading rate of the cell surface and low short-circuit current; (3) The printing paste consumes a large amount of precious metal silver, which greatly increases the production cost.

[0004] Chinese patent CN113972302B relates to a TOPCon cell, a preparation method thereof and an electrical equipment. A silicon wafer is formed with a pyramid suede by double-sided one-time texturing, a P+ layer is formed on the front surface of the silicon wafer by boron diffusion, and a PN junction is formed by the P+ layer and N-type crystalline silicon. The back surface is etched to remove the boron diffusion layer on the back surface while retaining the boron-silicon glass layer BSG on the front surface. Then, a tunneling layer and a polycrystalline silicon (Poly) passivation layer are deposited on the back surface of the cell using LPCVD. Next, the back surface Poly is doped with phosphorus to form an NN+ heterostructure with crystalline silicon. The front surface is etched to remove the poly silicon and BSG layer on the front surface. An aluminum oxide film is deposited on the front surface using ALD to passivate the boron diffusion surface. Silicon nitride is deposited on both surfaces of the cell using PECVD as an anti-reflection layer and a passivation layer of the cell. Finally, grid lines are printed on both surfaces using high-temperature sintering screen printing technology to obtain a conventional tunneling oxygen passivation contact heterojunction solar cell TOPCon. However, the prior art has the following disadvantages: (1) The Topcon solar cell process is complex and difficult, mainly including high boron diffusion difficulty, strict quality control of tunneling oxide layer (SiO2), and complex polycrystalline silicon deposition process; (2) TOPCon also uses screen printing technology to prepare electrodes, which is difficult to control in precision, and it is not easy to make narrow grid lines, which results in high shading rate of the cell surface, leading to low short-circuit current; (3) The consumption of precious metal silver in the printing paste is huge, greatly increasing the production cost; (4) The efficiency improvement is facing a bottleneck, and the space for future efficiency improvement is limited, and the complexity of the perovskite stack is high.

[0005] Japanese patent JP2009520369A5 uses photolithography or laser technology to transfer the front and back surfaces of the solar cell involved in the above prior art to the back surface to form a hybrid back contact heterojunction solar cell HBC or a tunneling oxide layer back contact solar cell TBC through a series of special patterns and process design. However, this prior art has the following disadvantages: (1) The printing precision of the BC cell back surface is high, and the silver paste consumption is large, which is 2-3 times that of HJT / TOPCon solar cells; (2) Because the precision of the screen printing technology is not easy to control, the BC cell back surface grid line shading area is large, resulting in a very low double-sided rate of the solar cell (60%-80%); (3) The front surface of the HBC solar cell is composed of intrinsic amorphous silicon and silicon nitride, which has poor reliability, and the cell efficiency is easily attenuated under long-term UV irradiation. SUMMARY

[0006] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a heterojunction solar cell and a preparation method of a photovoltaic module, in particular to a copper back contact silicon heterojunction solar cell without main grid and a preparation method thereof and a photovoltaic module.

[0007] The application provides a preparation method of a main-grid-free copper back contact heterojunction solar cell and a photovoltaic module, aiming to prepare fine grid lines on the back of a hybrid back contact heterojunction solar cell by using a copper electroplating technology, form a main-grid-free structure, and then install the module by means of dispensing, welding, laminating and frame wiring; the cell and the module can precisely control the height and width by the copper electroplating technology, are of the main-grid-free structure, reduce material cost and improve the bifaciality of the solar cell (from 60% to 80% to more than 90%); the conductivity of copper is better than that of silver paste, and therefore the short-circuit current, the fill factor and the efficiency of the solar cell structure can be improved.

[0008] The technical solution of the application is as follows: In a first aspect, the application provides a heterojunction solar cell, comprising a substrate; The front surface of the substrate is sequentially provided with a front surface passivation layer and a front surface anti-reflection layer from inside to outside; The back surface of the substrate has an N-type contact area and a P-type contact area; The N-type contact area is sequentially provided with a first passivation layer, a first conductive layer, a first mask layer, a seed layer, a copper grid electrode, insulating glue and a solder strip from inside to outside; The P-type contact area is sequentially provided with a second passivation layer, a second conductive layer, a third conductive layer, a seed layer, a copper grid electrode and a solder strip, and the sidewall of the copper grid electrode is provided with solder paste.

[0009] Optionally, the substrate is a silicon wafer; the front surface passivation layer is an Al2O3 film with a thickness of 4nm to 12nm; and the front surface anti-reflection layer is a SiN film with a thickness of 60nm to 120nm.

[0010] Optionally, the first passivation layer is a tunneling silicon oxide SiO2 with a thickness of 1nm to 3nm; the first conductive layer is an N-type polysilicon layer; the first mask layer is a silicon nitride mask layer; and the seed layer is a copper seed layer with a thickness of 30nm to 120nm.

[0011] Optionally, the second passivation layer is an intrinsic amorphous silicon passivation layer with a thickness of 5nm to 15nm; the second conductive layer is P-type amorphous silicon with a thickness of 5nm to 50nm; and the third conductive layer is a transparent conductive oxide layer TCO with a thickness of 40nm to 100nm.

[0012] In a second aspect, the application provides a preparation method of the main-grid-free copper back contact silicon-based heterojunction solar cell, comprising the following steps: S1, polishing and cleaning the substrate; S2, preparation of the first passivation layer: using low-pressure chemical vapor deposition (LPCVD) to deposit SiO2 on the front and back surfaces of the substrate to form a tunneling structure; S3, Preparation of the first conductive layer: Forming an N-Poly layer on the first passivation layer; S4, Removing the phosphosilicate glass layer PSG; S5, Preparation of the N region mask layer: Depositing a layer of silicon nitride SiN thin film on the back of the cell as the N region mask layer using plasma chemical vapor deposition PECVD; S6, Patterning 1: Using laser to open the SiN mask layer, N-Poly and SiO2 layer of the P region.

[0013] S7, Texturing the P region on the front and back of the cell; S8, Preparation of the front passivation layer and the front anti-reflective layer: Depositing an Al2O3 thin film on the front of the cell using atomic layer deposition ALD to passivate the silicon interface, and then forming a SiN thin film on the front using PECVD as an anti-reflective layer; S9, Preparation of the back P region film layer: Depositing intrinsic amorphous silicon on the back of the silicon wafer using PECVD to passivate the P region, and then depositing a layer of P-type amorphous silicon; S10, Laser crystallization: Using laser to scan the P region to induce crystallization of the amorphous silicon in the P region, enhancing the conductivity of the P region film layer; S11, Patterning 2: Using laser to open the P-type amorphous silicon layer, intrinsic amorphous silicon layer and SiN mask layer on the surface of the N region; S12, Preparation of the transparent conductive film layer and the electroplating seed layer: Sputtering a TCO thin film and a copper seed layer on the back of the cell using PVD.

[0014] S13, Patterning 3: Using exposure process, going through ink printing, exposure and development steps to mask other positions of the N region and P region on the back of the cell; S14, Copper grid line electroplating: Using vertical continuous electroplating to electroplate copper grid lines in the grid line groove; S15, Removing the ink mask layer; S16, Removing the back copper seed layer; S17, Patterning 4: Using laser to open the TCO film layer between the N region and the P region on the back of the cell to form an isolation region to prevent NP conduction and leakage; S18, High-precision dispensing; S19, Laminating and welding; S20, Installing the frame and the junction box, and obtaining the main grid-free copper back contact heterojunction solar cell after installation.

[0015] Optionally, in S2, the thickness of SiO2 is 1-3 nm; In S3, the method for forming the first conductive layer includes: introducing silane SiH4 in LPCVD, raising the temperature to 500 - 800 °C, and depositing intrinsic polysilicon with a thickness of 80 - 150 nm on the front and back sides of the substrate; placing the cell in a diffusion furnace, setting the temperature to 800 - 900 °C, using nitrogen as the carrier gas to carry phosphorus oxychloride POCl3 into the tube, and through the reaction, P atoms diffuse into the i-Poly layer to obtain the N-Poly layer; In S4, the method for removing the phosphosilicate glass layer PSG includes: immersing the silicon wafer in an HF solution, and through the reaction, removing the PSG layer on the surface of N-Poly; In S7, the method for texturing the P regions on the front and back sides of the cell includes: first, placing the silicon wafer in a KOH solution with a concentration of 10% - 30%, removing the laser damage on the back P region and the N-Poly and SiO2 layers on the front side of the silicon wafer, second, performing RCA cleaning on the silicon wafer to remove surface oil stains and impurities, and finally, placing the silicon wafer in a mixed solution of KOH with a concentration of 1% - 10% and isopropyl alcohol with a concentration of 2% - 5% for 800 - 1200 s to form a textured surface structure on the P regions on the front and back sides of the cell.

[0016] Optionally, in S8, the thickness of the Al2O3 thin film is 4 nm - 12 nm, and the thickness of the SiN thin film is 60 nm - 120 nm; In S9, the thickness of the intrinsic amorphous silicon passivating the P region is 5 nm - 15 nm, and the thickness of the P-type amorphous silicon is 5 nm - 50 nm; In S12, the thickness of the TCO thin film is 40 nm - 100 nm, and the thickness of the copper seed layer is 30 nm - 120 nm; Optionally, in S14, the gate line width of the N-type contact region is 10 μm - 150 μm, and the height is 5 μm - 50 μm; the width of the P-type contact region is 20 μm - 300 μm, and the height is 5 μm - 50 μm.

[0017] In S15, the method for removing the ink mask layer includes: covering a water film on the front side of the cell as a protective layer, using a chain etcher, placing the back side of the cell downwards, immersing the back side of the cell in a KOH solution for 30 s - 200 s to remove the ink mask layer; In S16, the method for removing the back copper seed layer includes: covering a water film on the front side of the cell as a protective layer, using a chain etcher, placing the back side of the cell downwards, covering the back side with a mixed solution of dilute sulfuric acid and dilute nitric acid for 30 s - 100 s to remove the seed layer other than the copper grid lines on the back side of the cell, and then cleaning it with ultrapure water and drying it.

[0018] Optionally, in S18, the high-precision dispensing method includes: first, pre-treating the battery cells by using UV ozone treatment to remove surface oxides from the grid lines on the back of the battery; then, aligning them by precisely aligning the fine grid positions using a vision system and arranging the battery cells in a series / parallel layout; then, using inkjet printing to apply epoxy resin insulating adhesive to the fine grids on the back of the battery, with the dispensing positions requiring the grid lines in the N and P regions to be staggered to ensure that the N and P regions do not short-circuit. In S19, the lamination welding method includes: applying low-temperature solder paste to the location where the solder strip and the battery need to be interconnected using stencil printing; then using a CCD positioning vision system to arrange the battery cells to ensure precise alignment of the grid and the interconnect solder strip; then pre-pressing and fixing, followed by lamination welding, wherein the lamination welding temperature is 120℃~180℃, the pressure is 0.5~1.2Mpa, the time is 10~30min, the vacuum degree is less than 1kpa, and the curing of the adhesive film, the melting of the solder paste and the curing of the insulating adhesive, and the bonding of the battery cell and the interconnect material are completed simultaneously.

[0019] Thirdly, the present invention provides a photovoltaic module, including the aforementioned heterojunction solar cell.

[0020] This invention has at least one of the following beneficial effects: The technical solution of this invention adopts a gridless structure, which can improve the bifaciality of the back-contact solar cells, thereby increasing the power generation of the module and increasing the system revenue. Because of the increased bifaciality, the back-contact cells involved in this solution can be adapted to bifacial modules. Bifacial modules typically adopt a double-glass structure (glass-cell-glass), which has better weather resistance and anti-PID (potential-induced degradation) performance compared to traditional single-glass modules, and extends the module life. The back heat dissipation is better, which can reduce the operating temperature and reduce the efficiency loss caused by high temperature.

[0021] In addition, the technical solution of this invention adopts copper electroplating technology, which greatly improves the flexibility of battery electrode preparation. The height and width of the electrode can be adjusted according to different needs. The use of copper greatly reduces the raw material cost. Moreover, the conductivity of metallic copper is better than that of low-temperature silver paste, which can reduce the contact resistance and series resistance between the grid line and the TCO, thereby improving the battery FF and efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a heterojunction solar cell without a main grid copper back contact in an embodiment of the present invention.

[0023] Figure 2 This is a process flow diagram of a heterojunction solar cell without a main grid copper back contact in an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of high-precision dispensing for a heterojunction solar cell without a main grid copper back contact, as shown in an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the welding of a heterojunction solar cell with copper back contact without a main grid.

[0026] The attached figures are labeled as follows: 1-Substrate (N-type silicon wafer); 2-First passivation layer (N-region tunneling silicon oxide SiO2); 3-First conductive layer (N-region N-type polycrystalline silicon layer N-Poly Si); 4-First mask layer (Silicon nitride SiN mask layer); 5-Front-side passivation layer (Front-side aluminum oxide Al2O3); 6-Front-side antireflection layer (Front-side silicon nitride SiN); 7-Second passivation layer (P-region intrinsic amorphous silicon i a-Si:H); 8-Second conductive layer (P-region P-type amorphous silicon p a-Si:H); 9-Third conductive layer (Transparent conductive oxide layer TCO); 10-Copper seed layer; 11-Copper gate electrode; 12-Insulating adhesive (epoxy resin); 13-Low-temperature solder paste; 14-Solder ribbon. Detailed Implementation

[0027] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0028] The following are the product solution process steps of the non-busbar copper back contact heterojunction solar cell involved in this invention, such as... Figures 2-4 As shown; Step 1: Cleaning and silicon wafer polishing. First, use KOH solution to polish the silicon wafer, and then use conventional cleaning process (RCA) to clean away impurities, oil, metal particles and oxide layer on the surface of the silicon wafer. Step 2: Preparation of tunneling oxide layer SiO2. Low-pressure chemical vapor deposition (LPCVD) is used to deposit 1-3 nm SiO2 on the front and back sides of the silicon wafer to form a tunneling structure, which helps selective carrier transport and passivates the silicon interface.

[0029] Step 3: Preparation of N-type polycrystalline silicon layer N-Poly. First, silane SiH4 is introduced into LPCVD and the temperature is raised to 500~800℃ to deposit intrinsic polycrystalline silicon (i-Poly) 80~150nm on the front and back sides of the silicon wafer. Next, the solar cell is placed in a diffusion furnace and the temperature is set to 800~900℃. Nitrogen gas N2 is used as a carrier gas to carry phosphorus oxychloride POCl3 into the tube. After reaction, P atoms diffuse into the i-Poly layer to obtain the N-Poly layer.

[0030] Step 4: Remove the PSG layer from the N-Poly surface. Immerse the silicon wafer in an HF solution and react to remove the PSG layer from the N-Poly surface.

[0031] Step 5: Preparation of N-region mask layer. A silicon nitride (SiN) thin film is deposited on the back of the cell as an N-region mask layer using plasma chemical vapor deposition (PECVD).

[0032] Step 6: Patterning 1, using a laser to etch the SiN mask layer, N-Poly and SiO2 layer in the P region.

[0033] Step 7: Texturing the P-area on the front and back of the battery. First, place the silicon wafer in a 10%~30% KOH solution to remove laser damage to the P-area on the back and the N-Poly and SiO2 layers on the front of the silicon wafer. Next, perform RCA cleaning on the silicon wafer to remove surface oil and impurities. Finally, place the silicon wafer in a mixed solution of 1%~10% KOH and 2%~5% isopropanol and react for 800~1200 seconds to form a textured surface structure on the P-area on the front and back of the battery.

[0034] Step 8: Preparation of front passivation layer and antireflection layer. Atomic layer deposition (ALD) is used to deposit a 4-12 nm Al2O3 thin film on the front of the cell to passivate the silicon interface. Then, PECVD is used to form a 60-120 nm SiN thin film on the front as an antireflection layer.

[0035] Step 9: Preparation of the P-region film on the back side. Using PECVD, first deposit a 5-15 nm intrinsic amorphous silicon passivation P-region on the back side of the silicon wafer, and then deposit a 5-50 nm P-type amorphous silicon layer to collect holes.

[0036] Step 10: Laser crystallization. Use a laser to scan the P-region to induce crystallization of the amorphous silicon in the P-region, thereby enhancing the conductivity of the P-region film.

[0037] Step 11: Patterning 2, using a laser to etch the P-type amorphous silicon layer, intrinsic amorphous silicon layer, and SiN mask layer on the surface of the N-region.

[0038] Step 12: Preparation of transparent conductive film and electroplating seed layer. A 40-100 nm TCO thin film and a 30-120 nm copper seed layer are sputtered onto the back of the battery using PVD.

[0039] Step 13: Patterning 3. Using an exposure process, after ink printing, exposure and development steps, a mask is applied to other locations in the N and P regions on the back of the battery.

[0040] Step 14: Copper grid line electroplating. Copper grid lines are electroplated in the grid line trench using a vertical continuous electroplating method. The grid line width of the N area on the back side is 10um-150um, and the height is 5-50um; the width of the P area on the back side is 20um-300um, and the height is 5-50um. Step 15: Remove the ink mask layer. Cover the front side of the battery with a water film as a protective layer. Using a chain etching machine, place the battery with the back side down and immerse the back side of the battery in a KOH solution for 30s-200s to remove the ink mask layer.

[0041] Step 16: Remove the copper seed layer on the back side. Cover the front side of the battery with a water film as a protective layer. Using a chain etching machine, place the battery with the back side facing down and cover the back side with a mixed solution of dilute sulfuric acid and dilute nitric acid for 30s-100s to remove the seed layer outside the copper grid lines on the back side of the battery. Then clean it with ultrapure water and dry it.

[0042] Step 17: Graphicalization 4. Use a laser to etch the TCO film layer between the N and P regions on the back of the battery to form an isolation area to prevent NP conduction and leakage.

[0043] Step 18: High-precision dispensing (e.g.) Figure 3 As shown, the cells are first pre-treated by using UV ozone treatment to remove surface oxides from the grid lines on the back of the cells. Then, alignment is performed by using a vision system (CCD) to precisely align the fine grid positions and arrange the cells in a series / parallel layout. Next, epoxy resin insulating adhesive is applied to the fine grids on the back of the cells using inkjet printing. The adhesive application points need to be staggered between the N and P grid lines to ensure that the N and P areas do not short-circuit.

[0044] Step 19: Lamination welding (e.g.) Figure 4 As shown in the figure, a low-temperature solder paste is applied to the location where the solder strip and the battery need to be interconnected using a stencil printing method. Then, a CCD positioning vision system is used to arrange the battery cells to ensure that the grid and the interconnect solder strip are precisely aligned. Then, pre-pressing and fixing are performed, followed by lamination welding. The lamination welding temperature is 120℃~180℃, the pressure is 0.5~1.2Mpa, the time is 10~30min, and the vacuum degree is less than 1kpa. The curing of the adhesive film, the melting of the solder paste and the curing of the insulating adhesive, and the bonding of the battery cell and the interconnect material are completed simultaneously.

[0045] Step 20: Install the frame and junction box. After installation, you will get a gridless copper back contact heterojunction solar cell and photovoltaic module.

[0046] The present invention will be further described in detail below with reference to specific embodiments, but the present invention is not limited to the following specific embodiments.

[0047] Example 1 like Figure 1 As shown, this embodiment provides a structure for a gridless copper back contact silicon-based heterojunction solar cell, comprising: Substrate 1; In this embodiment, substrate 1 is an N-type silicon wafer.

[0048] The front side of the substrate 1 is provided with a front passivation layer 5 and a front antireflection layer 6 from the inside to the outside. In this embodiment, the front passivation layer 5 is an Al2O3 thin film with a thickness of 4nm; the front antireflection layer 6 is a silicon nitride (SiN) thin film with a thickness of 60nm.

[0049] The back surface of the substrate 1 has an N-type contact area and a P-type contact area; The N-type contact area is provided with a first passivation layer 2, a first conductive layer 3, a first mask layer 4, a seed layer 10, a copper gate electrode 11, an insulating adhesive 12, and a solder ribbon 14 from the inside to the outside. Specifically, the top of the copper gate electrode 11 is in contact with the seed layer 10, the bottom of the copper gate electrode 11 and the side walls on both sides are provided with insulating adhesive 12, and the solder ribbon 14 is provided at the bottom of the insulating adhesive 12.

[0050] In this embodiment, the first passivation layer 2 is tunneling silicon oxide (SiO2) with a thickness of 1 nm; the first conductive layer 3 is an N-type polycrystalline silicon layer; the first mask layer 4 is a silicon nitride (SiN) mask layer; the seed layer 10 is a copper seed layer with a thickness of 30 nm; and the insulating adhesive 12 is epoxy resin.

[0051] The P-type contact area is provided with a second passivation layer 7, a second conductive layer 8, a third conductive layer 9, a seed layer 10, a copper gate electrode 11 and a solder ribbon 14 in sequence from the inside to the outside. Solder paste 13 is provided on the sidewalls on both sides of the copper gate electrode 11.

[0052] In this embodiment, the second passivation layer 7 is an intrinsic amorphous silicon passivation layer with a thickness of 5 nm; the second conductive layer 8 is a P-type amorphous silicon with a thickness of 5 nm; and the third conductive layer 9 is a transparent conductive oxide (TCO) layer with a thickness of 40 nm.

[0053] Example 2 like Figures 2-4 As shown, this embodiment provides a method for fabricating a gridless copper back contact silicon-based heterojunction solar cell, including the following steps: Step 1: Cleaning and silicon wafer polishing. First, use KOH solution to polish the substrate 1 (N-type silicon wafer). Then, use a conventional cleaning process (RCA) to clean away impurities, oil, metal particles and oxide layers on the surface of the silicon wafer.

[0054] Step 2: Preparation of tunneling oxide layer (first passivation layer 2, N-region tunneling silicon oxide SiO2). Low-pressure chemical vapor deposition (LPCVD) is used to deposit 2 nm SiO2 on the front and back sides of the silicon wafer to form a tunneling structure, which helps selective carrier transport and passivates the silicon interface.

[0055] Step 3: Preparation of N-type polycrystalline silicon layer N-Poly (first conductive layer 3, N-region N-type polycrystalline silicon layer N-Poly Si). First, silane SiH4 is introduced into LPCVD and the temperature is raised to 650℃ to deposit 100nm of intrinsic polycrystalline silicon (i-Poly) on the front and back sides of the silicon wafer. Next, the cell is placed in a diffusion furnace and the temperature is set to 800℃. Nitrogen gas N2 is used as a carrier gas to carry phosphorus oxychloride POCl3 into the tube. After reaction, P atoms diffuse into the i-Poly layer to obtain the N-Poly layer.

[0056] Step 4: Remove the PSG layer. Immerse the silicon wafer in an HF solution and react to remove the PSG layer on the N-Poly surface.

[0057] Step 5: Preparation of N-region mask layer (first mask layer 4, silicon nitride SiN mask layer): A silicon nitride SiN thin film is deposited on the back of the cell using PECVD as the N-region mask layer.

[0058] Step 6: Patterning 1, using a laser to etch the SiN mask layer, N-Poly and SiO2 layer in the P region.

[0059] Step 7: Texturing the front and back P-areas of the battery. First, place the silicon wafer in a 15% KOH solution to remove laser damage to the back P-area and the N-Poly and SiO2 layers on the front of the silicon wafer. Next, perform RCA cleaning on the silicon wafer to remove surface oil and impurities. Finally, place the silicon wafer in a mixed solution of 3% KOH and 4% isopropanol and react for 1000 seconds to form a textured surface structure on the front and back P-areas of the battery.

[0060] Step 8: Preparation of front passivation layer 5 (front alumina Al2O3) and front antireflection layer 6 (front silicon nitride SiN). A 6 nm Al2O3 thin film is deposited on the front of the cell using atomic layer deposition (ALD) to passivate the silicon interface. Then, an 80 nm SiN thin film is formed on the front as an antireflection layer using PECVD.

[0061] Step 9: Preparation of the P-region film on the back side. Using PECVD, first deposit an 8 nm intrinsic amorphous silicon passivation P-region (second passivation layer 7, intrinsic amorphous silicon i a-Si:H in the P-region) on the back side of the silicon wafer, and then deposit a 30 nm P-type amorphous silicon layer (second conductive layer 8, P-type amorphous silicon p a-Si:H in the P-region) to collect holes.

[0062] Step 10: Laser crystallization. Use a laser to scan the P-region to induce crystallization of the amorphous silicon in the P-region, thereby enhancing the conductivity of the P-region film.

[0063] Step 11: Patterning 2, using a laser to etch the P-type amorphous silicon layer, intrinsic amorphous silicon layer, and SiN mask layer on the surface of the N-region.

[0064] Step 12: Preparation of transparent conductive film layer (third conductive layer 9, transparent conductive oxide layer TCO) and electroplating seed layer 10 (copper seed layer). A 60 nm TCO thin film and an 80 nm copper seed layer are sputtered onto the back of the battery using PVD.

[0065] Step 13: Patterning 3. Using an exposure process, after ink printing, exposure and development steps, a mask is applied to other locations in the N and P regions on the back of the battery.

[0066] Step 14: Copper grid line electroplating. Copper grid lines are electroplated in the grid line trenches using a vertical continuous electroplating method. The grid line width of the N area on the back side is 50 μm and the height is 30 μm; the width of the P area on the back side is 100 μm and the height is 30 μm.

[0067] Step 15: Remove the ink mask layer. Cover the front of the battery with a water film as a protective layer. Using a chain etching machine, place the battery with the back facing down and immerse the back of the battery in a KOH solution for 100 seconds to remove the ink mask layer.

[0068] Step 16: Remove the copper seed layer on the back. Cover the front of the battery with a water film as a protective layer. Using a chain etching machine, place the battery with the back facing down and cover the back with a mixed solution of dilute sulfuric acid and dilute nitric acid for 80 seconds to remove the seed layer outside the copper grid lines on the back of the battery. Then clean it with ultrapure water and dry it.

[0069] Step 17: Graphicalization 4. Use a laser to etch the TCO film layer between the N and P regions on the back of the battery to form an isolation area to prevent NP conduction and leakage.

[0070] Step 18: High-precision dispensing (e.g.) Figure 3 As shown, the cells are first pre-treated by using UV ozone treatment to remove surface oxides from the grid lines on the back of the cells. Then, alignment is performed by precisely aligning the fine grid positions using a vision system (CCD) and arranging the cells in a series / parallel layout. Next, epoxy resin insulating adhesive (insulating adhesive 12, epoxy resin) is applied to the fine grid (copper grid electrode 11) on the back of the cells using inkjet printing. The N and P grid lines need to be misaligned at the adhesive application points to ensure that the N and P areas do not short-circuit.

[0071] Step 19: Lamination welding (e.g.) Figure 4 As shown in the figure, a low-temperature solder paste 13 is applied to the position where the solder strip 14 and the battery need to be interconnected using a stencil printing method. Then, a CCD positioning vision system is used to arrange the battery cells to ensure that the grid and the interconnect solder strip are precisely aligned. Then, pre-pressing and fixing are performed, followed by lamination welding. The lamination welding temperature is 100℃, the pressure is 0.8 MPa, the time is 20 min, and the vacuum degree is 0.5 kPa. The curing of the adhesive film, the melting of the solder paste and the curing of the insulating adhesive, and the bonding of the battery cells and interconnect materials are completed simultaneously.

[0072] Step 20: Install the frame and junction box. After installation, you will get a gridless copper hybrid back contact heterojunction solar cell and photovoltaic module.

[0073] Comparative Example 1 Silicon-based heterojunction solar cells with a main grid structure were prepared using existing technologies.

[0074] test The material cost, difaciality, short-circuit current, fill factor, and efficiency of Example 2 and Comparative Example 1 were tested, and the results are shown in Table 1: Table 1 As can be seen from Table 1, since the copper electroplating technology used in Example 2 can precisely control the height and width and has a gridless structure, compared with Comparative Example 1, it not only reduces the material cost and increases the bifaciality of the solar cell (from 60%~80% to over 90%), but also improves the short-circuit current, fill factor and efficiency of the solar cell structure because copper has better conductivity than silver paste.

[0075] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A heterojunction solar cell, characterized in that, Including the substrate (1); The front side of the substrate (1) is provided with a front passivation layer (5) and a front antireflection layer (6) from the inside to the outside. The back side of the substrate (1) has an N-type contact area and a P-type contact area; The N-type contact area is provided with a first passivation layer (2), a first conductive layer (3), a first mask layer (4), a seed layer (10), a copper grid electrode (11), an insulating adhesive (12), and a solder strip (14) from the inside to the outside. The P-type contact area is provided with a second passivation layer (7), a second conductive layer (8), a third conductive layer (9), a seed layer (10), a copper gate electrode (11), and a solder ribbon (14) from the inside to the outside. Solder paste (13) is provided on the side wall of the copper gate electrode (11).

2. The heterojunction solar cell according to claim 1, characterized in that, The substrate (1) is a silicon wafer; the front passivation layer (5) is an Al2O3 thin film with a thickness of 4nm~12nm; the front antireflection layer (6) is a SiN thin film with a thickness of 60nm~120nm.

3. The heterojunction solar cell according to claim 1, characterized in that, The first passivation layer (2) is tunneling silicon oxide (SiO2) with a thickness of 1nm-3nm; the first conductive layer (3) is an N-type polycrystalline silicon layer; the first mask layer (4) is a silicon nitride mask layer; and the seed layer (10) is a copper seed layer with a thickness of 30nm-120nm.

4. The heterojunction solar cell according to claim 1, characterized in that, The second passivation layer (7) is an intrinsic amorphous silicon passivation layer with a thickness of 5nm~15nm; the second conductive layer (8) is a P-type amorphous silicon with a thickness of 5nm~50nm; the third conductive layer (9) is a transparent conductive oxide layer (TCO) with a thickness of 40nm~100nm.

5. The method for preparing a heterojunction solar cell according to any one of claims 1 to 4, characterized in that, Includes the following steps: S1. Polish and clean the substrate (1); S2, Preparation of the first passivation layer (2): SiO2 was deposited on the front and back sides of the substrate (1) by low-pressure chemical vapor deposition (LPCVD) to form a tunneling structure; S3. Preparation of the first conductive layer (3): An N-Poly layer is formed on the first passivation layer (2); S4. Remove the PSG phosphate glass layer; S5, N-region mask layer preparation: A silicon nitride (SiN) thin film was deposited on the back of the battery as an N-region mask layer using plasma chemical vapor deposition (PECVD). S6, Patterning 1, using laser to etch the SiN mask layer, N-Poly and SiO2 layer of the P region; S7, texturing of the P area on the front and back of the battery; S8. Preparation of front passivation layer (5) and front antireflection layer (6): A layer of Al2O3 thin film is deposited on the front of the battery using atomic layer deposition (ALD) to passivate the silicon interface, and then a layer of SiN thin film is formed on the front as an antireflection layer using PECVD. S9. Preparation of P-region film on the back side: Using PECVD, an intrinsic amorphous silicon passivation P-region is first deposited on the back side of the silicon wafer, followed by the deposition of a layer of P-type amorphous silicon. S10, Laser crystallization: Using a laser to scan the P-region, the amorphous silicon in the P-region is induced to crystallize, enhancing the conductivity of the P-region film layer; S11, Patterning 2, using laser to etch the P-type amorphous silicon layer, intrinsic amorphous silicon layer and SiN mask layer on the surface of the N region; S12. Preparation of transparent conductive film and electroplating seed layer: A TCO thin film and a copper seed layer are sputtered onto the back of the battery using PVD. S13, Patterning 3, using an exposure process, through ink printing, exposure and development steps, masking is performed on other locations in the N and P regions on the back of the battery; S14, Copper grid line electroplating: Copper grid lines are electroplated in the grid line trenches using a vertical continuous electroplating method; S15, Remove ink mask layer; S16. Remove the copper seed layer on the back side; S17, Patterning 4: Use a laser to etch the TCO film layer between the N and P regions on the back of the battery to form an isolation area to prevent NP conduction and leakage. S18, high-precision dispensing; S19, lamination welding; S20, frame and junction box installation, after installation, a gridless copper back contact heterojunction solar cell is obtained.

6. The preparation method according to claim 5, characterized in that, In S2, the thickness of SiO2 is 1nm-3nm; In S3, the method for forming the first conductive layer (3) includes: introducing silane SiH4 into LPCVD, raising the temperature to 500~800℃, depositing intrinsic polycrystalline silicon 80~150nm on the front and back sides of the substrate (1); placing the cell in a diffusion furnace, setting the temperature to 800~900℃, using nitrogen as a carrier gas to carry phosphorus oxychloride POCl3 into the tube, and after reaction, P atoms diffuse into the i-Poly layer to obtain the N-Poly layer; In S4, the method for removing the phosphosilicate glass (PSG) layer includes: immersing the silicon wafer in an HF solution and removing the PSG layer on the N-Poly surface through a reaction. In S7, the method for texturing the front and back P-areas of the battery includes: first, placing the silicon wafer in a 10%~30% KOH solution to remove laser damage to the back P-area and the N-Poly and SiO2 layers on the front of the silicon wafer; second, performing RCA cleaning on the silicon wafer to remove surface oil and impurities; and finally, placing the silicon wafer in a mixed solution of 1%~10% KOH and 2%~5% isopropanol for 800~1200s to form a textured structure on the front and back P-areas of the battery.

7. The preparation method according to claim 5, characterized in that, In S8, the thickness of the Al2O3 film is 4nm~12nm, and the thickness of the SiN film is 60nm~120nm. In S9, the thickness of the intrinsic amorphous silicon passivation P-region is 5nm~15nm, and the thickness of the P-type amorphous silicon is 5nm~50nm. In S12, the thickness of the TCO film is 40nm~100nm, and the thickness of the copper seed layer is 30nm~120nm; In S14, the width of the grid line of the N-type contact area is 10um-150um and the height is 5um-50um; the width of the P-type contact area is 20um-300um and the height is 5um-50um.

8. The preparation method according to claim 5, characterized in that, In S15, the method for removing the ink mask layer includes: covering the front of the battery with a water film as a protective layer, using a chain etching machine, placing the battery with the back facing down, immersing the back of the battery in a KOH solution for 30s-200s, and removing the ink mask layer. In S16, the method for removing the copper seed layer on the back side includes: covering the front side of the battery with a water film as a protective layer, using a chain etching machine, placing the battery with the back side facing down, and covering the back side with a mixed solution of dilute sulfuric acid and dilute nitric acid for 30s-100s to remove the seed layer outside the copper grid lines on the back side of the battery, then cleaning it with ultrapure water and drying it.

9. The preparation method according to claim 5, characterized in that, In S18, the high-precision dispensing method includes: first, pre-treating the battery cells by using UV ozone treatment to remove surface oxides from the grid lines on the back of the battery; then, aligning them by precisely aligning the fine grid positions using a vision system and arranging the battery cells in a series / parallel layout; then, using inkjet printing to apply epoxy resin insulating adhesive to the fine grids on the back of the battery. The dispensing positions need to be staggered between the N and P grid lines to ensure that the N and P areas do not short-circuit. In S19, the lamination welding method includes: applying low-temperature solder paste to the location where the solder strip and the battery need to be interconnected using stencil printing; then using a CCD positioning vision system to arrange the battery cells to ensure precise alignment of the grid and the interconnect solder strip; then pre-pressing and fixing, followed by lamination welding, wherein the lamination welding temperature is 120℃~180℃, the pressure is 0.5~1.2Mpa, the time is 10~30min, the vacuum degree is less than 1kpa, and the curing of the adhesive film, the melting of the solder paste and the curing of the insulating adhesive, and the bonding of the battery cell and the interconnect material are completed simultaneously.

10. A photovoltaic module, characterized in that, Including the heterojunction solar cell according to any one of claims 1 to 4.

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