Photoelectric interconnection packaging structure and preparation method thereof

Abstract

The invention provides a photoelectric interconnection packaging structure and a preparation method thereof, and the method comprises the steps: forming a first blind hole and a second blind hole of which the bottoms are located on a glass substrate through a laser method, and then carrying out the thinning process from a first surface of the glass substrate and a second surface of the glass substrate, thereby forming a first through hole and a second through hole which are formed in a staggered manner, according to the invention, the high-performance TGV adapter plate which is small in spacing, small in CD size, thin, suitable for high-density setting and capable of effectively avoiding overlapping of metal columns can be prepared on the glass substrate based on a laser method and a thinning process; furthermore, an optical waveguide layer is arranged in the glass substrate and the rewiring layer, and an electric chip and an optical chip are connected by combining a TGV adapter plate, so that the metal wiring is more flexible, the photoelectric interconnection integration is realized, the packaging size is reduced, the power consumption is reduced, the reliability is improved, the optical waveguide layer is suitable for high-density integrated packaging, and good photoelectric signal transmission can be realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to an optoelectronic interconnect packaging structure and its fabrication method. Background Technology

[0002] Optical light has excellent properties such as low signal attenuation, low power consumption, high bandwidth and compatibility with CMOS. It is generally believed in the industry that introducing optical technology into semiconductor manufacturing processes can reduce chip size, reduce cost and power consumption, and improve reliability. Thus, functional chips can be connected by optical fiber through edge coupling. However, as the chip spacing shrinks, the application of optical fiber coupling has been limited.

[0003] In semiconductor 2.5D / 3D packaging, organic interposers, through-silicon via (TSV) interposers, and through-glass via (TGV) interposers are the mainstream interposer materials. The main purpose of setting up interposers is to solve some challenges in semiconductor packaging, such as improving integration, reducing costs, and improving electrical performance.

[0004] Glass, being an insulating material, has a low dielectric constant (approximately one-third that of silicon), a small loss factor (about 2-3 orders of magnitude lower than silicon), and excellent high-frequency performance. This allows glass to significantly reduce insertion loss and crosstalk at high frequencies. However, a key challenge facing TGV technology is the lack of a deep etching process similar to silicon, making it difficult to quickly fabricate high aspect ratio glass deep holes or trenches. Traditional TGV adapter board fabrication methods include sandblasting, mechanical drilling, dry etching, wet etching, focused discharge, and laser methods. However, all of these methods have significant drawbacks. Currently, the most widely used method is the laser method. However, because the energy curve emitted by a laser is a Gaussian energy curve, the glass vias formed by the laser method are conical, making it impossible to form 90° vertical straight holes. Therefore, in high-density hole fabrication, an overlayer phenomenon may occur at the top of the holes, causing contact between the metal filling in adjacent holes. To avoid the overlayer phenomenon, the pitch between adjacent TGV holes needs to be increased. Thus, the existing laser method cannot be applied to the fabrication of high-density, high-performance products.

[0005] Therefore, it is necessary to provide an optoelectronic interconnect packaging structure and its fabrication method. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an optoelectronic interconnect packaging structure and its fabrication method to solve the problem of limited application of optical fiber coupling in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an optoelectronic interconnect packaging structure, comprising the following steps:

[0008] A glass substrate is provided, the glass substrate including a first surface and a second surface disposed opposite to each other;

[0009] A first blind hole with its bottom located in the glass substrate is formed from a first surface using a first laser method, and a second blind hole with its bottom located in the glass substrate is formed from a second surface using a second laser method.

[0010] Thinning processes are performed on the first and second surfaces of the glass substrate respectively, so that the first blind hole is transformed into a first through hole that penetrates the glass substrate from top to bottom, and the second blind hole is transformed into a second through hole that penetrates the glass substrate from bottom to top, and the first through hole and the second through hole are staggered.

[0011] A first TGV metal pillar is formed in the first through hole to fill the first through hole, and a second TGV metal pillar is formed in the second through hole to fill the second through hole;

[0012] A third laser method is used to form a first groove with its bottom located in the glass substrate from the first surface of the glass substrate;

[0013] A first optical waveguide layer is formed in the first groove;

[0014] A first redistribution layer is formed on a first surface of the glass substrate, and a second redistribution layer is formed on a second surface of the glass substrate, wherein the first redistribution layer and the second redistribution layer are respectively electrically connected to the first TGV metal pillar and the second TGV metal pillar.

[0015] The first redistribution layer is graphically represented, and a second groove is formed in the first redistribution layer, wherein the second groove exposes the first optical waveguide layer;

[0016] A second optical waveguide layer is formed in the second groove, and the second optical waveguide layer is connected to the first optical waveguide layer;

[0017] An electrical chip and an optical chip with a photosensitive area are provided. The electrical chip and the optical chip are bonded to a first redistribution layer. Both the electrical chip and the optical chip are electrically connected to the first redistribution layer, and the photosensitive area of ​​the optical chip is correspondingly disposed with respect to the second optical waveguide layer.

[0018] Optionally, the first laser method includes laser ablation or laser-induced denaturation etching; the second laser method includes laser ablation or laser-induced denaturation etching; and the third laser method includes laser ablation or laser-induced denaturation etching.

[0019] Optionally, the first TGV metal pillar and the second TGV metal pillar are formed simultaneously, wherein the method for forming the first TGV metal pillar and the second TGV metal pillar includes chemical plating or electroplating.

[0020] Optionally, the method for forming the first redistribution layer on the first surface of the glass substrate includes a semiconductor process or a substrate bonding method; the method for forming the second redistribution layer on the second surface of the glass substrate includes a semiconductor process or a substrate bonding method.

[0021] Optionally, the distance between adjacent first through holes and second through holes ranges from 30 to 100 μm.

[0022] Optionally, the CD size of the first TGV metal column is 40-50 μm; the CD size of the second TGV metal column is 40-50 μm.

[0023] Optionally, the thickness of the glass substrate before thinning is 200-300 μm; the thickness of the glass substrate after thinning is 100-200 μm.

[0024] The present invention also provides an optoelectronic interconnect packaging structure, the optoelectronic interconnect packaging structure comprising:

[0025] A glass substrate, the glass substrate comprising a first surface and a second surface disposed opposite to each other;

[0026] A first through hole extends from the first surface of the glass substrate downwards through the glass substrate; a second through hole extends from the second surface of the glass substrate downwards through the glass substrate; and the first through hole and the second through hole are staggered.

[0027] The method for preparing the first through hole and the second through hole is as follows:

[0028] A first blind hole with its bottom located in the glass substrate is formed from a first surface using a first laser method, and a second blind hole with its bottom located in the glass substrate is formed from a second surface using a second laser method.

[0029] Thinning processes are performed on the first surface and the second surface of the glass substrate respectively, so that the first blind hole is transformed into the first through hole, and the second blind hole is transformed into the second through hole;

[0030] The first TGV metal pillar fills the first through hole;

[0031] The second TGV metal pillar fills the second through hole;

[0032] The first groove is prepared by a third laser method and extends from the first surface of the glass substrate into the glass substrate.

[0033] A first optical waveguide layer is located in the first groove;

[0034] A first redistribution layer is located on a first surface of the glass substrate, and the first redistribution layer is electrically connected to both the first TGV metal pillar and the second TGV metal pillar.

[0035] The second redistribution layer is located on the second surface of the glass substrate and is electrically connected to both the first TGV metal pillar and the second TGV metal pillar.

[0036] The second groove is located in the first rewiring layer and exposes the first optical waveguide layer;

[0037] The second optical waveguide layer is located in the second groove and is connected to the first optical waveguide layer.

[0038] An electrical chip and an optical chip with a photosensitive area are provided. The electrical chip and the optical chip are bonded to the first redistribution layer. Both the electrical chip and the optical chip are electrically connected to the first redistribution layer, and the photosensitive area of ​​the optical chip is correspondingly disposed with the second optical waveguide layer.

[0039] Optionally, the distance between adjacent first TGV metal pillars and second TGV metal pillars ranges from 30 to 100 μm; the CD dimension of the first TGV metal pillar is 40 to 50 μm; the CD dimension of the second TGV metal pillar is 40 to 50 μm; and the first TGV metal pillar and the second TGV metal pillar have the same morphology.

[0040] Optionally, it also includes a metal reflector located on the sidewall of the first groove; a convex lens located on the second optical waveguide layer; and a metal bump located on the second redistribution layer.

[0041] As described above, the optoelectronic interconnect packaging structure and its fabrication method of the present invention employ a first laser method to form a first blind hole with its bottom located on a glass substrate, and a second laser method to form a second blind hole with its bottom located on a glass substrate. Then, thinning processes are performed on the first and second surfaces of the glass substrate, respectively, transforming the first blind hole into a first through hole and the second blind hole into a second through hole. The formed first and second through holes are staggered. Therefore, this application can fabricate a high-performance TGV adapter board with smaller spacing, smaller CD size, and thinner profile on a glass substrate based on the laser method and thinning process, suitable for high-density fabrication, and effectively avoiding metal pillar overlap. Furthermore, by setting an optical waveguide layer in the glass substrate and the redistribution layer, and combining it with the TGV adapter board for connecting electrical and optical chips, the metal wiring becomes more flexible, enabling optoelectronic interconnect integration, reducing package size, lowering power consumption, improving reliability, and making it suitable for high-density integrated packaging, achieving good optoelectronic signal transmission. Attached Figure Description

[0042] Figure 1 The diagram shows a process flow diagram for preparing the optoelectronic interconnect packaging structure in an embodiment of the present invention.

[0043] Figure 2 The diagram shown is a structural schematic of the first and second blind holes after they are formed in an embodiment of the present invention.

[0044] Figure 3 The diagram shown is a structural schematic of the first and second through holes formed by the thinning process in an embodiment of the present invention.

[0045] Figure 4 The diagram shown is a structural schematic of the first TGV metal column and the second TGV metal column after they are formed in an embodiment of the present invention.

[0046] Figure 5 The diagram shown is a schematic representation of the structure after the first groove is formed in an embodiment of the present invention.

[0047] Figure 6 The diagram shown is a schematic representation of the structure after the metal reflector is formed in an embodiment of the present invention.

[0048] Figure 7 The diagram shown is a schematic representation of the structure after the formation of the first optical waveguide layer in an embodiment of the present invention.

[0049] Figure 8 The diagram shown is a structural schematic of the first and second redistribution layers after they have been formed in an embodiment of the present invention.

[0050] Figure 9 The diagram shown is a schematic representation of the structure after the second groove is formed in an embodiment of the present invention.

[0051] Figure 10 The diagram shown is a schematic representation of the structure after the formation of the second optical waveguide layer in an embodiment of the present invention.

[0052] Figure 11 The diagram shown is a schematic representation of the structure after the convex lens is formed in an embodiment of the present invention.

[0053] Figure 12 The diagram shows the structure of the bonding electrical chip, optical chip, and metal bumps in an embodiment of the present invention.

[0054] Explanation of reference numerals in the attached figures

[0055] 100 glass substrate

[0056] 101 First Blind Hole

[0057] 102 Second blind hole

[0058] 111 First Through Hole

[0059] 112 Second Through Hole

[0060] 103 First Groove

[0061] 104 Second Groove

[0062] 201 First TGV Metal Column

[0063] 202 Second TGV Metal Column

[0064] 300 Metal Reflector

[0065] 401 First optical waveguide layer

[0066] 402 Second optical waveguide layer

[0067] 501 First Rerouting Layer

[0068] 502 Second Rerouting Layer

[0069] 600 convex lens

[0070] 701 electrical chip

[0071] 702 Optical Chip

[0072] 712 Photosensitive Area

[0073] 800 metal bumps Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0076] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0077] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0078] See Figure 1 This embodiment provides a method for fabricating an optoelectronic interconnect packaging structure. It can fabricate a high-performance TGV adapter board with small spacing, small CD size, and thinness on a glass substrate based on laser method. This board is suitable for high-density setup and can effectively avoid metal pillar overlap. Furthermore, optical waveguide layers are set in the glass substrate and the redistribution layer, and the electrical chip and optical chip are connected in conjunction with the TGV adapter board. This makes the metal wiring more flexible, realizes optoelectronic interconnect integration, reduces package size, reduces power consumption, improves reliability, and is suitable for high-density integrated packaging, enabling good optoelectronic signal transmission.

[0079] The following is in conjunction with the appendix Figures 2 to 12 The fabrication of the aforementioned optoelectronic interconnect packaging structure is further described, specifically including:

[0080] First, refer to Figure 1 and Figure 2 Step S1 is executed, providing a glass substrate 100, the glass substrate 100 including a first surface and a second surface disposed opposite to each other.

[0081] Specifically, the glass substrate 100 may include a wafer-level glass substrate, such as 4-inch, 6-inch, 8-inch, 12-inch, etc. The thickness of the glass substrate 100 may be 200-300μm, such as 200μm, 250μm, 300μm, etc. However, the size of the glass substrate 100 is not limited to this and can be set as needed. No excessive restrictions are imposed here.

[0082] Next, refer to Figure 1 and Figure 2 In step S2, a first blind hole 101 with its bottom located in the glass substrate 100 is formed from the first surface of the glass substrate 100 using a first laser method, and a second blind hole 102 with its bottom located in the glass substrate 100 is formed from the second surface of the glass substrate 100 using a second laser method.

[0083] The first laser method may include laser ablation or laser-induced denaturation etching; similarly, the second laser method may include laser ablation or laser-induced denaturation etching. Preferably, the first and second laser methods employ the same preparation method to reduce process complexity and facilitate process management and operation. However, this is not a limitation; different preparation methods may be used for the first and second laser methods as needed. Specific operations of laser ablation and laser-induced denaturation etching are not detailed here; please refer to existing preparation methods.

[0084] Next, refer to Figure 1 and Figure 3 Step S3 is executed, and a thinning process is performed on the first surface and the second surface of the glass substrate 100 respectively, so that the first blind hole 101 is transformed into a first through hole 111 that penetrates the glass substrate 100 from top to bottom, and the second blind hole 102 is transformed into a second through hole 112 that penetrates the glass substrate 100 from bottom to top, and the first through hole 111 and the second through hole 112 are staggered.

[0085] Specifically, most existing methods for fabricating TGV adapter plates employ laser methods to create TGV holes in a glass substrate. However, the TGV holes formed by laser methods are tapered. (See [link to relevant documentation]). Figure 2The morphology of the first blind via 101 is shown. Therefore, to avoid the over-layer phenomenon between TGV vias, the distance between TGV vias is usually increased during the manufacturing process, such as setting the pitch of adjacent TGV vias to 120-150 μm. This method of avoiding over-layer TGV adapter boards by increasing the pitch is difficult to apply to high-density products. Therefore, refer to... Figure 2 In this embodiment, laser methods are cleverly applied to the first and second surfaces of the glass substrate 100 respectively, thereby forming the first blind hole 101 and the second blind hole 102 in the glass substrate 100, and referring to... Figure 3 After forming the first blind hole 101 and the second blind hole 102, the first blind hole 101 can be transformed into the first through hole 111 that penetrates the glass substrate 100 from top to bottom through a double-sided thinning process, and the second blind hole 102 can be transformed into the second through hole 112 that penetrates the glass substrate 100 from bottom to top, and the first through hole 111 and the second through hole 112 are staggered.

[0086] In this embodiment, the pitch between adjacent first through-hole 111 and second through-hole 112 can be reduced while effectively avoiding over-layering; the thickness of the thinned glass substrate 100 can be 100-200μm, such as 100μm, 150μm, 200μm, etc.; by thinning, the wider area in the blind hole can be removed, thereby reducing the CD size of the subsequently prepared TGV metal pillar.

[0087] The thinning process can be carried out by methods such as chemical mechanical polishing (CMP) or mechanical polishing, and no specific method is specified here.

[0088] See Figure 2 , Figure 3 and Figure 4 The first blind hole 101 is formed by laser method, so that the opening width is greater than the bottom width. Similarly, the second blind hole 102 is formed by laser method, so that the opening width is greater than the bottom width. The first blind hole 101 and the second blind hole 102 are overlapped, so that the first blind hole 101 and the second blind hole 102 can make full use of the effective space of the glass substrate 100 and reduce the distance D between adjacent TGV holes. The distance D between adjacent first through hole 111 and second through hole 112 can be in the range of 80 to 100 μm, such as 80 μm, 90 μm, 100 μm, etc.

[0089] In this embodiment, when the first blind hole 101 and the second blind hole 102 are prepared, there is an isolation space between adjacent first blind holes 101 and second blind holes 102, thereby effectively avoiding the phenomenon of over-layer.

[0090] In another embodiment, the first blind via 101 and the second blind via 102 may also overlap, i.e., the ends have an over-layer phenomenon. When performing a double-sided thinning process on the glass substrate 100, the overlapping area that causes the over-layer phenomenon can be removed by the thinning process, thereby further reducing the range of the spacing D. The spacing D between adjacent first blind vias 101 and second blind vias 102 can be 30 to 100 μm, such as 30 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc., thereby effectively avoiding the over-layer phenomenon, increasing the density of TGV hole distribution, and realizing the preparation of high-quality products.

[0091] Next, refer to Figure 1 and Figure 4 In step S4, a first TGV metal pillar 201 is formed in the first through hole 111 to fill the first through hole 111, and a second TGV metal pillar 202 is formed in the second through hole 112 to fill the second through hole 112.

[0092] Specifically, it is preferable that the first TGV metal column 201 and the second TGV metal column 202 are formed simultaneously to reduce the number of preparation steps. Of course, if necessary, the first TGV metal column 201 and the second TGV metal column 202 can also be prepared in steps, which is not limited here.

[0093] The method for forming the first TGV metal column 201 may include electroless plating or electroplating; the method for forming the second TGV metal column 202 may include electroless plating or electroplating. Specific preparation methods for the first TGV metal column 201 and the second TGV metal column 202 are not limited here. Specific operations for electroless plating or electroplating are not detailed here; please refer to existing preparation methods.

[0094] In this embodiment, the first TGV metal pillar 201 and the second TGV metal pillar 202 are made of copper, but the material of the TGV metal pillar is not limited to this, and other conductive metal materials can also be used.

[0095] Among them, such as Figure 4The critical dimension (CD) of the first TGV metal column 201, i.e., d, can be 40-50 μm, such as 40 μm, 45 μm, 50 μm, etc., and the critical dimension (CD) of the second TGV metal column 202 can be 40-50 μm, such as 40 μm, 45 μm, 50 μm, etc.

[0096] Furthermore, after the first through hole 111 and the second through hole 112 are prepared by laser method, in order to facilitate the formation of the first TGV metal pillar 201 and the second TGV metal pillar 202 that fill the through holes, the first through hole 111 and the second through hole 112 can be surface treated, such as by wet etching, so that the first through hole 111 and the second through hole 112 have smooth inner surfaces. The method of surface treatment is not limited here.

[0097] Furthermore, after forming the first TGV metal pillar 201 and the second TGV metal pillar 202, in order to facilitate the subsequent preparation of the redistribution layer, the glass substrate 100 can be surface treated, such as polishing or wet etching, to avoid electrical connections between the TGV metal pillars and obtain a flat surface.

[0098] Next, refer to Figure 1 and Figure 5 In step S5, a third laser method is used to form a first groove 103 with its bottom located in the glass substrate 100 from the first surface of the glass substrate 100.

[0099] The third laser method may include laser ablation or laser-induced denaturation etching. Preferably, the first laser method, the second laser method and the third laser method use the same preparation method to reduce process complexity and facilitate process management and operation. However, it is not limited to this. As needed, the first laser method, the second laser method and the third laser method may also use different preparation methods.

[0100] Since the first groove 103 is prepared by laser method, the opening width of the first groove 103 is greater than the bottom width, that is, the side wall of the first groove 103 has an inclined surface. The inclined surface is beneficial to the subsequent transmission of optical signals. The inclination angle of the inclined surface can be set according to specific needs and is not limited here.

[0101] Next, refer to Figure 1 , Figure 6 and Figure 7 Step S6 is executed to form a first optical waveguide layer 401 in the first groove 104.

[0102] Among them, see Figure 6To reduce light loss and improve light transmission efficiency, in this embodiment, it is preferable to form a metal reflector 300 on the sidewall of the first groove 103, such as a titanium metal reflector prepared by sputtering and etching. The metal reflector 300 formed can also cover the bottom of the first groove 103, which is not limited here.

[0103] When fabricating the first optical waveguide layer 401, a semiconductor process can be used, which involves steps such as coating, exposure, development, and etching. The first optical waveguide layer 401 formed may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer, etc.

[0104] Next, refer to Figure 1 and Figure 8 In step S7, a first redistribution layer 501 is formed on the first surface of the glass substrate 100, and a second redistribution layer 502 is formed on the second surface of the glass substrate 100, wherein the first redistribution layer 501 and the second redistribution layer 502 are respectively electrically connected to the first TGV metal pillar 201 and the second TGV metal pillar 202.

[0105] Specifically, the method for forming the first redistribution layer 501 on the first surface of the glass substrate 100 may include a semiconductor process method or a substrate bonding method. Similarly, the method for forming the second redistribution layer 502 on the second surface of the glass substrate 100 may include a semiconductor process method or a substrate bonding method.

[0106] The semiconductor manufacturing process is a method of preparing the first redistribution layer 501 and the second redistribution layer 502 on the glass substrate 100 through steps such as coating, exposure, development, deposition, and etching. The substrate bonding method is a method of preparing the required first redistribution layer 501 and the second redistribution layer 502 in advance, and then directly bonding the first redistribution layer 501 and the second redistribution layer 502 to the glass substrate 100.

[0107] The specific fabrication methods for the first redistribution layer 501 and the second redistribution layer 502 are not excessively limited here; they can be fabricated using the same method, or different methods can be used. The specific materials and structures of the first redistribution layer 501 and the second redistribution layer 502 are also not excessively limited here and can be selected as needed.

[0108] Next, refer to Figure 1 and Figure 9In step S8, the first redistribution layer 501 is graphically visualized, and a second groove 104 is formed in the first redistribution layer 501, with the second groove 104 exposing the first optical waveguide layer 401.

[0109] Specifically, the etching method for the first redistribution layer 501 can be selected as needed, and the morphology of the second groove 104 is not limited here.

[0110] Next, refer to Figure 1 and Figure 10 In step S9, a second optical waveguide layer 402 is formed in the second groove 104, and the second optical waveguide layer 402 is connected to the first optical waveguide layer 401.

[0111] Specifically, the second optical waveguide layer 402 can be fabricated using semiconductor processing methods, i.e., through steps such as coating, exposure, development, and etching. The resulting second optical waveguide layer 402 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer, etc. Preferably, the fabrication and material of the second optical waveguide layer 402 are the same as those of the first optical waveguide layer 401 to reduce process complexity.

[0112] See Figure 11 Furthermore, it is preferable to form a convex lens 600 on the second optical waveguide layer 402, so as to concentrate light and further reduce light loss. The method of fabricating the convex lens 600 is not limited here; bonding method can be used, but it is not limited to this.

[0113] Next, refer to Figure 1 and Figure 12 In step S10, an electrical chip 701 and an optical chip 702 with a photosensitive area 712 are provided. The electrical chip 701 and the optical chip 702 are bonded to the first redistribution layer 501. Both the electrical chip 701 and the optical chip 702 are electrically connected to the first redistribution layer 501, and the photosensitive area 712 of the optical chip 702 is correspondingly disposed with the second optical waveguide layer 402.

[0114] For details, please refer to Figure 12 The electrical leads of the electrical chip 701 and the optical chip 702 are electrically connected to the first redistribution layer 501 via metal bumps. The photosensitive area 712 of the optical chip 702 is correspondingly disposed with the second optical waveguide layer 402, so as to form an optical transmission path in conjunction with the first optical waveguide layer 401. Figure 12 The dashed line with an arrow is shown in the image.

[0115] For further details, please refer to [link / reference]. Figure 12Metal bumps 800 and the like can also be formed on the surface of the second redistribution layer 502 to facilitate subsequent electrical connections.

[0116] Understandably, in order to increase production capacity, Figure 12 The optoelectronic interconnect packaging structure described herein can be considered as a single-unit structure formed after a cutting process. Of course, depending on the needs, Figure 12 The optoelectronic interconnect packaging structure described herein can also be a monolithic structure directly prepared without a cutting process; no excessive restrictions are imposed here.

[0117] See Figures 2 to 12 This embodiment also provides an optoelectronic interconnect packaging structure, wherein the optoelectronic interconnect packaging structure can be directly prepared using the above-described preparation process. Therefore, the materials, structure, etc. of the optoelectronic interconnect packaging structure can be referred to the above content. Of course, the optoelectronic interconnect packaging structure can also be prepared using other preparation processes as needed.

[0118] In this embodiment, the optoelectronic interconnect packaging structure includes:

[0119] A glass substrate 100, the glass substrate 100 including a first surface and a second surface disposed opposite to each other;

[0120] A first through hole 111 extends from the first surface of the glass substrate 100 from top to bottom through the glass substrate 100; a second through hole 112 extends from the second surface of the glass substrate 100 from bottom to bottom through the glass substrate 100; and the first through hole 111 and the second through hole 112 are staggered.

[0121] The method for preparing the first through hole 111 and the second through hole 112 is as follows:

[0122] A first blind hole 101 with its bottom located in the glass substrate 100 is formed from a first surface of the glass substrate 100 using a first laser method, and a second blind hole 102 with its bottom located in the glass substrate 100 is formed from a second surface of the glass substrate 100 using a second laser method.

[0123] Thinning processes are performed on the first surface and the second surface of the glass substrate 100 respectively, so that the first blind hole 100 is transformed into the first through hole 111, and the second blind hole 102 is transformed into the second through hole 112.

[0124] The first TGV metal pillar 201 fills the first through hole 111;

[0125] The second TGV metal pillar 202 fills the second through hole 112;

[0126] The first groove 103 is prepared by a third laser method and extends from the first surface of the glass substrate 100 into the glass substrate 100.

[0127] The first optical waveguide layer 401 is located in the first groove 103;

[0128] A first redistribution layer 501 is located on a first surface of the glass substrate 100, and the first redistribution layer 501 is electrically connected to both the first TGV metal pillar 201 and the second TGV metal pillar 202.

[0129] The second redistribution layer 502 is located on the second surface of the glass substrate 100, and the second redistribution layer 502 is electrically connected to both the first TGV metal pillar 201 and the second TGV metal pillar 202.

[0130] The second groove 104 is located in the first rewiring layer 501 and exposes the first optical waveguide layer 401.

[0131] The second optical waveguide layer 402 is located in the second groove 104 and is connected to the first optical waveguide layer 401.

[0132] An electrical chip 701 and an optical chip 702 having a photosensitive area 712 are bonded to the first redistribution layer 501. Both the electrical chip 701 and the optical chip 702 are electrically connected to the first redistribution layer 501, and the photosensitive area 712 of the optical chip 702 is correspondingly disposed with the second optical waveguide layer 402.

[0133] The distance D between adjacent first TGV metal pillars 201 and second TGV metal pillars 202 can range from 30 to 100 μm, such as 30 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc. Since the first through hole 111 and the second through hole 112 are overlapped, the first TGV metal pillars 201 and the second TGV metal pillars 202 are overlapped, and an effective gap area can be formed between them to effectively avoid the phenomenon of over-layer, improve the density of TGV metal pillar distribution, and prepare high-quality products.

[0134] The glass substrate 100 may include a wafer-level glass substrate, such as 4-inch, 6-inch, 8-inch, 12-inch, etc. The thickness of the glass substrate 100 before thinning may be 200-300μm, such as 200μm, 250μm, 300μm, etc. The thickness of the glass substrate 100 after thinning may be 100-200μm, such as 10μm, 150μm, 200μm, etc. However, the size of the glass substrate 100 is not limited to these, and can be set as needed. No excessive restrictions are imposed here.

[0135] Among them, such as Figure 4 The CD (d) dimension of the first TGV metal pillar 201 can be 40-50 μm, such as 40 μm, 45 μm, 50 μm, etc., and the CD dimension of the second TGV metal pillar 202 can be 40-50 μm, such as 40 μm, 45 μm, 50 μm, etc.

[0136] Furthermore, the first TGV metal pillar 201 and the second TGV metal pillar 202 may have the same morphology, see reference. Figure 12 The illustration shows the first TGV metal pillar 201 and the second TGV metal pillar 202, both conical in shape and having the same morphology. However, this is not a limitation; the first TGV metal pillar 201 and the second TGV metal pillar 202 could also be conical with different dimensions. This can be achieved by adjusting the laser process to meet specific product requirements, and is not limited here. (See also...) Figure 6 and Figure 12 In order to reduce light loss and improve light transmission efficiency, in this embodiment, a metal reflector 300 is preferably provided on the side wall of the first groove 103. Of course, the metal reflector 300 may also cover the bottom of the first groove 103 as needed, which is not limited here.

[0137] For further details, please refer to [link / reference]. Figure 12 Preferably, a convex lens 600 is provided on the second optical waveguide layer 402 to concentrate light and further reduce light loss.

[0138] For further details, please refer to [link / reference]. Figure 12 Metal bumps 800 or similar features can also be provided on the surface of the second redistribution layer 502 to facilitate subsequent electrical connections.

[0139] In summary, the optoelectronic interconnect packaging structure and its fabrication method of the present invention employ a first laser method to form a first blind hole with its bottom located on a glass substrate, and a second laser method to form a second blind hole with its bottom located on a glass substrate. Then, thinning processes are performed on the first and second surfaces of the glass substrate, respectively, transforming the first blind hole into a first through hole and the second blind hole into a second through hole. The formed first and second through holes are staggered. Therefore, this application can fabricate a high-performance TGV adapter board with smaller spacing, smaller CD size, and thinner profile on a glass substrate based on the laser method and thinning process, suitable for high-density fabrication, and effectively avoiding metal pillar overlap. Furthermore, by setting an optical waveguide layer in the glass substrate and the redistribution layer, and combining it with the TGV adapter board for connecting electrical and optical chips, the metal wiring becomes more flexible, enabling optoelectronic interconnect integration, reducing package size, lowering power consumption, improving reliability, and making it suitable for high-density integrated packaging, achieving good optoelectronic signal transmission.

[0140] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating an optoelectronic interconnect package structure, comprising: The method comprises the following steps: ​ providing a glass substrate comprising a first surface and a second surface arranged oppositely; forming a first blind hole with a bottom in the glass substrate from the first surface of the glass substrate by a first laser method, and forming a second blind hole with a bottom in the glass substrate from the second surface of the glass substrate by a second laser method; performing a thinning process from the first surface of the glass substrate and the second surface of the glass substrate respectively, so that the first blind hole is converted into a first through hole penetrating through the glass substrate from top to bottom, and the second blind hole is converted into a second through hole penetrating through the glass substrate from bottom to top, and the first through hole and the second through hole are arranged alternately; forming a first TGV metal column filling the first through hole in the first through hole, and forming a second TGV metal column filling the second through hole in the second through hole; forming a first groove with a bottom in the glass substrate from the first surface of the glass substrate by a third laser method; forming a first optical waveguide layer in the first groove; forming a first rewiring layer on the first surface of the glass substrate, and forming a second rewiring layer on the second surface of the glass substrate, wherein the first rewiring layer and the second rewiring layer are electrically connected with the first TGV metal column and the second TGV metal column respectively; patterning the first rewiring layer to form a second groove in the first rewiring layer, and the second groove exposes the first optical waveguide layer; forming a second optical waveguide layer in the second groove, and the second optical waveguide layer is connected with the first optical waveguide layer; providing an electrical chip and an optical chip with a photosensitive region, and bonding the electrical chip and the optical chip on the first rewiring layer, wherein the electrical chip and the optical chip are electrically connected with the first rewiring layer, and the photosensitive region of the optical chip is arranged correspondingly with the second optical waveguide layer.

2. The method of claim 1, wherein: The first laser method comprises a laser ablation method or a laser-induced denaturation etching method; the second laser method comprises a laser ablation method or a laser-induced denaturation etching method; and the third laser method comprises a laser ablation method or a laser-induced denaturation etching method.

3. The method of claim 1, wherein: The first TGV metal column and the second TGV metal column are formed synchronously, and the method for forming the first TGV metal column and the second TGV metal column comprises chemical plating or electroplating.

4. The method of claim 1, wherein: The method for forming the first rewiring layer on the first surface of the glass substrate comprises a semiconductor process method or a substrate bonding method; and the method for forming the second rewiring layer on the second surface of the glass substrate comprises a semiconductor process method or a substrate bonding method.

5. The method of claim 1, wherein: The distance between the adjacent first through hole and the second through hole ranges from 30 to 100 μm.

6. The method of claim 1, wherein: The CD size of the first TGV metal column ranges from 40 to 50 μm; and the CD size of the second TGV metal column ranges from 40 to 50 μm.

7. The method of claim 1, wherein: The thickness of the glass substrate before thinning ranges from 200 to 300 μm; and the thickness of the glass substrate after thinning ranges from 100 to 200 μm.

8. An optoelectronic interconnect package structure, comprising: The optoelectronic interconnection packaging structure comprises: a glass substrate comprising a first surface and a second surface arranged oppositely; a first via hole and a second via hole, the first via hole and the second via hole being staggered; wherein the method for preparing the first via hole and the second via hole is: a first blind hole with a bottom in the glass substrate is formed from the first surface of the glass substrate by a first laser method, and a second blind hole with a bottom in the glass substrate is formed from the second surface of the glass substrate by a second laser method; a thinning process is performed from the first surface of the glass substrate and the second surface of the glass substrate respectively, so that the first blind hole is converted into the first via hole, and the second blind hole is converted into the second via hole; a first TGV metal column fills the first via hole; a second TGV metal column fills the second via hole; a first groove is prepared by a third laser method, and the first groove extends into the glass substrate from the first surface of the glass substrate; a first optical waveguide layer is located in the first groove; a first rewiring layer is located on the first surface of the glass substrate, and the first rewiring layer is electrically connected with the first TGV metal column and the second TGV metal column; a second rewiring layer is located on the second surface of the glass substrate, and the second rewiring layer is electrically connected with the first TGV metal column and the second TGV metal column; a second groove is located in the first rewiring layer, and the second groove exposes the first optical waveguide layer; a second optical waveguide layer is located in the second groove, and the second optical waveguide layer is connected with the first optical waveguide layer; an electrical chip and an optical chip with a photosensitive area are bonded on the first rewiring layer, the electrical chip and the optical chip are electrically connected with the first rewiring layer, and the photosensitive area of the optical chip is arranged correspondingly with the second optical waveguide layer.

9. The optoelectronic interconnect package structure of claim 8, wherein: The distance between the first TGV metal column and the second TGV metal column is in the range of 30-100 μm; the CD size of the first TGV metal column is 40-50 μm; the CD size of the second TGV metal column is 40-50 μm; the first TGV metal column and the second TGV metal column have the same morphology.

10. The optoelectronic interconnect package structure of claim 8, wherein: A metal mirror is further located on the sidewall of the first groove; a convex lens is further located on the second optical waveguide layer; and a metal bump is further located on the second rewiring layer.

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