Uncooled infrared reading circuit and device based on oversampling technology

Abstract

The invention relates to the technical field of infrared imaging, and provides an uncooled infrared reading circuit and equipment based on an oversampling technology, and the circuit comprises a detector biasing circuit, an automatic gain correction circuit and an oversampling analog-to-digital converter. The detector bias circuit is used for providing bias voltage for a sensitive pixel and a thermal short circuit pixel to obtain response current, and outputting the response current to the automatic gain correction circuit; the automatic gain correction circuit is used for converting the response current into gain output voltage; and the oversampling analog-to-digital converter is used for performing low-pass filtering processing on the gain output voltage by adopting an oversampling technology to obtain a digital signal. According to the invention, the problem of cost increase caused by large circuit area can be solved, and the requirements of middle-end and low-end applications are met.

Description

Technical Field

[0001] This application relates to the field of infrared imaging technology, and in particular to an uncooled infrared readout circuit and device based on oversampling technology. Background Technology

[0002] Uncooled infrared imaging technology has important applications in industry, agriculture, medicine, astronomy and other fields. The infrared focal plane array, which is the core of uncooled infrared imaging technology, consists of two parts: an infrared detector array and a readout circuit.

[0003] Among them, the microbolometer focal plane array (FPA) has high sensitivity and is the most widely used type of uncooled infrared focal plane array. In a microbolometer, the thermosensitive material is connected to the electrical path of the readout circuit through the bridge legs and piers, forming a temperature-sensitive pixel unit connected to the readout circuit. The readout circuit's function is to drive the sensitive pixel, filter and amplify the induced current, and sequentially read the output signal off-chip; it is a key component of the uncooled infrared detector.

[0004] However, users have increasingly higher requirements for uncooled infrared detectors, demanding not only high performance but also low cost, low power consumption, digitalization, and ease of use. To reduce noise, the detector needs to maximize integration time. Traditional infrared readout channels require large integrating capacitors and resistors, increasing the overall layout area and raising costs. This problem is more pronounced in low-to-mid-range applications with lower resolution or frame rates. Summary of the Invention

[0005] This application provides an uncooled infrared readout circuit and device based on oversampling technology, which can solve the problem of increased cost due to large circuit area and meet the needs of low- and mid-range applications.

[0006] In one aspect, this application provides an uncooled infrared readout circuit based on oversampling technology, the circuit including a detector bias circuit, an automatic gain correction circuit, and an oversampling analog-to-digital converter;

[0007] The detector bias circuit is used to provide bias voltage to the sensitive pixel and the thermally short-circuited pixel to obtain a response current, and outputs the response current to the automatic gain correction circuit.

[0008] The automatic gain correction circuit is used to convert the response current into a gain output voltage;

[0009] The oversampling analog-to-digital converter is used to perform low-pass filtering on the gain output voltage using oversampling technology to obtain a digital signal.

[0010] In some embodiments of this application, when the detector bias circuit uses a mirror circuit to generate the bias voltage, the automatic gain correction circuit is composed of a transimpedance amplifier composed of operational amplifiers, and the oversampling analog-to-digital converter adopts a fully differential first-order circuit structure.

[0011] The mirror circuit consists of a reference branch and a mirror branch, and a non-uniformity correction circuit exists at the coupling node between the detector output signal and the bias circuit; the transimpedance gain of the automatic gain correction circuit is determined based on the thermal short-circuit pixel resistance, and the reference bias voltage is connected to the non-inverting input terminal of the operational amplifier in the automatic gain correction circuit through the non-uniformity correction circuit.

[0012] In some embodiments of this application, when the bias circuit does not use a mirror circuit to generate the bias voltage, the automatic gain correction circuit uses a transimpedance network and a buffer composed of thermally short-circuited pixel resistors and capacitors to output the gain output voltage, and the oversampling analog-to-digital converter uses a fully differential first-order circuit structure.

[0013] In some embodiments of this application, the fully differential first-order circuit structure includes a switched-capacitor integrator, a comparator and a flip-flop, and a digital processing module;

[0014] The switched capacitor integrator is used to control the sampling capacitor in the switched capacitor integrator to sample or integrate signals to obtain a feedback voltage by means of a clock and the digital feedback signal of the flip-flop.

[0015] The comparator is used to obtain a differential signal based on the feedback voltage;

[0016] The trigger is used to convert the differential signal into a single-ended signal, and the single-ended signal serves as the digital feedback signal;

[0017] The digital processing module is used to downsample the single-ended signal to obtain the digital signal.

[0018] In some embodiments of this application, the clock includes a first clock and a second clock that do not overlap; when the detector bias circuit uses a mirror circuit to generate the bias voltage, the comparator is a continuous-time comparator, and the switched-capacitor integrator is connected to the continuous-time comparator via a switch controlled by the second clock.

[0019] When the first clock is valid, the switch controlled by the second clock is turned off. One end of the sampling capacitor is connected to the common-mode voltage through the switch controlled by the second clock, and the other end is connected to the gain output voltage and the reference bias voltage through the switch controlled by the second clock for signal sampling.

[0020] When the second clock is active, the switch controlled by the second clock is closed, and the signal charge stored in the sampling capacitor is transferred to the inverting input terminal of the operational amplifier through the switch controlled by the second clock, thus outputting the feedback voltage.

[0021] In some embodiments of this application, the digital feedback signal output by the trigger changes with the edge of the first clock;

[0022] If the digital feedback signal output by the trigger is high, the positive terminal of the sampling capacitor is switched to the preset first threshold and the preset second threshold respectively; if the digital feedback signal output by the trigger is low, the positive terminal of the sampling capacitor is switched to the preset second threshold and the preset first threshold respectively.

[0023] In some embodiments of this application, the clock includes a first clock and a second clock that do not overlap; when the bias circuit does not use a mirror circuit to generate the bias voltage, the comparator is a discrete-time comparator, the switched capacitor integrator is connected to the discrete-time comparator via a switch controlled by the second clock, the non-inverting input of the discrete-time comparator is connected to the lower plate of a sampling capacitor, and the inverting input of the discrete-time comparator is connected to the lower plate of another sampling capacitor;

[0024] When the first clock is valid, the switch controlled by the second clock is turned off, the first sampling capacitor collects the gain output voltage, and the other sampling capacitor collects the analog positive power supply voltage or the analog ground voltage respectively according to the digital feedback signal output by the flip-flop connected to the discrete time comparator.

[0025] When the second clock is active, the switch controlled by the second clock is closed, and the positive terminal of the sampling capacitor is switched to either the analog positive power supply voltage or the analog ground voltage according to the digital feedback signal output by the flip-flop connected to the discrete time comparator. The positive terminal of the other sampling capacitor is switched to the gain output voltage.

[0026] The discrete-time comparator is reset when the second clock is valid, and operates normally when the second clock is invalid; the flip-flop samples at the falling edge of the first clock.

[0027] In some embodiments of this application, when the detector bias circuit and the automatic gain correction circuit are combined, a differential voltage is output, and the differential voltage is processed by a switched capacitor integrator and a discrete-time comparator to obtain the digital signal; wherein, there are multiple sets of clock-controlled switches connected between the switched capacitor integrator and the discrete-time comparator.

[0028] In some embodiments of this application, the multiple sets of clock control switches include switches controlled by a first clock and switches controlled by a second clock, wherein the two phases of the first clock and the second clock do not overlap;

[0029] The discrete-time comparator is also connected to a clock latch; the output of the clock latch is updated according to the output of the discrete-time comparator when the first clock is valid, and the output of the clock latch remains unchanged when the first clock is invalid.

[0030] On the other hand, this application also provides an uncooled infrared detector device, including the uncooled infrared readout circuit based on oversampling technology as described in any one of the claims.

[0031] In another aspect, this application also provides an electronic device with infrared detection capabilities, including the aforementioned uncooled infrared detector device.

[0032] This application provides an uncooled infrared readout circuit and device based on oversampling technology. The circuit includes a detector bias circuit, an automatic gain correction circuit, and an oversampling analog-to-digital converter (ADC). The detector bias circuit provides bias voltages to sensitive pixels and thermally short-circuited pixels to obtain response currents, and outputs these response currents to the automatic gain correction circuit. The automatic gain correction circuit converts the response currents into a gain output voltage. The oversampling ADC performs low-pass filtering on the gain output voltage using oversampling technology to obtain a digital signal. By directly sampling and digitizing the gain output voltage of the automatic gain correction circuit using the oversampling ADC, large capacitors and resistors are not required, simplifying the signal path, reducing the layout area, and solving the problem of increased cost due to large circuit area, thus meeting the needs of low- to mid-range applications. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of an uncooled infrared readout circuit in related technologies;

[0034] Figure 2 This is a schematic diagram of the framework of an uncooled infrared readout circuit based on oversampling technology provided in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram of an uncooled infrared readout circuit based on oversampling technology provided in an embodiment of this application;

[0036] Figure 4 This is a schematic diagram of another uncooled infrared readout circuit based on oversampling technology provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of another uncooled infrared readout circuit based on oversampling technology provided in the embodiments of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The infrared focal plane array, the core of uncooled infrared imaging technology, consists of two parts: an infrared detector array and a readout circuit. Among them, the microbolometer focal plane array has high sensitivity and is the most widely used type of uncooled infrared focal plane array. Its working principle is that the temperature of the thermosensitive material changes after absorbing incident infrared radiation, which causes a change in its own resistance value. The magnitude of the infrared radiation signal is detected by measuring the change in its resistance value.

[0040] Microbolometers commonly employ a cantilever beam microbridge structure fabricated using micromachining technology. The bridge surface is deposited with a thermistor material possessing a high temperature coefficient of resistance (TCR). The bridge surface is supported by two legs with good mechanical properties and coated with conductive material. The contact points between the legs and the substrate serve as piers, which are electrically connected to the silicon readout integrated circuit (ROIC) beneath the microbolometer. Through the legs and piers, the thermistor material is connected to the electrical channels of the readout circuit, forming a temperature-sensitive pixel unit connected to the readout circuit.

[0041] Microbolometers are classified into three types according to their functions: sensitive pixel R s Thermal short circuit pixel R d and the occluded pixel R shd Sensitive pixel R s It can detect target radiation, while thermally short-circuited pixel R d The bridge surface and substrate are thermally short-circuited, and the temperature remains constant equal to the substrate temperature; the blocked pixel R shd Its structure is exactly the same as that of a sensitive microbolometer, but due to obstruction, it cannot sense target radiation. It utilizes the thermally short-circuited pixel R... d and the occluded pixel R shd It can effectively offset the output voltage fluctuation caused by the change in the resistance of sensitive pixels with the substrate temperature, and realize the TEC-free (Thermoelectric Cooler) function.

[0042] The function of the readout circuit is to provide the sensitive pixel R sIt provides the drive, filters and amplifies the induced current, and sequentially reads the output signal off-chip. The readout circuitry directly affects the detector's critical performance and determines the user interface, making it a key component of uncooled infrared detectors.

[0043] However, users have increasingly higher requirements for uncooled infrared detectors, demanding not only high performance but also low cost, low power consumption, digitalization, and ease of use.

[0044] To reduce noise, the detector needs to maximize the integration time. For example, such as... Figure 1 As shown, an uncooled infrared readout circuit is illustrated, including a detector bias circuit 101, an automatic gain control (AGC) circuit 102, an integrator (INT) 103, a sample and hold circuit (S / H) 104, and a Nyquist rate ADC (Analog-to-Digital Converter) 105.

[0045] Specifically, the detector bias circuit 101 supplies power to the sensitive pixel R. s and thermal short circuit image element R d Provide a bias voltage, the difference in current between the two is I sig The output is sent to the automatic gain correction circuit 102, and its gain is R. d2 If the thermal short-circuit pixel resistance is such that the output V of the gain correction circuit 102 is... o1 It is a voltage that hardly changes with the substrate temperature; then, the integrator can adjust V. o1 Integration is performed, where the integrator is actually a low-pass filter with amplification function, and the output V of integrator 103 is... int After being held by the sample-and-hold circuit 104, the sample-and-hold voltage V can be obtained. sh Sample holding voltage V sh After passing through a Nyquist-rate ADC105, such as a single-ramp ADC, it is converted into a digital signal D. out .

[0046] In such Figure 1 In the uncooled infrared readout circuit shown, the bandwidth of the integrator is Bandwidth is inversely proportional to integration time. To reduce noise, the noise bandwidth needs to be reduced, which means a longer integration time is required. This necessitates larger integrating capacitors and resistors, resulting in a larger layout area and increased circuit cost.

[0047] This application embodiment utilizes an oversampling analog-to-digital converter to directly sample and digitize the gain output voltage of the automatic gain correction circuit. This eliminates the need for large capacitors and resistors, simplifies the signal chain, reduces the layout area, and solves the problem of increased costs due to large circuit area, thus meeting the needs of low-to-mid-range applications.

[0048] Reference Figure 2 The diagram shows a schematic frame of an uncooled infrared readout circuit based on oversampling technology provided in an embodiment of this application.

[0049] Depend on Figure 2 As can be seen, the circuit provided in the embodiments of this application may include a detector bias circuit 201, an automatic gain correction circuit 202, and an oversampling analog-to-digital converter 203. The oversampling analog-to-digital converter 203, namely a Sigma delta ADC, may refer to an analog-to-digital converter that uses oversampling technology.

[0050] Specifically, the detector bias circuit 201 can be used to provide bias voltage to the sensitive pixel and the thermally short-circuited pixel to obtain the response current, and output the response current to the automatic gain correction circuit; the automatic gain correction circuit 202 can be used to convert the response current into a gain output voltage; the oversampling ADC 203 can be used to perform low-pass filtering on the gain output voltage using oversampling technology to obtain a digital signal.

[0051] Optionally, the detector bias circuit 201 supplies power to the sensitive pixel R. s and thermal short circuit image element R d Provide a bias voltage and respond with a current I sig Output to the back end; the automatic gain correction circuit 202 can adaptively respond to the current I. sig The response current I changes with the substrate temperature. sig Converted into a gain output voltage V that is almost independent of substrate temperature o1 The oversampling ADC 203 can process the aforementioned input signal, i.e., the gain output voltage V. o1 Low-pass filtering typically involves averaging to reduce noise. The output V of the automatic gain correction circuit... o1 Since it is already a voltage, and the Sigma delta ADC has the function of averaging the input signal, the readout circuit provided in this application embodiment can directly use the Sigma delta ADC to measure the output V of the automatic gain correction circuit. o1 Sampling and digitization simplify signal links and reduce the footprint.

[0052] It should be noted that, in order to ensure the noise reduction effect, the Sigma delta ADC can adopt a first-order structure; the Sigma delta ADC can be a conventional structure or an incremental structure, and the embodiments of this application do not limit the structure adopted by the Sigma delta ADC.

[0053] In some embodiments of this application, reference is made to Figure 3 This illustration shows a schematic diagram of an uncooled infrared readout circuit based on oversampling technology according to an embodiment of this application. This embodiment mainly illustrates the circuit configuration when a mirror circuit is used to generate the bias voltage in the detector bias circuit.

[0054] Specifically, when the detector bias circuit 201 uses a mirror circuit to generate the bias voltage, the automatic gain correction circuit 202 is composed of a transimpedance amplifier made up of operational amplifiers, and the oversampling analog-to-digital converter 203 can adopt a fully differential first-order circuit structure.

[0055] Optionally, the mirror circuit can consist of a reference branch and a mirror branch, and a non-uniformity correction circuit exists at the coupling node between the detector output signal and the bias circuit.

[0056] For example, such as Figure 3 As shown, the reference branch is characterized by the first source series resistance R. sn One end of the transistor is grounded, and the other end is connected to the source terminal of the field-effect transistor M4; the drain terminal of the field-effect transistor M4 is connected to the drain terminal of the field-effect transistor M3; the source terminal of the field-effect transistor M3 is connected to an adjustable resistor R. trn The second source series resistor R dn The second source series resistor R dn The other end is connected to an external bias voltage Vsk. The topology of the mirror branch is a mirror pair with that of the reference branch, and it is represented by the sensitive cell R. s One end of the transistor is grounded, and the other end is connected to the source terminal of the field-effect transistor M1; the gate voltage V of the field-effect transistor M1 is... fid The bias circuit Bias provides the current; the drain of MOSFET M1 is connected to the drain of MOSFET M2, which is also the source of the induced current I. sig The output terminal, let's assume it's named V. agc The gate voltage Veb of MOSFET M2 is also provided by the bias circuit Bias; the source terminal of MOSFET M2 is connected to an adjustable resistor R. tr Thermal short-circuit resistor R d Thermal short-circuit resistance R d The other end is connected to an external bias voltage Vsk. The connection point between the drain terminals of MOSFET M1 and MOSFET M2 in the mirror branch serves as the output terminal, generating a bias voltage.

[0057] The gate voltage Veb of MOSFET M3 is provided by the bias circuit Bias. At Veb, i.e., the connection node between MOSFETs M3 and M2, non-uniformity correction circuits Eocc and Emocc can be added to pull the output value when there is no signal to the target value, such as around 8192, to ensure the consistency of the array output. MOSFET M4 in the reference branch is connected to MOSFET M1 in the mirror branch through the PJC (Joule Heating Compensation Circuit) module.

[0058] In this embodiment, the aspect ratio of the resistors and MOSFETs (e.g., field-effect transistors M1, M2, M3, and M4) in the mirror circuit is 10 to 40 times that of the readout channel, thereby stabilizing the bias voltage. In other words, the mirror circuit can provide a stable bias voltage for the detector by utilizing the current / voltage mirroring characteristics.

[0059] Optionally, the automatic gain correction circuit is a transimpedance amplifier with an operational amplifier, whose transimpedance gain can be determined based on the thermally short-circuited pixel resistance, specifically, the transimpedance gain is equal to the thermally short-circuited pixel resistance R. d2 Furthermore, the reference bias voltage can be connected to the non-inverting input of the operational amplifier in the automatic gain correction circuit through the non-uniformity correction circuit.

[0060] For example, such as Figure 3 As shown, the automatic gain correction circuit exhibits thermal short-circuit behavior in pixel R. d2 With capacitor C f The parallel circuit forms an RC feedback network; the reference bias voltage Vref is connected to the non-inverting input of the op-amp through the non-uniformity correction circuit Foce; V agc The node input is connected to the inverting input of the op-amp, and a portion of the signal is fed back to the inverting input of the op-amp through the aforementioned RC feedback network to form negative feedback, which is used to stabilize the gain and bandwidth; the gain output voltage V ol The transimpedance amplifier converts the detector's current signal into a voltage signal, and the thermally short-circuited pixel resistance R... d2 The gain is determined by the combination of the non-uniformity correction circuit Foce and the reference bias voltage Vref, which correct the signal amplitude of different pixels to ensure the subsequent output V. ol The amplitude consistency ensures a stable input signal for the subsequent ADC.

[0061] Optional, such as Figure 3As shown, the fully differential first-order circuit structure used in the Sigma delta ADC can include a switched capacitor integrator (SC_int) 21, a comparator (Comp_Coarse Tuning, Comp_CT) 22 and a data flip-flop (DFF) 23, as well as a digital processing module (DSP) 24.

[0062] In this embodiment, the ADC adopts an architecture of "switched capacitor integration + time comparison + digital post-processing", and with non-overlapping clocks, it can achieve analog-to-digital conversion with different precision.

[0063] In some embodiments of this application, the gain output voltage and the reference bias voltage can be sampled and quantized by a Sigma delta ADC as positive and negative input signals, respectively, and the difference between them is converted into a digital signal.

[0064] Specifically, the switched capacitor integrator 21 can be used to control the sampling capacitor in the switched capacitor integrator to sample or integrate the signal through the digital feedback signals of the clock and the flip-flop to obtain the feedback voltage; the comparator 22 can be used to obtain the differential signal based on the feedback voltage, that is, the output of the comparator 22 changes with the output of the switched capacitor integrator 21; the flip-flop 23 can be used to convert the differential signal into a single-ended signal, and the single-ended signal serves as the digital feedback signal; the digital processing module 24 can be used to downsample the single-ended signal to obtain a digital signal.

[0065] For example, such as Figure 3 As shown, the clock consists of two non-overlapping phases: a first clock φ1 and a second clock φ2, meaning that the first clock φ1 and the second clock φ2 are not effective simultaneously. The topology of the switched-capacitor integrator SC_int includes an operational amplifier, a sampling capacitor Cs, and a switch controlled by the first clock φ1 and the second clock φ2, connected to V. ol (AGC output), Vref, VrefL (preset first threshold, which is the maximum value of the ADC reference voltage, such as 3V), VrefL (preset second threshold, which is the minimum value of the ADC reference voltage, such as 1V).

[0066] The gain output voltage is connected to the first switch controlled by the first clock φ1, and the first switch is connected to the differential switch network; one end of the sampling capacitor Cs is connected to the output of the differential switch network, and the other end is controlled by the second clock φ2 switch and the feedback capacitor C. F And connect the non-inverting and inverting input terminals of the op-amp; feedback capacitor C F Connected to the op-amp input.

[0067] In some embodiments of this application, when the detector bias circuit uses a mirror circuit to generate the bias voltage, the comparator can be a continuous-time comparator, and the switched-capacitor integrator SC_int and the continuous-time comparator Comp_CT are connected via a switch controlled by a second clock φ2.

[0068] Optionally, when the first clock φ1 is active, it indicates that the sampling phase is in progress. The switch controlled by the second clock φ2 is open, and the preceding signal can be coupled to the sampling capacitor. This is manifested as one end of the sampling capacitor Cs being connected to the common-mode voltage V through the switch controlled by the second clock φ2. cm The other end is connected to the gain output voltage V via a switch controlled by the second clock φ2. o1 The signal is sampled using the reference bias voltage Vref, and the output of the switched capacitor integrator remains unchanged during this process.

[0069] When the second clock φ2 is active, it indicates that the integration phase is underway. The switch controlled by the second clock φ2 is closed, and the signal charge stored in the sampling capacitor Cs is transferred to the inverting input of the operational amplifier through the switch controlled by the second clock φ2, resulting in an output feedback voltage. Specifically, this can be manifested as the signal being transferred to the feedback capacitor Cs. F The operational amplifier passes through the feedback capacitor C. F The negative feedback automatically adjusts the output to obtain a new output by accumulating the output with the sampled value, thereby realizing integral operation.

[0070] The continuous-time comparator Comp_CT and the flip-flop DFF are responsible for converting the integrated analog signal into a digital timing signal. The flip-flop DFF receives the differential output V of the continuous-time comparator Comp_CT. cmp V cmn It is converted into a single-ended signal d through internal logic, and the single-ended signal d serves as a digital feedback signal.

[0071] The digital feedback signal output by the flip-flop DFF changes with the edge of the first clock φ1, that is, it only changes at the rising or falling edge of the first clock φ1.

[0072] Optionally, if the digital feedback signal d output by the flip-flop DFF is high (i.e., 1), then the sampling capacitor C... s The positive terminal can be switched to the maximum value VrefH and the minimum value VrefL of the ADC reference voltage, respectively; if the digital feedback signal d output by the flip-flop DFF is low (i.e., 0), then the sampling capacitor C s The positive terminal can be switched to the minimum value VrefL of the ADC reference voltage and the maximum value of the ADC reference voltage, respectively, to mark the signal exceeding the upper or lower limit based on the charge difference.

[0073] When the digital feedback signal d is high, there is a sampling capacitor C.s The positive charge difference indicates that the signal exceeds the upper limit, and upper limit calibration can be performed, for example, by clipping the signal to the maximum value of the ADC reference voltage VrefH, such as 3V; when the digital feedback signal d is low, there is a sampling capacitor C. s If the positive terminal charge difference is a negative charge difference, it means that the signal exceeds the lower limit and lower limit calibration can be performed. For example, the signal can be raised to the minimum value of the ADC reference voltage, VrefL, such as 1V.

[0074] It should be noted that adjusting the signal at the positive terminal of the sampling capacitor Cs will affect the output of the switched capacitor integrator SC_int, thereby affecting the output of the continuous-time comparator Comp_CT.

[0075] The digital processing module (DSP) performs noise reduction and downsampling on the single-ended digital signal d to output the final digital signal D. out Specifically, this can be manifested as the digital processing module (DSP) directly receiving the single-ended digital signal d, and then, through its internal processing links, including digital filters (such as sinc filters) and downsampling units, downsampling d using an oversampling rate M. The downsampled signal is the final digital signal D. out It should be noted that the digital signal D out The signal frequency can be determined based on the oversampling rate M, which is typically 1 / M; each V ol The pulse width is the time of one line. In order to increase the noise reduction effect, the oversampling M can take a relatively large value, such as 128, 256, 512, etc. This application embodiment does not limit this.

[0076] In some embodiments of this application, reference is made to Figure 4 This illustration shows another uncooled infrared readout circuit based on oversampling technology provided in this application embodiment. This embodiment mainly illustrates the circuit configuration when the detection bias circuit does not use a mirror circuit to generate the bias voltage.

[0077] Specifically, when the bias circuit 201 does not use a mirror circuit to generate the bias voltage, the automatic gain correction circuit 202 can use a transimpedance network and a buffer composed of thermally short-circuited pixel resistors and capacitors to output the gain output voltage, and the oversampling analog-to-digital converter 203 can use a fully differential first-order circuit structure.

[0078] Optionally, since the detection bias circuit 201 does not use a mirror circuit, external bias voltages Vsk, Veb, and V are required. fid A relatively large capacitor, such as 4.7uF, is connected to Vref; the automatic gain correction circuit 202 can detect the induced current I. sig After thermal short-circuiting, the pixel resistor R 2d and capacitor C fThe transresistance network formed will convert the induced current I sig The voltage is converted to voltage, and then buffered by buffer buf1 to enhance the load-driving capability of the transimpedance network, thereby increasing the output gain voltage V. ol Among them, the thermal short-circuit pixel resistance R 2d and R d Similarly, it can convert the response current I sig Converted to an output voltage V with almost no temperature coefficient o1 Capacitor C f Used for low-pass filtering, the filter size is determined by the line time.

[0079] The ADC used in this embodiment is a single-ended input first-order sigma delta ADC, but it can also be a similar ADC. Figure 3 The same structure can be described in detail in the above-mentioned content, and the embodiments of this application will not be repeated here.

[0080] For example, such as Figure 4 As shown, it includes the input analog signal V ol (Output from AGC, single-ended signal, in G) NDA (For reference ground), two sampling capacitors (usually of equal value, used for charge sampling and transfer), multiple sets of clock control switches (controlled by two non-overlapping clocks, the first clock φ1 and the second clock φ2, and the feedback digital signal d), a comparator (single-ended input, output high and low levels), a D flip-flop (DFF, data terminal connected to the comparator output, clock terminal connected to the falling edge of φ1), and an analog power supply V. DDA Simulated ground G NDA Two non-overlapping clocks, φ1 and φ2 (the first clock φ1 and the second clock φ2 are not effective at the same time to avoid the switch being turned on at the same time).

[0081] When the bias circuit does not use a mirror circuit to generate the bias voltage, the comparator can be a discrete-time comparator Comp_DT or something similar. Figure 3 The continuous-time comparator Comp_CT shown in this application embodiment is not limited thereto.

[0082] This embodiment uses a discrete-time comparator as an example. The switched-capacitor integrator SC_int and the discrete-time comparator Comp_DT are connected via a switch controlled by the second clock φ2. A sampling capacitor C is connected to the non-inverting input of the discrete-time comparator Comp_DT. s The lower plate of the discrete-time comparator Comp_DT is connected to another sampling capacitor C. s The lower electrode plate.

[0083] Optionally, when the first clock φ1 is active, indicating that the sampling phase is underway, the switch controlled by the second clock φ2 is open, and a sampling capacitor C... s Acquired gain output voltage V ol Another sampling capacitor C s Based on the digital feedback signal d output by the flip-flop DFF connected to the discrete-time comparator Comp_DT, the analog positive power supply voltage V is collected respectively. DDA Or simulated ground voltage G NDA .

[0084] When the second clock φ2 is active, it indicates that the integration phase is in progress. The switch controlled by the second clock φ2 is closed, and the sampling capacitor C... s The positive terminal is switched to the analog positive power supply voltage V according to the digital feedback signal d output by the flip-flop DFF connected to the discrete-time comparator Comp_DT. DDA Or simulated ground voltage G NDA Another sampling capacitor C s The positive terminal is switched to the gain output voltage V. ol .

[0085] The flip-flop DFF samples the signal at the falling edge of the first clock φ1. The DSP can then downsample the signal sampled at the falling edge of the flip-flop DFF to obtain the final output digital signal D. out The discrete-time comparator Comp_DT is reset when the second clock φ2 is valid. At this time, the output of the switched capacitor integrator SC_int does not affect the output of the discrete-time comparator Comp_DT. The first clock φ1 is invalid, and the output of the flip-flop DFF remains unchanged. The discrete-time comparator Comp_DT works normally when the second clock φ2 is invalid.

[0086] In some embodiments of this application, reference is made to Figure 5 This illustration shows a schematic diagram of another uncooled infrared readout circuit based on oversampling technology provided in this application embodiment. This embodiment mainly illustrates the circuit configuration when the detector bias circuit and automatic gain correction circuit are combined.

[0087] Specifically, when the detector bias circuit 201 and the automatic gain correction circuit 202 are combined, a differential voltage can be output. The differential voltage is then processed by the switched capacitor integrator 21 and the comparator 22 to obtain a digital signal.

[0088] Optionally, the detector bias and AGC circuit integrate detector bias and automatic gain correction through active device matching and feedback mechanisms, outputting a differential voltage V. bs and V bsm Due to voltage V bs and V bsmSince it hardly changes with the substrate temperature, the Sigma delta ADC can directly acquire the difference between Vbs and Vbsm to obtain the response signal. This response signal is the signal sampled by the oversampling ADC. Specifically, the response signal can be sampled once per φ1 and φ2 cycle, and a total of M samples are taken per row.

[0089] It should be noted that, Figure 5 The switched capacitor integrator SC_int in the middle can be used with Figure 3 The integrators in the same way; Figure 5 If a discrete-time comparator is used in the comparator, it can be compared with... Figure 4 The comparator in the previous section is the same; if a continuous-time comparator is used, it can be compared with... Figure 3 The comparator is the same as that in the present application, and will not be described in detail here.

[0090] This embodiment uses a discrete-time comparator as an example. Multiple sets of clock-controlled switches are connected between the switched-capacitor integrator SC_int and the discrete-time comparator Comp_DT. These switches are turned on and off according to the clock sequence, realizing the transfer of charge between capacitors and thus completing the integration operation. The multiple sets of clock-controlled switches may include switches controlled by a first clock φ1 and switches controlled by a second clock φ2. The two phases of the first clock φ1 and the second clock φ2 do not overlap, meaning that the first clock φ1 and the second clock φ2 are not effective simultaneously. Under the alternating timing of the first clock φ1 and the second clock φ2, the input differential voltage V... bs and V bsm It is converted into a discrete-time integral voltage.

[0091] The discrete-time comparator Comp_DT is reset when the second clock φ2 is valid, that is, the previous state is cleared. At this time, the output of the switched capacitor integrator SC_int does not affect the output of the discrete-time comparator Comp_DT. The first clock φ1 is invalid, and the output of the flip-flop DFF remains unchanged. The discrete-time comparator Comp_DT works normally when the second clock φ2 is invalid, performs threshold comparison on the switched capacitor integrator SC_int, and outputs high and low levels.

[0092] Optional, such as Figure 5 As shown, the discrete-time comparator 22 is also connected to a clocked latch (i.e., CLK_latch) 25. The clocked latch CLK_latch is specifically composed of a latch circuit and a first clock φ1 control terminal. When the first clock φ1 is valid, the output of the clocked latch CLK_latch is updated according to the output of the discrete-time comparator Comp_DT; when the first clock φ1 is invalid, the output of the clocked latch CLK_latch remains unchanged, so as to latch the discrete comparison result of the comparator into a stable digital signal, providing a timing-stable digital stream for subsequent DSP processing.

[0093] The digital processing module (DSP) processes the digital stream and ultimately outputs a high-precision multi-digit digital signal D. out .

[0094] In this embodiment, by using an oversampling analog-to-digital converter to directly sample and digitize the gain output voltage of the automatic gain correction circuit, large capacitors and resistors are not required, which simplifies the signal link, reduces the layout area, solves the problem of increased cost due to large circuit area, and meets the needs of low-end and mid-range applications.

[0095] This application also provides an uncooled infrared detector device, including the uncooled infrared readout circuit based on oversampling technology from the foregoing embodiments. It should be noted that the location of the uncooled infrared readout circuit based on oversampling technology in the infrared detector device can be adaptively configured according to the needs of the actual application scenario, and this application does not impose any limitations on this.

[0096] In the embodiments of this application, the uncooled infrared readout circuit included in the uncooled infrared detector device directly samples and digitizes the gain output voltage of the automatic gain correction circuit by using an oversampling analog-to-digital converter. This eliminates the need for large capacitors and resistors, simplifies the signal link, reduces the layout area, solves the problem of increased cost due to large circuit area, and meets the needs of low- and mid-range applications.

[0097] This application also provides an electronic device with infrared detection capabilities, including the uncooled infrared detector device described in the foregoing embodiments.

[0098] In the embodiments of this application, the uncooled infrared readout circuit in the uncooled infrared detector device included in the electronic device directly samples and digitizes the gain output voltage of the automatic gain correction circuit by using an oversampling analog-to-digital converter. This eliminates the need for large capacitors and resistors, simplifies the signal link, reduces the layout area, solves the problem of increased cost due to large circuit area, and meets the needs of low- and mid-range applications.

[0099] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0100] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products, or devices. The division of modules in the embodiments of this application is merely a logical division; in actual applications, there may be other division methods. For example, multiple modules may be combined into or integrated into another system, or some features may be ignored or not performed. Additionally, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interface, and the indirect coupling or communication connection between modules may be electrical or other similar forms, none of which are limited in the embodiments of this application. Furthermore, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed among multiple circuit modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of this application.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0102] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this application to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. An uncooled infrared readout circuit based on oversampling technology, characterized in that, The circuit includes a detector bias circuit, an automatic gain correction circuit, and an oversampling analog-to-digital converter; The detector bias circuit is used to provide bias voltage to the sensitive pixel and the thermally short-circuited pixel to obtain a response current, and outputs the response current to the automatic gain correction circuit. The automatic gain correction circuit is used to convert the response current into a gain output voltage; The oversampling analog-to-digital converter is used to perform low-pass filtering on the gain output voltage using oversampling technology to obtain a digital signal.

2. The circuit according to claim 1, characterized in that, When the detector bias circuit uses a mirror circuit to generate the bias voltage, the automatic gain correction circuit is composed of a transimpedance amplifier composed of operational amplifiers, and the oversampling analog-to-digital converter adopts a fully differential first-order circuit structure. The mirror circuit consists of a reference branch and a mirror branch, and a non-uniformity correction circuit exists at the coupling node between the detector output signal and the bias circuit; the transimpedance gain of the automatic gain correction circuit is determined based on the thermal short-circuit pixel resistance, and the reference bias voltage is connected to the non-inverting input terminal of the operational amplifier in the automatic gain correction circuit through the non-uniformity correction circuit.

3. The circuit according to claim 1, characterized in that, When the bias circuit does not use a mirror circuit to generate the bias voltage, the automatic gain correction circuit uses a transimpedance network and a buffer composed of thermally short-circuited pixel resistors and capacitors to output the gain output voltage, and the oversampling analog-to-digital converter uses a fully differential first-order circuit structure.

4. The circuit according to claim 2 or 3, characterized in that, The fully differential first-order circuit structure includes a switched capacitor integrator, a comparator and a flip-flop, and a digital processing module. The switched capacitor integrator is used to control the sampling capacitor in the switched capacitor integrator to sample or integrate signals to obtain a feedback voltage by means of a clock and the digital feedback signal of the flip-flop. The comparator is used to obtain a differential signal based on the feedback voltage; The trigger is used to convert the differential signal into a single-ended signal, and the single-ended signal serves as the digital feedback signal; The digital processing module is used to downsample the single-ended signal to obtain the digital signal.

5. The circuit according to claim 4, characterized in that, The clock includes a first clock and a second clock that do not overlap; when the detector bias circuit uses a mirror circuit to generate the bias voltage, the comparator is a continuous-time comparator, and the switched-capacitor integrator is connected to the continuous-time comparator via a switch controlled by the second clock. When the first clock is valid, the switch controlled by the second clock is turned off. One end of the sampling capacitor is connected to the common-mode voltage through the switch controlled by the second clock, and the other end is connected to the gain output voltage and the reference bias voltage through the switch controlled by the second clock for signal sampling. When the second clock is active, the switch controlled by the second clock is closed, and the signal charge stored in the sampling capacitor is transferred to the inverting input terminal of the operational amplifier through the switch controlled by the second clock, thus outputting the feedback voltage.

6. The circuit according to claim 5, characterized in that, The digital feedback signal output by the trigger changes with the edge of the first clock. If the digital feedback signal output by the trigger is high, the positive terminal of the sampling capacitor is switched to the preset first threshold and the preset second threshold respectively; if the digital feedback signal output by the trigger is low, the positive terminal of the sampling capacitor is switched to the preset second threshold and the preset first threshold respectively.

7. The circuit according to claim 4, characterized in that, The clock includes a first clock and a second clock that do not overlap; when the bias circuit does not use a mirror circuit to generate the bias voltage, the comparator is a discrete-time comparator, the switched capacitor integrator is connected to the discrete-time comparator via a switch controlled by the second clock, the non-inverting input of the discrete-time comparator is connected to the lower plate of a sampling capacitor, and the inverting input of the discrete-time comparator is connected to the lower plate of another sampling capacitor. When the first clock is valid, the switch controlled by the second clock is turned off, the first sampling capacitor collects the gain output voltage, and the other sampling capacitor collects the analog positive power supply voltage or the analog ground voltage respectively according to the digital feedback signal output by the flip-flop connected to the discrete time comparator. When the second clock is active, the switch controlled by the second clock is closed, and the positive terminal of the sampling capacitor is switched to either the analog positive power supply voltage or the analog ground voltage according to the digital feedback signal output by the flip-flop connected to the discrete time comparator. The positive terminal of the other sampling capacitor is switched to the gain output voltage. The discrete-time comparator is reset when the second clock is valid, and operates normally when the second clock is invalid; the flip-flop samples at the falling edge of the first clock.

8. The circuit according to claim 1, characterized in that, When the detector bias circuit and the automatic gain correction circuit are combined, a differential voltage is output, and the differential voltage is processed by a switched capacitor integrator and a discrete-time comparator to obtain the digital signal; wherein, there are multiple sets of clock-controlled switches connected between the switched capacitor integrator and the discrete-time comparator.

9. The circuit according to claim 8, characterized in that, The multiple sets of clock control switches include switches controlled by a first clock and switches controlled by a second clock, wherein the two phases of the first clock and the second clock do not overlap. The discrete-time comparator is also connected to a clock latch; the output of the clock latch is updated according to the output of the discrete-time comparator when the first clock is valid, and the output of the clock latch remains unchanged when the first clock is invalid.

10. An uncooled infrared detector device, characterized in that, Includes an uncooled infrared readout circuit based on oversampling technology as described in any one of claims 1 to 9.

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