An intelligent generation system of a vector simulation gating-based amplitude modulation signal source scheme

Abstract

The application relates to the technical field of chip intelligent testing, in particular to an amplitude modulation signal source scheme intelligent generation system based on vector simulation gating, which comprises a data acquisition module used for acquiring a response characteristic vector of a chip to be tested; a state inference module used for inferring an underlying state vector based on the response characteristic vector and a preset probability agent model; a risk calculation module used for calculating an uncertainty index based on the underlying state vector and a preset risk weight coefficient; a risk judgment module used for judging the risk level of the chip to be tested according to the uncertainty index and a preset risk threshold; a resource allocation module used for allocating a calculation time budget according to the risk level; a scheme generation module used for determining an optimal test scheme from a preset candidate scheme library within the calculation time budget; and a test execution module used for executing the optimal test scheme; and the application avoids wasting unnecessary time on a large number of healthy chips and significantly improves resource utilization efficiency.

Description

Technical Field

[0001] This invention relates to the field of intelligent chip testing technology, specifically to an intelligent generation system for an amplitude modulation signal source scheme based on vector analog gating. Background Technology

[0002] In the mass production of integrated circuits, chip testing is a core link to ensure product quality and reliability. However, traditional testing methods generally face an inherent contradiction between testing accuracy and testing efficiency. To ensure high coverage and high accuracy, testing schemes often require a lot of time, which directly affects the overall throughput of the production line. Conversely, reducing testing time may lead to the missed detection of abnormal chips, resulting in quality risks.

[0003] Existing testing technologies suffer from the following limitations: Traditional methods employ a uniform and fixed testing process and resource allocation for all chips under test. This one-size-fits-all approach fails to identify and address individual chip variations caused by factors such as manufacturing process drift. Furthermore, the inability to perceive the internal state of individual chips in real time leads to inefficient resource allocation due to static strategies. Many healthy chips consume unnecessary in-depth testing time, while a few potentially risky chips may not be adequately diagnosed due to time constraints. The rigid trade-off between accuracy and efficiency forces production lines to make static, compromised choices between testing accuracy and production efficiency, failing to achieve a dynamic balance. This makes it difficult to accurately and deeply diagnose a small number of high-risk abnormal chips without sacrificing overall production line throughput. Therefore, current technology urgently needs an intelligent solution generation system capable of sensing the individual chip state in real time and dynamically and differentiatedly allocating testing resources accordingly. This would break the static trade-off between testing speed and accuracy, achieving optimal production efficiency and product quality. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an intelligent generation system for amplitude modulation signal sources based on vector analog gating. Specifically, the technical solution of this invention includes:

[0005] A smart generation system for amplitude modulation signal source schemes based on vector analog gating includes:

[0006] The data acquisition module is used to acquire the response feature vector of the chip under test;

[0007] The state inference module is used to infer the potential state vector based on the response feature vector and the preset probabilistic proxy model.

[0008] The risk calculation module is used to calculate the uncertainty index based on the potential state vector and preset risk weight coefficients;

[0009] The risk assessment module is used to determine the risk level of the chip under test based on the uncertainty index and the preset risk threshold.

[0010] The resource allocation module is used to allocate the computation time budget according to the risk level;

[0011] The scheme generation module is used to determine the optimal test scheme from a pre-set candidate scheme library within the computation time budget.

[0012] The test execution module is used to execute the optimal test plan.

[0013] Preferably, the probabilistic proxy model is a deep encoder network trained offline, which receives the response feature vector as input and outputs the latent state vector.

[0014] Preferably, the risk calculation module is used for:

[0015] Multiply each component of the potential state vector by its corresponding risk weight coefficient;

[0016] The uncertainty index is obtained by performing square root and square root operations on the product.

[0017] Preferably, the risk assessment module is used for:

[0018] When the uncertainty index is greater than the high-risk threshold, the risk level is classified as high.

[0019] When the uncertainty index is between the low-risk threshold and the high-risk threshold, the risk level is determined to be medium.

[0020] When the uncertainty index is less than or equal to the low-risk threshold, the risk level is determined to be low.

[0021] Preferably, the resource allocation module is used for:

[0022] Invoke the budget multiplier tied to the risk level;

[0023] The calculation time budget is determined based on the product of the budget multiplier and the baseline calculation time.

[0024] Preferably, the process by which the solution generation module determines the optimal test solution includes:

[0025] The diagnostic value of each candidate test solution is determined based on the uncertainty index calculated by the risk calculation module, the inherent diagnostic sensitivity coefficient of each candidate test solution in the candidate solution library, and the estimated execution time.

[0026] Preferably, it further includes:

[0027] The diagnostic value of each candidate test plan is divided by the corresponding estimated execution time to calculate the information utility.

[0028] Preferably, it further includes:

[0029] Within the time budget, the candidate test plan with the greatest information utility is selected as the optimal test plan.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. This system realizes the transformation from static unified testing to dynamic adaptive testing. By acquiring and analyzing the response characteristics of each chip under test in real time, it infers its unique internal state and builds a closed-loop control system from state perception to resource allocation. It can dynamically adjust the testing strategy according to the individual differences of the chips, overcoming the limitations of the traditional one-size-fits-all approach.

[0032] 2. This system achieves precise and differentiated configuration of test resources. Based on the real-time calculated uncertainty index, it determines the risk level of the chip and allocates differentiated computing time budgets to chips with different risk levels. It prioritizes the use of limited test resources for in-depth diagnosis of a few high-risk chips, avoiding unnecessary time wasted on a large number of healthy chips and significantly improving resource utilization efficiency.

[0033] 3. This system effectively solves the inherent contradiction between testing accuracy and testing efficiency. By performing refined and long-term diagnosis of high-risk chips and rapid screening of low-risk chips, it significantly improves the detection accuracy and coverage of abnormal chips without sacrificing the overall throughput of the production line, and successfully breaks the rigid trade-off between speed and accuracy in traditional testing.

[0034] 4. This system transforms the selection of test schemes into an intelligent and efficient optimization process. By introducing quantitative evaluation indicators of diagnostic value and information utility, it can scientifically select the test scheme with the highest information acquisition efficiency from many candidate schemes within a given time budget, so that every test decision tends to be optimized, realizing the transformation from blindly pursuing accuracy to intelligently pursuing utility. Attached Figure Description

[0035] The present invention will be further explained below with reference to the accompanying drawings and embodiments:

[0036] Figure 1 This is a structural diagram of the system of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0038] Example 1:

[0039] Please see Figure 1 A smart generation system for amplitude modulation signal source scheme based on vector analog gating, characterized in that it includes:

[0040] The data acquisition module is used to acquire the response feature vector of the chip under test;

[0041] The state inference module is used to infer the potential state vector based on the response feature vector and the preset probabilistic proxy model.

[0042] The risk calculation module is used to calculate the uncertainty index based on the potential state vector and preset risk weight coefficients;

[0043] The risk assessment module is used to determine the risk level of the chip under test based on the uncertainty index and the preset risk threshold.

[0044] The resource allocation module is used to allocate the computation time budget according to the risk level;

[0045] The scheme generation module is used to determine the optimal test scheme from a pre-set candidate scheme library within the computation time budget.

[0046] The test execution module is used to execute the optimal test plan.

[0047] This invention provides an intelligent generation system for amplitude modulation signal source schemes based on vector analog gating. The system constructs a complete, adaptive closed-loop control system from chip state perception to dynamic allocation of test resources, aiming to solve the contradiction between test accuracy and test efficiency in traditional test methods.

[0048] This invention uses an amplitude modulation signal source test scheme as an example for illustration. Different test schemes correspond to different signal source configurations and gating measurement strategies. However, the intelligent generation method proposed in this system is universal and can also be applied to other types of chip test scenarios. For example, a specific 110GHz upconversion module's main function is to receive the host's local oscillator signal, such as 22.3GHz~37GHz, and multiply it to the required frequency band, such as 67~110GHz, through a frequency multiplier. At the same time, it receives the host's IQ signal to achieve IQ vector modulation function from 67GHz to 110GHz, or selects analog source output. This module filters out spurious signals generated by frequency multiplication through a gating filter module composed of filter banks and switches, and autonomously selects vector modulation or analog modulation function through switch gating. Its output signal goes through multiple stages, such as a 3-stage dynamic module, to achieve a wide dynamic range, such as 90dB dynamic control. Finally, the power amplifier module and ALC ensure precise control of the output power.

[0049] The vector analog gating described in this invention refers to a high-dimensional chip response feature extraction technology. Specifically, it does not use traditional full waveform acquisition or single-point measurement. Instead, under the excitation of the test signal, it uses high-speed hardware synchronous control to sample the analog output signal of the chip in parallel and at high speed in multiple preset, discrete key time windows or frequency domain windows. The sampled values ​​of these windows are combined into a high-dimensional response feature vector r. Here, the vector is reflected in the feature set composed of multi-window parallel sampling, and analog gating refers to the process of accurately gating and measuring the analog signal at a specific node.

[0050] Different test schemes correspond to different vector analog gating strategies, such as the position, number, and width of the gating window. The core of this system is to intelligently generate the optimal combination of gating strategies to diagnose the chip status most efficiently. In the 110GHz amplitude modulation signal source hardware scheme, this gating strategy is specifically reflected in the precise control of a series of internal high-speed RF switches SPDT. For example, the switches select different filter paths, select whether the signal enters the IQ vector modulation module or is directly used as an analog source output, and control the signal to pass through cascaded dynamic attenuation modules.

[0051] The system comprises a data acquisition module, a state inference module, a risk calculation module, a risk assessment module, a resource allocation module, a solution generation module, and a test execution module. The data acquisition module aims to acquire raw data that characterizes the intrinsic quality of the chip under test. It applies a preset, standardized, minimalist probe signal to the chip and uses a specific vector simulation gating strategy to collect the chip's feedback performance response parameters. The response feature vector r, a high-dimensional vector organized from these response parameters, serves as the logical starting point for the entire intelligent decision-making process and is obtained in real-time through test hardware acquisition. The state inference module aims to transform the high-dimensional, observable chip response into a low-dimensional intrinsic state that reveals potential drifts in the manufacturing process.

[0052] Probabilistic surrogate model f E It is a deep neural network model that has been trained and solidified offline using massive amounts of historical chip test data. Its function is to establish a nonlinear mapping relationship from the response feature vector r to the latent state vector z. The module receives the response feature vector r as input, performs forward calculation through a probabilistic surrogate model, and infers the latent state vector z. Each dimension of the vector is designed to correspond to a relatively independent manufacturing process drift mode, thus forming a digital profile of the chip's intrinsic quality.

[0053] The purpose of the risk calculation module is to quantify the degree to which the chip deviates from the ideal state based on the inferred potential state; this module is based on the input potential state vector z and a set of preset risk weight coefficients. Calculate the uncertainty index of a single scalar. The purpose of the risk assessment module is to transform continuous risk indicators into discrete risk levels that are easy to use for subsequent strategy invocation; this module is based on the uncertainty index. With preset risk thresholds, including high-risk thresholds and low risk threshold The risk level L of the chip under test is determined as high, medium or low;

[0054] The purpose of the resource allocation module is to achieve differentiated and dynamic allocation of computing resources based on the risk level of the chip; this module allocates a corresponding computing time budget for the subsequent solution generation stage based on the risk level L. Allocate more computing time to chips with higher risk levels;

[0055] The purpose of the solution generation module is to determine the test solution with the highest information acquisition efficiency under given resource constraints; this module calculates the time budget. Internally, from a pre-defined candidate solution library The search and evaluation process is conducted to ultimately determine the optimal test plan. The purpose of the test execution module is to implement the decision results. It is responsible for calling and executing the optimal test plan determined by the plan generation module. That is, the optimal vector simulation gating measurement scheme controls the test hardware to complete the final measurement of the chip;

[0056] This embodiment, through the organic combination of the above modules, can perceive the individual differences of each chip under test in real time and transform them into a dynamic and asymmetric configuration of test resources. Without sacrificing the overall throughput of the production line, it achieves accurate and in-depth diagnosis of a very small number of high-risk abnormal chips, thereby effectively solving the technical contradiction of static trade-off between speed and accuracy.

[0057] Example 2:

[0058] The probabilistic surrogate model is a deep encoder network trained offline, which receives the response feature vector as input and outputs the latent state vector.

[0059] Based on Example 1, the probabilistic proxy model is a digital twin that represents the statistical laws of the entire chip manufacturing process. By mapping the high-dimensional performance space to the low-dimensional potential space, it simplifies the complexity of subsequent risk assessment and decision-making.

[0060] The probabilistic surrogate model is specifically implemented as a deep encoder network f trained offline. ETo build this model, in the offline phase, massive amounts of historical chip test data are collected and processed. This data is used to train the deep encoder network. The training objective is to learn a nonlinear mapping from the observable, high-dimensional chip performance response space to the unobservable, low-dimensional latent state space. After training convergence, the network parameter set of the model is obtained. It is solidified and deployed into the online testing system;

[0061] During online state inference, the deep encoder network receives the real-time response feature vector r provided by the data acquisition module as input and instantaneously calculates and outputs the corresponding low-dimensional latent state vector z; its mathematical expression is as follows: ;

[0062] Where z is the latent state vector, a low-dimensional vector, each dimension of which corresponds to a manufacturing process drift mode, calculated by this module; r is the response feature vector, which is the model input and represents the initial response of the chip under test to the standardized probe signal, acquired by the data acquisition module; f E For deep encoder networks, it is the core model for implementing mapping; The set of network parameters consists of the weights and biases of the deep encoder network. These parameters are obtained through iterative training on millions of historical chip data samples, with the optimization objective of minimizing the reconstruction loss and the potential spatial distribution regularization term.

[0063] By concretizing the probabilistic surrogate model into a deep encoder network, this invention can more profoundly and accurately uncover the nonlinear correlation information hidden behind the response feature vector r, generating a more physically meaningful and discriminative latent state vector z, providing a solid foundation for the accuracy of all subsequent adaptive decisions. In order to cope with novel process drift or defect patterns that have not appeared in historical data, the deep encoder network model adopted by this system supports periodic online or offline retraining to continuously update and iterate its understanding of the statistical laws of the chip manufacturing process, ensuring the long-term effectiveness and robustness of the model.

[0064] Example 3:

[0065] The risk calculation module is used for:

[0066] Multiply each component of the potential state vector by its corresponding risk weight coefficient;

[0067] The uncertainty index is obtained by performing square root and square root operations on the product.

[0068] Based on Example 1, the risk calculation module transforms the multidimensional potential state vector z output by the state inference module into a single metric that can intuitively reflect the overall risk level of the chip, namely the uncertainty index. ;

[0069] The computational logic performed by this module is based on the principle of weighted vector norms within the latent space; its underlying logic lies in the fact that different manufacturing process drift modes have varying degrees of impact on the final chip performance, thus requiring the introduction of risk weight coefficients. Differentiation considerations are taken into account; the calculation process includes dividing the components of the potential state vector. With the corresponding risk weight coefficient Multiply, then perform a square root operation on the product; risk weight coefficient. It is a preset coefficient value that corresponds one-to-one with each component of the potential state vector. Its function is to quantify the correlation between the process drift mode represented by the component and the final chip yield or key performance indicators. It is determined by performing correlation analysis on historical data and quantifying the statistical correlation between each potential state dimension and the chip's key performance indicators.

[0070] This process is described by the following formula: ;

[0071] in The uncertainty index is a dimensionless deviation measure. Its physical meaning is the weighted distance of the chip state from the ideal center, which is calculated by this module. Let be the k-th component of the input potential state vector z; Here, represents the risk weight coefficient; N is the dimension of the potential space, an integer representing the number of components in the potential state vector z; this model aggregates risks using a weighted vector norm, simplifying calculations while effectively characterizing the overall deviation. Although this model does not explicitly express the nonlinear coupling effect between different process drift modes, in engineering practice, it serves as a risk metric with computational efficiency and good interpretability, sufficient to meet the needs of rapid decision-making on production lines.

[0072] This embodiment makes the final calculated uncertainty index It can more accurately reflect the true risks of chips and highlight the impact of key risk factors, thereby significantly improving the accuracy and reliability of risk assessment.

[0073] Example 4:

[0074] The risk assessment module is used for:

[0075] When the uncertainty index is greater than the high-risk threshold, the risk level is classified as high.

[0076] When the uncertainty index is between the low-risk threshold and the high-risk threshold, the risk level is determined to be medium.

[0077] When the uncertainty index is less than or equal to the low-risk threshold, the risk level is determined to be low.

[0078] Based on Example 1, the risk assessment module will calculate the continuously changing uncertainty index from the previous steps. The risk level L is mapped to a discrete level that can be directly used for subsequent control strategies.

[0079] The risk level is classified as high. ,middle ,Low Level 3; this module makes a judgment through a preset threshold comparison logic; when the uncertainty index Greater than the high-risk threshold At that time, the risk level L was determined to be high. High-risk threshold It is a threshold value used to identify statistically rare anomalous individuals, and its source can be set to production line history. The 95th percentile of the value distribution is used to ensure that only statistically significant deviations are marked as high risk; when the uncertainty index... Between low risk threshold With high risk threshold In between, that is The risk level L is classified as medium. When the uncertainty index Less than or equal to the low-risk threshold At that time, the risk level L was determined to be low. Low risk threshold It is a threshold value used to distinguish between typical qualified products and potentially risky products, and its source can be set as production line history. The 50th percentile of the value distribution represents a typical group in the production line;

[0080] Through the above three-level threshold judgment logic, this invention transforms the abstract risk index into a specific and operable risk level, providing a direct and reliable decision input for achieving precise resource allocation and differentiated testing strategies.

[0081] Example 5:

[0082] The resource allocation module is used for:

[0083] Invoke the budget multiplier tied to the risk level;

[0084] The calculation time budget is determined based on the product of the budget multiplier and the baseline calculation time.

[0085] Based on Example 1, the resource allocation module transforms the discrete risk level L output by the risk assessment module into specific resource constraints for the subsequent scheme generation module, i.e., the calculation time budget. ;

[0086] The allocation algorithm of this module aims to prioritize the allocation of limited computing resources to high-risk chips; its implementation involves calling a budget multiplier tied to the risk level. And based on the budget multiplier and benchmark calculation time The product of these factors determines the computation time budget. Budget multiplier This is a dimensionless coefficient associated with the risk level L. Its function is to amplify or reduce the baseline calculation time. It is empirically set based on the convergence characteristics of algorithms with different complexities and the overall production line time window constraints. (Baseline calculation time) It is a preset time constant, which serves as a baseline for resource allocation. Its value is set according to the overall production line cycle time requirements.

[0087] The mathematical model for this allocation rule is as follows: ;

[0088] in The time budget is the upper limit of runtime allocated to the solution generation module, which is calculated by this module. The calculation time is based on the baseline. This is the budget multiplier, and its value is determined by the risk level L.

[0089] This embodiment transforms the resource allocation strategy into a precise and executable mathematical calculation rule by introducing a budget multiplier and a baseline time, thereby achieving the optimal allocation of test resources and maximizing the efficiency of the entire production line.

[0090] Example 6:

[0091] Building upon Example 1, the process by which the scheme generation module determines the optimal test scheme is further explained. This process aims to address the computational time budget provided by the resource allocation module. Internally, it searches the candidate solution library and determines the optimal test solution with the highest information acquisition efficiency. To achieve this goal, this embodiment introduces two core metrics: diagnostic value and information utility. The specific steps are as follows:

[0092] Determine the diagnostic value of each candidate test scheme;

[0093] Based on the uncertainty index calculated by the risk calculation module, the inherent diagnostic sensitivity coefficient of each candidate test solution in the candidate solution library, and the estimated execution time, the diagnostic value of each candidate test solution is determined. It is an indicator used to measure how much information gain a specific test scheme S can bring under the current chip state, and its calculation formula is: ;

[0094] in For diagnostic value; It is an uncertainty index; This is the inherent diagnostic sensitivity coefficient; To estimate the execution time; To test the physical characteristics of the hardware platform's time constant;

[0095] Calculate the information utility of each candidate test scheme;

[0096] To balance diagnostic value and time cost, the diagnostic value of each candidate test plan is divided by the corresponding estimated execution time to calculate the information utility. The diagnostic value obtained per unit of time is calculated using the following formula: ;

[0097] Select the optimal test plan;

[0098] The solution generation module should not exceed the computation time budget. Within a given timeframe, iterate through a subset of candidate solutions in the pool and calculate the information utility for each solution. The solution with the highest information utility value is then output as the optimal solution for this test. .

[0099] By defining and calculating diagnostic value and information utility sequentially, and taking maximizing information utility as the optimization objective, this invention transforms the complex problem of test scheme selection into a mathematical problem with a clear optimization objective. This achieves a shift from blindly pursuing accuracy to intelligently pursuing utility, ensuring that every test decision reaches the theoretical optimum while meeting production line cycle constraints.

[0100] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A vector analog gated based amplitude modulation signal source scheme intelligent generation system, characterized in that, The method comprises the following steps: a data acquisition module is configured to obtain a response feature vector of a chip under test; a state inference module is configured to infer a latent state vector based on the response feature vector and a preset probabilistic agent model; a risk calculation module is configured to calculate an uncertainty index based on the latent state vector and a preset risk weight coefficient; a risk determination module is configured to determine a risk level of the chip under test according to the uncertainty index and a preset risk threshold; a resource allocation module is configured to allocate a computation time budget according to the risk level; a scheme generation module is configured to determine an optimal test scheme from a preset candidate scheme library within the computation time budget; a test execution module is configured to execute the optimal test scheme. The risk calculation module is configured to: multiply each component of the latent state vector by a corresponding risk weight coefficient; and square and take the square root of the product to obtain the uncertainty index. The process is described by the following equation: ; wherein is an uncertainty index, a dimensionless bias metric, whose physical meaning is the weighted distance of the chip state from the ideal center, calculated by the present module; is the input latent state vector is the kth component of the input latent state vector is a risk weight coefficient; is the dimension of the latent space, an integer, representing the number of components of the latent state vector ; The scheme generation module is configured to determine the optimal test scheme by: determining the diagnostic value of each candidate test scheme based on the uncertainty index calculated by the risk calculation module, the inherent diagnostic sensitivity coefficient of each candidate test scheme in the candidate scheme library, and the estimated execution time. The calculation formula is ; wherein is a diagnostic value; is an uncertainty index; is an intrinsic diagnostic sensitivity coefficient; is an estimated execution time; is a physical characteristic time constant of the test hardware platform; Further comprising: dividing the diagnostic value of each candidate test scheme by the corresponding estimated execution time to calculate the information utility. Further comprising: selecting the candidate test scheme with the maximum information utility as the optimal test scheme within the computation time budget.

2. The intelligent generation system of a vector-modeled-gated amplitude modulation signal source scheme according to claim 1, wherein, The probabilistic agent model is a deep encoder network trained offline, configured to receive the response feature vector as input and output the latent state vector.

3. The intelligent generation system of a vector-modeled-gated amplitude modulation signal source scheme according to claim 1, wherein, The risk determination module is configured to: determine the risk level as high when the uncertainty index is greater than a high risk threshold; determine the risk level as medium when the uncertainty index is between a low risk threshold and the high risk threshold; determine the risk level as low when the uncertainty index is less than or equal to the low risk threshold.

4. The intelligent generation system of a vector-modeled-gated amplitude modulation signal source scheme according to claim 1, wherein, The resource allocation module is configured to: call a budget multiplier bound to the risk level; and determine the computation time budget based on the product of the budget multiplier and a baseline computation time.

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