Edge coupling light emitting type 3D optical co-packaging preparation method and structure supporting plastic packaging

Abstract

The invention provides an edge coupling light emitting type 3D optical co-packaging preparation method supporting plastic packaging. The method adopts a 3D stacking scheme that an electric chip is arranged on the upper portion and an optical chip is arranged on the lower portion, and comprises the steps that S1, a plurality of rewiring layers and a micro bonding pad are prepared on the upper portion of the optical chip; s2, enabling the optical chip to be electrically connected with the electric chip through the multi-layer rewiring layer and the micro bonding pad; and S3, leading out signal input and output interfaces of the electric chip, the optical chip and the ASIC / switching chip downwards through silicon through holes in the optical chip, and realizing electric connection with the ASIC / switching chip through a substrate or an adapter plate. According to the invention, plastic package can be supported, the light emitting efficiency of the optical port is not influenced by a plastic package material after RDL and EIC bonding and plastic package processes are manufactured, the adhesion of the plastic package material or PI particles on the optical port during mechanical cutting is relieved, and the coupling efficiency is ensured.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a preparation method and structure of an edge-coupling light output type 3D optical co-packaging supporting plastic packaging. BACKGROUND

[0002] CPO (co-packaged optics) is an optical co-packaging technology, which refers to highly integrating silicon optical chips (EIC electric chips and PIC optical chips) and computing / switching (XPU / Switch) chips in an advanced packaging form (2.5D / 3D process) to greatly reduce volume and weight, shorten connection distance, reduce signal delay, improve signal transmission speed and bandwidth, and realize low latency, low power consumption and high performance. With the growing demand for more data and faster communication, CPO has become a promising solution to meet the challenging requirements of the next generation network.

[0003] Optoelectronic co-packaging refers to integrating silicon optical chips (PIC), driving / TIA electric chips (EIC) and computing / switching (XPU / Switch) chips in an advanced packaging form to improve signal transmission speed and bandwidth, realize low latency, low power consumption and high performance, and solve the core problems of improving performance and integration, improving thermal management capability and reliability, avoiding optical port pollution of optical chips, and facilitating fiber interconnection.

[0004] The core process difficulty of CPO co-packaging lies in: (1) Avoiding pollution to the PIC optical port as much as possible during the packaging process, improving the efficiency of optical coupling, and facilitating fiber interconnection.

[0005] (2) EIC and PIC 3D stacking, signal extraction and connection to the computing / switching chip.

[0006] (3) Thermal management, warpage control, reliability improvement, etc. after co-packaging of high-power optoelectronic chips.

[0007] At present, various optoelectronic co-packaging technologies are basically developed around the above problems. The above three aspects interact and restrict each other. Overall, it is very difficult to use molding process to handle PIC to avoid pollution to the PIC optical port and to realize efficient edge coupling output of the optical port. Different placement positions of EIC and PIC lead to different heat dissipation efficiencies and affect different signal extraction methods, which involves the use of TGV, TSV, TMV and other processes. Different optical port coupling methods also affect the overall packaging scheme. At present, various schemes are developing and verifying technical solutions around the above difficulties, each having advantages and disadvantages, and no clear mass production process route has been formed. Various schemes are in the stage of hundred flowers blooming. SUMMARY

[0008] In view of the above problems existing in the prior art, the present application provides a plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method, which adopts a 3D stacking scheme of an electrical chip on the top and an optical chip on the bottom, and is characterized in that the method comprises the following steps: Step S1, a plurality of re-distribution layers and micro-bumps are prepared above the optical chip; Step S2, the optical chip is electrically connected with the electrical chip via the plurality of re-distribution layers and the micro-bumps; and Step S3, the signal input and output interfaces of the electrical chip, the optical chip and an ASIC / exchange chip are led downward through a through-silicon via on the optical chip, and the electrical connection with the ASIC / exchange chip is realized through a substrate or an adapter board.

[0009] In addition, preferably, in the plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method of the present application, in the step S3, a blind hole backside copper-exposed process is performed on the optical chip to expose the through-silicon via, and a subsequent re-distribution layer and a controllable chip connection bump are prepared for physical connection with the substrate or the adapter board.

[0010] In addition, preferably, in the plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method of the present application, in the step S3, a glass sheet is placed above the optical chip and the edge-coupling structure of the optical port.

[0011] In addition, preferably, in the plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method of the present application, the thickness of the glass sheet is thinner than or substantially the same as the thickness of the re-distribution layer.

[0012] In addition, preferably, in the plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method of the present application, the glass sheet is bonded above the wafer of the optical chip, and is located directly above the position of the edge-coupling structure of the optical port.

[0013] In addition, preferably, in the plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method of the present application, the edge length of the glass sheet ranges from 1 to 2 mm, and the thickness of the glass sheet is 5-100 um.

[0014] In addition, preferably, in the plastic-sealed edge-coupling light-out 3D optical co-packaging preparation method of the present application, the glass sheet is a single glass sheet with a mark point for alignment, and is achieved through D2W anodic bonding or W2W anodic bonding. The entire glass wafer is grooved, and is ground after bonding, so that the glass part is located directly above the position of the edge-coupling structure of the optical port.

[0015] Furthermore, preferably, in the edge coupling light-out type 3D optical co-packaging preparation method supporting plastic packaging of the present application, the step 2 further comprises: core granulation of the electrical chip, micro-bump process is used to make micro-bumps on the EIC wafer, and then cutting into particles.

[0016] Furthermore, preferably, in the edge coupling light-out type 3D optical co-packaging preparation method supporting plastic packaging of the present application, the step 1 comprises: coating polyimide on the optical chip, then performing exposure, development, hard baking, then performing PVD deposition of copper seed layer, then performing coating, exposure, development to achieve patterning, then performing copper electroplating process to deposit a conductive layer, and finally performing glue removal and wet metal etching to remove excess copper, and repeatedly performing the above processes to make a multi-layer redistribution layer.

[0017] Furthermore, preferably, in the edge coupling light-out type 3D optical co-packaging preparation method supporting plastic packaging of the present application, after the multi-layer redistribution layer is made, a separation layer and a seed layer are deposited, then coating, exposure, development are performed to achieve patterning, then micro-bump electroplating is performed, then glue removal and metal etching are performed, and finally micro-bump forming is performed.

[0018] Furthermore, preferably, the present application further provides an edge coupling light-out type 3D optical co-packaging structure supporting plastic packaging, which is prepared by the edge coupling light-out type 3D optical co-packaging preparation method supporting plastic packaging of the present application, in the structure, a 3D stacking scheme of electrical chip on top and optical chip on bottom is adopted, a multi-layer redistribution layer and a micro-bump are prepared above the optical chip; the optical chip is electrically connected with the electrical chip via the multi-layer redistribution layer and the micro-bump; the signal input and output interfaces of the electrical chip, the optical chip and the ASIC / switch chip are led downward through the through silicon vias on the optical chip, and the electrical connection with the ASIC / switch chip is realized through a substrate or an adapter plate.

[0019] By using the present application, plastic packaging can be supported, and the light-out efficiency of the optical port can be ensured not to be affected by the plastic packaging material after the RDL, EIC bonding and plastic packaging processes are made, the adhesion of the plastic packaging material or PI particles on the optical port when mechanical cutting is used is alleviated, and the coupling efficiency is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic diagram showing the serious warping condition when a multi-layer redistribution layer is made below a silicon adapter plate in the prior art.

[0021] Figure 2 is a schematic diagram showing the condition of a multi-layer redistribution layer with controlled warping deformation made below a silicon adapter plate according to an embodiment of the present application.

[0022] Figure 3This is a schematic diagram illustrating the specific steps of stage 1 in a specific fabrication process of a packaging structure according to an embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram illustrating the specific steps of stage 2 in a specific fabrication process of a packaging structure according to an embodiment of the present invention.

[0024] Figure 5 This is a schematic diagram illustrating some specific steps in stage 3 of a specific fabrication process method for a packaging structure according to an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram illustrating some specific steps in stage 3 of a specific fabrication process method for a packaging structure according to an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0027] In the future, silicon photonics processes supporting TSVs will be a trend, and the technology will become more mature. Considering the above factors, this invention proposes an optoelectronic packaging method that allows 3D stacking of PIC chips and EIC chips with TSVs, supporting edge-coupled side output of the optical port, and supporting molding. Since molding materials affect the optical coupling structure, they can significantly reduce light output efficiency. This invention, by placing a glass sheet of a certain thickness above the PIC and the edge coupling structure of the optical port, ensures that the light output efficiency of the optical port is not affected by the molding material after RDL fabrication, EIC bonding, and molding processes. It also alleviates the adhesion of molding material or PI particles to the optical port during mechanical cutting, ensuring a smooth and clean exposed optical port, facilitating coupling with the FAU, guaranteeing coupling efficiency, and solving the problem of difficult light output after molding.

[0028] Furthermore, preferably, the advantages of the various technical solutions involved in this invention also include: (1) The EIC and PIC are vertically stacked and interconnected, with the EIC on top and the PIC on the bottom, which is conducive to heat dissipation.

[0029] (2) EIC with plastic encapsulation can provide long-term reliability; at the same time, based on the plastic encapsulation process, wafer-level packaging technology can be used to prepare the RDL and bumps under the PIC and subsequent process steps, thereby improving packaging efficiency and reducing costs.

[0030] (3) Supports edge coupling and has high optical port coupling efficiency.

[0031] (4) The upper surface of the cut photoelectric engine is flat, which is also very conducive to the subsequent process of integration with the substrate.

[0032] (5) PIC comes with TSV, eliminating the need for TMV process, resulting in a simple overall packaging process and low packaging cost.

[0033] With the explosive growth of data traffic, the demand for data communication solutions with higher speeds, lower power consumption, and lower latency is increasing daily. Due to the limitations of Moore's Law, traditional pluggable optical modules face constraints in terms of bandwidth, latency, energy efficiency, and speed. Silicon-based optoelectronics technology, on the other hand, utilizes semiconductor manufacturing technology to interconnect optoelectronic components on silicon chips, opening up new possibilities for high-density, multi-channel solution designs.

[0034] Driven by this market demand, CPO co-packaging technology has emerged and has become a promising alternative to pluggable solutions. It is currently a research hotspot in the fields of optical communication and optoelectronic packaging and integration.

[0035] Multi-system heterogeneous integration of PIC and EIC devices as well as ASICs / switches can be achieved using both 2.5D and 3D packaging technologies.

[0036] For 2.5D optoelectronic co-packaging, the EIC and PIC are integrated side-by-side on an interposer, which connects the ASIC / switch, EIC, and PIC via micro-bumps. The interposer also supports fiber optic assemblies with PIC fiber blocks, which requires very high alignment accuracy (1μm) to achieve good optical coupling efficiency.

[0037] For 3D optoelectronic co-packaging, EIC and PIC are stacked vertically, which can further reduce the area, further reduce the distance between the optical engine and the computing chip, and further reduce latency and loss.

[0038] Currently, the mainstream solution in the industry is 3D stacking.

[0039] For example, Broadcom uses a CPO process based on EIC fanout technology; the PIC is on top, and the EIC is below, stacked vertically; it uses TMV technology; the EIC is interconnected via RDL and TMV, substrate traces, and switch chips. The PIC does not require TSV technology; the EIC needs to be thinned to 100um; similar to the CoWoS-L process; RDL traces are flexible and can be densely arranged; capacitors are easy to add; heat dissipation of the EIC is relatively difficult.

[0040] TSMC's process route places the PIC (Computer Integrated Circuit) at the bottom and the EIC (Engineering Integrated Circuit) on top, using hybrid bonding and vertical stacking. The PIC incorporates a TSV (Transmission Vector Unit) and employs its own special silicon photonics process, with vertical optical coupling and no EMC filling. Advanced packaging processes and other circuits can be used to achieve electrical connections. The EIC connects to the computing chip via the TSV and switch, supporting interposer processes. The number of RDL (Relative Layer Count) layers is determined by the inetpsoer process, allowing for a L / S ratio of less than 1µm, resulting in superior SI (Integration Interface) performance compared to substrate routing. The top placement of the EIC facilitates heat dissipation. However, the high integration density of the EIC presents significant challenges for design companies, as hybrid bonding shifts the design process forward, and adding decoupling capacitors is difficult. Implementation using front-end processes results in high packaging costs.

[0041] Marvell's process route embeds the PIC chip within a molding compound, which incorporates a vertically connected metal VIA (Through Molding Via). The TMV, 300µm in height, connects to the RDL metal layers on the front and back of the PIC. The front layer has two RDL metal layers, while the back layer has one. The back RDL is connected to the substrate via a C4 bump, while the front RDL is connected to the EIC chip via a micro-bump. The EIC is positioned on top for better heat dissipation.

[0042] Currently, various solutions are under development and verification, each with its own advantages and disadvantages. No clear process route for large-scale mass production has yet been formed, and various solutions are in a stage of flourishing.

[0043] Therefore, this invention proposes an optoelectronic packaging method that allows for 3D stacking of PIC chips with TSV and EIC chips, supporting side output from the optical port and enabling plastic encapsulation. This solves the problems of difficult light output from the optical port and ensuring light output efficiency after plastic encapsulation. Specifically, as follows... Figure 1 As shown.

[0044] Figure 1 This is a schematic diagram illustrating a 3D stacking scheme according to an embodiment of the present invention.

[0045] Preferably, according to one embodiment of the present invention, a 3D stacking scheme with the EIC chip on top and the PIC chip below is adopted. Multilayer RDL and micro PADs are fabricated on top of the PIC to realize electrical interconnection with the EIC. At the same time, the I / O of the EIC, PIC and ASIC / switching chips, etc. are led out to the bottom of the PIC chip through TSV on the PIC, and then electrically connected to the ASIC / switching chip through a substrate or adapter board. Therefore, the PIC needs to undergo VBR process to expose the TSV, as well as subsequent RDL routing and C4 bump fabrication, to facilitate physical connection with the substrate or adapter board.

[0046] By placing a glass plate above the PIC and the edge coupling structure of the optical port, it can be ensured that the light output efficiency of the optical port is not affected by the molding material after the fabrication of RDL, EIC bonding and molding process. At the same time, it can reduce the adhesion of molding material or PI particles to the optical port when mechanical cutting is used, which can ensure the flatness and cleanliness of the exposed optical port, which is conducive to coupling with FAU and ensures coupling efficiency.

[0047] The specific preparation process based on this technical solution is described in detail in the embodiments.

[0048] A method and structure for fabricating a 3D CPO package with edge-coupled light emission supporting molding encapsulation is proposed. The structure is characterized by vertically stacked interconnected EIC and PIC, with the EIC on top and the PIC below. The PIC faces upwards and employs a side-emitting light structure. A glass sheet is placed above the edge-coupled structure of the PIC's optical port. The PIC has multilayer RDL and micro-PADs for electrical connection with the EIC. The glass sheet can be thinner than or flush with the RDL layers. The presence of the glass sheet ensures that the molding compound does not affect the light emission efficiency of the optical port. After the EIC is bonded to the PIC, it is surrounded by molding material. The PIC has a TSV (Transient Vibration Vessel). RDL and micro-bumps are fabricated below for connection to the substrate.

[0049] And the corresponding process method for this structure. Key steps include: A glass sheet is bonded on top of the PIC wafer. The glass sheet is located directly above the coupling structure at the edge of the optical port. The recommended side length is about 1-2 mm, and the recommended thickness is about 5-100 μm (thicker is also acceptable). The glass sheet can be a single piece with markings to facilitate alignment. This is achieved through D2W anodic bonding.

[0050] Alternatively, W2W anodic bonding can be used. The entire glass disc is grooved, bonded, and then ground, ensuring the glass portion is positioned directly above the coupling structure at the edge of the optical port. The specific implementation process is as follows: Figure 2 As shown.

[0051] Since glass sheets are bonded on the PIC wafer, when the thickness does not exceed 10 μm, or when the thickness exceeds 10 μm, a dry film process is used to coat the photoresist during the fabrication of the RDL. Since the distance between the glass sheet position and the circuit trace in the actual PIC circuit is relatively large, gaps in the dry film glass sheet bonding are acceptable and do not affect the fabrication of the RDL.

[0052] Phase 1, Chip Granulation: Microbumps are fabricated on EIC wafers using a bumping process for later use, and then diced into chips, or off-the-shelf EIC chips with microbumps are used. Specific solutions are as follows... Figure 3 As shown.

[0053] Phase 2, Optoelectronic Integration Process: A glass sheet is bonded on top of the PIC wafer. The glass sheet is positioned directly above the optical port edge coupling structure. A side length of approximately 1-2 mm and a thickness of approximately 5-100 μm (thicker is also acceptable) are recommended. The glass sheet can be a single piece with markings for easy alignment, achieved through D2W anodic bonding; alternatively, W2W anodic bonding can be used, where the entire glass wafer is recessed, ensuring the glass portion is precisely positioned above the optical port edge coupling structure. Specific solutions are as follows... Figure 4 As shown.

[0054] The subsequent fabrication of the RDL and micropads involves coating them with polyimide, followed by exposure, development, and hard baking. A copper seed layer is then deposited using PVD, followed by coating, exposure, and development to achieve patterning. Next, copper electroplating is performed to deposit a conductive layer. Finally, resist removal and wet metal etching are performed to remove excess copper, thus completing the fabrication of one RDL layer. This process is repeated to create multiple redistribution layers. After the redistribution layers, micropads are fabricated. Specifically, an isolation layer and seed layer are deposited, followed by coating, exposure, and development to achieve patterning. Next, micropad electroplating is performed, followed by resist removal and metal etching, finally shaping the micropads.

[0055] Because the PIC wafer has a glass sheet bonded on it, and the photoresist is coated using a dry film process, the glass sheet is located far from the circuit traces. This process does not affect the circuit performance.

[0056] Subsequently, D2W thermo-press bonding was used to achieve vertical interconnection between the battery chip and the optical wafer. The interconnected chip underwent underfilling to increase its robustness and durability. Following this, a molding process was performed, flipping the wafer to thin the back side and expose the TSV vias. Then, a back redistribution layer and C4 bumps were fabricated. After fabrication, a wafer-level mechanical dicing process was performed to expose the optical ports, resulting in the optical engine chip formed by the 3D stacking of EIC and PIC.

[0057] Because of the glass plate above the optical port, the light output efficiency of the optical port is not affected by the molding compound. Furthermore, during mechanical cutting, molding compound or PI particles will not adhere to the optical port, ensuring its smoothness and achieving good optical coupling efficiency. Specific solutions are as follows: Figure 5 As shown.

[0058] For example, an optical engine composed of EIC and PIC is bonded to a computing / switching chip on a packaging substrate to form an optoelectronic co-packaged product. This part belongs to a mature substrate packaging technology and will not be described in detail here. Specific solutions are as follows: Figure 6 As shown.

[0059] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0060] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0061] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0062] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a 3D optical co-package with edge coupling of light supporting plastic encapsulation, employing a 3D stacking scheme with the electrical chip on top and the optical chip below, characterized in that... The methods include: Step S1: Prepare multiple redistribution layers and micro pads on top of the optical chip; Step S2, the optical chip is electrically connected to the electrical chip via the multilayer redistribution layer and the micro pads; Step S3: The signal input / output interfaces of the electrical chip, the optical chip, and the ASIC / switching chip are led out downwards through the through-silicon vias on the optical chip, and electrical connection with the ASIC / switching chip is achieved through a substrate or adapter board.

2. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 1, characterized in that, In step S3, the optical chip is subjected to a blind via back copper exposure process to expose the through-silicon via, and a subsequent redistribution layer and controllable collapse chip connection bumps are prepared for physical connection with the substrate or adapter board.

3. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 2, characterized in that, In step S3, a glass sheet is placed above the optical chip and the optical port edge coupling structure.

4. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 3, characterized in that, The thickness of the glass sheet is thinner than or approximately the same as the thickness of the gravity wiring layer.

5. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 3, characterized in that, The glass sheet is bonded above the wafer of the optical chip, and the glass sheet is located directly above the optical port edge coupling structure.

6. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 5, characterized in that, The side length of the glass sheet is 1-2 mm, and the thickness of the glass sheet is 5-100 μm.

7. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 6, characterized in that, The glass sheet is a single glass sheet with alignment markings, achieved through D2W anodic bonding or W2W anodic bonding. The entire glass disc is grooved, bonded, and then ground, ensuring that the glass portion is positioned directly above the optical port edge coupling structure.

8. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 1, characterized in that, Step 2 further includes: chip granulation of the electronic chip, which involves creating microbumps on the EIC wafer using a bumping process, and then cutting them into particles.

9. The method for fabricating edge-coupled light-emitting 3D optical co-packages supporting plastic encapsulation according to claim 1, characterized in that, Step 1 includes: coating polyimide on the optical chip, then exposing, developing, and hard baking, then depositing a copper seed layer using PVD, then coating, exposing, and developing to achieve patterning, then performing an electroplating copper process to deposit a conductive layer, and finally performing resist removal and wet metal etching to remove excess copper. The above process is repeated to produce a multilayer redistribution layer.

10. A 3D optical co-package structure with edge-coupled light emission supporting plastic encapsulation, fabricated using the 3D optical co-package fabrication method with edge-coupled light emission supporting plastic encapsulation as described in any one of claims 1 to 9, characterized in that, A 3D stacking scheme with electrical chips on top and optical chips on the bottom is adopted, and multiple redistribution layers and micro pads are fabricated on top of the optical chips; The optical chip is electrically connected to the electrical chip via the multilayer redistribution layer and the micro pads; The signal input / output interfaces of the electrical chip, the optical chip, and the ASIC / switching chip are led out downwards through through-silicon vias on the optical chip and electrically connected to the ASIC / switching chip via a substrate or adapter board.

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